OFDM frame synchronization control method and system based on system information CRC cross-layer feedback

Abstract

The invention discloses an OFDM (Orthogonal Frequency Division Multiplexing) frame synchronization control method and system based on system information CRC (Cyclic Redundancy Check) cross-layer feedback. The system information decoding module executes CRC (cyclic redundancy check) on the system information in the balanced subcarrier data, and feeds back a result to the frame synchronization state machine in a cross-layer manner; after the state machine enters a tracking state, a wide period is set, and CRC failures are not accumulated in the period; an asymmetric threshold strategy-CRC is adopted after the broad period, and a continuous failure counter is cleared in time, and if CRC fails, increasing is carried out; when the counter reaches a preset threshold value, emptying an accumulation buffer, resetting a subframe timing boundary and returning an action chain in a capture state; cyclic prefix correlation is utilized to apply clipping integer sampling corrections to subframe timing boundaries during the tracking state. According to the invention, the upper layer protocol verification result is synchronously and deeply coupled with the physical layer, so that the audio interruption time of the receiver in the FM co-frequency environment is obviously reduced.

Description

Technical Field

[0001] This invention belongs to the field of digital broadcast receiver technology, specifically relating to an OFDM frame synchronization control method and system based on cross-layer feedback of system information CRC, and particularly to a technology that uses the CRC check result of system information for cross-layer feedback to drive the physical layer frame synchronization state machine. Background Technology

[0002] Orthogonal Frequency Division Multiplexing (OFDM) technology is widely used in digital broadcasting systems due to its excellent resistance to multipath fading and high spectral efficiency. In the China Digital Broadcasting (CDR) standard (GY / T 268.1-2013), the physical layer signal frame consists of a beacon and several OFDM data symbols. The receiver needs to determine the timing boundaries of subframes through frame synchronization in order to correctly segment and demodulate the data.

[0003] In traditional OFDM receivers, frame synchronization is typically performed independently within the physical layer: during the acquisition phase, the receiver uses the autocorrelation or cross-correlation characteristics of the beacon signal to detect the subframe start position and estimate the carrier frequency offset; after entering the tracking phase, it relies on cyclic prefix (CP) correlation to maintain timing tracking. The limitation of this architecture is that the physical layer frame synchronization module only uses the indicators generated by the physical layer itself to determine the validity of the synchronization state, without utilizing feedback information from the upper-layer decoding module.

[0004] In the actual propagation environment of FM co-channel broadcasting (SFN / MFN), receivers frequently encounter short-duration deep fading—FM co-channel interference and multipath effects cause the signal-to-noise ratio to drop sharply within seconds. During this period, system information (SI) decoding may temporarily fail, but the physical layer frame timing remains valid. If the receiver lacks fault tolerance mechanisms, the physical layer will frequently trigger "false lockout" judgments due to upper-layer decoding failures, subsequently entering the reacquisition process. However, the cost of OFDM receivers recovering from the acquisition state to the stable tracking state is high: beacon detection, channel estimation convergence, frequency offset correction stabilization, and other processes typically take several seconds, during which the receiver outputs zero, resulting in noticeable audio interruptions and stuttering experienced by end users.

[0005] Several existing technologies utilize control information verification results for synchronization state determination. For example, the ISDB-T system uses TMCC control information reliability assessment to assist frame synchronization determination, but it is based on analog quantity "reliability" calculation rather than deterministic binary CRC determination. In WCDMA systems, there are schemes that use CRC history and sliding window thresholds for synchronization determination, but their determination mechanism is geared towards the CDMA frame structure and does not involve physical layer operations such as OFDM subframe boundary reset and cumulative buffer clearing. In the data link layer, there are also protocol mechanisms that use CRC results to drive the synchronization state machine and tolerate certain errors, but these are limited to link layer frame processing and do not involve physical layer sampling-level timing fine-tuning.

[0006] None of the aforementioned existing technical solutions provide a complete closed-loop solution in OFDM physical layer scenarios that deeply couples the upper-layer CRC check result with the frame synchronization state machine, and incorporates a forgiveness period exemption mechanism, an asymmetric threshold strategy, a physical resource release action chain, and sampling-level timing fine-tuning. Summary of the Invention

[0007] To address the shortcomings of the existing technologies, the present invention aims to provide an OFDM frame synchronization control method and system based on system information CRC cross-layer feedback, so as to effectively suppress misjudgment and re-acquisition caused by short-term channel fading in harsh propagation environments such as FM co-channel broadcasting, while ensuring that physical layer resource release and state rollback can be completed quickly when the lock is truly lost.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] An OFDM frame synchronization control method based on system information CRC cross-layer feedback, applied to an OFDM digital broadcast receiver including a physical layer frame synchronization module and a system information decoding module, includes the following steps:

[0010] S1 Acquisition Step: In the acquisition state, the frame synchronization module performs beacon detection on the received IQ sampled data to obtain the subframe timing boundary and carrier frequency offset estimate. After successful beacon detection, the continuous failure counter F is initialized to zero, the subframe counter C is initialized to zero, and the frame synchronization state machine is switched to the tracking state.

[0011] S2 Tracking Decoding Steps: In tracking mode, the frame synchronization module cuts subframe data from the accumulation buffer according to the subframe timing boundary, performs frequency offset compensation and OFDM demodulation on the subframe data; the system information decoding module extracts system information from the equalized subcarrier data, performs CRC check on the data bits of the system information after convolutional decoding, and obtains the CRC check result.

[0012] S3 Forgiveness Period Judgment Steps: After each subframe is processed, the subframe counter C is incremented by 1; if the CRC check result is a failure and the subframe counter C does not exceed the preset forgiveness period threshold N, the tracking state is maintained and the continuous failure counter F is not updated.

[0013] S4 Asymmetric Threshold Update Steps: If the CRC check result is successful, the consecutive failure counter F is immediately cleared to zero; if the CRC check result is unsuccessful and the subframe counter C exceeds the forgiveness period threshold N, the consecutive failure counter F is incremented by 1.

[0014] S5 Threshold Trigger Action Chain Steps: If the continuous failure counter F reaches the preset continuous failure threshold M, the following action chain is executed in sequence: clear all sampled data in the accumulation buffer; reset the subframe timing boundary to zero; clear both the continuous failure counter F and the subframe counter C to zero; and roll back the frame synchronization state machine to the capture state.

[0015] S6 Sampling-level timing fine-tuning steps: During the tracking state, the sampling timing error is estimated by using the correlation between the cyclic prefix of the OFDM symbol and the tail of the symbol body. The sampling timing error is smoothed by weighted coefficients and accumulated to the timing error accumulator. When the absolute value of the accumulated value of the timing error accumulator exceeds the preset correction threshold, an integer sample correction is applied to the subframe timing boundary, and the correction amount is limited to within the preset maximum correction amount ± K samples.

[0016] The present invention also provides an OFDM frame synchronization control system based on system information CRC cross-layer feedback, including a frame synchronization module and a system information decoding module. The frame synchronization module is configured with a frame synchronization state machine, a beacon detector, an accumulation buffer, a continuous failure counter, a subframe counter and a timing fine-tuning unit. The cooperation relationship of each module corresponds to the steps of the above method.

[0017] The beneficial effects of this invention are as follows:

[0018] First, by setting a grace period in the early stage of the tracking state, the CRC failure that triggers reacquisition before the channel estimation and frequency offset correction have converged is avoided, thus eliminating the zero-output window of several seconds caused by prematurely abandoning the tracking state.

[0019] Second, an asymmetric threshold strategy is adopted. A single successful CRC check proves that the frame synchronization is still valid and immediately resets the failure counter. A single failed CRC check may only be due to momentary channel fading, requiring continuous accumulation to trigger a state backoff. This asymmetric design gives the receiver a strong tolerance to occasional channel fading.

[0020] Third, when consecutive failures reach the threshold, a four-step action chain is executed: clearing the accumulated buffer, resetting the subframe timing boundary, clearing both the consecutive failure counter and the subframe counter to zero, and reverting to the frame synchronization state machine. This ensures that all accumulated states at the physical layer are completely cleared, preventing dirty data from interfering with subsequent recapture processes.

[0021] Fourth, the sampling-level timing fine-tuning is coupled with the CRC-driven frame synchronization state machine: the timing fine-tuning is only performed in the tracking state; further, in the preferred embodiment, the accumulated timing error and the accumulated phase of frequency offset compensation are synchronously cleared to zero when the state is rolled back, forming a complete physical layer closed loop. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the frame synchronization state machine transition of the present invention.

[0023] Figure 2 This is the architecture diagram of the cross-layer feedback closed-loop system of the present invention.

[0024] Figure 3 This is a flowchart of the CRC feedback processing of the present invention.

[0025] Figure 4 This is a closed-loop block diagram of the sampling-level timing fine-tuning of the present invention. Detailed Implementation

[0026] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. The following embodiments are based on CDR (China Digital Broadcasting, GY / T 268.1-2013) transmission mode 1, with a sampling rate of 816000 Hz, a subframe length of 130560 samples (corresponding to 160ms), each subframe containing 1 beacon and 57 OFDM data symbols, and an OFDM symbol length of 2288 samples (of which the cyclic prefix length is 240 samples and the FFT length is 2048 samples).

[0027] I. System Overall Architecture

[0028] like Figure 2 As shown, the OFDM frame synchronization control system based on system information CRC cross-layer feedback according to the present invention includes the following main modules: frame synchronization state machine 101, accumulation buffer 102, continuous failure counter 103, subframe counter 104, system information decoding module 105, timing fine-tuning unit 106, beacon detector 107, OFDM demodulator 108, channel estimator 109, phase accumulator 110, and timing error accumulator 111.

[0029] After the IQ sampling data enters the receiver, it is first stored in the accumulation buffer 102. The frame synchronization state machine 101 controls the overall workflow, and its transition relationship between the acquisition state and the tracking state is as follows: Figure 1As shown: In the acquisition state, the beacon detector 107 searches for beacon signals in the accumulation buffer 102; in the tracking state, the frame synchronization state machine 101 cuts subframe data from the accumulation buffer 102 according to the subframe timing boundary, and after frequency offset compensation, sends it to the OFDM demodulator 108. The frequency domain data output by the OFDM demodulator 108 is then sent to the channel estimator 109 for channel estimation and equalization. The system information decoding module 105 extracts system information (SI) from the equalized subcarrier data output by the channel estimator 109, performs CRC check, and feeds back the check result (pass or fail) to the frame synchronization state machine 101, forming a cross-layer feedback closed loop. The timing fine-tuning unit 106 continuously estimates and corrects the sampling timing error during the tracking state.

[0030] II. Implementation of the capture step (S1)

[0031] When frame synchronization state machine 101 is in the acquisition state, the received IQ sampled data is continuously written to accumulation buffer 102. When the amount of data in accumulation buffer 102 reaches at least one subframe length (130,560 samples), beacon detector 107 performs two-step RMD (Repeated Modulation Domain) beacon detection on the data. The first step is coarse detection, which calculates the autocorrelation of the beacon half on the signal after FM bandpass filtering; the second step is fine synchronization, which determines the start position of the subframe (i.e., the start sampling position of the beacon cyclic prefix) and estimates the fractional frequency offset.

[0032] After successful beacon detection, frame synchronization state machine 101 performs the following initialization operations: sets the value of continuous failure counter 103 to zero; sets the value of subframe counter 104 to zero; clears phase accumulator 110; clears timing error accumulator 111; records the frequency offset estimate obtained from beacon detection to the frequency offset storage register; and sets the subframe timing boundary to the position determined by beacon detection. After completing the above initialization, frame synchronization state machine 101 switches from acquisition state to tracking state.

[0033] In this embodiment, the beacon detector 107 also performs blind detection of the spectral mode and interpolation factor NI. The fine synchronization process uses raw (unfiltered) IQ data to analyze the beacon frequency domain to determine the spectral mode and subcarrier configuration parameters of the current broadcast signal.

[0034] III. Implementation of the Tracking Decoding Step (S2)

[0035] After the frame synchronization state machine 101 enters the tracking state, whenever enough data has accumulated in the accumulation buffer 102, that is, the data of a complete subframe is segmented starting from the subframe timing boundary. During the segmentation, an additional 16 samples are extracted as a search margin for timing tracking.

[0036] The segmented subframe data first undergoes frequency offset compensation. Frequency offset compensation uses the continuous phase maintained by phase accumulator 110, multiplying each IQ sample in the subframe by the corresponding phase rotation factor exp(-j·2π·f_offset·n / f_s), where f_offset is the current frequency offset estimate, n is the sample number, and f_s is the sampling rate. Phase accumulator 110 maintains phase continuity across subframes and takes the modulus of the accumulated phase to prevent loss of floating-point precision.

[0037] After frequency offset compensation, the subframe data is divided into a beacon portion and an OFDM data symbol portion. The OFDM demodulator 108 performs a symbol-by-symbol de-cyclic prefix and FFT operation on the data symbol portion. The channel estimator 109 performs channel estimation and equalization on the frequency domain data using pilot subcarriers.

[0038] The system information decoding module 105 extracts system information symbols from the equalized subcarrier data. According to the GY / T268.1-2013 standard, in transmission mode 1, the system information is QPSK modulated and coded in 4 columns and 27 rows in each of the upper and lower subbands (i.e., each subframe contains 108 SI symbols), and is repeated once in each of the upper and lower subbands and once in the row direction, forming a total of four copies.

[0039] The system information decoding module 105 adopts a multi-level backoff decoding strategy, attempting decoding in the following order of priority:

[0040] Level 1: Perform symbol-by-symbol phase alignment on each of the four SI replicas (using the fourth power residual phase estimation of the data subcarriers), and then combine the log likelihood ratios (LLRs) of the four replicas for joint decoding, which results in a signal-to-noise ratio gain of approximately 6 dB compared to a single replica.

[0041] Level 2: Skip symbol-by-symbol phase alignment and directly merge and decode the four copies of the LLR.

[0042] Level 3: Decoding only the two line duplicate copies of the lower half of the subband is performed, resulting in a signal-to-noise ratio gain of approximately 3dB.

[0043] Level 4: Decode only the two duplicate copies of the upper half of the subband.

[0044] Level 5: Use only a single copy of the lower half of the subband for rollback decoding.

[0045] Each decoding stage attempts four 90-degree phase rotation candidates (0°, 90°, 180°, 270°) to accommodate different carrier phase ambiguity situations. The merged LLR is deinterleaved and Viterbi convolutional decoded to output 48 bits of system information hard decision data.

[0046] In the decoded 48-bit system information data, the first 42 bits are information bits, and the last 6 bits are the CRC-6 checksum. The generator polynomial of CRC-6 is G6(x) = x 6 + x 5 + x³ + x² + x + 1, the register is initially set to all 1s (i.e., 0x3F). The system information decoding module 105 recalculates the CRC-6 for the first 42 bits and compares it with the received 6-bit checksum: if they are equal, the CRC check passes; otherwise, the CRC check fails.

[0047] After the CRC check passes, a spectrum pattern voting confirmation is required. The system information decoding module 105 includes a spectrum pattern voting confirmation unit: the decoded spectrum pattern index is compared with the candidate value. If the same spectrum pattern index is obtained in L consecutive decoding attempts (L=3 in this embodiment), the index is confirmed as valid and locked. If the CRC passes but the spectrum pattern is inconsistent with the confirmed value, it is considered a false CRC positive and the decoding result is discarded. This design utilizes the statistical characteristic that the false pass probability of CRC-6 is approximately 1 / 64, reducing the false positive probability to a negligible level through multiple consistency verifications.

[0048] Finally, the system information decoding module 105 feeds back the CRC check result to the frame synchronization state machine 101: if the check passes, the CRC success notification interface of the frame synchronization module is called; if the check fails, the CRC failure notification interface is called.

[0049] IV. Implementation of the Forgiveness Period Judgment Step (S3)

[0050] like Figure 3 As shown, in the tracking state, the frame synchronization state machine 101 increments the subframe counter 104 by 1 after processing each subframe. The value of the subframe counter 104 represents the total number of subframes processed since entering the tracking state.

[0051] When a CRC failure is received, the frame synchronization state machine 101 first checks whether the current value of the subframe counter 104 exceeds the forgiveness period threshold N. In this embodiment, N is 40 subframes, corresponding to 6.4 seconds (160ms × 40 = 6400ms per subframe).

[0052] If the value of subframe counter 104 does not exceed 40, the frame synchronization state machine 101 determines that it is still within the forgiveness period, maintains the tracking state, and does not perform any operation on the continuous failure counter 103. It should be noted that during the forgiveness period, the frame synchronization module still normally segments and processes subframe data according to the existing subframe timing boundaries, and does not perform the clearing operation of the accumulation buffer 102; the processed subframe data is pruned and removed from the accumulation buffer 102 according to the normal process. Therefore, there is no problem of dirty data accumulating or spreading in the buffer due to transient CRC failure. The forgiveness period is set based on the following: After the receiver switches from the acquisition state to the tracking state, the channel estimator 109 needs approximately 30 to 50 subframes to complete the initial convergence of the channel estimation, and the frequency offset correction loop also needs a similar amount of time to stabilize. During this convergence process, the channel equalization and frequency offset compensation accuracy of OFDM symbols are insufficient, resulting in a low SI decoding success rate. Without a grace period, CRC failures during channel estimation convergence will trigger the accumulation of the consecutive failure counter 103, which may misjudge the system as lost lock and cause it to fall back to the capture state before the system reaches a steady state, resulting in a vicious cycle of experiencing a 6.4-second grace period after each recapture.

[0053] V. Implementation of the Asymmetric Threshold Update Step (S4)

[0054] After the grace period ends (i.e., the value of subframe counter 104 is greater than N=40), frame synchronization state machine 101 performs an asymmetric threshold update on the CRC check result:

[0055] When the CRC check passes, the frame synchronization state machine 101 immediately resets the consecutive failure counter 103 to zero (F←0). The technical basis for this is that a successful CRC-6 check means that the 48 bits of system information are completely correct (the probability of a false pass is only about 1 / 64, and it is further reduced after confirmation by spectrum mode voting), which is sufficient to prove that the current frame synchronization is still valid and the subframe timing boundary is still correct. Therefore, a single successful CRC check can eliminate all previously accumulated failure counts.

[0056] When the CRC check fails, the frame synchronization state machine 101 increments the consecutive failure counter 103 by 1 (F←F+1). Consecutive failures may be caused by the following reasons: instantaneous enhancement of FM co-channel interference, multipath fading leading to a decrease in signal-to-noise ratio, sampling clock drift causing timing offset to exceed the tolerance range, etc. A single CRC failure is insufficient to determine that frame synchronization has failed; multiple consecutive failures are required for confirmation.

[0057] The engineering rationale for this asymmetric design lies in the fact that in mobile receiving environments, channel fading is typically transient—the signal-to-noise ratio (SNR) recovers after the receiver passes through the fading region. If a symmetric threshold (i.e., requiring multiple successes to reset) is used, the failure counter will slowly climb and be difficult to recover during intermittent fading, ultimately leading to unnecessary reacquisition. The asymmetric threshold ensures that as soon as channel conditions recover to a level sufficient for successfully decoding an SI, the failure counter is immediately reset to zero, and the receiver continues to maintain tracking.

[0058] VI. Implementation of Threshold-Triggered Action Chain Step (S5)

[0059] When the value of the consecutive failure counter 103 reaches the consecutive failure threshold M, the frame synchronization state machine 101 determines that frame synchronization has truly failed and needs to be reacquired. In this embodiment, M is set to 20 times. Combined with the 160ms period of each subframe, a consecutive failure threshold M=20 means that all SI decoding failures must occur for 3.2 consecutive seconds after the forgiveness period before triggering state backoff. Adding the 6.4 seconds of the forgiveness period N=40, at least 9.6 seconds of unsuccessful decoding is required from entering the tracking state to triggering backoff. In a normal FM co-channel broadcast environment, the probability of channel fading lasting longer than 9.6 seconds is extremely low; therefore, M=20 can effectively distinguish between short-term fading and true frame synchronization failure.

[0060] Upon triggering, frame synchronization state machine 101 executes the following four-step action chain in sequence:

[0061] The first step is to clear all sampled data in the accumulation buffer 102. The accumulation buffer 102 may contain a large amount of IQ data acquired during the unlocked state, and the timing boundaries of this data are unreliable. If it is not cleared and the system directly enters the capture state, the beacon detector 107 may detect false beacons at incorrect locations, leading to capture failure or incorrect locking.

[0062] The second step is to reset the subframe timing boundary to zero. The subframe timing boundary is a pointer used by the frame synchronization state machine 101 to mark the start position of the next subframe in the accumulation buffer 102. In the unlocked state, this pointer no longer points to the correct subframe boundary and must be reset to ensure that the search starts from the beginning when recaptured.

[0063] The third step is to clear both the continuous failure counter 103 and the subframe counter 104 to prepare for the next round of tracking.

[0064] The fourth step is to roll back the state of frame synchronization state machine 101 from the tracking state to the capture state.

[0065] In addition, during the execution of the above four-step action chain, the frame synchronization state machine 101 also synchronously executes: clearing the phase accumulator 110 to eliminate the failed frequency offset compensation accumulated phase; and clearing the timing error accumulator 111 to eliminate the failed sampling timing error accumulated amount. This ensures that the old physical layer accumulated state will not affect the re-acquisition.

[0066] VII. Implementation of the sampling-level timing fine-tuning step (S6)

[0067] like Figure 4 As shown, the timing fine-tuning unit 106 operates continuously during the tracking state to compensate for the small sampling clock frequency difference between the receiver oscillator and the transmitter oscillator.

[0068] The timing error estimation is implemented as follows: Every two subframes (i.e., 320ms intervals), the timing fine-tuning unit 106 performs timing error estimation on the OFDM data symbol region of the current subframe. First, the first eight OFDM symbol data after the beacon are taken and filtered by an FM bandpass filter (preserving the digital subband signal from ±100kHz to 250kHz and suppressing center FM interference). Then, cyclic prefix correlation is performed on each filtered OFDM symbol: the conjugate of the cyclic prefix region (length L=240 samples) is multiplied and accumulated sample by sample with the tail of the corresponding OFDM symbol body (offset N=2048 samples), and scanned within a search range of ±8 samples before and after the subframe timing boundary to obtain the accumulated correlation values ​​of the eight symbols.

[0069] The peak position of the cumulative correlation amplitude is taken as the integer sample estimate of the timing error. To obtain subsampling accuracy, a quadratic interpolation refinement is performed on the peak and its two adjacent points: let the correlation amplitude at the peak position be y0, the previous point be y₋1, and the next point be y₊1, then the refined offset is (y₋1 - y₊1) / (2·(2y0 - y₋1 - y₊1)). When the absolute value of the timing error estimate is less than 5.0 samples (i.e., the estimation result is reliable), this value is multiplied by a weighting coefficient of 0.25 and accumulated to the timing error accumulator 111. The weighting coefficient of 0.25 acts as a low-pass filter to suppress noise fluctuations in a single estimate.

[0070] When the absolute value of the accumulated value of the timing error accumulator 111 exceeds the correction threshold of 1.0 sample, an integer sample correction is applied to the subframe timing boundary. The correction amount is the integer part of the accumulated value (truncated to zero), and the corrected amount is subtracted from the accumulated value after correction. The correction amount is limited to within ±8 samples to prevent abnormally large correction values ​​from causing the cyclic prefix protection interval to fail—in this embodiment, the cyclic prefix length is 240 samples, and the ±8 sample correction amount is much smaller than the cyclic prefix length, ensuring that the corrected timing position is still within the effective protection range of the cyclic prefix.

[0071] VIII. Implementation of Frequency Offset Tracking Dual-Loop

[0072] During the tracking state, the frame synchronization module also performs a frequency offset tracking dual-loop to compensate for receiver local oscillator drift and Doppler frequency shift:

[0073] The first loop is the beacon half-body correlation loop. Each subframe's beacon consists of two repeating half-bodies (each half-body is Nb samples long). The timing fine-tuning unit 106 calculates the correlation value between the conjugate of the second half and the first half, and extracts the residual frequency offset estimate from the phase angle of the correlation value. This residual frequency offset updates the total frequency offset estimate with a step size coefficient α1 = 0.15. The update condition for this loop is that the beacon correlation amplitude is greater than 0.1, ensuring that the frequency offset is updated only when the beacon quality is reliable.

[0074] The second loop is the Common Phase Error (CPE) feedback loop. After performing channel estimation on the OFDM symbols, the channel estimator 109 outputs a common phase error estimate (the average phase residual of all data subcarriers). This CPE feedback value updates the total frequency offset estimate with a step size α2 = 0.05, but a 0.5Hz dead zone is set: if the absolute value of the frequency offset correction corresponding to the CPE is less than 0.5Hz, no update is performed. The dead zone design prevents oscillation between the CPE loop and the beacon loop—both loops simultaneously correct the same frequency offset estimate; without a dead zone, small estimation noise would be amplified back and forth between the two loops.

[0075] The setting of α1=0.15 > α2=0.05 reflects the division of labor between the two loops: the frequency offset estimation provided by the beacon half-body correlation has a high signal-to-noise ratio and is updated once per subframe, which is suitable for fast tracking with a larger step size; the CPE feedback is based on the statistics of all data subcarriers, which is greatly affected by data modulation, and uses a smaller step size for fine correction.

[0076] IX. Specific Parameter Values ​​and Engineering Basis

[0077] The values ​​of each parameter in this embodiment and their engineering basis are summarized as follows:

[0078] parameter symbol Value Engineering basis Forgiveness period threshold N 40 subframes (6.4 seconds) Channel estimation convergence requires 30-50 subframes. consecutive failure threshold M 20 times The probability of FM decay lasting longer than 3.2 seconds is extremely low. Maximum correction K ±8 samples Much smaller than the CP length of 240, ensuring effective CP protection. Correction threshold — 1.0 sample To prevent small biases from triggering spurious corrections during frequency offset correction Weighting coefficients — 0.25 Low-pass filtering suppresses single-shot estimation noise Timed estimation interval Q 2 subframes (320ms) Reduce computational load while tracking slow drift CP related symbol count P 8 OFDM symbols Multi-symbol accumulation improves the estimated signal-to-noise ratio Search scope R ±8 samples Covering the normal sampling clock deviation range beacon loop step size <![CDATA[α1]]> 0.15 High signal-to-noise ratio for beacon correlation, enabling fast tracking. CPE loop step size <![CDATA[α2]]> 0.05 Data modulation has a significant impact; conservative updates are recommended. CPE dead zone D 0.5 Hz Preventing dual-loop oscillation Number of vote confirmations L 3 times The CRC false positive rate has been reduced to approximately (1 / 64)³

Claims

1. An OFDM frame synchronization control method based on system information CRC cross-layer feedback, applied to an OFDM digital broadcast receiver including a physical layer frame synchronization module and a system information decoding module, characterized in that, Includes the following steps: S1 Acquisition Step: In the acquisition state, the frame synchronization module performs beacon detection on the received IQ sampled data to obtain the subframe timing boundary and carrier frequency offset estimate. After successful beacon detection, the continuous failure counter F is initialized to zero, the subframe counter C is initialized to zero, and the frame synchronization state machine of the frame synchronization module is switched to the tracking state. S2 Tracking Decoding Steps: In the tracking state, the frame synchronization module cuts subframe data from the accumulation buffer according to the subframe timing boundary, and performs frequency offset compensation and OFDM demodulation on the subframe data; The system information decoding module extracts system information from the equalized subcarrier data, performs CRC check on the data bits of the system information after convolutional decoding, and obtains the CRC check result. S3 Forgiveness Period Judgment Step: After each subframe is processed, the subframe counter C is incremented by 1; if the CRC check result is a failure and the subframe counter C does not exceed the preset forgiveness period threshold N, the tracking state is maintained and the continuous failure counter F is not updated; S4 Asymmetric threshold update step: If the CRC check result is passed, the continuous failure counter F is immediately cleared to zero; If the CRC check result is a failure and the subframe counter C exceeds the forgiveness period threshold N, then the consecutive failure counter F is incremented by 1. S5 Threshold Triggered Action Chain Steps: If the continuous failure counter F reaches the preset continuous failure threshold M, the following action chain is executed in sequence: clear all sampled data in the accumulation buffer; reset the subframe timing boundary to zero; clear both the continuous failure counter F and the subframe counter C to zero; and revert the frame synchronization state machine to the capture state. S6 Sampling-level timing fine-tuning step: During the tracking state, the sampling timing error is estimated by using the correlation between the cyclic prefix of the OFDM symbol and the tail of the symbol body. The sampling timing error is smoothed by weighted coefficients and accumulated to a timing error accumulator. When the absolute value of the accumulated value of the timing error accumulator exceeds a preset correction threshold, an integer sample correction is applied to the timing boundary of the subframe, and the correction amount is limited to within a preset maximum correction amount ± K samples.

2. The method according to claim 1, characterized in that, The preset forgiveness period threshold N is 30 to 60 subframes.

3. The method according to claim 1, characterized in that, The preset consecutive failure threshold M is between 10 and 30 times.

4. The method according to claim 1, characterized in that, In the S6 sampling level timing fine-tuning step: Perform cyclic prefix correlation on the first P OFDM symbols in the subframe data after FM bandpass filtering, with a search range of ±R samples before and after the timing boundary of the subframe. The peak position of the result of the cyclic prefix correlation operation after multi-symbol accumulation is obtained, and the timing error estimate of subsampling precision is obtained by second interpolation refinement. The timing error estimation is performed once every Q subframes.

5. The method according to claim 1, characterized in that, The tracking state also executes a frequency offset tracking dual-loop circuit, including: Beacon half-body correlation loop: The residual frequency offset is estimated by using the correlation phase difference between the first half and the second half of the beacon in the subframe, and the total frequency offset estimate is updated with the first step long coefficient α1; Common phase error feedback loop: The total frequency offset estimate is updated using the common phase error estimate output by the channel estimator with a second step size coefficient α2, and the common phase error is not updated when its absolute value is less than a preset dead zone threshold D; Wherein, the first step length coefficient α1 is greater than the second step length coefficient α2.

6. The method according to claim 1, characterized in that, In the S5 threshold trigger action chain step, the following operations are also performed simultaneously: clearing the phase accumulator for frequency offset compensation to zero; clearing the timing error accumulator to zero.

7. The method according to claim 1, characterized in that, In the S2 tracking decoding step, the system information decoding module adopts a multi-level backoff decoding strategy, attempting the following sequentially: Level 1: Perform symbol-by-symbol phase alignment and then merge decoding on the four copies of the system information; Level 2: Directly merge and decode the four copies; Level 3: Merge and decode the two copies of the lower half subband; Level 4: Merge and decode the two copies of the upper half subband; Level 5: Back-down decoding of a single copy of the lower half subband; Four 90-degree phase rotation candidates are tried in each stage of decoding, and after the CRC check passes, the spectrum mode is confirmed by voting. Only after obtaining the same spectrum mode index after L consecutive decodings is it considered valid, in order to filter out CRC false positives.

8. An OFDM frame synchronization control system based on system information CRC cross-layer feedback, applied to an OFDM digital broadcast receiver, characterized in that, include: The frame synchronization module is configured with a frame synchronization state machine, which has a capture state and a tracking state. The frame synchronization module includes a beacon detector, an accumulation buffer, a continuous failure counter, a subframe counter, and a timing fine-tuning unit. An OFDM demodulator is used to perform decyclic prefix and FFT operations on subframe data; A channel estimator is used to perform channel estimation and equalization on frequency domain data using pilot subcarriers; The system information decoding module is used to extract system information from the equalized subcarrier data output by the channel estimator and perform CRC check, and feed back the CRC check result to the frame synchronization module; In the capture state, the frame synchronization module performs beacon detection on the IQ sampled data through the beacon detector. After successful detection, the continuous failure counter and the subframe counter are initialized to zero, and the frame synchronization state machine is switched to the tracking state. In the tracking state, the frame synchronization module cuts subframe data from the accumulation buffer according to the subframe timing boundary, outputs it to the OFDM demodulator after frequency offset compensation, and the output of the OFDM demodulator is equalized by the channel estimator and sent to the system information decoding module; the system information decoding module performs CRC check and returns the CRC check result to the frame synchronization module; after each subframe processing is completed, the frame synchronization module increments the subframe counter by 1; When the CRC check fails and the value of the subframe counter does not exceed the preset forgiveness period threshold N, the frame synchronization module maintains the tracking state and does not update the continuous failure counter; when the CRC check passes, the frame synchronization module immediately clears the continuous failure counter to zero; when the CRC check fails and the value of the subframe counter exceeds the forgiveness period threshold N, the frame synchronization module increments the continuous failure counter. When the continuous failure counter reaches the preset continuous failure threshold M, the frame synchronization module clears the accumulation buffer, resets the subframe timing boundary to zero, clears both the continuous failure counter and the subframe counter to zero, and rolls back the frame synchronization state machine to the capture state. During the tracking state, the timing fine-tuning unit estimates and accumulates the sampling timing error using cyclic prefix correlation. When the absolute value of the accumulated value exceeds a preset correction threshold, it applies an amplitude-limited integer sampling correction to the subframe timing boundary.

9. The system according to claim 8, characterized in that, The frame synchronization module also includes a phase accumulator and a timing error accumulator; when the continuous failure counter reaches the preset continuous failure threshold M and the frame synchronization state machine reverts from the tracking state to the capture state, the frame synchronization module synchronously clears the phase accumulator and the timing error accumulator to zero.

10. The system according to claim 8, characterized in that, The system information decoding module includes a multi-level backoff decoding unit and a spectrum mode voting confirmation unit. The multi-level backoff decoding unit attempts to decode sequentially according to the priority of four-replica phase alignment merging, four-replica direct merging, dual-replica merging, and single-replica backoff. The spectrum mode voting confirmation unit checks the continuity and consistency of the spectrum mode index after the CRC check passes, and outputs a valid confirmation signal after L consecutive consistency.

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