Flash memory and forming method thereof
By first forming the first sidewall in the flash memory, and then etching grooves and forming metal silicide between adjacent gate structures, the problem of reduced erase current caused by sidewall parasitic resistance is solved, programming interference is improved and the current performance of the memory is maintained.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-02-27
- Publication Date
- 2026-05-19
AI Technical Summary
The parasitic resistance of the sidewalls of flash memory reduces the erase current of the flash memory, leading to programming interference problems.
In the formation of flash memory, a first sidewall is first formed, and then a groove is etched in the substrate between adjacent first gate structures in the device region. The sidewalls and bottom walls of the groove expose the substrate material, and metal silicide is formed at the bottom and sidewalls of the groove to optimize the sidewall resistance.
It improves the programming interference of flash memory without affecting the current performance of the memory.
Smart Images
Figure CN122069723A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a flash memory and a method for forming the same. Background Technology
[0002] Nord flash memory devices, with their advantages of low cost, low power consumption, and fast access speed, have occupied an increasingly important position in the field of non-volatile memory.
[0003] As NORD flash memory cells continue to shrink, the distance between adjacent floating gates becomes increasingly shorter, making crosstalk a critical issue affecting the reliability of NORD flash. During testing, a new crosstalk mode was discovered: when programming a selected row, the row closest to it experiences more severe crosstalk than other rows.
[0004] To improve the programming disturbance of adjacent rows in NORD Flash (non-volatile flash memory technology), a Flash silicon trench etching scheme was proposed. Experimental results have proven its effectiveness. However, due to the parasitic resistance of the trench sidewalls, it also reduces the erase ("1") current of the flash memory. Summary of the Invention
[0005] The purpose of this invention is to provide a flash memory and a method for forming the same, so as to solve the problem that the parasitic resistance of the sidewalls of the flash memory reduces the erase current of the flash memory.
[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a flash memory, comprising:
[0007] A substrate is provided, the substrate including a device region and a peripheral circuit region, a plurality of first gate structures are formed on the device region, and a plurality of second gate structures are formed on the peripheral circuit region;
[0008] A first sidewall and a second sidewall are formed. The first sidewall is located in the device region and covers the sidewall of the first gate structure and the substrate of the device region. The second sidewall is located in the peripheral circuit region and covers the sidewall of the second gate structure and the substrate of the peripheral circuit region. A portion of the substrate of the peripheral circuit region is exposed between adjacent second sidewalls.
[0009] A groove is formed, the groove being located within the substrate between adjacent first gate structures in the device region, and the sidewalls and bottom wall of the groove are exposed substrate material;
[0010] Metal silicides are formed at the bottom and sidewalls of the groove and on the substrate exposed in the peripheral circuit area.
[0011] Optionally, both the first sidewall and the second sidewall have an ONO structure. The first sidewall includes a first oxide layer, a first silicon nitride layer, and a second oxide layer, and the second sidewall includes a third oxide layer, a second silicon nitride layer, and a fourth oxide layer.
[0012] Optionally, the step of forming the groove includes:
[0013] Remove the second oxide layer in the first sidewall of the device area and the fourth oxide layer in the second sidewall of the peripheral circuit area;
[0014] The peripheral circuit area is shielded, the first sidewall on the substrate of the device area is etched, and a portion of the substrate thickness is etched to form a groove, the sidewalls and bottom wall of the groove exposing the substrate material.
[0015] Optionally, the depth of the groove is 180 angstroms to 220 angstroms.
[0016] Optionally, after the groove is formed, the first sidewall is in the shape of a vertical strip.
[0017] Optionally, after the groove is formed, the second sidewall is L-shaped.
[0018] Optionally, the first gate structure includes a floating gate, an inter-gate dielectric layer, a control gate, and a word line.
[0019] Optionally, in the step of forming the metal silicide, the top surface of the word line is formed with a metal silicide.
[0020] Optionally, in the step of forming the metal silicide, a metal silicide is formed on the top surface of the second gate structure.
[0021] Based on the same inventive concept, the present invention also provides a flash memory, which is prepared by any of the flash memory forming methods described above.
[0022] In the flash memory and its formation method provided by the present invention, a substrate is provided, the substrate including a device region and a peripheral circuit region, a plurality of first gate structures are formed on the device region, and a plurality of second gate structures are formed on the peripheral circuit region; a first sidewall and a second sidewall are formed, the first sidewall being located in the device region and covering the sidewalls of the first gate structures and the substrate of the device region, the second sidewall being located in the peripheral circuit region and covering the sidewalls of the second gate structures and the substrate of the peripheral circuit region, with a portion of the substrate of the peripheral circuit region exposed between adjacent second sidewalls; a groove is formed, the groove being located in the substrate between adjacent first gate structures in the device region, the sidewalls and bottom wall of the groove exposing substrate material; a metal silicide is formed, the metal silicide being located at the bottom and sidewalls of the groove and on the substrate exposed in the peripheral circuit region. The present invention improves programming crosstalk between adjacent rows of co-located contact holes by first forming the first sidewall in the device region and then forming the groove in the substrate between adjacent first gate structures, ensuring that the source / drain region is lower than the channel surface. Furthermore, the sidewalls and bottomwalls of the groove expose the substrate material. During the formation of metal silicide, metal silicide is formed on the bottom and sidewalls of the groove, which optimizes the sidewall resistance of the groove and improves programming interference without affecting the current of the flash memory. Attached Figure Description
[0023] Figure 1 This is a flowchart of a method for forming a flash memory according to an embodiment of the present invention.
[0024] Figures 2 to 11 This is a schematic diagram of the structure corresponding to the steps of the flash memory formation method according to an embodiment of the present invention.
[0025] In the picture,
[0026] 10a - Device area; 10b - Peripheral circuit area; 11 - First gate structure; 11a - Word line; 11b - Isolation layer; 11c - Floating gate; 11d - Control gate; 11e - Word line metal silicide; 12 - Second gate structure; 12a - Second gate material layer; 12b - Second gate metal silicide; 13 - First sidewall; 13a - First oxide layer; 13b - First silicon nitride layer; 13c - Second oxide layer; 14 - Second sidewall; 14a - Third oxide layer; 14b - Second silicon nitride layer; 14c - Fourth oxide layer; 15 - Trench; 15a - Trench metal silicide; 20 - First photomask. Detailed Implementation
[0027] The flash memory and its formation method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, only for the purpose of conveniently and clearly illustrating the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different proportions may be used in different drawings to illustrate different aspects.
[0028] Figure 1 This is a flowchart illustrating a method for forming a flash memory according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a flash memory, including:
[0029] Step S10: Provide a substrate, the substrate including a device region and a peripheral circuit region, a plurality of first gate structures are formed on the device region, and a plurality of second gate structures are formed on the peripheral circuit region;
[0030] Step S20: Form a first sidewall and a second sidewall. The first sidewall is located in the device region and covers the sidewall of the first gate structure and the substrate of the device region. The second sidewall is located in the peripheral circuit region and covers the sidewall of the second gate structure and the substrate of the peripheral circuit region. A portion of the substrate of the peripheral circuit region is exposed between adjacent second sidewalls.
[0031] Step S30: Forming a groove, the groove being located in the substrate between adjacent first gate structures in the device region, the sidewalls and bottom wall of the groove exposing the substrate material;
[0032] Step S40: Forming a metal silicide located at the bottom and sidewalls of the groove and on the substrate exposed in the peripheral circuit area.
[0033] Figures 2 to 11 This is a schematic diagram showing the structural steps corresponding to the method for forming a flash memory according to an embodiment of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 2 to 11 Specific embodiments of the present invention will be described in detail below.
[0034] like Figure 2As shown, a substrate is provided, which serves as an operating platform for subsequent processes. It can be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components, such as a bare die or a wafer processed by epitaxial growth. Specifically, the substrate may be, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the substrate is a silicon substrate. The substrate includes a device region 10a and a peripheral circuit region 10b.
[0035] Please continue to refer to this. Figure 2 A gate stack and a word line 11a located between the gate stacks are formed on the device region 10a. The gate stack includes a floating gate material layer, an inter-gate dielectric layer and a control gate material layer from bottom to top. The sidewalls of the word line are formed with word line sidewalls.
[0036] like Figure 3 As shown, a second gate material layer 12a is formed on the peripheral circuit region 10b. The material of the second gate material layer 12a is, for example, polysilicon, which can be formed using a chemical vapor deposition process. Figure 4 As shown, a first etching process is performed to etch a portion of the second gate material layer 12a, and the remaining portion of the second gate material layer 12a constitutes the second gate structure 12.
[0037] like Figure 5 As shown, a second etching process is performed to sequentially etch the control gate material layer, the inter-gate dielectric layer, and the floating gate material layer to form multiple first gate structures 11. The first gate structure 11 includes a floating gate 11c, a control gate 11d, a word line 11a, and an isolation layer 11b.
[0038] like Figure 6 and Figure 7 As shown, a first sidewall 13 and a second sidewall 14 are formed. The first sidewall 13 is located in the device region 10a and covers the sidewall of the first gate structure 11 and the substrate of the device region 10a. The second sidewall 14 is located in the peripheral circuit region 10b and covers the sidewall of the second gate structure 12 and the substrate of the peripheral circuit region 10b. The substrate of the peripheral circuit region 10b is exposed between adjacent second sidewalls 14. Both the first sidewall 13 and the second sidewall 14 are ONO structures. Figure 6 As shown, the first sidewall 13 includes a first oxide layer 13a, a first silicon nitride layer 13b, and a second oxide layer 13c. Figure 7As shown, the second sidewall 14 includes a third oxide layer 14a, a second silicon nitride layer 14b, and a fourth oxide layer 14c. The thicknesses of the first oxide layer 13a and the third oxide layer 14a range from 80 angstroms to 120 angstroms, for example, 100 angstroms. The thicknesses of the first silicon nitride layer 13b and the second silicon nitride layer 14b range from 180 angstroms to 220 angstroms, for example, 200 angstroms. The thicknesses of the second oxide layer 13c and the fourth oxide layer 14c range from 650 angstroms to 700 angstroms, for example, 670 angstroms. Due to the large gaps between adjacent second gate structures 14 on the peripheral circuit region 10b, the substrate of the peripheral circuit region 10b between adjacent second sidewalls 14 is exposed during sidewall etching. In contrast, the spacing between adjacent first gate structures 11 on the device region 10a is small, and a portion of the thickness of the second oxide layer 13c is etched during sidewall etching.
[0039] like Figure 8 and Figure 9 As shown, a recess 15 is formed within the substrate of the device region 10a adjacent to the first gate structure 11, and the sidewalls and bottom wall of the recess 15 expose the substrate material, i.e., the sidewalls and bottom wall of the recess 15 expose silicon. The depth of the recess 15 ranges from 180 angstroms to 220 angstroms, for example, 200 angstroms. Before forming the recess 15, the second oxide layer 13c on the device region 10a and the fourth oxide layer 14c on the peripheral circuit region 10b are removed. The second oxide layer 13c and the fourth oxide layer 14c are removed using a wet etching process, such as hydrofluoric acid. At this time, the first sidewall 13 is vertically shaped. The second sidewall 14 is L-shaped. Next, the first silicon nitride layer 13b and the first oxide layer 13a on device region 10a are etched using an etching process, and a portion of the substrate material is further etched to form a groove 15. The sidewalls and bottom wall of the groove 15 expose the substrate material. The groove 15 ensures that the source / drain regions are below the channel surface, improving programming crosstalk between adjacent rows of co-located contact holes. The etching process, for example, is a dry etching process. Figure 9 As shown, when a groove 15 is formed on the substrate of the etched device region 10a, the peripheral circuit region 10b is shielded by a first mask 20.
[0040] like Figure 10 and Figure 11 As shown, a metal silicide is formed on the bottom and sidewalls of the recess 15 and on the substrate exposed in the peripheral circuit region 10b. The recess 15 ensures that the source / drain regions are below the channel surface, improving programming crosstalk between adjacent rows of co-located contact holes. Prior to the metal silicide formation step, the isolation layer 11b on top of the word line 11a is etched to expose the top surface of the word line 11a. A metal layer is deposited and annealed to form the metal silicide on the exposed silicon surface. Figure 10As shown, metal silicides, i.e., groove metal silicides 15a, are formed on both the sidewalls and the bottom of the groove 15. In the prior art, the groove is formed first, and then the sidewalls are formed. The sidewalls of the groove are covered by the sidewalls. When forming metal silicides, metal silicides can only be formed at the bottom part of the groove, resulting in parasitic resistance on the sidewalls of the groove, which in turn reduces the erase ("1") current of the flash memory. In this embodiment, the first sidewall is formed first, and then the substrate of the device area is etched to form the groove. The sidewalls of the groove expose silicon. When forming metal silicides, metal silicides are formed not only at the bottom of the groove, but also on the sidewalls of the groove. That is, the programming interference of the flash memory is improved without affecting the current of the flash memory.
[0041] Please continue to refer to this. Figure 10 Metal silicides are also formed at the top of the word lines, namely word line metal silicides 11e, to facilitate the subsequent extraction of word lines 11a.
[0042] Please continue to refer to this. Figure 11 Metal silicide is also formed on the top of the second gate structure 12, namely the second gate metal silicide 12b, to facilitate the subsequent extraction of the second gate structure.
[0043] Please continue to refer to this. Figure 10 and Figure 11 This embodiment also provides a flash memory, fabricated using the flash memory formation method described in any one of the above embodiments, comprising:
[0044] The substrate includes a device region 10a and a peripheral circuit region 10b;
[0045] A first gate structure 11 is located on the device region 10a. The first gate structure 11 includes a floating gate, an inter-gate dielectric layer, a control gate, a word line 11a, and a word line metal silicide 11e.
[0046] The second gate structure 12 is located on the peripheral circuit region 10b;
[0047] The first sidewall 13 is located in the device region 10a and covers the sidewall of the first gate structure 11. The first sidewall 13 is in the shape of a vertical strip.
[0048] The second sidewall 14 is located in the peripheral circuit area 10b and covers the sidewall of the second gate structure 12. The second sidewall 14 is L-shaped.
[0049] The groove metal silicide 15a is located in the substrate between the first gate structure 11 in the device region 10a.
[0050] The second gate metal silicide 12b is located on top of the second gate structure 12.
[0051] The metal silicide is also located in the substrate between the peripheral circuit region 10b and the adjacent second gate structure 12.
[0052] In summary, the flash memory and its formation method provided in this embodiment of the invention include a substrate comprising a device region and a peripheral circuit region. A plurality of first gate structures are formed on the device region, and a plurality of second gate structures are formed on the peripheral circuit region. First sidewalls and second sidewalls are formed. The first sidewalls are located in the device region and cover the sidewalls of the first gate structures and the substrate of the device region. The second sidewalls are located in the peripheral circuit region and cover the sidewalls of the second gate structures and the substrate of the peripheral circuit region. A portion of the substrate of the peripheral circuit region is exposed between adjacent second sidewalls. A groove is formed within the substrate between adjacent first gate structures in the device region. The sidewalls and bottom wall of the groove expose substrate material. A metal silicide is formed at the bottom and sidewalls of the groove and on the exposed substrate of the peripheral circuit region. This invention improves programming crosstalk between adjacent rows of co-located contact holes by first forming first sidewalls in the device region and then forming grooves within the substrate between adjacent first gate structures. The grooves ensure that the source / drain regions are below the channel surface. Furthermore, in this embodiment, the sidewalls and bottom walls of the groove are exposed with substrate material. When forming metal silicide, metal silicide is formed on the bottom and sidewalls of the groove, which optimizes the sidewall resistance of the groove and improves programming interference without affecting the current of the flash memory.
[0053] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.
[0054] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for forming a flash memory, characterized in that, include: A substrate is provided, the substrate including a device region and a peripheral circuit region, a plurality of first gate structures are formed on the device region, and a plurality of second gate structures are formed on the peripheral circuit region; A first sidewall and a second sidewall are formed. The first sidewall is located in the device region and covers the sidewall of the first gate structure and the substrate of the device region. The second sidewall is located in the peripheral circuit region and covers the sidewall of the second gate structure and the substrate of the peripheral circuit region. A portion of the substrate of the peripheral circuit region is exposed between adjacent second sidewalls. A groove is formed, the groove being located within the substrate between adjacent first gate structures in the device region, and the sidewalls and bottom wall of the groove are exposed substrate material; Metal silicides are formed at the bottom and sidewalls of the groove and on the substrate exposed in the peripheral circuit area.
2. The method for forming a flash memory as described in claim 1, characterized in that, Both the first sidewall and the second sidewall have an ONO structure. The first sidewall includes a first oxide layer, a first silicon nitride layer, and a second oxide layer. The second sidewall includes a third oxide layer, a second silicon nitride layer, and a fourth oxide layer.
3. The method for forming a flash memory as described in claim 2, characterized in that, The steps for forming the groove include: Remove the second oxide layer in the first sidewall of the device area and the fourth oxide layer in the second sidewall of the peripheral circuit area; The peripheral circuit area is shielded, the first sidewall on the substrate of the device area is etched, and a portion of the substrate thickness is etched to form a groove, the sidewalls and bottom wall of the groove exposing the substrate material.
4. The method for forming a flash memory as described in claim 3, characterized in that, The depth of the groove is 180 angstroms to 220 angstroms.
5. The method for forming a flash memory as described in claim 3, characterized in that, After the groove is formed, the first sidewall becomes a vertical strip.
6. The method for forming a flash memory as described in claim 1, characterized in that, After the groove is formed, the second sidewall is L-shaped.
7. The method for forming a flash memory as described in claim 1, characterized in that, The first gate structure includes a floating gate, an inter-gate dielectric layer, a control gate, and a word line.
8. The method for forming a flash memory as described in claim 7, characterized in that, In the step of forming the metal silicide, a word line metal silicide is formed on the top surface of the word line.
9. The method for forming a flash memory as described in claim 1, characterized in that, In the step of forming the metal silicide, a second gate metal silicide is formed on the top surface of the second gate structure.
10. A flash memory, characterized in that, It is prepared using the flash memory formation method as described in any one of claims 1 to 9.