Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a method of manufacturing the same, the semiconductor device including a plurality of memory cells, each memory cell including: a first electrode layer; a memory layer; and a selector layer for selecting the memory layer, the selector layer being formed on an upper or lower portion of the memory layer and over the first electrode layer, in which the selector layer includes a dielectric material layer doped with a first dopant, and in which the first dopant is doped with a second dopant. A dopant concentration of a lower region of the dielectric material layer of the selector layer adjacent to the first electrode layer is lower than a dopant concentration of an upper region of the dielectric material layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0164786, filed on November 19, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to semiconductor technology, and more specifically to a semiconductor device including a memory cell with a selector, and a method of manufacturing the semiconductor device. Background Technology

[0004] In recent years, to address the trends of miniaturization, low power consumption, high performance, and diversification in electronic devices, there has been a demand for semiconductor devices capable of storing data in various electronic devices, such as computers and portable communication devices. Researchers and industry are actively researching and developing such semiconductor devices. Semiconductor devices include those that can store data by utilizing the characteristic of switching between different resistance states according to the applied voltage or current, such as resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electric fuses.

[0005] Additionally, memory devices with variable resistance elements may include selectors as elements for selecting a specific memory cell from a plurality of memory cells in an array, and the selector may be implemented as a thin layer in the memory cell. Summary of the Invention

[0006] This disclosure relates to a semiconductor device that prevents damage to the interface between the selector layer and the lower electrode layer during the formation of the selector layer of a memory cell, and a method for manufacturing the semiconductor device.

[0007] According to one embodiment of the present disclosure, a semiconductor device includes: a plurality of memory cells, each memory cell including a first electrode layer; a memory layer; and a selector layer, the selector layer being adapted to select the memory layer, the selector layer being formed above or below the memory layer and above the first electrode layer, wherein the selector layer includes a dielectric material layer doped with a first dopant, and wherein the dopant concentration in the lower region of the dielectric material layer of the selector layer adjacent to the first electrode layer is lower than the dopant concentration in the upper region of the dielectric material layer.

[0008] According to another embodiment of this disclosure, a method for manufacturing a semiconductor device is provided, the semiconductor device including a selector layer in a memory cell for controlling electrical access to one of a plurality of arrayed memory cells, the method comprising: forming a first electrode layer on a substrate; forming a dielectric material layer for a selector on the first electrode layer; and forming the selector layer by performing multiple dopant implantation processes on the dielectric material layer using different ion implantation energies, wherein the dopant concentration in a lower region of the dielectric material layer adjacent to the first electrode layer is lower than the dopant concentration in an upper region thereof.

[0009] These and other features and advantages of this disclosure will become clearer from the description of embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0010] Figure 1 This is a perspective view showing a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2 It shows in detail the basis Figure 1 A cross-sectional view of the structure of the selector unit in an embodiment.

[0012] Figure 3 It shows Figure 2 The operation of the selector unit shown.

[0013] Figures 4A to 4D This is a cross-sectional view showing a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure.

[0014] Figures 5A to 5D This is a cross-sectional view showing a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure. Detailed Implementation

[0015] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, these embodiments may be embodied in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure more comprehensive and to fully convey the scope of the disclosure to those skilled in the art. In the various drawings and embodiments of this disclosure, the same reference numerals denote the same parts.

[0016] Different embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0017] The accompanying drawings are not necessarily drawn to scale, and in some cases the scale may be exaggerated in order to clearly illustrate the features of the embodiments. When referring to the first layer as being "on" the second layer or "on" the substrate, it means not only that the first layer is formed directly on the second layer or the substrate, but also that there is a third layer between the first layer and the second layer or the substrate.

[0018] Figure 1 This is a perspective view showing a semiconductor device according to an embodiment of the present disclosure.

[0019] refer to Figure 1 The semiconductor device may include a substrate 100 and a plurality of first interconnects 110 disposed on the substrate 100. Each first interconnect 110 extends along a first direction. In one embodiment, the first interconnects 110 are spaced apart from each other at regular intervals along a second direction. The semiconductor device may also include a plurality of second interconnects 120, which are spaced apart from each other at regular intervals along the first direction and disposed on the first interconnects 110 and extend along the second direction. The second direction intersects the first direction. The semiconductor device also includes a plurality of memory cells MC, which are configured to overlap with the intersection regions between the first interconnects 110 and the second interconnects 120, respectively. In one embodiment, the plurality of memory cells MC are disposed between the first interconnects 110 and the second interconnects 120. Here, the first direction and the second direction may refer to directions substantially parallel to the surface of the substrate 100. Directions substantially perpendicular to the surface of the substrate 100 may be referred to hereinafter as vertical directions.

[0020] The substrate 100 may include a semiconductor material, such as silicon. Furthermore, a predetermined lower structure (not shown) may be formed in the substrate 100. For example, an integrated circuit for driving the first interconnect 110 and / or the second interconnect 120 may be formed in the substrate 100.

[0021] Multiple first interconnects 110 may be spaced apart from each other along a second direction. Each first interconnect 110 may contain a conductive material selected from, for example, metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), etc., metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), etc., and combinations thereof. Each first interconnect 110 may have a single-layer or multi-layer structure.

[0022] Multiple second interconnects 120 may be arranged at regular intervals along a first direction. The second interconnects 120 may contain a conductive material selected from, for example, metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), etc., metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), etc., and combinations thereof. The second interconnects 120 may have a single-layer or multi-layer structure. One of the first interconnects 110 and the second interconnects 120 may be used as a word line, and the other as a bit line. Although this embodiment of the present disclosure describes a single-layer crossover structure, two or more crossover structures may be stacked in the vertical direction.

[0023] Each memory cell may include a memory unit MU (which is the portion where the actual data is stored) and a selector unit SU (which controls access to the memory unit MU). For example, a memory cell MC may include a stacked structure of a lower electrode layer 130, a selector layer 140, an intermediate electrode layer 150, a variable resistor layer 160, and an upper electrode layer 170. The selector unit SU may include the lower electrode layer 130, the selector layer 140, and the intermediate electrode layer 150. The memory unit MU may include the intermediate electrode layer 150, the variable resistor layer 160, and the upper electrode layer 170. That is, the intermediate electrode layer 150 may be shared by the selector unit SU and the memory unit MU. Each memory cell MC may include a memory layer, which may be the variable resistor layer 160.

[0024] The lower electrode layer 130 and the upper electrode layer 170 can be disposed at both ends of the memory cell MC, i.e., at the bottom and top respectively, and can be used to transmit the voltage or current required for the operation of the memory cell MC. The intermediate electrode layer 150 can electrically connect the selector layer 140 and the variable resistor layer 160 to each other and physically isolate them from each other. The lower electrode layer 130, the intermediate electrode layer 150, or the upper electrode layer 170 can contain a variety of conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), etc., metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), etc., and combinations thereof. In addition, the lower electrode layer 130, the intermediate electrode layer 150, or the upper electrode layer 170 can include carbon electrodes. For example, the lower electrode layer 130 and the intermediate electrode layer 150 can include a TiN thin layer. The TiN thin layer used herein refers to a layer with a thickness of 5 nm to 100 nm, more specifically, a thickness of 5 nm to 50 nm.

[0025] Selector layer 140 serves to prevent current leakage between memory cells MC sharing the first interconnect 110 or the second interconnect 120 and to control access to variable resistor layer 160. To this end, selector layer 140 may have threshold switching characteristics: when the voltage level applied to the upper and lower ends of selector layer 140 is below a predetermined threshold voltage, current is blocked or almost stopped; then, when the voltage level applied to the upper and lower ends of selector layer 140 is equal to or higher than the threshold voltage, current is allowed to flow rapidly. Selector layer 140 can be turned on at voltage levels equal to or higher than the threshold voltage and turned off at voltage levels below the threshold voltage. For example, selector layer 140 may include a dielectric material implanted with dopants. Reference will be made below. Figure 2 and Figure 3The detailed description includes selector units SU of selector layer 140 and their operation. Each memory cell MC may include a thin carbon (C) layer located at the interface between selector layer 140 and intermediate electrode layer 160. As used herein, a thin carbon (C) layer refers to a layer with a thickness of 0.5 nm to 20 nm, or more specifically, 0.5 nm to 5 nm.

[0026] Figure 2 It shows in detail the basis Figure 1 A cross-sectional view of the structure of the selector unit SU in an embodiment.

[0027] refer to Figure 2 The selector unit SU may include a lower electrode layer 130, a selector layer 140, and an intermediate electrode layer 150.

[0028] As described above, the lower electrode layer 130 and the intermediate electrode layer 150 may comprise various conductive materials, such as metals, metal nitrides, etc. The lower electrode layer 130 and the intermediate electrode layer 150 may be formed of the same material, and therefore they may have the same work function. For example, the lower electrode layer 130 and the intermediate electrode layer 150 may comprise titanium nitride (TiN) with a work function of approximately 4.4 to 4.6 eV. In this document, the term "approximately" when referring to a numerical range means within ±5% of a given value. However, the concept and scope of this disclosure are not limited thereto, and the lower electrode layer 130 and the intermediate electrode layer 150 may be formed of different materials to have different work functions.

[0029] Selector layer 140 may include dielectric material layer 142 and dopant 144 implanted into dielectric material layer 142.

[0030] The dielectric layer 142 may include a dielectric material with a relatively wide band gap, for example, a dielectric material with a band gap of approximately 5.0 eV or greater. For example, the dielectric layer 142 may include a silicon-containing dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.), a dielectric metal oxide, a dielectric metal nitride, or a combination thereof. For example, an oxide layer such as silicon dioxide (SiO2) may be formed by mixing a source gas containing silicon (Si) and oxygen (O) using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The dielectric layer 142 may have deep traps whose energy levels are closer to the valence band level than the conduction band level of the dielectric layer 142. Dopant 144 may be used to create shallow traps, providing channels for conductive charge carriers (e.g., electrons or holes) to move within the dielectric layer 142. The energy levels of the shallow traps are closer to the conduction band level than the valence band level of the dielectric layer 142. The dopant incorporated into selector layer 140 may include n-type or p-type dopant, and may be implanted via ion implantation. For example, when dielectric layer 142 comprises silicon, dopant 144 may comprise a metal with a different valence state than silicon, such as gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), tungsten (W), and combinations thereof. Furthermore, when dielectric layer 142 comprises a metal, dopant 144 may comprise a metal with a different valence state than that metal (e.g., silicon). For example, dielectric layer 142 may comprise silicon oxide such as silicon dioxide (SiO2), and dopant 144 may comprise arsenic (As). Selector layer 140 may comprise arsenic (As)-doped silicon dioxide (SiO2).

[0031] The following is for reference. Figure 3 To describe the operation of the selector unit SU.

[0032] Figure 3 It shows Figure 2 The operation of the selector unit SU is shown.

[0033] refer to Figure 3 In the off state where no voltage is applied to the selector unit SU, conductive charge carriers (e.g., electrons "e") can be trapped in the deep trap T1 of the selector layer 140.

[0034] When a voltage equal to or higher than the threshold voltage is applied to the selector unit SU, which is in the off state, through the lower electrode layer 130 and the upper electrode layer 150, the selector unit SU can be turned on. Specifically, when a voltage equal to or higher than the threshold voltage is applied to the selector unit SU, the conductive carriers trapped in the deep trap T1 can jump to the shallow trap T2 through a thermoemission process or a tunneling process. The conductive carriers can move through the shallow trap T2 to establish a conductive path coupling the lower electrode layer 130 and the upper electrode layer 150.

[0035] When the voltage applied to the selector unit SU in the on state decreases, the number of conductive charge carriers moving from the deep trap T1 to the shallow trap T2 also decreases, allowing the selector unit SU to return to the off state.

[0036] In this way, the selector unit SU can be turned on and off.

[0037] Reference Figure 1 The variable resistance layer 160 can be a portion of the memory cell MC that stores data. For this purpose, the variable resistance layer 160 can have variable resistance characteristics: switching between different resistance states according to the applied voltage. The variable resistance layer 160 can have a single-layer or multi-layer structure, including various materials used in resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), etc., such as metal oxides like transition metal oxides, perovskite-based materials, phase-change materials like chalcogenide-based materials, ferroelectric materials, ferromagnetic materials, etc. For example, the variable resistance layer 160 can include a magnetic tunnel junction structure, which can store data by switching between different resistance states by changing the magnetization direction.

[0038] Figures 4A to 4D This is a cross-sectional view showing a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure.

[0039] First, the manufacturing method of semiconductor devices is described.

[0040] refer to Figure 4A A substrate 200 having a predetermined lower structure is provided. The substrate 200 may contain various desired circuits. The substrate 200 may contain... Figure 1 The first interconnect 110 is similar to the interconnect.

[0041] Subsequently, a lower electrode layer 210, a barrier layer 220, and a dielectric material layer 230 can be formed on the substrate 200. The lower electrode layer 210, barrier layer 220, and dielectric material layer 230 can be formed sequentially on the substrate 200 in the order described above. The lower electrode layer 210 can be formed on the substrate 200 by depositing a conductive material on the substrate 200. Then, the barrier layer 220 can be formed on the lower electrode layer 210. The barrier layer 220 can be disposed between the lower electrode layer 210 and the dielectric material layer 230. The barrier layer 220 prevents damage to the lower electrode layer 210 during the ion implantation process described below. The barrier layer 220 may include silicon nitride, carbon, or a transition metal oxide. The barrier layer 220 can be deposited on the lower electrode layer 210 using a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. Furthermore, the barrier layer 220 can be formed directly on the surface of the lower electrode layer 210 via a thermal oxidation process, or it can be formed by applying an oxidant to the surface of the lower electrode layer 210 to form an oxide layer. The dielectric material layer 230 can be formed using a mixed source gas through processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The thickness of the dielectric material layer 230 is approximately 50 to 150 Å.

[0042] refer to Figure 4B The initial selector layer 240 can be formed by depositing a dielectric material layer 230 on the barrier layer 220 and then implanting dopants into the dielectric material layer 230. Dopant implantation can be performed, for example, by an ion implantation process, and can be performed in a direction substantially perpendicular to the surface of the substrate 200 toward the dielectric material layer 230, such as... Figure 4B As indicated by arrow ①. The dopant implantation process can be referred to below as the first dopant implantation process.

[0043] The dopant implanted here can be at least one selected from nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), etc. In one embodiment, the dopant can be arsenic (As). The implanted dopant can be an important factor determining the electrical properties of the selector layer. The first dopant implantation process can be a low-energy ion implantation process, wherein the ion implantation energy is set within a specific range such that the ion implantation depth Rp is formed at a distance of approximately 30% to 50% of the entire thickness of the dielectric material layer from the lower surface of the dielectric material layer. The height L1 of the ion implantation depth Rp can correspond to a position at a distance of approximately 0.3 to 0.5 times the thickness of the entire dielectric material layer from the lower surface of the dielectric material layer 230. In one embodiment, the implantation energy can be set in the range of approximately 3 keV to 7 keV. When the implantation range is controlled within this range, the dopant can be properly diffused within the dielectric material layer 230 to minimize damage to the lower electrode layer 210 and the barrier layer 220, and to uniformly form the selector layer.

[0044] The first dopant implantation process can continue until the dopant is implanted throughout the dielectric layer 230. At this point, the dopant scattering can only diffuse to a limited extent to the lower part of the ion implantation depth Rp. Subsequent doses will be mainly concentrated in the upper part of the ion implantation depth Rp. Through the first dopant implantation process, the dopant can be implanted into the dielectric layer 230 to form the initial selector layer 240.

[0045] refer to Figure 4C Additional dopant can be injected into the already doped initial selector layer 240. This dopant injection process can be referred to as the second dopant injection process.

[0046] The dopant implanted during the second dopant implantation process can be the same as the dopant implanted during the first dopant implantation process. For example, when arsenic (As) is implanted during the first dopant implantation process, arsenic (As) can also be implanted during the second dopant implantation process.

[0047] Furthermore, the second dopant implantation process can be performed, for example, by ion implantation towards the initial selector layer 240, with the implantation direction substantially perpendicular to the surface of the substrate 200 or the surface of the initial selector layer 240, such as... Figure 4D As indicated by arrow ②, the second dopant implantation process can be performed using an ion implantation energy lower than that of the first dopant implantation process. The ion implantation energy during the second dopant implantation process can be set to approximately 3 keV or lower. This prevents dopant from being implanted into portions outside the initial selector layer 240, such as the lower electrode layer 210 or the barrier layer 220, and from causing damage, effectively preventing device performance degradation due to damage to these layers. Furthermore, this allows for the formation of a high concentration of dopant in the final selector layer 250. Additionally, the dose of the second dopant implantation process can be set lower than that of the first dopant implantation process. Therefore, when the dopant is fully implanted into the entire initial selector layer 240 by the first dopant implantation process, the scattering effect produced by the second dopant implantation process can reduce the thickness of the initial selector layer 240. This process allows for more precise control of the final selector layer (see...). Figure 4D The thickness of 250 (in the middle) is improved, and the thickness distribution is improved.

[0048] refer to Figure 4DA final selector layer 250 can be formed through a second dopant implantation process. The final selector layer 250 has a low-concentration dopant layer at the bottom and a high-concentration dopant layer at the top. The final selector layer 250 may have a dopant concentration that gradually increases from bottom to top. The lower region of the final selector layer 250 may contain a lower layer 251 with a relatively low dopant concentration, while the upper region of the final selector layer 250 may contain an upper layer 252 with a relatively high dopant concentration. The thickness L2 of the lower layer 251 may be approximately 80% to 60% of the total thickness of the final selector layer 250, and the thickness of the upper layer 252 may be approximately 20% to 40% of the total thickness of the final selector layer 250. Through the second ion implantation process, the thickness of the final selector layer 250 can be less than the thickness of the dielectric material layer 230. The thickness of the final selector layer 250 may, for example, be approximately 30 to 120 Å.

[0049] A semiconductor device according to an embodiment of the present disclosure can be manufactured using the process described above.

[0050] Refer again Figure 4D A semiconductor device according to one embodiment of the present disclosure may include a substrate 200, a lower electrode layer 210 formed on the substrate 200, a barrier layer 220 formed on the lower electrode layer 210, and a final selector layer 250 formed on the barrier layer 220.

[0051] The thickness L2 of the lower layer 251 can be approximately 80% to 60% of the total thickness of the final selector layer 250, while the thickness of the upper layer 252 can be approximately 20% to 40% of the total thickness of the final selector layer 250.

[0052] According to the embodiments and manufacturing methods described in this disclosure, since the lower layer 251 has a relatively low dopant concentration below the final selector layer 250, it can essentially function as a barrier layer 220 rather than a selector layer. Furthermore, the barrier layer 220 and the lower electrode layer 210 formed below the barrier layer 220 can be protected from damage through a two-step dopant implantation process. Therefore, leakage current in the off state can be blocked. Moreover, not only can a high concentration of dopant be formed in the final selector layer 250, but the thickness of the final selector layer 250 can also be more precisely controlled and its thickness distribution improved.

[0053] Figures 5A to 5D This is a cross-sectional view showing a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure.

[0054] refer to Figures 5A to 5DAccording to this disclosure, the semiconductor device may include a memory cell MC formed between a first interconnect 310 extending in a first direction and a second interconnect 390 extending in a second direction, so as to overlap with the intersection region between the first interconnect 310 and the second interconnect 390.

[0055] refer to Figure 5A The memory cell MC may include a stacked structure of a selector layer 330, a lower electrode layer 320, a barrier layer 325, an intermediate electrode layer 340, a variable resistor layer 350, and an upper electrode layer 360. The selector layer 330 is formed on the substrate 300 and the first interconnect 310 through a two-step low-energy ion implantation process. The selector layer 330 may have a dopant concentration distribution that increases from bottom to top. The dopant concentration at the bottom of the selector layer 330 may be lower than that at the top. During the formation of the selector layer 330, the lower electrode layer 320 and the barrier layer 325 can be protected from damage, thereby effectively preventing device performance degradation.

[0056] according to Figures 5A to 5D The resulting structure can be with Figure 1 The structures are basically the same. The first interconnect 310, lower electrode layer 320, selector layer 330, intermediate electrode layer 340, variable resistor layer 350 and upper electrode layer 360 can respectively correspond to Figure 1 The first interconnect 110, lower electrode layer 130, selector layer 140, intermediate electrode layer 150, variable resistor layer 160, and upper electrode layer 170 are included. Therefore, the elements mentioned above can be omitted. Figure 1 The structure corresponds to a detailed description of the structure.

[0057] refer to Figure 5B A hard mask layer 370 can be formed over the upper electrode layer 360. The hard mask layer 370 can be formed by forming a material layer and a photoresist pattern (not shown), and then etching the material layer of the hard mask layer 370 using the photoresist pattern as an etch barrier. The hard mask layer 370 can provide an etch barrier when etching the memory cell MC. The hard mask layer 370 can contain various materials that ensure etch selectivity relative to the memory cell MC. For example, the material layer of the hard mask layer 370 can have a multilayer or single-layer structure containing various dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0058] refer to Figure 5CUsing a hard mask layer 370 as an etch stop layer, the upper electrode layer 360, variable resistor layer 350, intermediate electrode layer 340, selector layer 330, stop layer 325, and lower electrode layer 320 are etched sequentially to form a memory cell MC including an upper electrode pattern 360A, a variable resistor pattern 350A, an intermediate electrode pattern 340A, a selector pattern 330A, a stop pattern 325A, and a lower electrode pattern 320A. The sidewalls of the variable resistor pattern 350A and the sidewalls of the selector pattern 330A can be aligned with each other.

[0059] According to the embodiments described in this disclosure, the hard mask layer 370 can be removed during the memory cell (MC) etching process. However, according to another embodiment of this disclosure, the hard mask layer 370 may be partially or entirely retained and can be removed during the planarization process, as described below.

[0060] refer to Figure 5D An interlayer dielectric layer 380 may be formed on top of the memory cells MC. The interlayer dielectric layer 380 may have a thickness sufficient to fill the space between the memory cells MC and cover the upper part of the memory cells MC. The interlayer dielectric layer 380 may have a single-layer structure or a multi-layer structure, and may contain a variety of dielectric materials, such as silicon oxide, silicon nitride, or combinations thereof.

[0061] Subsequently, a planarization process, such as chemical mechanical polishing (CMP), can be performed on the interlayer dielectric layer 380 until the upper surface of the memory cell MC is exposed. Even if the hard mask layer 370 is not completely removed and remains in the above-mentioned memory cell MC etching process, the hard mask layer 370 can still be removed because a planarization process is performed in this process until the upper surface of the memory cell MC is exposed.

[0062] Subsequently, a plurality of second interconnects 390 may be formed on the memory cell MC and the interlayer dielectric layer 380, these second interconnects 390 being arranged along a second direction intersecting the first direction (e.g., Figure 1 The second interconnect 390 extends in the second direction shown and is coupled to the upper surface of the memory cell MC. The second interconnect 390 can be formed by depositing a conductive material and patterning the conductive material. The space between the second interconnects 390 can be filled with a dielectric material (not shown).

[0063] Through the above process, it is possible to manufacture such as Figure 5D The semiconductor device shown is an embodiment of this disclosure. Furthermore, all the advantages described in the above embodiments of this disclosure can be obtained according to this embodiment.

[0064] According to embodiments of the present disclosure, the semiconductor device and its manufacturing method prevent damage to the interface between the selector layer and the lower electrode layer, thereby blocking leakage current in the off state, while increasing the dopant concentration of the ion-implanted selector layer and improving the thickness distribution of the selector layer.

[0065] While the present invention has been described with reference to specific embodiments, those skilled in the art will understand that various modifications and improvements can be made to these embodiments without departing from the technical concept and scope defined by the claims. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: Multiple storage units, each of the storage units comprising: First electrode layer; Memory layer; and A selector layer, adapted to select the memory layer and formed in the upper or lower part of the memory layer and above the first electrode layer. The selector layer includes a dielectric material layer doped with a first dopant, and In this process, the dopant concentration in the lower region of the dielectric material layer of the selector layer adjacent to the first electrode layer is lower than the dopant concentration in the upper region of the dielectric material layer.

2. The semiconductor device according to claim 1, wherein, The thickness of the upper region in the dielectric material layer of the selector layer is approximately 80% to 60% of the total thickness of the selector layer, and The thickness of the lower region in the dielectric material layer of the selector layer is approximately 20% to 40% of the total thickness of the selector layer.

3. The semiconductor device according to claim 1, wherein, The selector layer has a thickness of approximately 30 to 120 Å.

4. The semiconductor device according to claim 1, wherein, The storage unit also includes a barrier layer disposed below the selector layer, and The barrier layer comprises silicon nitride, carbon, or transition metal oxide.

5. The semiconductor device according to claim 4, wherein, The storage unit also includes, The first electrode layer disposed below the barrier layer, and A second electrode layer is disposed above the selector layer.

6. The semiconductor device according to claim 5, wherein, The first electrode layer and the second electrode layer include TiN layers.

7. The semiconductor device according to claim 5, further comprising: A carbon C layer at the interface between the selector layer and the second electrode layer.

8. The semiconductor device according to claim 1, wherein, The sidewalls of the memory layer are aligned with the sidewalls of the selector layer.

9. The semiconductor device according to claim 1, wherein, The first dopant includes gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), tungsten (W), or a combination thereof.

10. The semiconductor device according to claim 1, wherein, The first dopant includes arsenic (As).

11. The semiconductor device according to claim 1, wherein, The memory layer is a variable resistance layer.

12. A method of manufacturing a semiconductor device, the semiconductor device including a selector layer in a memory cell to control electrical access to one of a plurality of arrayed memory cells, the method comprising: A first electrode layer is formed on the substrate; A dielectric material layer for the selector layer is formed on top of the first electrode layer; as well as The selector layer is formed by performing multiple dopant implantation processes on the dielectric material layer using different ion implantation energies, wherein the dopant concentration in the lower region of the dielectric material layer adjacent to the first electrode layer is lower than the dopant concentration in the upper region of the dielectric material layer.

13. The method according to claim 12, wherein, The dopant implantation process is performed twice, and The first dopant implantation process is performed with ion implantation energy such that the ion implantation depth (Rp) is formed at a height point approximately 30% to 50% of the total thickness of the dielectric material layer from the lower surface of the dielectric material layer, and The second dopant implantation process is performed at an ion implantation energy lower than that of the first dopant implantation process.

14. The method according to claim 13, wherein, The ion implantation energy range of the first dopant implantation process is approximately 3 keV to 7 keV.

15. The method according to claim 12, wherein, The thickness of the lower region of the dielectric material layer is approximately 80% to 60% of the total thickness of the selector layer, and The thickness of the upper region of the dielectric material layer is approximately 20% to 40% of the total thickness of the selector layer.

16. The method according to claim 13, wherein, Perform the first dopant implantation process until the first dopant is implanted throughout the entire dielectric material layer.

17. The method of claim 12, further comprising: A barrier layer is formed between the first electrode layer and the selector layer.

18. The method according to claim 17, wherein, The barrier layer is formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

19. The method of claim 17, wherein, The barrier layer comprises silicon nitride, carbon, or transition metal oxide.

20. The method according to claim 12, wherein, The dopants ion-implanted into the dielectric material layer include gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), tungsten (W), or combinations thereof.

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