Method for forming self-aligned silicide barrier layer

Abstract

The invention provides a method for forming a self-aligned silicide barrier layer. The method comprises the following steps: sequentially depositing a bottom dielectric layer, an etching stop layer and a top dielectric layer on a substrate to form a composite film layer; defining a retaining region of the barrier layer through photoetching; etching the top dielectric layer and stopping on the etching stop layer; carrying out adhesive wet cleaning to remove the residual top dielectric layer in the narrow gap area; removing the photoresist; removing the exposed etching stop layer; heat treatment; and removing the exposed bottom dielectric layer. According to the method, the photoresist is utilized to protect the film layer in the LDMOS region from thickness loss while the residual dielectric layer in the CMOS narrow-spacing region is thoroughly removed through the adhesive wet cleaning process, so that the contradiction between the thick film layer requirement and fine-spacing cleaning is solved, and the compatibility of the pressure resistance of the high-voltage device and the contact hole process is ensured.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming a self-aligned silicide barrier layer. Background Technology

[0002] In semiconductor integrated circuit manufacturing processes, as technology nodes advance towards miniaturization (e.g., 90nm BCD process), integrating different types of devices onto the same process platform becomes increasingly difficult. This is especially true in the integration of high-voltage power devices and low-voltage logic devices, where process compatibility challenges are often encountered.

[0003] In existing BCD (Bipolar-CMOS-DMOS) processes, laterally diffused metal-oxide semiconductors (LDMOS, especially LDMOS with PBODY and contact hole shielding structures) typically require a relatively thick self-aligned silicide block (SAB) film. This is to ensure that the contact hole shield (CTS) has sufficient height, thereby ensuring that the LDMOS device has a high breakdown voltage capability.

[0004] However, when growing thick SAB films to meet the voltage withstand requirements of LDMOS, SAB film stacking is highly likely to occur in the complementary metal-oxide-semiconductor (CMOS) region, especially in areas with narrow polysilicon gate gaps. This stacking makes it difficult for subsequent etching processes to completely remove the SAB film at the bottom of the narrow gap, resulting in film residue. These residual dielectric layers can block the formation of contact holes, preventing them from being effectively led out and severely impacting yield.

[0005] Existing conventional SAB (Surface Mount Alternating Layer) processes present a contradiction between the high voltage withstand requirements of LDMOS (requiring thick films) and the fine-pitch integration of CMOS (requiring thin films or easy removal), limiting the upper limit of SAB thickness and hindering the integration of high-performance devices. Therefore, a new manufacturing method is needed that can ensure the film thickness in the LDMOS region to maintain voltage withstand performance while effectively avoiding residual problems in the narrow-pitch CMOS region. Summary of the Invention

[0006] The technical problem to be solved by the present invention is that in the existing semiconductor manufacturing process, a thicker self-aligned silicide barrier layer (SAB) is required to ensure the withstand voltage performance of laterally diffused metal-oxide semiconductor (LDMOS). However, this will lead to difficult-to-remove film stacking and residues in the complementary metal-oxide semiconductor (CMOS) region, especially in the narrow gap region, thereby affecting the lead-out of contact holes and device integration.

[0007] To address the aforementioned technical problems, this invention provides a method for forming a self-aligned silicide barrier layer, comprising the following steps:

[0008] Step 1: Provide a substrate, and sequentially deposit a bottom dielectric layer, an etch stop layer, and a top dielectric layer on the substrate surface to form a composite film structure;

[0009] Step 2: Coat photoresist on the top dielectric layer and perform photolithography to form a mask pattern that defines the self-aligned silicide barrier layer retention area;

[0010] Step 3: Using the mask pattern as a mask, etch the top dielectric layer, stopping the etching at the surface of the etching stop layer;

[0011] Step 4: Perform wet cleaning with adhesive to remove the top dielectric layer remaining in the narrow gap area of ​​the pattern in Step 3;

[0012] Step 5: Remove the photoresist;

[0013] Step 6: Remove the exposed etch stop layer;

[0014] Step 7: Perform heat treatment on the substrate;

[0015] Step 8: Remove the exposed underlying media layer.

[0016] Preferably, in step one, the bottom dielectric layer and the top dielectric layer are made of silicon oxide, and the etching stop layer is made of silicon nitride, thereby forming a silicon oxide-silicon nitride-silicon oxide stacked structure.

[0017] Preferably, in step one, the thickness of the underlying dielectric layer ranges from 250 angstroms to 350 angstroms.

[0018] Preferably, in step one, the thickness of the etching stop layer ranges from 350 angstroms to 450 angstroms.

[0019] Preferably, in step one, the thickness of the top dielectric layer ranges from 1050 angstroms to 1250 angstroms.

[0020] Preferably, in step three, the etching is dry etching, during which the etching stop layer is partially lost, and a portion of the top dielectric layer remains at the bottom of the narrow gap region of the pattern.

[0021] Preferably, in step three, the thickness of the top dielectric layer remaining at the bottom of the narrow gap region of the pattern is 50 to 150 angstroms.

[0022] Preferably, in step four, the wet cleaning with adhesive is used to rinse away the top dielectric layer remaining in the narrow gap area of ​​the pattern, while the photoresist protects the top dielectric layer under its coverage area from thickness loss.

[0023] Preferably, in step six, a wet etching process is used to remove the exposed etching stop layer; in step eight, a wet etching process is used to remove the exposed underlying dielectric layer.

[0024] Preferably, in step seven, the heat treatment is a rapid thermal annealing process, with a process temperature of 1000 degrees Celsius to 1030 degrees Celsius and a processing time of 5 to 15 seconds.

[0025] Preferably, in step seven, the specific parameters of the heat treatment are 1015 degrees Celsius for 10 seconds.

[0026] Preferably, the formation method is used for the integrated fabrication of a laterally diffused metal-oxide-semiconductor (LMSD) device and a complementary metal-oxide-semiconductor (CMOS) device; in step one, the substrate defines a LMSD region and a CMOS region; in step two, the mask pattern covers the LMSD region to retain the composite film structure in the LMSD region as the self-aligned silicide barrier layer.

[0027] Preferably, in step three, the etching is applied to the top dielectric layer on the complementary metal-oxide-semiconductor region; in step four, the patterned narrow gap region is located between adjacent gate structures within the complementary metal-oxide-semiconductor region; the wet cleaning with adhesive is used to prevent residual film from forming in the complementary metal-oxide-semiconductor region, thus avoiding the formation of contact hole leads.

[0028] As described above, the method for forming a self-aligned silicide barrier layer of the present invention has the following beneficial effects:

[0029] The self-aligned silicide barrier layer formation method provided by this invention resolves the contradiction of inconsistent film thickness requirements in different device regions by employing a composite film structure (e.g., an ONO structure) consisting of a bottom dielectric layer, an etch stop layer, and a top dielectric layer, combined with dry etching and a unique wet cleaning process with photoresist. Specifically, this method can thoroughly remove dielectric layer residues in narrow-pitch CMOS regions, ensuring effective contact hole routing. Simultaneously, utilizing the protective effect of photoresist, it ensures no thickness loss in the SAB film layer of the LDMOS region during wet cleaning, maintaining the original deposition thickness of the SAB film layer (especially the top dielectric layer). The resulting SAB structure provides sufficient height for the contact hole shielding layer, ensuring that the LDMOS device has a high withstand voltage capability of over 24V, achieving high-quality integration of high-voltage power devices and low-voltage logic devices on the same process platform, and improving product yield and reliability. Attached Figure Description

[0030] Figure 1 The diagram shows a process flow diagram of the method for forming a self-aligned silicide barrier layer according to the present invention.

[0031] Figure 2 The diagram shows the structure after the composite film structure is deposited in step one of the self-aligned silicide barrier layer formation method of the present invention.

[0032] Figure 3 The diagram shows the structure after the mask pattern is formed in step two of the method for forming the self-aligned silicide barrier layer of the present invention.

[0033] Figure 4 The diagram shows the structure after etching the top dielectric layer in step three of the method for forming the self-aligned silicide barrier layer of the present invention.

[0034] Figure 5 The diagram shown is a structural schematic of the self-aligned silicide barrier layer formation method of the present invention after wet cleaning with adhesive in step four.

[0035] Figure 6 The diagram shows the structure after removing the photoresist in step five of the method for forming the self-aligned silicide barrier layer of the present invention.

[0036] Figure 7 The diagram shows the structure after removing the exposed etch stop layer in step six of the method for forming the self-aligned silicide barrier layer of the present invention.

[0037] Figure 8 The diagram shown is a structural schematic of the self-aligned silicide barrier layer formation method of the present invention after removing the exposed underlying dielectric layer in step eight. Detailed Implementation

[0038] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0039] like Figure 1 As shown, a method for forming a self-aligned silicide barrier layer includes the following steps:

[0040] Step 1: Provide a substrate 101, and sequentially deposit a bottom dielectric layer 103, an etch stop layer 104, and a top dielectric layer 105 on the surface of the substrate 101 to form a composite film structure.

[0041] In some embodiments, the formation method is used for the integrated fabrication of a laterally diffused metal-oxide-semiconductor device and a complementary metal-oxide-semiconductor device; in step one, the substrate 101 defines a laterally diffused metal-oxide-semiconductor region and a complementary metal-oxide-semiconductor region.

[0042] like Figure 2 As shown, a gate structure 102 is formed on the substrate 101. The formation of the gate structure 102 typically involves depositing a gate dielectric layer material and a gate electrode material, followed by a patterning process.

[0043] First, a gate dielectric layer is formed on substrate 101. The gate dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. The high-k dielectric material may be selected from metal oxides, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), and combinations thereof. The formation process of the gate dielectric layer may employ thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0044] Next, a gate electrode layer is deposited on the gate dielectric layer. The gate electrode layer can be polysilicon, which can be doped in situ or through a subsequent ion implantation process to adjust the work function. In some advanced processes or metal gate processes, the gate electrode layer can include metals, metal alloys, or metal silicides, such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium carbide (TiC), tungsten silicide (WSi), nickel silicide (NiSi), cobalt silicide (CoSi), and combinations thereof. Furthermore, the gate structure 102 may also include sidewalls located on the sidewalls, which are typically formed of dielectric materials, such as silicon oxide, silicon nitride, silicon carbonitride (SiCN), or multilayer combinations thereof, to isolate the gate electrode from the subsequently formed source / drain regions.

[0045] Subsequently, the deposited film layer is patterned using photolithography and etching processes to form the gate structure 102 shown in the figure. The photolithography process may include steps such as coating photoresist, exposure, and development; the etching process may include dry etching (such as reactive ion etching, RIE) or wet etching. After forming the gate structure 102, source / drain ion implantation and the formation of a lightly doped drain (LDD) structure are typically performed to enhance the transistor's functionality.

[0046] Substrate 101 may include elemental semiconductors, such as crystalline silicon, diamond, or germanium; it may also include compound semiconductors, such as silicon carbide (SiC), gallium nitride (GaN), gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; and it may also include alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, or gallium arsenide phosphide. Furthermore, substrate 101 may also be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. To enhance device performance, substrate 101 may include strained structures to enhance carrier mobility, or it may include an epitaxial layer formed on the bulk semiconductor. Substrate 101 may have any suitable crystal orientation, such as (100), (110), or (111) crystal orientations. According to the laterally diffused metal-oxide-semiconductor region ( Figure 2 CFP SAB region and complementary metal-oxide-semiconductor region ( Figure 2 For specific process nodes in the CMOS normal region and CMOS narrow-pitch region, the substrate 101 can undergo various doping configurations, such as forming P-type doped regions, N-type doped regions, or deep buried layers, as well as shallow trench isolation structures for isolating active regions. Before depositing the composite film structure, the surface of the substrate 101 can be subjected to standard RCA cleaning or other pretreatment processes to remove the surface native oxide layer, organic contaminants, or metal ions.

[0047] In some embodiments, in step one, the bottom dielectric layer 103 and the top dielectric layer 105 are made of silicon oxide, and the etching stop layer 104 is made of silicon nitride, thereby forming a silicon oxide-silicon nitride-silicon oxide stacked structure. Figure 2 As shown, a composite film structure covers the substrate 101 and the gate structure 102, wherein a bottom dielectric layer 103, an etch stop layer 104, and a top dielectric layer 105 are stacked sequentially. This material combination utilizes the high selectivity of silicon oxide and silicon nitride in dry etching and wet etching, enabling precise control of the remaining thickness of the film. The bottom dielectric layer 103 and the top dielectric layer 105 can be formed using processes such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or high-density plasma-enhanced chemical vapor deposition (HDP-CVD). The process gas can be a combination of silane (SiH4), dichlorosilane (DCS), or tetraethyl orthosilicate (TEOS) with nitrous oxide (N2O) or oxygen (O2). The etch stop layer 104 can be formed using LPCVD or PECVD processes, and the process gas can be a combination of silane or dichlorosilane with ammonia (NH3).

[0048] In some embodiments, in step one, the thickness of the underlying dielectric layer 103 ranges from 250 angstroms to 350 angstroms. Specifically, the thickness of the underlying dielectric layer 103 can be 300 angstroms. This thickness provides basic protection for subsequent processes, preventing damage to the underlying gate structure 102 or active region, while being thin enough to be easily removed in the final step.

[0049] In some embodiments, in step one, the thickness of the etch stop layer 104 ranges from 350 angstroms to 450 angstroms. Specifically, the thickness of the etch stop layer 104 can be 400 angstroms. This thickness of silicon nitride layer is sufficient to act as a barrier when etching the top dielectric layer 105, preventing over-etching through to the bottom dielectric layer 103, while it can also be completely removed in subsequent wet processes.

[0050] In some embodiments, in step one, the thickness of the top dielectric layer 105 ranges from 1050 angstroms to 1250 angstroms. Specifically, the thickness of the top dielectric layer 105 can be 1150 angstroms. A thicker top dielectric layer 105 is key to ensuring the withstand voltage performance of high-voltage devices. Together with the bottom dielectric layer 103 and the etch stop layer 104, the total thickness of the entire SAB stack structure can meet the height requirements of the contact hole shielding layer.

[0051] Step 2: Coat photoresist 106 on the top dielectric layer 105 and perform photolithography to form a mask pattern that defines the self-aligned silicide barrier layer retention area.

[0052] In some embodiments, in step two, the mask pattern covers the laterally diffused metal-oxide-semiconductor region to retain the composite film structure within the laterally diffused metal-oxide-semiconductor region as a self-aligned silicide barrier layer. For example... Figure 3 As shown, photoresist 106 covers the laterally diffused metal-oxide-semiconductor region (CFP SAB region), while exposing the complementary metal-oxide-semiconductor region (CMOS region). The photolithography process can be performed using a deep ultraviolet (DUV) lithography machine or an I-line lithography machine. The photoresist 106 defines the high-voltage device regions where the SAB needs to be preserved, thereby enabling the integration of devices at different voltage levels.

[0053] Step 3: Using the mask pattern (i.e., the patterned photoresist 106) as a mask, etch the top dielectric layer 105, and stop the etching on the surface of the etch stop layer 104.

[0054] In some embodiments, in step three, the etching targets the top dielectric layer 105 on the complementary metal-oxide-semiconductor region. The etching employs a dry etching process, such as reactive ion etching (RIE) or inductively coupled plasma (ICP) etching. The etching gas can be a fluorine-containing gas, such as CF4, CHF3, or C4F8. By adjusting the gas ratio and bias power, a high etching rate for the top dielectric layer 105 (silicon oxide) and a high selectivity for the etch stop layer 104 (silicon nitride) can be achieved.

[0055] In some embodiments, in step three, the etching is dry etching. During the etching process, the etching stop layer 104 is partially lost, and a portion of the top dielectric layer 105 remains at the bottom of the narrow gap region of the pattern. Figure 4 As shown, in the CMOS region, due to the different arrangement densities of the gate structures 102, micro-load effects or high aspect ratio etching difficulties may occur in areas with smaller gaps between the gate structures 102 (the narrow-pitch CMOS region in the figure). This results in the inability of conventional etching time to completely remove the top dielectric layer 105 at the bottom of the gap, leaving a residue of the top dielectric layer 105. If the etching time is forcibly increased to remove the residue, the etch stop layer 104 in the open area (normal CMOS region) will be etched through, damaging the bottom dielectric layer 103 and even the substrate 101. In this embodiment, this residue is retained instead of being forcibly removed during the dry etching stage. The etch stop layer 104 may experience slight wear in the open area, but it is not penetrated.

[0056] In some embodiments, in step three, the thickness of the residual top dielectric layer 105 at the bottom of the narrow gap region of the pattern is 50 to 150 angstroms. For example, the thickness of the residual top dielectric layer 105 may be around 100 angstroms. If this level of residue is not treated, it will prevent the formation of subsequent contact holes, leading to device failure.

[0057] Step 4: Perform wet cleaning with adhesive to remove the top dielectric layer 105 that remained in the narrow gap area of ​​the pattern in Step 3.

[0058] In some embodiments, in step four, the narrow gap region of the pattern is located between adjacent gate structures 102 within the complementary metal-oxide-semiconductor (CMOS) region; wet cleaning with adhesive is used to avoid the formation of residual top dielectric layer 105 in the CMOS region that would obstruct the contact hole lead-out. Figure 5 As shown, photoresist 106 is retained in this step. The cleaning solution can be diluted hydrofluoric acid (DHF) or buffered oxide etchant (BOE).

[0059] In some embodiments, in step four, wet cleaning with photoresist is used to rinse away the residual top dielectric layer 105 in the narrow gap area of ​​the pattern, while using photoresist 106 to protect the top dielectric layer 105 under its coverage area from thickness loss. Figure 5 As shown, after this step, the residue of the top dielectric layer 105 at the bottom of the narrow-pitch CMOS region is completely removed, exposing the underlying etch stop layer 104. Since the photoresist 106 still covers the LDMOS region, the wet etching solution cannot reach the top dielectric layer 105 below the photoresist 106. Therefore, the isotropic properties of wet etching can be safely utilized to remove residues without concern about loss of SAB film thickness in the LDMOS region.

[0060] Step 5: Remove photoresist 106.

[0061] like Figure 6 As shown, after removing the photoresist 106, the LDMOS region retains the complete SAB stack structure (bottom dielectric layer 103 + etch stop layer 104 + top dielectric layer 105), while the CMOS region exposes the etch stop layer 104. The photoresist 106 can be removed using an oxygen plasma ashing process, followed by cleaning with a mixed solution of sulfuric acid and hydrogen peroxide (SPM) to thoroughly remove organic residues.

[0062] Step 6: Remove the exposed etch stop layer 104.

[0063] In some embodiments, in step six, a wet etching process is used to remove the exposed etch stop layer 104. For example... Figure 7 As shown, the etch stop layer 104 of the CMOS region is removed. Silicon nitride can be removed by wet etching using a hot phosphoric acid bath. Hot phosphoric acid has an extremely high etching rate on the etch stop layer 104 (silicon nitride) and an extremely low etching rate on the underlying dielectric layer 103 (silicon oxide), thus enabling it to self-stop on the underlying dielectric layer 103 and protect the active region from damage.

[0064] Step 7: Perform heat treatment on substrate 101.

[0065] In some embodiments, in step seven, the heat treatment is a rapid thermal annealing process, with a process temperature of 1000 degrees Celsius to 1030 degrees Celsius and a processing time of 5 seconds to 15 seconds.

[0066] In some embodiments, in step seven, the specific parameters for the heat treatment are 1015 degrees Celsius for 10 seconds. High-temperature rapid thermal annealing can make the deposited composite film structure more compact, repair lattice damage that may be caused by dry etching and ion implantation, and improve the quality of the film interface.

[0067] Step 8: Remove the exposed underlying media layer 103.

[0068] In some embodiments, in step eight, a wet etching process is used to remove the exposed underlying dielectric layer 103. For example... Figure 8 As shown, this step can be performed by briefly soaking in dilute hydrofluoric acid to remove the remaining approximately 300 angstroms of the underlying dielectric layer 103. At this point, the active region of the CMOS area and the top of the gate structure 102 are fully exposed, preparing for subsequent self-aligned silicide processes (such as the formation of nickel silicide or cobalt silicide), and there is no problem of residual oxide layer blocking the contact holes.

[0069] In some embodiments, a self-aligned silicide barrier layer is used to cover the laterally diffused metal-oxide-semiconductor region. The self-aligned silicide barrier layer retained in the laterally diffused metal-oxide-semiconductor region using this formation method has a total thickness of the bottom dielectric layer 103, the etch stop layer 104, and the top dielectric layer 105 sufficient to meet the withstand voltage requirements of devices above 24V. Figure 8 As shown, the LDMOS region ultimately retains a complete SAB film layer, namely an ONO structure consisting of a bottom dielectric layer 103 (300 Å), an etch stop layer 104 (400 Å), and a top dielectric layer 105 (1150 Å). The total height of this structure (approximately 1850 Å) provides sufficient physical isolation distance for the contact hole shielding structure, thereby ensuring that the LDMOS device (especially the PBODY+CTS structure) has a high withstand voltage capability of over 24V. This manufacturing method successfully achieves stable integration of high-voltage LDMOS and advanced process CMOS on the same substrate 101.

[0070] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0071] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for forming a self-aligned silicide barrier layer, characterized in that, At least including: Step 1: Provide a substrate, and sequentially deposit a bottom dielectric layer, an etch stop layer, and a top dielectric layer on the substrate surface to form a composite film structure; Step 2: Coat photoresist on the top dielectric layer and perform photolithography to form a mask pattern that defines the self-aligned silicide barrier layer retention area; Step 3: Using the mask pattern as a mask, etch the top dielectric layer, stopping the etching at the surface of the etching stop layer; Step 4: Perform wet cleaning with adhesive to remove the top dielectric layer remaining in the narrow gap area of ​​the pattern in Step 3; Step 5: Remove the photoresist; Step 6: Remove the exposed etch stop layer; Step 7: Perform heat treatment on the substrate; Step 8: Remove the exposed underlying media layer.

2. The method for forming a self-aligned silicide barrier layer according to claim 1, characterized in that: In step one, the bottom dielectric layer and the top dielectric layer are made of silicon oxide, and the etching stop layer is made of silicon nitride, thereby forming a silicon oxide-silicon nitride-silicon oxide stacked structure.

3. The method for forming a self-aligned silicide barrier layer according to claim 2, characterized in that: In step one, the thickness of the underlying dielectric layer ranges from 250 angstroms to 350 angstroms.

4. The method for forming a self-aligned silicide barrier layer according to claim 2, characterized in that: In step one, the thickness of the etching stop layer ranges from 350 angstroms to 450 angstroms.

5. The method for forming a self-aligned silicide barrier layer according to claim 2, characterized in that: In step one, the thickness of the top dielectric layer ranges from 1050 angstroms to 1250 angstroms.

6. The method for forming a self-aligned silicide barrier layer according to claim 1, characterized in that: In step three, the etching is dry etching. During the etching process, the etching stop layer is partially lost, and a portion of the top dielectric layer remains at the bottom of the narrow gap region of the pattern.

7. The method for forming a self-aligned silicide barrier layer according to claim 6, characterized in that: In step three, the thickness of the top dielectric layer remaining at the bottom of the narrow gap region of the pattern is 50 to 150 angstroms.

8. The method for forming a self-aligned silicide barrier layer according to claim 6, characterized in that: In step four, the wet cleaning with adhesive is used to rinse away the top dielectric layer remaining in the narrow gap area of ​​the pattern, while the photoresist protects the top dielectric layer under its coverage area from thickness loss.

9. The method for forming a self-aligned silicide barrier layer according to claim 2, characterized in that: In step six, a wet etching process is used to remove the exposed etching stop layer; in step eight, a wet etching process is used to remove the exposed underlying dielectric layer.

10. The method for forming a self-aligned silicide barrier layer according to claim 1, characterized in that: In step seven, the heat treatment is a rapid thermal annealing process, with a process temperature of 1000 degrees Celsius to 1030 degrees Celsius and a processing time of 5 to 15 seconds.

11. The method for forming a self-aligned silicide barrier layer according to claim 10, characterized in that: In step seven, the specific parameters for the heat treatment are 1015 degrees Celsius for 10 seconds.

12. The method for forming a self-aligned silicide barrier layer according to any one of claims 1 to 11, characterized in that: This formation method is used for the integrated fabrication of laterally diffused metal-oxide-semiconductor devices and complementary metal-oxide-semiconductor devices; in step one, the substrate defines a laterally diffused metal-oxide-semiconductor region and a complementary metal-oxide-semiconductor region. In step two, the mask pattern covers the laterally diffused metal-oxide-semiconductor region to retain the composite film structure in the laterally diffused metal-oxide-semiconductor region as the self-aligned silicide barrier layer.

13. The method for forming a self-aligned silicide barrier layer according to claim 12, characterized in that: In step three, the etching is applied to the top dielectric layer on the complementary metal-oxide-semiconductor region; In step four, the patterned narrow gap region is located between adjacent gate structures within the complementary metal-oxide-semiconductor region; the adhesive wet cleaning process avoids the formation of residual film layers in the complementary metal-oxide-semiconductor region that would obstruct the contact hole lead-out.

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