Embedded flash memory and forming method thereof
By using a protective layer to cover the gate in embedded flash memory and utilizing logic sidewalls to block ion implantation, the problem of gate thickness limiting the implantation depth of high-voltage lightly doped drain regions is solved, thereby improving the reliability and mass production capability of embedded flash memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-02-27
- Publication Date
- 2026-05-19
AI Technical Summary
In existing embedded flash memory (eFlash) technology, as logic nodes shrink, the width of the gate sidewalls becomes smaller, leading to severe hot carrier injection effects and gate-induced drain leakage effects. The injection depth of the high-voltage lightly doped drain region is limited, affecting reliability.
When forming a high-voltage lightly doped drain region under the gate and logic sidewalls, a protective layer is used to cover the gate. A non-self-aligned ion implantation process is used to limit the implanted ions by utilizing the blocking ability of the logic sidewalls, ensuring implantation depth and uniformity.
It effectively reduces gate asymmetry caused by non-self-aligned injection, improves the reliability and mass production of embedded flash memory, and improves the hot carrier injection effect and gate-induced drain leakage effect.
Smart Images
Figure CN122069744A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to an embedded flash memory and a method for forming the same. Background Technology
[0002] Current embedded flash memory (eFlash) technology typically requires a gate to control the erase / write voltage (approximately 10V). However, as eFlash logic nodes become smaller and the gate sidewall width decreases, the Hot Carrier Injection (HCI) effect becomes increasingly severe, leading to unacceptable reliability. Gate-Induced Drain Leakage (GIDL) also contributes to the decreasing drain breakdown voltage. To improve the hot carrier injection and gate-induced drain leakage effects, it is usually necessary to increase the injection depth of the High Voltage Lightly Doped Drain (HV LDD) region, moving the electric field peak near the drain gate away from the surface. However, as nodes become smaller, the gate thickness also decreases, limiting the injection energy of the high voltage lightly doped drain region to the thickness of the gate polysilicon. This restricts the injection depth of the high voltage lightly doped drain region, and the hot carrier injection and gate-induced drain leakage effects are not improved. Summary of the Invention
[0003] The purpose of this invention is to provide an embedded flash memory and a method for forming the same, so as to solve the problems that the thinning of the gate thickness limits the injection depth of the high-voltage lightly doped drain region, and the hot carrier injection effect and gate-induced drain leakage effect cannot be improved.
[0004] To address the aforementioned technical problems, the present invention provides a method for forming embedded flash memory, comprising:
[0005] A substrate is provided on which a gate and logic sidewalls located on both sides of the gate are formed;
[0006] A protective layer is formed, the protective layer at least covering the top surface of the gate;
[0007] An ion implantation process is performed to form a high-voltage lightly doped drain region within the substrate under the gate and the logic sidewall, wherein the protective layer is used to protect the gate during the ion implantation process.
[0008] Optionally, the protective layer covers the top surface of the gate and the top surface and sidewalls of the logic sidewalls.
[0009] Optionally, the protective layer covers the top surface of the gate, a portion of the top surface of one logic sidewall, and the top surface and sidewall of the other logic sidewall.
[0010] Optionally, the overlay deviation between the protective layer and the gate does not exceed half the width of the logic sidewall.
[0011] Optionally, the material of the protective layer includes at least one of photoresist, SOC, and BARC.
[0012] Optionally, the doping type of the high-voltage lightly doped drain region is opposite to the doping type of the substrate.
[0013] Optionally, the ion implantation process for forming the high-voltage lightly doped drain region includes HVNLDD or HVPLDD processes, wherein the implantation energy of the HVNLDD process is 20 keV to 160 keV, and the implantation dose of the HVNLDD process is 5E12 Atom / cm². 2 Up to 5E14Atom / cm 2 The HVPLDD process uses an implantation energy of 10 keV to 60 keV and an implantation dose of 5E12 atm / cm². 2 Up to 5E14Atom / cm 2 .
[0014] Optionally, the implantation depth of the high-voltage lightly doped drain region is 200 angstroms to 2000 angstroms.
[0015] Optionally, after forming the high-voltage lightly doped drain region, a source region and a drain region are formed, the source region and the drain region being located in the substrate on both sides of the gate, the doping type of the source region and the drain region being the same as the doping type of the high-voltage lightly doped drain region, and the doping type of the source region and the drain region being opposite to the doping type of the substrate.
[0016] Based on the same inventive concept, the present invention also provides an embedded flash memory, which is prepared by the embedded flash memory forming method described in any of the above claims.
[0017] In the embedded flash memory formation method provided by the present invention, a substrate is provided, on which a gate and logic sidewalls located on both sides of the gate are formed; a protective layer is formed, the protective layer at least covering the top surface of the gate; an ion implantation process is performed to form a high-voltage lightly doped drain region in the substrate under the gate and the logic sidewalls, wherein the protective layer is used to protect the gate in the ion implantation process. After the gate and logic sidewalls are formed, this invention uses a non-self-aligned method, that is, by defining the implantation boundary of the high-voltage lightly doped drain region near the middle position of the logic sidewall using a photomask. In the ion implantation process for forming the high-voltage lightly doped drain region, the protective layer protects the gate. Therefore, the implantation energy of the high-voltage lightly doped drain region is not affected by the gate thickness. Although the boundary of the protective layer is deviated due to the overlay accuracy, the logic sidewall is usually made of silicon nitride, which has a high blocking ability for ion implantation. Therefore, on the side exposed to the logic sidewall, the implanted ions of the high-voltage lightly doped drain region are blocked by the logic sidewall and confined to the vicinity of the logic sidewall boundary. On the side covered by the protective layer, since the protective layer has a relatively weaker ability, high-energy implanted ions can penetrate the protective layer but are blocked by the logic sidewall and confined to the vicinity of the logic sidewall boundary. Therefore, the self-alignment effect still exists, reducing the gate asymmetry caused by non-self-aligned implantation. Attached Figure Description
[0018] Figure 1 This is a flowchart of the embedded flash memory formation method according to an embodiment of the present invention.
[0019] Figures 2 to 6 This is a schematic diagram of the structure corresponding to the steps of the embedded flash memory formation method according to an embodiment of the present invention; wherein, Figure 2 This is a schematic diagram of the embedded flash memory structure after the formation of the gate and logic sidewalls according to an embodiment of the present invention;
[0020] Figure 3 This is a schematic diagram of the embedded flash memory structure after the formation of the protective layer according to an embodiment of the present invention;
[0021] Figure 4 This is a schematic diagram of the embedded flash memory structure after forming a high-voltage lightly doped drain region under ideal conditions according to an embodiment of the present invention;
[0022] Figure 5 This is a schematic diagram of the embedded flash memory structure after forming a high-voltage lightly doped drain region under a non-ideal condition according to an embodiment of the present invention;
[0023] Figure 6 This is a schematic diagram of the embedded flash memory structure after the source and drain regions are formed according to an embodiment of the present invention.
[0024] In the picture,
[0025] 10-Substrate; 11-Gate oxide layer; 12-Gate; 13-Logic sidewall; 14-Protective layer; 15-High voltage lightly doped drain region; 16-Drain region; 17-Source region. Detailed Implementation
[0026] The embedded flash memory and its formation method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, only for the purpose of conveniently and clearly illustrating the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different proportions may be used in different drawings to illustrate different aspects.
[0027] Figure 1 This is a flowchart illustrating a method for forming embedded flash memory according to an embodiment of the present invention. Figure 1 As shown, an embodiment of the present invention provides a method for forming an embedded flash memory, comprising:
[0028] Step S10: A substrate is provided, on which a gate and logic sidewalls located on both sides of the gate are formed;
[0029] Step S20: Form a protective layer that at least covers the top surface of the gate;
[0030] Step S30: Perform an ion implantation process to form a high-voltage lightly doped drain region in the substrate under the gate and the logic sidewall, wherein the protective layer is used to protect the gate during the ion implantation process.
[0031] Figures 2 to 6 This is a schematic diagram of the structure corresponding to the steps of the embedded flash memory formation method according to an embodiment of the present invention; to make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 2 to 6 Specific embodiments of the present invention will be described in detail below.
[0032] Figure 2 This is a schematic diagram of the embedded flash memory structure after the formation of the gate and logic sidewalls according to an embodiment of the present invention. (Combined with...) Figure 2 Detailed steps S10 are described below. Figure 2As shown, a substrate 10 is provided. Substrate 10 provides an operating platform for subsequent processes. It can be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components, such as a bare die or a wafer processed by epitaxial growth. Specifically, the substrate is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc. In this embodiment, the substrate 10 is a silicon substrate. The doping type of the substrate 10 is a first doping type.
[0033] Please continue to refer to this. Figure 2 A gate 12 and logic sidewalls 13 located on both sides of the gate 12 are formed on the substrate 10. The gate 12 is made of polysilicon, for example, and can be formed using a chemical vapor deposition process. The gate 12 is used to form a high-voltage device, and the gate 12 is relatively thin, for example, 300 angstroms to 1000 angstroms thick. The logic sidewalls 13 include a first logic sidewall and a second logic sidewall, both of which are ON (silicon oxide and silicon nitride) structures and can be formed using a chemical vapor deposition process. A gate oxide layer 11 is also formed between the gate 12 and the substrate 10. The gate oxide layer 11 is made of silicon oxide and can be formed using a thermal oxidation process or a chemical vapor deposition process.
[0034] Figure 3 This is a schematic diagram of the embedded flash memory structure after the formation of the protective layer according to an embodiment of the present invention; combined with Figure 3 Detailed steps S20 are described below. Figure 3As shown, a protective layer 14 is formed, which at least covers the top surface of the gate 12. In this embodiment, the protective layer 14 covers the top surface of the gate 12 and the top surface and sidewalls of the logic sidewall 13. Ideally, the boundary of the protective layer 14 is located in the middle of the logic sidewall 13, that is, the boundary of the implantation of the high-voltage lightly doped drain region defined by the photomask is located in the middle of the logic sidewall 13. However, in actual production, there are overlay deviations, and the overlay deviation between the protective layer 14 and the gate 12 does not exceed half the width of the logic sidewall 13. That is, in an irrational case, the protective layer 14 covers the top surface of the gate 12, a portion of the top surface of one side of the logic sidewall 13, and the top surface and sidewalls of the other side of the logic sidewall 13, wherein the portion of the top surface of one side of the logic sidewall 13 is not less than half the width of the top surface of the logic sidewall 13. The material of the protective layer 14 includes at least one of photoresist, SOC (Spin On Carbon), and BARC (Bottom Anti-Reflective Coating).
[0035] Figure 4 This is a schematic diagram of the embedded flash memory structure after forming a high-voltage lightly doped drain region under ideal conditions according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the embedded flash memory structure after forming a high-voltage lightly doped drain region under a non-ideal condition according to an embodiment of the present invention; combined with Figure 4 and Figure 5 Detailed steps S30 are described below. For example... Figure 4 and Figure 5 As shown, an ion implantation process is performed to form a high-voltage lightly doped drain region 15 within the substrate 10 beneath the gate 12 and the logic sidewall 13. During the ion implantation process, the protective layer 14 protects the gate 12. The doping type of the high-voltage lightly doped drain region 15 is opposite to that of the substrate 10. That is, if the substrate 10 has a first doping type, then the high-voltage lightly doped drain region 15 has a second doping type. When the first doping type is P-type, the second doping type is N-type. In other words, if the substrate 10 has a P-type doping type, then the high-voltage lightly doped drain region 15 has an N-type doping type, meaning the ion implantation process is an HVNLDD process. In the HVNLDD process, the doping ion is, for example, P (phosphorus), the implantation energy is, for example, 20 keV to 160 keV, and the implantation dose is 5E12 Atom / cm². 2 Up to 5E14Atom / cm 2When the first doping type is N-type, the second doping type is P-type. That is, when the substrate 10 is N-type doped, the high-voltage lightly doped drain region 15 is P-type doped, meaning the ion implantation process is HVPLDD. In the HVPLDD process, the doping ions are, for example, B or BF2, the implantation energy is, for example, 10 keV to 60 keV, and the implantation dose is 5E12 Atom / cm². 2 Up to 5E14Atom / cm 2 The implantation depth for both HVNLDD and HVPLDD processes ranges from 200 angstroms to 2000 angstroms.
[0036] like Figure 4 As shown, in the ion implantation process for forming the high-voltage lightly doped drain region 15, since the gate 12 is protected by the protective layer 14, the implantation energy of the high-voltage lightly doped drain region 15 is not affected by the thickness of the gate 12. Figure 5 As shown, although the boundary of the protective layer 14 is deviated due to the overlay accuracy of the non-self-aligned method, the logic sidewall 13 is usually made of silicon nitride. Silicon nitride has a high blocking ability for implanted ions (the blocking ability of silicon nitride for implanted ions is about 3 times that of photoresist). Therefore, on the side exposed by the logic sidewall 13, the implanted ions are blocked by the logic sidewall 13 and confined to the vicinity of the boundary of the logic sidewall 13. On the side covered by the protective layer 14 (photoresist), since the photoresist has a relatively weaker ability, high-energy implanted ions can penetrate the photoresist but are blocked by the logic sidewall 13 and confined to the vicinity of the boundary of the logic sidewall 13. Therefore, the self-alignment effect still exists, reducing the asymmetry of high-voltage devices caused by non-self-aligned implantation. Even if the deviation of the protective layer area exceeds the coverage range, such as the protective layer 14 not completely covering the top surface of the gate 12 and being penetrated by implanted ions, the partial penetration will not have a significant impact on the device performance due to the large area of the high-voltage device, ensuring mass production capability.
[0037] Figure 6 This is a schematic diagram of the embedded flash memory structure after the source and drain regions are formed according to an embodiment of the present invention. Figure 6 As shown, after forming the high-voltage lightly doped drain region 15, a source region 17 and a drain region 16 are formed, located within the substrate 10 on both sides of the gate 12. The doping type of the source region 17 and the drain region 16 is the same as that of the high-voltage lightly doped drain region 15. The doping type of the source region 17 and the drain region 16 is opposite to that of the substrate 10. That is, when the substrate 10 is P-type doped, the source region 17 and the drain region 16 are N-type doped. When the substrate 10 is N-type doped, the source region 17 and the drain region 16 are P-type doped.
[0038] Please continue to refer to this. Figure 6 This embodiment also provides an embedded flash memory, which is fabricated using the embedded flash memory formation method described in any one of the above embodiments, including:
[0039] A substrate 10 is provided, on which a gate 12 and logic sidewalls 13 located on both sides of the gate 12 are formed. The gate 12 is made of polysilicon, and the logic sidewalls 13 include a first logic sidewall and a second logic sidewall. Both the first logic sidewall and the second logic sidewall are ON (silicon oxide and silicon nitride) structures.
[0040] Gate oxide layer 11, wherein the gate oxide layer 11 is located between the substrate 10 and the gate 12;
[0041] A high-voltage lightly doped drain region 15 is located within the substrate 10 below the gate 12 and the logic sidewall 13. The doping type of the high-voltage lightly doped drain region 15 is opposite to that of the substrate. The implantation depth of the high-voltage lightly doped drain region 15 is 200 angstroms to 2000 angstroms. The high-voltage lightly doped drain region 15 can be HVNLDD or HVPLDD. The implantation energy of HVNLDD is, for example, 20 keV to 160 keV; the implantation energy of HVPLDD is, for example, 10 keV to 60 keV.
[0042] Drain region 16 is located in the substrate 10 under the logic sidewall 13 on one side. The doping type of drain region 16 is the same as that of high voltage lightly doped drain region 15, and the doping type of drain region 16 is opposite to that of substrate 10.
[0043] Source region 17 is located within the substrate 10 below the logic sidewall 13 on the other side. The doping type of source region 17 is the same as that of the high-voltage lightly doped drain region 15, and the doping type of source region 17 is opposite to that of substrate 10.
[0044] In summary, in the embedded flash memory formation method provided in the embodiments of the present invention, a substrate is provided, on which a gate and logic sidewalls located on both sides of the gate are formed; a protective layer is formed, the protective layer at least covering the top surface of the gate; an ion implantation process is performed to form a high-voltage lightly doped drain region in the substrate under the gate and the logic sidewalls, wherein the protective layer is used to protect the gate in the ion implantation process. After the gate and logic sidewalls are formed, this invention uses a non-self-aligned method, that is, by defining the implantation boundary of the high-voltage lightly doped drain region using a photomask, which is located near the middle position of the logic sidewall. In the ion implantation process for forming the high-voltage lightly doped drain region, the protective layer protects the gate. Therefore, the implantation energy of the high-voltage lightly doped drain region is not affected by the gate thickness. Although the boundary of the protective layer is deviated due to the overlay accuracy, the logic sidewall is usually made of silicon nitride, which has a high blocking ability for ion implantation. Therefore, on the side exposed to the logic sidewall, the implanted ions are blocked by the logic sidewall and confined to the vicinity of the logic sidewall boundary. On the side covered by the protective layer, since the protective layer has a relatively weaker ability, high-energy implanted ions can penetrate the protective layer but are blocked by the logic sidewall and confined to the vicinity of the logic sidewall boundary. Therefore, the self-alignment effect still exists, reducing the gate asymmetry caused by non-self-aligned implantation.
[0045] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.
[0046] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for forming an embedded flash memory, characterized in that, include: A substrate is provided on which a gate and logic sidewalls located on both sides of the gate are formed; A protective layer is formed, the protective layer at least covering the top surface of the gate; An ion implantation process is performed to form a high-voltage lightly doped drain region within the substrate under the gate and the logic sidewall, wherein the protective layer is used to protect the gate during the ion implantation process.
2. The method for forming embedded flash memory as described in claim 1, characterized in that, The protective layer covers the top surface of the gate and the top surface and sidewalls of the logic sidewalls.
3. The method for forming embedded flash memory as described in claim 2, characterized in that, The protective layer covers the top surface of the gate, a portion of the top surface of one logic sidewall, and the top surface and sidewall of the other logic sidewall.
4. The method for forming embedded flash memory as described in claim 3, characterized in that, The overlay deviation between the protective layer and the gate does not exceed half the width of the logic sidewall.
5. The method for forming embedded flash memory as described in any one of claims 1 to 4, characterized in that, The material of the protective layer includes at least one of photoresist, SOC, and BARC.
6. The method for forming embedded flash memory as described in claim 1, characterized in that, The doping type of the high-voltage lightly doped drain region is opposite to that of the substrate.
7. The method for forming embedded flash memory as described in claim 1, characterized in that, The ion implantation process for forming the high-voltage lightly doped drain region includes either the HVNLDD process or the HVPLDD process. The implantation energy of the HVNLDD process is 20 keV to 160 keV, and the implantation dose of the HVNLDD process is 5E12 Atom / cm². 2 Up to 5E14Atom / cm 2 The HVPLDD process uses an implantation energy of 10 keV to 60 keV and an implantation dose of 5E12 atm / cm². 2 Up to 5E14Atom / cm 2 .
8. The method for forming embedded flash memory as described in claim 1, characterized in that, The implantation depth of the high-voltage lightly doped drain region is 200 angstroms to 2000 angstroms.
9. The method for forming embedded flash memory as described in claim 1, characterized in that, After forming the high-voltage lightly doped drain region, a source region and a drain region are formed. The source region and the drain region are located in the substrate on both sides of the gate. The doping type of the source region and the drain region is the same as that of the high-voltage lightly doped drain region, and the doping type of the source region and the drain region is opposite to that of the substrate.
10. An embedded flash memory, characterized in that, It is prepared by the method for forming embedded flash memory as described in any one of claims 1 to 9.