Ferroelectric field effect transistor, memory device including same, and electronic apparatus including same

Abstract

A ferroelectric field effect transistor (FeFET), a memory device including the FeFET, and an electronic apparatus including the FeFET are provided. The FeFET includes a gate electrode, a ferroelectric layer disposed on the gate electrode, an intermediate conductive layer disposed on the ferroelectric layer, a gate insulating layer disposed on the intermediate conductive layer, a channel layer disposed on the gate insulating layer, and a source electrode and a drain electrode disposed on the channel layer. The source electrode and the drain electrode are each in contact with the gate insulating layer.

Description

Technical Field

[0001] This disclosure relates to ferroelectric field-effect transistors (FeFETs), memory devices including FeFETs, and electronic devices including FeFETs. Background Technology

[0002] Ferroelectrics are materials that exhibit ferroelectric properties. That is, even without an externally applied electric field, ferroelectrics maintain spontaneous polarization by aligning their internal dipole moments. Typically, ferroelectrics possess spontaneous dipoles (electric dipoles) within their crystalline material structure, i.e., spontaneous polarization, because the charge distribution within the unit cell is non-centrosymmetric. Therefore, even when no external electric field is applied to a ferroelectric material, it exhibits residual polarization due to the dipoles. Recently, research has been conducted on the application of ferroelectric field-effect transistors (FeFETs) in memory devices. FeFETs are semiconductor devices with memory characteristics achieved by controlling the threshold voltage according to the polarization direction of the ferroelectric material using a ferroelectric material as the gate insulating film. FeFETs offer advantages such as low operating voltage and fast programming speed. Summary of the Invention

[0003] Ferroelectric field-effect transistors (FeFETs) are provided, as well as memory devices including FeFETs and electronic devices including FeFETs.

[0004] Other aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0005] According to one aspect of this disclosure, a FeFET includes: a gate electrode; a ferroelectric layer on the gate electrode; an intermediate conductive layer on the ferroelectric layer such that the ferroelectric layer is between the intermediate conductive layer and the gate electrode; a gate insulating layer on the intermediate conductive layer such that the intermediate conductive layer is between the gate insulating layer and the ferroelectric layer; a channel layer on the gate insulating layer such that the gate insulating layer is between the channel layer and the intermediate conductive layer; a source electrode and a drain electrode, both of which are in direct contact with the gate insulating layer.

[0006] The channel layer can define a first via and a second via. The source electrode can contact the gate insulating layer through the first via, and the drain electrode can contact the gate insulating layer through the second via.

[0007] The channel layer may include at least one of group IV semiconductors, group III-V semiconductor compounds, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional (2D) semiconductors, quantum dots, and organic semiconductors.

[0008] The channel layer may include a doped region that contacts at least one of the source electrode and the drain electrode.

[0009] The interface layer may be located between the channel layer and at least one of the source electrode and the drain electrode.

[0010] Each of the gate electrode and the intermediate conductive layer may independently comprise at least one of a metal, a metal nitride, a metal oxide, and highly doped polysilicon.

[0011] The ferroelectric layer may include at least one of fluorite-based ferroelectric materials, nitride-based ferroelectric materials, and perovskite-based ferroelectric materials.

[0012] The gate insulating layer may include at least one of silicon oxide, silicon nitride, hafnium oxide, and zirconium oxide.

[0013] According to another aspect of this disclosure, a memory device includes a plurality of memory cells perpendicular to a substrate, each of the plurality of memory cells including: a gate electrode; a ferroelectric layer on the gate electrode; an intermediate conductive layer on the ferroelectric layer such that the ferroelectric layer is located between the intermediate conductive layer and the gate electrode; a gate insulating layer on the intermediate conductive layer such that the intermediate conductive layer is located between the gate insulating layer and the ferroelectric layer; a channel layer on the gate insulating layer such that the gate insulating layer is located between the channel layer and the intermediate conductive layer; and a source electrode and a drain electrode on the channel layer, both of the source electrode and the drain electrode being in direct contact with the gate insulating layer.

[0014] Each of the source and drain electrodes can be configured to extend in a direction perpendicular to the substrate and be shared by multiple memory cells.

[0015] The source electrode and the drain electrode can be spaced apart from each other in a first direction parallel to the substrate.

[0016] The gate electrode, ferroelectric layer, intermediate conductive layer, gate insulating layer and channel layer can be stacked in a second direction parallel to the substrate.

[0017] The gate electrode, ferroelectric layer, intermediate conductive layer, gate insulating layer, and channel layer can be disposed on both sides of each of the source electrode and the drain electrode.

[0018] The gate electrode, ferroelectric layer, intermediate conductive layer, gate insulating layer, and channel layer can be disposed on one side of each of the source electrode and the drain electrode.

[0019] The gate electrode can be configured to extend in a direction perpendicular to the substrate and be shared by multiple memory cells.

[0020] The source and drain electrodes can be spaced apart from each other in a direction parallel to the substrate.

[0021] The ferroelectric layer, intermediate conductive layer, and gate insulating layer can surround the gate electrode.

[0022] The channel region may include a doped region that is in contact with at least one of the source electrode and the drain electrode.

[0023] The interface layer may be located between the channel layer and at least one of the source electrode and the drain electrode.

[0024] According to another aspect of this disclosure, an electronic device is provided, which includes processing circuitry and the storage device described above.

[0025] According to another aspect of this disclosure, a method of manufacturing a memory device includes: alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate; forming vias perpendicular to the substrate that penetrate the plurality of interlayer insulating layers and the plurality of sacrificial layers; forming a plurality of recesses by etching the plurality of sacrificial layers exposed by the vias; forming an intermediate conductive layer to fill the interior of each of the plurality of recesses; sequentially forming a gate insulating layer and a channel layer on the inner wall of the vias, and forming a filling insulating layer inside the channel layer to fill the vias; after removing each of the plurality of sacrificial layers, sequentially forming a ferroelectric layer and a gate electrode in the intermediate conductive layer; forming source vias and drain vias by etching the filling insulating layer and the channel layer perpendicular to the substrate; and forming source electrodes and drain electrodes to fill the source vias and drain vias.

[0026] Each of the source and drain electrodes can be formed to contact the gate insulating layer.

[0027] Each of the source and drain electrodes can be formed to extend in a direction perpendicular to the substrate.

[0028] The source electrode and the drain electrode can be formed to be spaced apart from each other in a first direction parallel to the substrate.

[0029] The gate electrode, ferroelectric layer, intermediate conductive layer, gate insulating layer and channel layer can be stacked in a second direction parallel to the substrate.

[0030] The channel layer may include at least one of group IV semiconductors, group III-V semiconductor compounds, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, 2D semiconductors, quantum dots, or organic semiconductors.

[0031] Each of the gate electrode and the intermediate conductive layer may independently comprise at least one of a metal, a metal nitride, a metal oxide, or highly doped polysilicon.

[0032] The ferroelectric layer may include at least one of fluorite-based ferroelectric materials, nitride-based ferroelectric materials, or perovskite-based ferroelectric materials.

[0033] According to another aspect of this disclosure, a method of manufacturing a memory device includes: alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate; forming vias perpendicular to the substrate that penetrate the plurality of interlayer insulating layers and the plurality of sacrificial layers; forming a plurality of recesses by etching the plurality of sacrificial layers exposed by the vias; sequentially forming a channel layer, a gate insulating layer, and an intermediate conductive layer to fill the interior of each of the plurality of recesses; forming a ferroelectric layer on the inner wall of the vias; and forming a gate electrode inside the ferroelectric layer to fill the vias; after removing each of the plurality of sacrificial layers, exposing a portion of the gate insulating layer by etching a portion of the channel layer; and forming a source electrode and a drain electrode on the channel layer to contact the exposed portion of the gate insulating layer.

[0034] The gate electrode can be formed to extend in a direction perpendicular to the substrate.

[0035] The source electrode and the drain electrode can be formed to be spaced apart from each other in a direction parallel to the substrate.

[0036] The ferroelectric layer, intermediate conductive layer, and gate insulating layer can be formed around the gate electrode.

[0037] The channel layer may include at least one of group IV semiconductors, group III-V semiconductor compounds, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, 2D semiconductors, quantum dots, or organic semiconductors.

[0038] Each of the gate electrode and the intermediate conductive layer may independently comprise at least one of a metal, a metal nitride, a metal oxide, or highly doped polysilicon.

[0039] The ferroelectric layer may include fluorite-based ferroelectric materials, nitride-based ferroelectric materials, or perovskite-based ferroelectric materials. Attached Figure Description

[0040] The above and other aspects, features and advantages of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0041] Figure 1 This is a schematic cross-sectional view of a ferroelectric field-effect transistor (FeFET) according to at least one example embodiment;

[0042] Figure 2 This is a cross-sectional view of the FeFET based on the comparative example;

[0043] Figure 3 This is a cross-sectional view of a FeFET according to at least one example embodiment;

[0044] Figure 4 This is a cross-sectional view of a FeFET according to at least one example embodiment;

[0045] Figure 5AThis is a plan view illustrating a storage device according to at least one example embodiment;

[0046] Figure 5B It shows Figure 5A The planar structure of each memory cell in the shown memory device;

[0047] Figure 5C It is along Figure 5A A cross-sectional view taken from line I-I';

[0048] Figure 6 It is a plan view of a storage device according to at least one example embodiment;

[0049] Figure 7A It is a plan view of a storage device according to at least one example embodiment;

[0050] Figure 7B It is along Figure 7A A cross-sectional view taken from line II-II';

[0051] Figures 8A to 16B This is a diagram illustrating a method of manufacturing a storage device according to at least one example embodiment;

[0052] Figures 17A to 26B This is a diagram illustrating a method of manufacturing a storage device according to at least one example embodiment;

[0053] Figure 27 It is a conceptual diagram that schematically illustrates a device architecture applicable to electronic devices;

[0054] Figure 28 It is a block diagram of a storage system according to at least one example embodiment; and

[0055] Figure 29 It is a block diagram of a neuromorphic device and an external device connected thereto, according to at least one example embodiment. Detailed Implementation

[0056] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always denote the same elements. In this respect, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain various aspects. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire list of elements when preceding it and do not modify individual elements in the list.

[0057] In the following detailed description, embodiments are given with reference to the accompanying drawings. In the drawings below, the same reference numerals denote the same constituent elements, and the dimensions of each constituent element may be exaggerated for ease of explanation and clarity. The embodiments described below are exemplary, and other modifications may be made from them. Additionally, when the terms “about” or “substantially” are used in conjunction with numerical and / or geometric terms in this specification, the numerical values ​​intended to be associated include manufacturing tolerances (e.g., ±10%) around said values. Furthermore, regardless of whether numerical and / or geometric terms are modified to “about” or “substantially,” it should be understood that these values ​​should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around said values ​​and / or geometry.

[0058] When a component is positioned “above” or “on top” another component, the component may be directly on or above the other component, either directly or in a non-contact manner. Furthermore, spatial relative terms, such as above, below, etc., are used herein based on the orientations shown in the accompanying drawings and may be used in other ways when the orientation of the respective objects changes. In other words, such spatial relative terms are intended to cover different orientations of the device in use or operation, in addition to those depicted in the accompanying drawings, such that the device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative terms used herein are interpreted accordingly.

[0059] As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated feature or element, but do not exclude the presence or addition of one or more other features or elements.

[0060] In the context of describing this disclosure, the terms “a,” “the,” and similar indicators should be interpreted to cover both singular and plural. Furthermore, unless otherwise stated herein or the context clearly contradicts it, the operations of all methods described herein can be performed in any suitable order. This disclosure is not limited to the order of the described steps.

[0061] Furthermore, terms such as “…part,” “…unit,” “…module,” and “…block” used in this disclosure may refer to a unit configured to perform at least one function or operation, and such unit may be embodied in and / or include a processing circuitry system, such as hardware, software, or a combination of hardware and software. For example, the processing circuitry may include, but is not limited to, a central processing unit (CPU), an application processor (AP), an arithmetic logic unit (ALU), a graphics processing unit (GPU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, or an application-specific integrated circuit (ASIC), unless otherwise expressly stated.

[0062] Furthermore, the connecting lines or connectors shown in the various accompanying figures are intended to represent functional relationships and / or physical or logical connections between various components. It should be noted that many alternative or additional functional relationships, physical connections, or logical connections may exist in actual devices.

[0063] Unless otherwise stated, any and all examples or language (e.g., "such as") provided herein are intended only to better illustrate this disclosure and do not constitute a limitation on the scope of this disclosure.

[0064] A ferroelectric field-effect transistor (FeFET) is a semiconductor device that exhibits non-volatile memory characteristics by utilizing the phenomenon that the threshold voltage of the transistor changes through spontaneous polarization switching. A FeFET can have a minimum threshold voltage and a maximum threshold voltage determined by the polarization state of the ferroelectric material, and the difference between the minimum and maximum threshold voltages can be a memory window (MW) corresponding to the sensing margin.

[0065] Figure 1 This is a schematic cross-sectional view of FeFET 100 according to at least one example embodiment. Figure 1 The FeFET 100 shown can be referred to as having a metal ferroelectric metal-insulator semiconductor (MFMIS) structure. For example, each memory cell of a memory device comprising multiple memory cells may include... Figure 1 The FeFET 100 is shown. Furthermore, as mentioned above, the FeFET 100 may also be referred to as a semiconductor device herein.

[0066] Reference Figure 1 The FeFET 100 may include a gate electrode 110, a ferroelectric layer 120, an intermediate conductive layer 130, a gate insulating layer 140, a channel layer 150, a source electrode 161, and a drain electrode 162, which are stacked in sequence.

[0067] The gate electrode 110 comprises a conductive material (e.g., a zero-bandgap material, etc.). For example, the gate electrode 110 may comprise a metal, a metal nitride, a metal oxide, polycrystalline silicon, etc. For example, the gate electrode 110 may comprise at least one of W, TiN, TaN, WN, NbN, Mo, Ru, Ir, RuO, IrO, and / or highly doped polycrystalline silicon. However, this disclosure is not limited thereto. The gate electrode 110 may have a stacked structure of various materials. For example, the gate electrode 110 may have a stacked structure of metal nitride layers / metal layers such as TiN / W. However, this is merely an example, and this disclosure is not limited thereto.

[0068] A ferroelectric layer 120 is disposed on the gate electrode 110. The ferroelectric layer 120 includes a ferroelectric material. As mentioned above, a ferroelectric material is a material exhibiting ferroelectric properties, that is, the internal electric dipole moments of the ferroelectric material are aligned to maintain spontaneous polarization. Even without an externally applied electric field, the ferroelectric material possesses residual polarization due to the dipoles. In a ferroelectric material, the polarization direction can be switched on a domain-by-domain basis by applying an external electric field.

[0069] The ferroelectric layer 120 may include, for example, fluorite-based materials, nitride-based materials, and / or perovskite-based materials. Fluorite-based materials may include at least one non-centrosymmetric phase selected from, for example, hafnium oxide (HfO), zirconium oxide (ZrO), and / or hafnium zirconium oxide (HfZrO). Nitride-based materials may include, for example, AlScN. Perovskite-based materials may include lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), barium titanate (BTO), and the like. The ferroelectric layer 120 may further include some kind of dopant. The dopant may include, for example, at least one selected from, La, Y, Gd, Si, Al, Mg, Sr, and / or Ba. However, these are merely examples, and this disclosure is not limited thereto.

[0070] An intermediate conductive layer 130 is disposed on the ferroelectric layer 120. The intermediate conductive layer 130 can serve as a floating electrode. The intermediate conductive layer 130 contains a conductive material similar to that of the gate electrode 110. For example, the intermediate conductive layer 130 may include a metal, a metal nitride, a metal oxide, polysilicon, etc. For example, the intermediate conductive layer 130 may include at least one of W, TiN, TaN, WN, NbN, Mo, Ru, Ir, RuO, IrO, and / or highly doped polysilicon. However, this disclosure is not limited thereto. The intermediate conductive layer 130 may include the same material as the gate electrode 110, but is not limited thereto; the intermediate conductive layer 130 may include a material different from that of the gate electrode 110.

[0071] A gate insulating layer 140 is disposed on the intermediate conductive layer 130. The gate insulating layer 140 includes an insulator, such as at least one selected from silicon oxide (SiO), silicon nitride (SiN), hafnium oxide (HfO), and / or zirconium oxide (ZrO). However, this is merely an example, and the present disclosure is not limited thereto.

[0072] A channel layer 150 is disposed on a gate insulating layer 140. The channel layer 150 includes a semiconductor, such as a group IV semiconductor like Si, Ge, SiGe, etc., and / or a group III-V semiconductor compound. In at least one example embodiment, the channel layer 150 may include, for example, an oxide semiconductor (such as indium gallium zinc oxide (IGZO)), a nitride semiconductor, and / or an oxide nitride semiconductor. In at least one example embodiment, the channel layer 150 may include, for example, a two-dimensional (2D) semiconductor material, quantum dots, and / or an organic semiconductor. A 2D semiconductor material is a semiconductor material having a layered structure in which the constituent atoms are 2D bonded. A 2D semiconductor material may include, for example, a transition metal dichalcogenide (TMD), which is a compound of a transition metal and a chalcogenide. The channel layer 150 may also include a dopant. Here, the dopant may include a p-type dopant or an n-type dopant. A p-type dopant may include, for example, B, Al, Ga, In, etc., and an n-type dopant may include, for example, P, As, Sb, etc. However, the above materials are merely examples, and this disclosure is not limited thereto.

[0073] Source electrode 161 and drain electrode 162 are disposed on channel layer 150. Source electrode 161 and drain electrode 162 may be disposed on opposite sides of channel layer 150, and a channel may be formed between source electrode 161 and drain electrode 162. The channel may be configured to electrically connect source electrode 161 and drain electrode 162 when switched on. Source electrode 161 and drain electrode 162 are configured to contact gate insulating layer 140 through channel layer 150.

[0074] For example, a first via 161a and a second via 162a are formed on both sides of the channel layer 150, exposing the upper surface of the gate insulating layer 140; and the source electrode 161 is configured to contact the upper surface of the gate insulating layer 140 through the first via 161a, and the drain electrode 162 is configured to contact the upper surface of the gate insulating layer 140 through the second via 162a. Additionally, the source electrode 161 and the drain electrode 162 are configured to contact the channel layer 150. Similar to the gate electrode 110 and the intermediate conductive layer 130, the source electrode 161 and the drain electrode 162 may each comprise a conductive material.

[0075] In the FeFET 100 according to at least one example embodiment, the source electrode 161 and drain electrode 162 are configured to be in direct contact with the gate insulating layer 140. Therefore, a metal-ferroelectric-metal-insulator-metal (MFMIM) structure can be formed in region A1 where the source electrode 161 is located and region A2 where the drain electrode 162 is located. Because the source electrode 161 and drain electrode 162 are in direct contact with the gate insulating layer 140, there is no channel depletion region between the source / drain electrodes 161 and 162 and the gate insulating layer 140, thereby reducing the write voltage and / or increasing the write speed.

[0076] Figure 2 This is a cross-sectional view of the FeFET 10 based on the comparative example. The following mainly describes the differences from the embodiments described above.

[0077] Reference Figure 2 The source electrode 61 and drain electrode 62 are respectively disposed on both sides of the channel layer 150. Here, the source electrode 61 and drain electrode 62 are disposed on the upper part of the channel layer 150, in contact with the channel layer 150, and / or spaced apart from the gate insulating layer 140. That is, as referenced above... Figure 1 Unlike at least one of the described example embodiments, the source electrode 61 and drain electrode 62 are configured not to contact the gate insulating layer 140.

[0078] In the FeFET 10 according to the comparative example, the source electrode 61 and drain electrode 62 are configured to contact the channel layer 150 but not the gate insulating layer 140, and thus a metal-ferroelectric-metal-insulator-semiconductor-metal (MFMISM) structure can be formed in the A1 region where the source electrode 61 is located and the A2 region where the drain electrode 62 is located. In this structure, when the charge for shielding ferroelectric polarization is insufficient in the channel material, a depletion region is formed in the channel layer 150 between the source / drain electrodes 61 and 62 and the gate insulating layer 140, thereby reducing the capacitance, and thus the voltage required to change the ferroelectric polarization may increase.

[0079] However, in the FeFET 100 according to at least one of the above example embodiments, the source electrode 161 and the drain electrode 162 are in direct contact with the gate insulating layer 140, and therefore there is no channel depletion region between the source / drain electrodes 161 and 162 and the gate insulating layer 140, thereby reducing the write voltage and / or increasing the write speed.

[0080] Figure 3 This is a cross-sectional view of the FeFET 200 according to at least one example embodiment. In the following description, the main focus will be on... Figure 1 The differences shown are those of the FeFET 100.

[0081] Reference Figure 3A source electrode 161 and a drain electrode 162 are respectively disposed on opposite sides of the channel layer 150. The source electrode 161 and drain electrode 162 are configured to contact the upper surface of the gate insulating layer 140 through the channel layer 150. Additionally, the source electrode 161 and drain electrode 162 are configured to contact the channel layer 150. When the channel layer 150 comprises, for example, a group IV semiconductor such as Si, a first doped region 171 contacting the source electrode 161 can be formed in the channel layer 150, and a second doped region 172 contacting the drain electrode 162 can be formed in the channel layer 150. The first doped region 171 can reduce the contact resistance between the source electrode 161 and the channel layer 150, and the second doped region 172 can reduce the contact resistance between the drain electrode 162 and the channel layer 150.

[0082] The first doped region 171 and the second doped region 172 may be doped with p-type dopant or n-type dopant. For example, when the channel layer 150 includes a p-type semiconductor, the first doped region 171 and the second doped region 172 may be doped with n-type dopant, and when the channel layer 150 includes an n-type semiconductor, the first doped region 171 and the second doped region 172 may be doped with p-type dopant.

[0083] Figure 4 This is a cross-sectional view of the FeFET 300 according to at least one example embodiment. In the following description, the main focus will be on... Figure 1 The differences shown are those of the FeFET 100.

[0084] Reference Figure 4 A source electrode 161 and a drain electrode 162 are respectively disposed on opposite sides of the channel layer 150. The source electrode 161 and drain electrode 162 are configured to contact the upper surface of the gate insulating layer 140 through the channel layer 150. Additionally, the source electrode 161 and drain electrode 162 are configured to contact the channel layer 150. When the channel layer 150 comprises an oxide semiconductor such as IGZO, a first interface layer 181 can be formed between the source electrode 161 and the channel layer 150, and a second interface layer 182 can be formed between the drain electrode 162 and the channel layer 150. The first interface layer 181 can reduce the contact resistance between the source electrode 161 and the channel layer 150, and the second interface layer 182 can reduce the contact resistance between the drain electrode 162 and the channel layer 150. The first interface layer 181 and the second interface layer 182 may each comprise a conductive oxide such as ITO, but the examples are not limited thereto.

[0085] Figure 5A This is a plan view showing a storage device 500 according to at least one example embodiment. Figure 5B The planar structure of each storage cell MC of the storage device 500 according to at least one example embodiment is shown. Figure 5C It is along Figure 5AThe cross-sectional view taken from line I-I'. Figures 5A to 5C The storage device 500 shown may be a three-dimensional (3D) ferroelectric storage device (e.g., a vertical NAND flash memory device).

[0086] Reference Figures 5A to 5C The storage device 500 includes a plurality of cell arrays CA disposed on a substrate 501. Figure 5A and 5C Two cell arrays CA are shown, but the invention is not limited thereto, and the memory device 100 may include various numbers of cell arrays CA. Each cell array CA includes a plurality of memory cells MC stacked in a direction perpendicular to the substrate 501 (z-axis direction), and each memory cell MC may include a FeFET having the MFMIS structure described above. Furthermore, the two cell arrays CA are shown as staggered; however, this disclosure is not limited thereto.

[0087] Substrate 501 may comprise various materials. For example, substrate 501 may comprise a single-crystal silicon substrate, a compound semiconductor substrate, and / or a silicon-on-insulator (SOI) substrate. However, these are merely examples, and substrate 501 may be made of a variety of materials. Furthermore, substrate 501 may also comprise, for example, impurity regions caused by doping, electronic devices such as transistors, and / or peripheral circuitry for selecting and controlling storage cells that store data.

[0088] Multiple memory cells MC are stacked in a direction perpendicular to the substrate 501 (z-axis direction), and each memory cell MC includes a gate electrode 510, a ferroelectric layer 520, an intermediate conductive layer 530, a gate insulating layer 540, a channel layer 550, a source electrode 561, and a drain electrode 562. Here, the gate insulating layer 540, the channel layer 550, the source electrode 561, and the drain electrode 562 can be configured to extend in a direction perpendicular to the substrate 501, and therefore can be shared by multiple memory cells MC.

[0089] The gate electrode 510 comprises a conductive material. For example, the gate electrode 510 may comprise a metal, a metal nitride, a metal oxide, polycrystalline silicon, etc. For example, the gate electrode 510 may comprise at least one of W, TiN, TaN, WN, NbN, Mo, Ru, Ir, RuO, IrO, and highly doped polycrystalline silicon. However, this disclosure is not limited thereto.

[0090] The ferroelectric layer 520 includes a ferroelectric material, such as a fluorite-based ferroelectric material, a nitride-based ferroelectric material, and / or a perovskite-based ferroelectric material. The fluorite-based material may include at least one of, for example, hafnium oxide (HfO), zirconium oxide (ZrO), and hafnium zirconium oxide (HfZrO). The nitride-based material may include, for example, AlScN. The perovskite-based material may include, for example, PZT, SBT, BTO, etc. The ferroelectric layer 520 may also include a dopant. The dopant may include at least one of, for example, La, Y, Gd, Si, Al, Mg, Sr, and / or Ba. However, this disclosure is not limited thereto. The intermediate conductive layer 530 may include a conductive material. For example, the intermediate conductive layer 530 may include a metal, a metal nitride, a metal oxide, polycrystalline silicon, etc.

[0091] The gate insulating layer 540 includes an insulator, such as at least one of silicon oxide (SiO), silicon nitride (SiN), hafnium oxide (HfO), and / or zirconium oxide (ZrO). However, these are merely examples, and this disclosure is not limited thereto.

[0092] The channel layer 550 may include a semiconductor, such as group IV semiconductors like Si, Ge, and SiGe, group III-V semiconductor compounds, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, 2D semiconductor materials, quantum dots, and / or organic semiconductors. The channel layer 150 may also include a dopant. The source electrode 561 and drain electrode 562 may each comprise a conductive material.

[0093] Multiple first insulating layers 591 are stacked and spaced apart from each other in a direction perpendicular to the substrate 501 (z-axis direction), and a second insulating layer 592 may be disposed on the uppermost first insulating layer 591. In addition, multiple through holes H penetrating the first insulating layer 591 and the second insulating layer 592 are formed to extend in a direction perpendicular to the substrate 501 (z-axis direction).

[0094] Gate electrode 510, ferroelectric layer 520, and intermediate conductive layer 530 are stacked on each of the plurality of first insulating layers 591 in a direction parallel to substrate 501. Furthermore, gate insulating layer 540 extends in a direction perpendicular to substrate 501 (z-axis direction) and contacts intermediate conductive layer 530, and channel layer 550 extends in a direction perpendicular to substrate 501 (z-axis direction) and is disposed on gate insulating layer 540. Gate insulating layer 540 and channel layer 550 can be shared by multiple memory cells (MCs).

[0095] Source electrode 561 and drain electrode 562 are disposed on the inner wall of each via H, spaced apart from each other in a direction parallel to the substrate 501. Here, source electrode 561 and drain electrode 562 are configured to contact the gate insulating layer 540 and the channel layer 550. Source electrode 561 and drain electrode 562 are configured to extend in a direction perpendicular to the substrate 501 (z-axis direction) and can be shared by multiple memory cells MC. The via H between source electrode 561 and drain electrode 562 can be filled with a third insulating layer 593. The third insulating layer 593 can also be referred to as an internal support.

[0096] Source electrode 561 and drain electrode 562 are disposed on channel layer 550 and spaced apart from each other in a first direction (y-axis direction) parallel to substrate 501. Furthermore, gate electrode 510, ferroelectric layer 520, intermediate conductive layer 530, gate insulating layer 540, and channel layer 550 can be sequentially stacked in a second direction (x-axis direction) parallel to substrate 501. Gate electrode 510, ferroelectric layer 520, intermediate conductive layer 530, gate insulating layer 540, and channel layer 550 can be disposed on both sides of source / drain electrodes 561 and 562, respectively. Here, as... Figure 5B As shown, the gate electrode 510, ferroelectric layer 520, intermediate conductive layer 530, gate insulating layer 540, and channel layer 550 can be symmetrically arranged relative to the source electrode 561 and drain electrode 562. Furthermore, although not shown in the figures, doped regions can be further formed in the channel layer 550 that contacts the source electrode 561 and drain electrode 562, or an interface layer can be further formed between the source electrode 561 and drain electrode 562 and the channel layer 550.

[0097] In the memory device 500 according to the embodiment, the source electrode 561 and the drain electrode 562 are configured to be in direct contact with the gate insulating layer 540, and therefore there is no channel depletion region between the source electrode 561 and the drain electrode 562 and the gate insulating layer 540, thereby reducing the write voltage and / or increasing the write speed.

[0098] Figure 6 This is a plan view of a memory device 600 according to at least one example embodiment. In the following description, the description will primarily focus on the aforementioned... Figures 5A to 5C The differences in the storage device 500 shown.

[0099] In each memory cell MC of the aforementioned memory device 500, a gate electrode 510, a ferroelectric layer 520, an intermediate conductive layer 530, a gate insulating layer 540, and a channel layer 550 are respectively disposed on both sides of the source electrode 561 and the drain electrode 562. According to... Figure 6In each memory cell MC of the memory device 600 of the illustrated embodiment, a gate electrode 510, a ferroelectric layer 520, an intermediate conductive layer 530, a gate insulating layer 540, and a channel layer 550 are disposed on one side of the source electrode 561 and the drain electrode 562. Specifically, in the memory cell MC of the first cell array CA1, the gate electrode 510, ferroelectric layer 520, intermediate conductive layer 530, gate insulating layer 540, and channel layer 550 are disposed on the left side of the source electrode 561 and the drain electrode 562. In the memory cell MC of the second cell array CA2, the gate electrode 510, ferroelectric layer 520, intermediate conductive layer 530, gate insulating layer 540, and channel layer 550 are disposed on the right side of the source electrode 561 and the drain electrode 562.

[0100] The first cell array CA1 and the second cell array CA2 of the memory device 600 according to at least one example embodiment can be manufactured by dividing the source electrode 561 and drain electrode 562 of the cell array CA of the memory device 500 according to the above embodiment into two separate parts in a second direction (x-axis direction) parallel to the substrate. Therefore, the memory device 600 according to the embodiment can double the number of memory cells MC in the same area compared to the memory device 500 described above.

[0101] Figure 7A This is a plan view of a storage device 700 according to at least one example embodiment. Figure 7A It is a plan view of each cell array CA of the storage device 700 according to at least one example embodiment. Figure 7B It is along Figure 7A The cross-sectional view taken from line II-II'.

[0102] Reference Figure 7A and Figure 7B The storage device 700 includes a plurality of 2D cell arrays CA disposed on a substrate 701. Although for convenience... Figure 7B The diagram shows a cell array CA, but the memory device 700 may include a variety of numbers of cell arrays CA. Each cell array CA includes a plurality of memory cells MC stacked in a direction perpendicular to the substrate 701 (z-axis direction), and each memory cell MC may include a FeFET having the MFMIS structure described above.

[0103] Substrate 701 may comprise various materials. For example, substrate 701 may comprise a single-crystal silicon substrate, a compound semiconductor substrate, and / or an SOI substrate. Furthermore, substrate 701 may also comprise, for example, impurity regions induced by doping, electronic devices such as transistors, and / or peripheral circuitry for selecting and controlling storage cells that store data.

[0104] Multiple memory cells MC are stacked in a direction perpendicular to the substrate 701 (z-axis direction), and each memory cell MC includes a gate electrode 710, a ferroelectric layer 720, an intermediate conductive layer 730, a gate insulating layer 740, a channel layer 750, a source electrode 761, and a drain electrode 762. Here, the gate electrode 710 and the ferroelectric layer 720 can be configured to extend in a direction perpendicular to the substrate 701 (z-axis direction) and can be shared by multiple memory cells MC.

[0105] The gate electrode 710 includes a conductive material. For example, the gate electrode 710 may include a metal, a metal nitride, a metal oxide, polysilicon, etc. The ferroelectric layer 720 includes a ferroelectric material, such as a fluorite-based ferroelectric material, a nitride-based ferroelectric material, and / or a perovskite-based ferroelectric material. The ferroelectric layer 720 may further include a dopant. The intermediate conductive layer 730 may include a conductive material. The gate insulating layer 740 includes an insulator, such as at least one selected from silicon oxide (SiO), silicon nitride (SiN), hafnium oxide (HfO), and / or zirconium oxide (ZrO). The channel layer 750 includes a semiconductor, such as a group IV semiconductor, a group III-V semiconductor compound, an oxide semiconductor, a nitride semiconductor, an oxide nitride semiconductor, a 2D semiconductor material, a quantum dot, and / or an organic semiconductor. The channel layer 750 may further include a dopant. The source electrode 761 and the drain electrode 762 may each include a conductive material.

[0106] Multiple first insulating layers 791 are stacked and spaced apart from each other in a direction perpendicular to the substrate 701 (z-axis direction), and a second insulating layer 792 may be disposed in the uppermost first insulating layer 791. A via H penetrating the first insulating layer 791 and the second insulating layer 792 is formed to extend in a direction perpendicular to the substrate 701 (z-axis direction). Here, the via H may be formed to have, for example, a circular cross-section.

[0107] A ferroelectric layer 720 is disposed on the inner wall of the via H, and a gate electrode 710 is disposed within the via H inside the ferroelectric layer 720. The gate electrode 710 is configured to extend in a direction perpendicular to the substrate 701 (z-axis direction), and the ferroelectric layer 720 is configured to surround the gate electrode 710. The ferroelectric layer 720 may be provided to contact an intermediate conductive layer 730 disposed perpendicular to the substrate 701, which will be described below.

[0108] An intermediate conductive layer 730 and a gate insulating layer 740 are respectively disposed between a plurality of first insulating layers 791 to surround the ferroelectric layer 720, and a channel layer 750 is disposed in the gate insulating layer 740. Here, the channel layer 750 is provided to expose both sides of the gate insulating layer 740. A source electrode 761 and a drain electrode 762 are disposed on the channel layer 750 to be spaced apart from each other in a first direction (x-axis direction) parallel to the substrate 701. Specifically, the source electrode 761 is disposed on the channel layer 750 to contact a portion of the exposed gate insulating layer 740, and the drain electrode 762 is disposed on the channel layer 750 to contact another portion of the exposed gate insulating layer 740. Each of the source electrode 761 and the drain electrode 762 is configured to extend in a second direction (y-axis direction) parallel to the substrate 701 and can be shared by memory cells MC disposed in the direction (y-axis direction) parallel to the substrate 701. Meanwhile, although not shown in the accompanying drawings, a doped region in contact with the source electrode 761 and the drain electrode 762 may be further formed in the channel layer 750, or an interface layer may be further formed between the source electrode 761 and the drain electrode 762 and the channel layer 750.

[0109] In the memory device 700 according to at least one example embodiment, the source electrode 761 and the drain electrode 762 are configured to be in direct contact with the gate insulating layer 740, and therefore there is no channel depletion region between the source electrode 761 and the drain electrode 762 and the gate insulating layer 740, thereby reducing the write voltage and / or increasing the write speed.

[0110] Figures 8A to 16B This is a diagram used to explain a method of manufacturing a storage device 500 according to at least one example embodiment. Figures 8A to 16B The manufacturing process is shown in the diagram. Figures 5A to 5C The method of the storage device 500 shown.

[0111] Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A It is a cross-sectional view of the manufactured structure, and Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B and Figure 16B This is a plan view of the manufactured structure. (Refer to...) Figure 8A and Figure 8BMultiple interlayer insulating layers 591 and multiple sacrificial layers 595 are stacked alternately in a direction perpendicular to the substrate 501 (z-axis direction), and then an insulating layer 592 is stacked on top of them.

[0112] Substrate 501 may comprise various materials. For example, substrate 501 may comprise a single-crystal silicon substrate, a compound semiconductor substrate, and / or an SOI substrate. However, this is merely an example, and substrate 501 may be made of various materials. Furthermore, substrate 501 may also comprise, for example, impurity regions induced by doping, electronic devices such as transistors, and / or peripheral circuitry for selecting and controlling storage cells that store data.

[0113] Interlayer insulation layer 591 corresponds to Figure 5C The first insulating layer 591 shown above may include, but is not limited to, at least one of, for example, SiO, SiOC, and / or SiON. The sacrificial layer 595 may include a material having etch selectivity relative to the interlayer insulating layer 591. For example, the sacrificial layer 591 may include SiN, but is not limited to. The upper insulating layer 592 corresponds to... Figure 5C The second insulating layer 592 is shown, and can be configured to pattern the interlayer insulating layer 591 and the sacrificial layer 595. The upper insulating layer 592 may include a material that has etch selectivity relative to the interlayer insulating layer 591 and the sacrificial layer 595.

[0114] Reference Figure 9A and Figure 9B After the upper insulating layer 592 is patterned, the patterned upper insulating layer 592 is used as an etching mask to form multiple vias H that penetrate the interlayer insulating layer 591 and the sacrificial layer 595. Figure 9A and 9B Two vias H are shown. The vias H can be formed to extend in a direction perpendicular to the substrate 501 (z-axis direction). The side surfaces of the interlayer insulating layer 591 and the sacrificial layer 595 can be exposed through the vias H.

[0115] Reference Figure 10A and Figure 10B The recess R is formed by etching the side surface of the sacrificial layer 595 exposed by the via H. Here, each recess R can extend from the side surface of the sacrificial layer 595 to a certain depth parallel to the surface of the substrate 501.

[0116] Reference Figure 11A and Figure 11BAn intermediate conductive material layer 530' is formed to cover the side surfaces and recesses R of the interlayer insulating layer 591. Here, the intermediate conductive material layer 530' may include conductive materials such as metals, metal nitrides, metal oxides, and polycrystalline silicon. For example, the intermediate conductive material layer 530' may include at least one of W, TiN, TaN, WN, NbN, Mo, Ru, Ir, RuO, IrO, and / or highly doped polycrystalline silicon. However, this is merely an example, and the intermediate conductive material layer 530' may include a variety of other conductive materials.

[0117] Reference Figure 12A and Figure 12B Multiple intermediate conductive layers 530 are formed by etching intermediate conductive material layers 530' until the side surfaces of the interlayer insulating layer 591 are exposed. Each intermediate conductive layer 530 contacts the side surface of the sacrificial layer 595 and can be configured to fill the recess R.

[0118] Reference Figure 13A and 13B A gate insulating material layer 540' and a channel material layer 550' are sequentially formed to cover the upper surface of the upper insulating layer 592 and the inner wall of the via H. The gate insulating material layer 540' may include at least one of, for example, silicon oxide (SiO), silicon nitride (SiN), hafnium oxide (HfO), and / or zirconium oxide (ZrO). However, this is merely an example. For example, the channel material layer 550' may include group IV semiconductors, group III-V semiconductor compounds, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, 2D semiconductor materials, quantum dots, and / or organic semiconductors such as Si, Ge, SiGe, etc. The channel material layer 150' may further include a dopant.

[0119] Reference Figure 14A and Figure 14B After forming the filled insulating layer 593 to fill the via H, a planarization process is performed. The filled insulating layer 593 can correspond to... Figure 5C The third insulating layer 593 is shown. Therefore, the gate insulating layer 540 can be formed on the inner wall of each via H to contact the intermediate conductive layer 530, and the channel layer 550 can be formed in the gate insulating layer 540. Here, the gate insulating layer 540 and the channel layer 550 can be formed to extend in a direction perpendicular to the substrate 501 (z-axis direction).

[0120] Reference Figure 15A and Figure 15BAfter removing the sacrificial layer 595 between the interlayer insulating layers 591, a ferroelectric layer 520 and a gate electrode 510 are sequentially formed in the intermediate conductive layer 530 exposed by removing the sacrificial layer 595. The ferroelectric layer 520 may include, for example, a fluorite-based ferroelectric material, a nitride-based ferroelectric material, and / or a perovskite-based ferroelectric material. The fluorite-based material may include at least one of, for example, hafnium oxide (HfO), zirconium oxide (ZrO), and / or hafnium zirconium oxide (HfZrO). The nitride-based material may include, for example, AlScN. The perovskite-based material may include PZT, SBT, BTO, etc. The ferroelectric layer 520 may also include a dopant. The dopant may include at least one of, for example, La, Y, Gd, Si, Al, Mg, Sr, and / or Ba. However, this disclosure is not limited thereto. The gate electrode 510 may include a conductive material. For example, the gate electrode 510 may include a metal, a metal nitride, a metal oxide, polysilicon, etc. For example, the gate electrode 510 may include at least one of W, TiN, TaN, WN, NbN, Mo, Ru, Ir, RuO, IrO and / or highly doped polycrystalline silicon. However, this disclosure is not limited thereto.

[0121] Figure 16A It is along Figure 16B The cross-sectional view taken from line I-I'. (Refer to...) Figure 16A and Figure 16B Source vias (not shown) and drain vias (not shown) are formed by etching the filling insulating layer 593 and both sides of the channel layer 550 in a direction perpendicular to the substrate 501 (z-axis direction), respectively. Here, the source vias and drain vias can be formed to be spaced apart from each other in a first direction parallel to the substrate 501 (y-axis direction). The gate insulating layer 540 can be exposed through the source vias and drain vias. Subsequently, a source electrode 561 is formed to fill the source via, and a drain electrode 562 is formed to fill the drain via. Therefore, the source electrode 561 and drain electrode 562 can be formed to directly contact the gate insulating layer 540 on both sides of the channel layer 550.

[0122] The source electrode 561 and drain electrode 562 may each comprise a conductive material. The source electrode 561 and drain electrode 562 may be formed to extend in a direction perpendicular to the substrate 501 (z-axis direction). The source electrode 561 and drain electrode 562 may be formed to be spaced apart from each other in a first direction parallel to the substrate 501 (y-axis direction). The gate electrode 510, ferroelectric layer 520, intermediate conductive layer 530, gate insulating layer 540, and channel layer 550 may be sequentially stacked in a second direction parallel to the substrate 501 (x-axis direction). The gate electrode 510, ferroelectric layer 520, intermediate conductive layer 530, gate insulating layer 540, and channel layer 550 may be respectively disposed on both sides of the source electrode 561 and drain electrode 562.

[0123] Figures 17A to 26B This is a diagram illustrating a method of manufacturing a storage device 700 according to at least one example embodiment. Figures 17A to 26B Manufacturing process shown Figure 7A and Figure 7B The method of the storage device 700 shown.

[0124] Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A and Figure 26A It is a cross-sectional view of the manufacturing structure. Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B and Figure 26B This is a floor plan of the manufacturing structure. (Refer to...) Figure 17A and Figure 17B Multiple interlayer insulating layers 791 and multiple sacrificial layers 795 are stacked alternately in a direction perpendicular to the substrate 701 (z-axis direction), and then an insulating layer 792 is stacked on top of them.

[0125] Substrate 701 may comprise various materials. For example, substrate 701 may comprise a single-crystal silicon substrate, a compound semiconductor substrate, and / or an SOI substrate. However, this is merely an example, and substrate 701 may be made of various materials. Furthermore, substrate 701 may also include, for example, impurity regions induced by doping, electronic devices such as transistors, and / or peripheral circuitry for selecting and controlling storage cells that store data.

[0126] Interlayer insulation layer 791 corresponds to Figure 7B The first insulating layer 591 is shown, and may include, but is not limited to, at least one of, SiO, SiOC, and / or SiON. The sacrificial layer 795 may include a material having etch selectivity relative to the interlayer insulating layer 791. The upper insulating layer 792 corresponds to... Figure 7B The second insulating layer 792 is shown, and can be configured to pattern the interlayer insulating layer 791 and the sacrificial layer 795. The upper insulating layer 792 may include a material that has etch selectivity relative to the interlayer insulating layer 791 and the sacrificial layer 795.

[0127] Reference Figure 18A and Figure 18BAfter patterning the upper insulating layer 792, the patterned upper insulating layer 792 is used as an etching mask to form a first via H1 that penetrates the interlayer insulating layer 791 and the sacrificial layer 795. The first via H1 can be formed with, for example, a circular cross-section. Figure 18A and 18B Two first vias H1 are shown. The first vias H1 can be formed to extend in a direction perpendicular to the substrate 701 (z-axis direction). The side surfaces of the interlayer insulating layer 791 and the sacrificial layer 795 can be exposed through the first vias H1.

[0128] Reference Figure 19A and Figure 19B The first recess R1 is formed by etching the side surface of the sacrificial layer 795 exposed by the first via H1. Here, each first recess R1 can extend from the side surface of the sacrificial layer 795 parallel to the surface of the substrate 701 to a certain depth.

[0129] Reference Figure 20A and Figure 20B A channel layer 750 and a gate insulating layer 740 are sequentially formed on a sacrificial layer 795 exposed through a first recess R1. The channel layer 750 may include, for example, group IV semiconductors (such as Si, Ge, and SiGe), group III-V semiconductor compounds, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, 2D semiconductor materials, quantum dots, and / or organic semiconductors. The channel layer 750 may further include dopants. For example, the gate insulating layer 740 may include at least one of silicon oxide (SiO), silicon nitride (SiN), hafnium oxide (HfO), and / or zirconium oxide (ZrO). However, this is merely an example.

[0130] Reference Figure 21A and Figure 21B An intermediate conductive layer 730 is formed on the channel layer 740. The intermediate conductive layer 730 may be formed to fill the first recess R1. The intermediate conductive layer 730 may include a conductive material, such as a metal, metal nitride, metal oxide, polysilicon, etc. For example, the intermediate conductive layer 730 may include at least one of W, TiN, TaN, WN, NbN, Mo, Ru, Ir, RuO, IrO and / or highly doped polysilicon. However, this is merely an example, and the intermediate conductive layer 730 may include a variety of other conductive materials.

[0131] Reference Figure 22A and 22B A ferroelectric layer 720 is formed on the inner wall of each first via H1 to contact the intermediate conductive layer 730, and then a gate electrode 710 is formed on the ferroelectric layer 720. Each of the ferroelectric layer 720 and the gate electrode 710 may be formed to extend in a direction perpendicular to the substrate 701 (z-axis direction). The gate electrode 710 may be formed to fill, for example, the first via H1.

[0132] The ferroelectric layer 720 may include, for example, fluorite-based ferroelectric materials, nitride-based ferroelectric materials, and / or perovskite-based ferroelectric materials. Fluorite-based materials may include at least one of, for example, hafnium oxide (HfO), zirconium oxide (ZrO), and / or hafnium zirconium oxide (HfZrO). Nitride-based materials may include, for example, AlScN. Perovskite-based materials may include PZT, SBT, and / or BTO. The ferroelectric layer 720 may further include a dopant. The dopant may include at least one of, for example, La, Y, Gd, Si, Al, Mg, Sr, and / or Ba. However, this disclosure is not limited thereto. The gate electrode 710 may include a conductive material. For example, the gate electrode 710 may include a metal, a metal nitride, a metal oxide, polycrystalline silicon, etc. For example, the gate electrode 710 may include at least one of W, TiN, TaN, WN, NbN, Mo, Ru, Ir, RuO, IrO, and / or highly doped polycrystalline silicon. However, this disclosure is not limited thereto.

[0133] Reference Figure 23A and 23B The upper insulating layer 792 is patterned, and then the patterned upper insulating layer 792 is used as an etching mask to form a second via H2 that penetrates the interlayer insulating layer 791 and the sacrificial layer 795. The second via H2 can be used to... Figure 7A The adjacent cell arrays CA are separated from each other. Subsequently, a second recess R2 is formed by removing the sacrificial layer 795 exposed by the second via H2 to expose the channel layer 750.

[0134] Reference Figure 24A and Figure 24B Both sides of the gate insulating layer 740 are exposed by etching and removing a portion of the channel layer 750. Figure 24B This is a plan view showing both sides of the gate insulating layer 740 exposed by etching the channel layer 750, and Figure 24A It is along Figure 24B The cross-sectional view taken from line II-II'.

[0135] Reference Figure 25A and Figure 25B A source electrode 761 and a drain electrode 762 are formed on opposite sides of the channel layer 750. Each of the source electrode 761 and drain electrode 762 may comprise a conductive material. The source electrode 761 may be formed to directly contact one side of the gate insulating layer 740, and the drain electrode 762 may be formed to directly contact the other side of the gate insulating layer 740. Figure 25B This is a plan view showing the source electrode 761 and drain electrode 762 formed to contact both sides of the gate insulating layer 740, and Figure 25A yes Figure 25B Cross-sectional view. (Refer to...) Figure 26A and Figure 26B A filling insulating layer 793 is formed to fill the second through hole H2 and the second recess R2.

[0136] The semiconductor devices 100, 200, and 300 and the memory devices 500, 600, and 700 according to the above embodiments can be applied to various electronic devices. Figure 27 It is a conceptual diagram that schematically illustrates a device architecture applicable to electronic devices.

[0137] Reference Figure 27 The cache memory 2511, arithmetic logic unit (ALU) 2512, and control unit 2513 can constitute a central processing unit (CPU) 2510, and the cache memory 2511 may include static random access memory (SRAM). In addition to the CPU 2510, main memory 2520 and auxiliary memory 2530 may also be provided. Furthermore, input / output devices 2500 may be further provided. Main memory 2520 and auxiliary memory 2530 may each include the aforementioned semiconductor devices 100, 200, and / or 300 and / or memory devices 500, 600, and / or 700. In some cases, the device architecture may be implemented with computing unit components and storage unit components adjacent to each other on a single chip without distinguishing sub-units.

[0138] The aforementioned storage devices 500, 600, and 700 are implemented as memory blocks in the form of chips and can be used as neuromorphic computing platforms or for building neural networks.

[0139] Figure 28 This is a block diagram of a storage system 2600 according to at least one example embodiment.

[0140] Reference Figure 28 The storage system 2600 may include a storage controller 2601 and a storage device 2602. The storage controller 2601 performs control operations on the storage device 2602. For example, the storage controller 2601 provides the storage device 2602 with an address (ADD) and a command (CMD) to perform programming (or writing), reading, and / or erasing operations relative to the storage device 2602. Additionally, data for programming operations and data for reading can be transferred between the storage controller 2601 and the storage device 2602.

[0141] Storage device 2602 may include storage cell array 2610 and voltage generator 2620. Storage cell array 2610 may include a plurality of storage cells, the aforementioned semiconductor devices 100, 200 and / or 300 and / or storage devices 500, 600 and / or 700.

[0142] The memory controller 2601 may include processing circuitry, such as hardware including logic circuitry, hardware / software combinations such as processor-executing software, and / or combinations thereof. For example, as described above, the processing circuitry may include a CPU, ALU, digital signal processor, microcomputer, field-programmable gate array (FPGA), system-on-a-chip (SoC), programmable logic unit, microprocessor, application-specific integrated circuit (ASIC), etc., but this disclosure is not limited thereto. The memory controller 2601 may be configured to operate in response to a request from a host (not shown), access the memory device 2602, and control the control operations disclosed above (e.g., write / read operations), thereby transforming the memory controller 2601 into a dedicated controller. The memory controller 2601 may generate an address (ADD) and a command (CMD) to perform programming / read / erase operations on the memory cell array 2610. Additionally, in response to the command (CMD) from the memory controller 2601, a voltage generator 2620 (e.g., power supply circuitry) may generate voltage control signals to control the voltage levels of word lines used for data programming or data reading in the memory cell array 2610.

[0143] Additionally, the storage controller 2601 can perform operations to determine the data read from the storage device 2602. For example, it can determine the number of on and / or off cells based on the data read from the storage cells. The storage device 2602 can provide a pass / fail signal P / F to the storage controller 2601 based on the read data result. The storage controller 2601 can refer to the pass / fail signal P / F to control the write and read operations of the storage cell array 2610.

[0144] Figure 29 This is a block diagram of a neuromorphic device 2700 and an external device 2730 connected thereto, according to at least one example embodiment.

[0145] Reference Figure 29 The neuromorphic device 2700 may include processing circuitry 2710 and / or on-chip memory 2720. The neuromorphic device 2700 may include the aforementioned semiconductor devices 100, 200 and / or 300 and / or memory devices 500, 600 and 700.

[0146] In some embodiments, processing circuitry 2710 may be configured to control the functions of driving neuromorphic device 2700. For example, processing circuitry 2710 may be configured to control neuromorphic device 2700 by executing a program stored in on-chip memory 2720. For example, processing circuitry 2710 may include a CPU, graphics processing device (GPU), application processor (AP) included in neuromorphic device 2700, ALU, digital signal processor, microcomputer, FPGA, SoC, programmable logic unit, microprocessor, ASIC, etc., but this disclosure is not limited thereto. In some embodiments, processing circuitry 2710 may be configured to perform read / write of various data relative to external device 2730, and / or operate neuromorphic device 2700 using the read / write data. In some embodiments, external device 2730 may include external memory and / or a sensor array including an image sensor (e.g., CMOS image sensor circuitry).

[0147] In some embodiments, Figure 29 The neuromorphic device 2700 can be applied to machine learning systems. Such machine learning systems can utilize various artificial neural networks to organize and process models, such as convolutional neural networks (CNNs), deconvolutional neural networks, recurrent neural networks (RNNs) that optionally include long short-term memory (LSTM) units and / or gated recurrent units (GRUs), stacked neural networks (SNNs), state-space dynamic neural networks (SSDNNs), deep belief networks (DBNs), generative adversarial networks (GANs), and / or restricted Boltzmann machines (RBMs).

[0148] Alternatively or additionally, such machine learning systems may include other forms of machine learning models, such as, for example, linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction (such as principal component analysis), and expert systems; and / or combinations thereof, including ensembles such as random forests. Such machine learning models can be used to provide a variety of services and / or applications, such as image classification services, user authentication services based on biometrics or biometric data, advanced driver assistance systems (ADAS) services, voice assistant services, automatic speech recognition (ASR) services, etc., and can be performed by other electronic devices.

[0149] It should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

[0150] Cross-references to related applications

[0151] This application is based on and claims priority to Korean Patent Application No. 10-2024-0164385, filed on November 18, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A ferroelectric field-effect transistor (FeFET), comprising: Gate electrode; Ferroelectric layer on the gate electrode; An intermediate conductive layer is provided on the ferroelectric layer, such that the ferroelectric layer is located between the intermediate conductive layer and the gate electrode; A gate insulating layer is provided on the intermediate conductive layer, such that the intermediate conductive layer is located between the gate insulating layer and the ferroelectric layer. A channel layer is provided on the gate insulating layer, such that the gate insulating layer is located between the channel layer and the intermediate conductive layer. and The source electrode and the drain electrode are on the channel layer, and both the source electrode and the drain electrode are in direct contact with the gate insulating layer.

2. The ferroelectric field-effect transistor according to claim 1, wherein, The channel layer defines a first through hole and a second through hole. The source electrode contacts the gate insulating layer through the first via, and The drain electrode is in contact with the gate insulating layer through the second via.

3. The ferroelectric field-effect transistor according to claim 1, wherein the channel layer comprises at least one of group IV semiconductors, group III-V semiconductor compounds, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional (2D) semiconductors, quantum dots, and organic semiconductors.

4. The ferroelectric field-effect transistor of claim 1, wherein the channel layer includes a doped region in contact with at least one of the source electrode and the drain electrode.

5. The ferroelectric field-effect transistor according to claim 1, further comprising: The interface layer is located between the channel layer and at least one of the source electrode and the drain electrode.

6. The ferroelectric field-effect transistor of claim 1, wherein each of the gate electrode and the intermediate conductive layer independently comprises at least one of a metal, a metal nitride, a metal oxide, and highly doped polysilicon.

7. The ferroelectric field-effect transistor according to claim 1, wherein the ferroelectric layer comprises at least one of fluorite-based ferroelectric materials, nitride-based ferroelectric materials, and perovskite-based ferroelectric materials.

8. The ferroelectric field-effect transistor according to claim 1, wherein the gate insulating layer comprises at least one selected from silicon oxide, silicon nitride, hafnium oxide, and zirconium oxide.

9. A storage device, comprising: A plurality of memory cells perpendicular to the substrate, each of the plurality of memory cells comprising: Gate electrode, Ferroelectric layer, on the gate electrode, An intermediate conductive layer is provided on the ferroelectric layer, such that the ferroelectric layer is located between the intermediate conductive layer and the gate electrode. A gate insulating layer is provided on the intermediate conductive layer, such that the intermediate conductive layer is located between the gate insulating layer and the ferroelectric layer. A channel layer, on the gate insulating layer, such that the gate insulating layer is located between the channel layer and the intermediate conductive layer; and The source electrode and the drain electrode are on the channel layer, and both the source electrode and the drain electrode are in direct contact with the gate insulating layer.

10. The memory device of claim 9, wherein each of the source electrode and the drain electrode is configured to extend in a direction perpendicular to the substrate and is shared by the plurality of memory cells.

11. The memory device of claim 10, wherein the source electrode and the drain electrode are spaced apart from each other in a first direction parallel to the substrate.

12. The memory device of claim 11, wherein the gate electrode, the ferroelectric layer, the intermediate conductive layer, the gate insulating layer, and the channel layer are stacked in a second direction parallel to the substrate.

13. The memory device of claim 12, wherein the gate electrode, the ferroelectric layer, the intermediate conductive layer, the gate insulating layer, and the channel layer are on both sides of each of the source electrode and the drain electrode.

14. The memory device of claim 12, wherein the gate electrode, the ferroelectric layer, the intermediate conductive layer, the gate insulating layer, and the channel layer are on one side of each of the source electrode and the drain electrode.

15. The memory device of claim 9, wherein the gate electrode is configured to extend in a direction perpendicular to the substrate and is shared by the plurality of memory cells.

16. The memory device of claim 15, wherein the source electrode and the drain electrode are spaced apart from each other in a direction parallel to the substrate.

17. The memory device of claim 16, wherein the ferroelectric layer, the intermediate conductive layer, and the gate insulating layer surround the gate electrode.

18. The memory device of claim 9, wherein the channel layer includes a doped region in contact with at least one of the source electrode and the drain electrode.

19. The storage device according to claim 9, further comprising: An interface layer is located between the channel layer and at least one of the source electrode and the drain electrode.

20. An electronic device comprising: Processing circuitry; and The storage device according to claim 9.

Images