Bidirectional power device and preparation method thereof

Abstract

A bidirectional power device and a preparation method thereof relate to the technical field of semiconductors. The bidirectional power device comprises a supporting substrate, a buried oxide layer and a semiconductor layer which are stacked in sequence, the semiconductor layer is provided with a deep trench isolation ring which is used for forming a device region in a surrounding manner, and at least two symmetrical power units which are spaced by a deep trench isolation structure are arranged in the semiconductor layer in the device region; the power unit comprises a gate structure, an N-type drift region and a P-type body region, and the gate structure is in contact with the P-type body region and the N-type drift region; the P-type body region is respectively provided with a source electrode contact region and a body electrode contact region; the N-type drift region is provided with a drain contact region; the gate structures, the source contact regions and the body electrode contact regions of two adjacent power units are electrically connected respectively; and the drain electrode contact regions of two adjacent power units are electrically isolated. According to the device, the reliability is remarkably improved while bidirectional conduction is realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a bidirectional power device and its fabrication method. Background Technology

[0002] In power management circuits, power switches capable of bidirectional current control are often required. Laterally diffused metal-oxide-semiconductor (LDMOS) is a commonly used power device, but ordinary LDMOS can only achieve unidirectional current conduction.

[0003] To address this, the industry has developed a bidirectional LDMOS structure based on silicon-on-insulator (SOI) substrates, which involves fabricating two LDMOS cells side-by-side on the P-type top silicon layer of the SOI substrate. Each cell includes a P-well region and an adjacent N-type drift region, with the N-type drift regions of the two LDMOS cells adjacent to each other. The P-well region is used to form the channel and body region of the device, while the N-type drift region is used to withstand high voltages. When a voltage is applied to the common gate, a conductive channel is formed on the surface of each of the two P-wells. Current flows from the source in one direction, through its channel, through the N-type drift region on its side, and then through the drift region and channel on the opposite side, finally flowing out from the source on the opposite side, thus achieving bidirectional controlled conduction.

[0004] However, due to the low doping concentration and limited thickness of the P-type top silicon and P-well, when a high voltage is applied to either drain terminal, the depletion region between the two N-type drift regions, which should be mutually insulated, is prone to over-expansion and loss of insulation. This results in a direct conductive path between the two N-type drift regions that is not controlled by the gate, causing the device to fail prematurely before reaching the expected withstand voltage value, thus limiting its reliability in high-voltage applications. Summary of the Invention

[0005] The purpose of this invention is to provide a bidirectional power device and its fabrication method, which can achieve bidirectional conductivity while effectively preventing the formation of a direct conductive path uncontrolled by the gate due to excessive expansion of the depletion region under high voltage, thus significantly improving the high-voltage operating reliability of the device.

[0006] The embodiments of the present invention are implemented as follows: In one aspect, the present invention provides a bidirectional power device, comprising: a support substrate, a buried oxide layer, and a semiconductor layer stacked sequentially; a deep trench isolation ring for enclosing a device region is provided on the semiconductor layer; at least two symmetrically distributed power units are provided within the semiconductor layer of the device region, and the power units are spaced apart from each other by the deep trench isolation structure; each power unit includes an N-type drift region and a P-type body region disposed adjacently, and a gate structure located on the junction of the N-type drift region and the P-type body region; a source contact region and a body electrode contact region are provided on the side of the P-type body region away from the buried oxide layer; a drain contact region is provided on the side of the N-type drift region away from the buried oxide layer; the gate structure, source contact region, and body electrode contact region of two adjacent power units are electrically connected; and the drain contact regions of two adjacent power units are electrically isolated.

[0007] Optionally, the deep trench isolation structure extends to contact the buried oxide layer along the direction perpendicular to the supporting substrate; the deep trench isolation ring extends to contact the buried oxide layer along the direction perpendicular to the supporting substrate.

[0008] Optionally, the deep trench isolation structure extends through the device region along an extension direction parallel to the supporting substrate and parallel to the gate structure, and is connected to the deep trench isolation ring.

[0009] Optionally, the bidirectional power device further includes: a shallow trench isolation structure located in the semiconductor layer of the device region, wherein the shallow trench isolation structure is used to divide the semiconductor layer into multiple active regions, wherein the source contact region, the body contact region and the drain contact region are all formed in the corresponding active regions, and at least one side of the source contact region, the body contact region and the drain contact region is adjacent to the shallow trench isolation structure.

[0010] Optionally, both the source and drain contact regions are heavily doped N+ regions, and the bulk electrode contact region is a heavily doped P+ region.

[0011] Optionally, the gate structure, source contact region, and body electrode contact region of two adjacent power units are electrically connected through an interconnect structure. The interconnect structure includes an interlayer dielectric layer disposed on the gate structure, source contact region, or body electrode contact region, and a through-hole located in the interlayer dielectric layer, wherein a metal interconnect is inserted in the through-hole. The gate structure, source contact region, and body electrode contact region of two adjacent power units are electrically connected through the metal interconnect.

[0012] Optionally, the semiconductor layer is a P-type top silicon layer.

[0013] Optionally, the gate structure includes a gate dielectric layer and a polysilicon gate electrode located on the gate dielectric layer.

[0014] In another aspect, the present invention provides a method for fabricating a bidirectional power device, comprising: providing a substrate structure, the substrate structure comprising a support substrate, a buried oxide layer, and a semiconductor layer sequentially stacked; forming a deep trench isolation ring in the semiconductor layer, the deep trench isolation ring surrounding a device region; within the semiconductor layer of the device region, forming at least two symmetrical power units spaced apart and formed by forming a deep trench isolation structure, wherein forming each power unit comprises: forming an adjoining N-type drift region and a P-type body region in the semiconductor layer; forming a gate structure that contacts at least a portion of the P-type body region and at least a portion of the N-type drift region; performing ion implantation in the semiconductor layer to form a source contact region and a body electrode contact region on top of the P-type body region, and a drain contact region on top of the N-type drift region; forming an electrical connection between the gate structures of two adjacent power units; forming an electrical connection between the source contact regions of two adjacent power units; and forming an electrical connection between the body electrode contact regions of two adjacent power units.

[0015] Optionally, forming a deep trench isolation structure includes: etching the semiconductor layer along a direction perpendicular to the supporting substrate until it contacts the buried oxide layer to form a deep trench isolation structure; Forming a deep trench isolation ring in a semiconductor layer includes etching the semiconductor layer along a direction perpendicular to the supporting substrate until it contacts the buried oxide layer to form a deep trench isolation ring.

[0016] The beneficial effects of this invention include: This application provides a bidirectional power device, comprising a support substrate, a buried oxide layer, and a semiconductor layer stacked sequentially. A deep trench isolation ring is provided on the semiconductor layer to enclose the device region. This deep trench isolation ring structure, together with the buried oxide layer, forms a surrounding insulating barrier. At least two symmetrically distributed power units are provided within the semiconductor layer of the device region. The power units are separated from each other by the deep trench isolation structure. Compared to the low-doped P-type silicon in the prior art, which is easily permeable between adjacent high-voltage drift regions, this application uses a deep trench structure to isolate the drift regions of two adjacent power units, fundamentally eliminating the hidden danger of excessive expansion and loss of insulation of the depletion region between two drift regions under high-voltage conditions, as is common in conventional structures. The power unit includes... The N-type drift region and P-type body region are connected in an adjacent manner, and a gate structure is located on the junction of the N-type drift region and the P-type body region. This symmetrical layout provides a physical carrier for bidirectional current conduction. The P-type body region has a source contact region and a body electrode contact region on the side facing away from the buried oxide layer; the N-type drift region has a drain contact region on the side facing away from the buried oxide layer. The gate structure, source contact region, and body electrode contact region of two adjacent power units are electrically connected correspondingly through interconnection structures, so that the two power units are controlled by the same gate signal, achieving completely symmetrical bidirectional conduction and control functions. The drain contact regions of two adjacent power units are electrically isolated to form the two terminal electrodes of the bidirectional power device, enabling the bidirectional power device to be connected in series in a circuit to achieve bidirectional switching. This bidirectional power device, while achieving bidirectional conduction, effectively prevents excessive expansion of the depletion region caused by low-doped regions, thus preventing the formation of a direct conductive path uncontrolled by the gate, significantly improving the reliability of the device. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is one of the structural schematic diagrams of a bidirectional power device provided in an embodiment of the present invention; Figure 2 This is a second schematic diagram of the structure of the bidirectional power device provided in an embodiment of the present invention; Figure 3 This is the third schematic diagram of the structure of the bidirectional power device provided in the embodiment of the present invention; Figure 4 This is one of the schematic diagrams illustrating the fabrication process of the bidirectional power device provided in an embodiment of the present invention; Figure 5This is the second schematic diagram of the fabrication process of the bidirectional power device provided in the embodiment of the present invention.

[0019] Icons: 100 - Bidirectional power device; 110 - Support substrate; 120 - Buried oxide layer; 130 - Semiconductor layer; 141 - Deep trench isolation ring; 142 - Deep trench isolation structure; 143 - Shallow trench isolation structure; 150 - Power cell; 151 - Gate structure; 1511 - Gate dielectric layer; 1512 - Polysilicon gate electrode; 152 - N-type drift region; 1521 - Drain contact region; 153 - P-type body region; 1531 - Source contact region; 1532 - Body electrode contact region; 160 - Interconnect structure; 161 - Through-hole; 162 - Metal interconnect; 163 - Interface terminal. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0023] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed during use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0024] Furthermore, terms such as "horizontal" and "vertical" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0025] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0026] Please refer to Figure 1 This embodiment provides a bidirectional power device 100, which may include: a support substrate 110, a buried oxide layer 120, and a semiconductor layer 130 stacked sequentially; the semiconductor layer 130 is provided with a deep trench isolation ring 141 for enclosing a device region; at least two symmetrically distributed power units 150 are provided within the semiconductor layer 130 of the device region, and the power units 150 are spaced apart from each other by a deep trench isolation structure 142; the power unit 150 includes an N-type drift region 152 and a P-type body region 153 disposed in contact with each other, and A gate structure 151 is located at the junction of the N-type drift region 152 and the P-type body region 153; the P-type body region 153 is provided with a source contact region 1531 and a body electrode contact region 1532 on the side away from the buried oxide layer 120; the N-type drift region 152 is provided with a drain contact region 1521 on the side away from the buried oxide layer 120; the gate structure 151, source contact region 1531 and body electrode contact region 1532 of two adjacent power units 150 are electrically connected respectively; the drain contact regions 1521 of two adjacent power units 150 are electrically isolated.

[0027] Specifically, such as Figure 1 As shown, the bidirectional power device 100 adopts a silicon-on-insulator (SiI) substrate structure, which may include a support substrate 110, a buried oxide layer 120, and a semiconductor layer 130 stacked sequentially. The support substrate 110 serves as a mechanical support carrier for the bidirectional power device 100, mainly playing the role of fixing and protecting the upper structure.

[0028] Preferably, the support substrate 110 is not a P-type substrate layer to improve the withstand voltage performance of the bidirectional power device 100.

[0029] In this embodiment, a buried oxide layer 120 is located above the support substrate 110 and between the support substrate 110 and the semiconductor layer 130, serving to achieve electrical isolation. The buried oxide layer 120 has good insulation properties, effectively blocking parasitic conduction paths between the support substrate 110 and the semiconductor layer 130, preventing leakage between the support substrate 110 and the upper device structure, thereby reducing the parasitic capacitance and leakage loss of the bidirectional power device 100.

[0030] The top of the buried oxide layer 120 is provided with a semiconductor layer 130.

[0031] In one embodiment of this application, the semiconductor layer 130 is a P-type top silicon layer. The doping characteristics of the P-type top silicon can form a PN junction structure with the N-type drift region 152 and the P-type body region 153 formed on the P-type top silicon, thereby optimizing the electric field distribution inside the bidirectional power device 100 and improving the carrier transport efficiency. At the same time, the P-type doped semiconductor layer 130 can provide a good substrate for the formation of the P-type body region 153, ensuring the uniformity and stability of the doping concentration of the P-type body region 153, so that the bidirectional power device 100 can maintain consistent electrical characteristics during bidirectional conduction and avoid current transmission distortion.

[0032] like Figure 1 As shown, a deep trench isolation ring 141 is provided on the semiconductor layer 130. The deep trench isolation ring 141 extends into the support substrate 110 along the stacking direction of the support substrate 110, the buried oxide layer 120, and the semiconductor layer 130, thereby enclosing the semiconductor layer 130 to form a device region. The deep trench isolation ring 141 enables efficient electrical isolation between the bidirectional power device 100 and surrounding circuits or other device units, avoiding external signal interference and parasitic coupling, and ensuring the stability of the bidirectional power device 100.

[0033] In this embodiment, within the device region enclosed by the deep trench isolation ring 141, a deep trench isolation structure 142 is provided within the semiconductor layer 130. The deep trench isolation structure 142 divides the device region into two symmetrical parts, each part being used to fabricate a power unit 150.

[0034] Optionally, along a direction perpendicular to the support substrate 110, the deep trench isolation ring 141 extends to contact the buried oxide layer 120 to form an isolation barrier penetrating the semiconductor layer 130 to the support substrate 110, thereby improving the electrical isolation effect and mechanical strength of the bidirectional power device 100, reducing electric field distortion and punch-through risk under high voltage conditions, and further improving the withstand voltage performance and stability of the bidirectional power device 100.

[0035] like Figure 1As shown, the power unit 150 may include an N-type drift region 152 and a P-type body region 153 sequentially formed within the semiconductor layer 130 using ion implantation technology. The N-type drift region 152 and the P-type body region 153 are laterally connected. Since the two power units 150 are symmetrically arranged about the deep trench isolation structure 142 as an axis of symmetry, the N-type drift regions 152 of the two power units 150 are close to each other, while the P-type body regions 153 of the two power units 150 are far apart. Electrical isolation is achieved between the N-type drift regions 152 of the two power units 150 through the deep trench isolation structure 142. Compared to the prior art which uses easily permeable, low-doped P-type silicon between adjacent high-voltage drift regions, this application uses a deep trench structure to isolate the drift regions of two adjacent power units 150 that are close together, fundamentally eliminating the hidden danger of excessive expansion and loss of insulation of the depletion region between the two drift regions under high-voltage conditions, as is common in conventional structures.

[0036] Optionally, along a direction perpendicular to the support substrate 110, the deep trench isolation structure 142 extends to contact the buried oxide layer 120 to form an isolation barrier penetrating the semiconductor layer 130 to the support substrate 110. This improves the electrical isolation effect and mechanical strength of the bidirectional power device 100, reduces electric field distortion and punch-through risk under high voltage conditions, and further improves the withstand voltage performance and stability of the bidirectional power device 100. Figure 2 As shown, a gate structure 151 is also deposited on the junction area of ​​the N-type drift region 152 and the P-type body region 153 of each power unit 150 to achieve effective control of the conductive channel of the bidirectional power device 100.

[0037] In one possible implementation of this application, such as Figure 2 As shown, the gate structure 151 may include a gate dielectric layer 1511 deposited on top of at least a portion of the P-type body region 153 and at least a portion of the N-type drift region 152, and a polysilicon gate electrode 1512 deposited on the gate dielectric layer 1511. Preferably, the gate dielectric layer 1511 is an insulating material layer such as silicon oxide to ensure electrical insulation between the gate structure 151 and the semiconductor layer 130.

[0038] like Figure 2 As shown, the P-type body region 153 is formed by ion implantation on the side away from the buried oxide layer 120 to form the source contact region 1531 and the body electrode contact region 1532; the N-type drift region 152 is formed by ion implantation on the side away from the buried oxide layer 120 to form the drain contact region 1521.

[0039] In a preferred embodiment of this application, both the source contact region 1531 and the drain contact region 1521 are heavily doped N+ regions, and the body electrode contact region 1532 is a heavily doped P+ region. Heavy doping makes the connection between the contact region and the external circuit more reliable, reducing energy loss during signal transmission. Simultaneously, the P+ body electrode contact region 1532 can effectively fix the potential of the P-type body region 153.

[0040] Optionally, such as Figure 3 As shown, along the extension direction parallel to the support substrate 110 and parallel to the gate structure 151, the deep trench isolation structure 142 penetrates the device region and is connected to the deep trench isolation ring 141 to significantly enhance the mechanical stability of the isolation structure. At the same time, this structure enables the drain contact regions 1521 of the two power units 150 to maintain absolutely reliable electrical isolation even under extremely high voltage, further improving the reliability of its electrical isolation.

[0041] To further optimize the active region definition and isolation effect of the device, in one embodiment of this application, a shallow trench isolation structure 143 is also provided in the semiconductor layer 130 of the device region. The shallow trench isolation structure 143 is used to divide the semiconductor layer 130 into multiple active regions. The source contact region 1531, the body electrode contact region 1532 and the drain contact region 1521 are all formed in the corresponding active regions, and at least one side of the source contact region 1531, the body electrode contact region 1532 and the drain contact region 1521 is adjacent to the shallow trench isolation structure 143.

[0042] Specifically, such as Figure 2 and Figure 3 As shown, the shallow trench isolation structure 143 is embedded in the semiconductor layer 130 in a trench configuration. The depth of the shallow trench isolation structure 143 is less than the depth of the deep trench isolation ring 141 and the deep trench isolation structure 142. It extends only along the stacking direction of the supporting substrate 110, the buried oxide layer 120 and the semiconductor layer 130 to a predetermined depth inside the semiconductor layer 130, without penetrating the buried oxide layer 120. This achieves lateral isolation without compromising the structural integrity of the interlayer structure between the semiconductor layer 130 and the buried oxide layer 120.

[0043] Each power unit 150 has two shallow trench isolation structures 143 in its semiconductor layer 130. The two shallow trench isolation structures 143 are arranged laterally to divide the semiconductor layer 130 into multiple active regions. The source contact region 1531, the body contact region 1532, or the drain contact region 1521 are respectively set in independent active regions to ensure that each functional region is independent in terms of physical structure and electrical characteristics.

[0044] The active region where the source contact region 1531 is located is adjacent to the active region where the body electrode contact region 1532 is located, and the boundary between the two is defined by the shallow trench isolation structure 143 to avoid parasitic conduction between the source electrode and the body electrode; the active region where the drain contact region 1521 is located is adjacent to the active regions corresponding to the P-type body region 153 and the N-type drift region 152, and the functional boundary is also defined by the shallow trench isolation structure 143.

[0045] In the above embodiments, at least one side of the source contact region 1531, the body contact region 1532, and the drain contact region 1521 is directly adjacent to the shallow trench isolation structure 143, so that the shallow trench isolation structure 143 can directly act on the edge of each contact region. Through the physical isolation and electrical blocking of the insulating medium, the lateral diffusion of charge carriers between each contact region is suppressed, and parasitic current and signal interference are reduced.

[0046] In one specific embodiment of this application, such as Figure 2 As shown, the drain contact region 1521 of the N-type drift region 152 is disposed between one of the shallow trench isolation structures 143 and one sidewall of the deep trench isolation ring 141; the body electrode contact region 1532 of the P-type body region 153 is disposed between the other shallow trench isolation structure 143 and the other sidewall of the deep trench isolation ring 141; the source contact region 1531 of the P-type body region 153 is disposed on the side of the shallow trench isolation structure 143 away from the body electrode contact region 1532.

[0047] Optionally, the deep trench isolation ring 141 and / or the shallow trench isolation structure 143 are filled with an insulating medium.

[0048] Preferably, both the deep trench isolation ring 141 and the shallow trench isolation structure 143 are filled with an insulating medium, such as silicon oxide, to further improve the insulation reliability of the isolation structure.

[0049] Preferably, the inner pages of the deep trench isolation structure 142 are filled with an insulating medium, such as silicon oxide, to further improve the insulation reliability of the isolation structure.

[0050] like Figure 2 and Figure 3As shown, the gate structure 151, source contact region 1531 and body electrode contact region 1532 of two adjacent power units 150 are electrically connected through interconnection structure 160 respectively. The electrical connection of the gate structure 151 ensures that the two power units 150 can receive synchronous control signals. When an effective positive voltage is applied to the gate structure 151, conductive channels can be formed simultaneously on the surfaces of the P-type body regions 153 of the two power units 150. When the voltage of the gate structure 151 is removed or reversed, the two conductive channels can be closed synchronously, avoiding current transmission disorder caused by asynchronous control signals and ensuring the consistency of the switching state of the bidirectional power device 100. The electrical connection of the source contact region 1531 constructs a unified carrier transport channel for the two power units 150, enabling carriers to flow between the two power units 150 and breaking the unidirectional conductivity limitation of a single power unit 150. The electrical connection of the body electrode contact region 1532 can fix the potential of the two P-type body regions 153, avoiding threshold voltage drift and other problems caused by floating P-type body regions 153, while ensuring that the electrical environment of the two P-type body regions 153 is consistent, thus improving the working stability of the bidirectional power device 100.

[0051] When current flows into one terminal electrode of the bidirectional power device 100 (i.e., the drain contact region 1521 of one of the power units 150), the current first enters the N-type drift region 152 corresponding to that power unit 150. Under the control of the gate structure 151, it reaches its source contact region 1531 through the conductive channel formed by the P-type body region 153 of that power unit 150. Since the source contact regions 1531 of the two power units 150 are connected through the interconnection structure 160, the current will be directly conducted to the other power unit 150. The source contact region 1531, under the control of the signal from the same gate structure 151, enters the N-type drift region 152 of the power unit 150 through its conductive channel, and finally flows out from the drain contact region 1521 of the power unit 150 (i.e., the other terminal electrode of the bidirectional power device 100). When the current direction is reversed, the two terminal electrodes of the bidirectional power device 100 interchange functions; the terminal electrode that was originally the source terminal becomes the drain terminal, and the terminal electrode that was originally the drain terminal becomes the source terminal, and the current is transmitted along the opposite path. In order to facilitate a good electrical connection between the drain contact region 1521 and external devices, an interface terminal 163 is provided on the drain contact region 1521, and the drain contact region 1521 is electrically connected to external devices through the interface terminal 163.

[0052] Optionally, the gate structure 151, source contact region 1531, and body electrode contact region 1532 of two adjacent power units 150 are electrically connected through an interconnect structure 160. The interconnect structure 160 includes an interlayer dielectric layer disposed on the gate structure 151, source contact region 1531, or body electrode contact region 1532, and a through-hole 161 located in the interlayer dielectric layer. A metal interconnect 162 is inserted into the through-hole 161. The gate structure 151, source contact region 1531, and body electrode contact region 1532 of two adjacent power units 150 are electrically connected through the metal interconnect 162.

[0053] Specifically, the interlayer dielectric layer uses insulating materials such as silicon oxide and silicon nitride, and is deposited on top of the gate structure 151, source contact region 1531, or body electrode contact region 1532. On the one hand, the interlayer dielectric layer can isolate electrical signals between different metal interconnects 162, avoiding parasitic conduction and signal interference. On the other hand, it provides a stable support and packaging environment for the metal interconnects 162, preventing damage to the connected components from the external environment.

[0054] like Figure 3 As shown, multiple through-holes 161 are formed on the interlayer dielectric layer along the stacking direction of the bidirectional power device 100, i.e., perpendicular to the surface of the semiconductor layer 130. Preferably, the through-holes 161 are filled with a highly conductive metal material such as aluminum, copper, or their alloys to further improve their conductivity. The ends of the metal interconnects 162 are inserted into the through-holes 161 to realize that the gate structure 151, source contact region 1531, and body electrode contact region 1532 of the two power units 150 are electrically connected respectively through the interconnect structure 160.

[0055] Among them, such as Figure 2 As shown, the body electrode contact area 1532 and gate structure 151 of the two power units 150 are electrically connected through metal interconnect 162, and an interface terminal 163 is also provided on the metal interconnect 162, which is used to electrically connect with external devices.

[0056] It should be noted that, in one possible embodiment of this application, each of the two end electrodes extends into two interconnect structures 160 for electrical connection with an external circuit.

[0057] Another aspect of the embodiments of this application also provides a method for fabricating a bidirectional power device 100, such as... Figure 4 As shown, it can specifically include the following steps: Step S100: Provide a substrate structure, the substrate structure including a support substrate 110, a buried oxide layer 120 and a semiconductor layer 130 stacked sequentially.

[0058] Step S200: A deep trench isolation ring 141 is formed in the semiconductor layer 130, and the deep trench isolation ring 141 encloses the device region.

[0059] Specifically, the pattern of the deep trench isolation ring 141 is defined by photolithography, and then the deep trench is formed in the semiconductor layer 130 by etching, with the etching depth extending into the support substrate 110.

[0060] Preferably, after the deep trench isolation ring 141 is etched, an insulating medium such as silicon oxide can be filled into the deep trench isolation ring 141 to form a deep trench isolation ring 141 surrounding the device area, thereby achieving electrical isolation between the device and the external environment.

[0061] In step S300, at least two symmetrical power units 150 are spaced and formed by forming a deep trench isolation structure 142 within the semiconductor layer 130 of the device region.

[0062] like Figure 5 As shown, forming each power unit 150 may include: Step S310: Forming an adjacent N-type drift region 152 and a P-type body region 153 in the semiconductor layer 130.

[0063] Specifically, an N-type drift region 152 and a P-type body region 153 are formed laterally connected in the semiconductor layer 130 by an ion implantation process. After ion implantation, a rapid thermal annealing process is used to repair the lattice damage caused by ion implantation, while activating doped ions and improving the electrical performance of the doped region.

[0064] Step S320: Form a gate structure 151, making it contact at least a portion of the P-type body region 153 and at least a portion of the N-type drift region 152.

[0065] Specifically, a gate dielectric layer 1511 and a polysilicon layer are formed sequentially through a deposition process, and then the polysilicon layer and the gate dielectric layer 1511 are patterned through photolithography and etching processes, so that the gate structure 151 contacts at least a portion of the P-type body region 153 and at least a portion of the N-type drift region 152, to ensure effective control of the conductive channel by the gate.

[0066] Step S330: Ion implantation is performed in the semiconductor layer 130 to form a source contact region 1531 and a body electrode contact region 1532 on top of the P-type body region 153, and a drain contact region 1521 on top of the N-type drift region 152.

[0067] Step S400: An electrical connection is formed between the gate structures 151 of two adjacent power units 150.

[0068] Specifically, a uniform interlayer dielectric layer is deposited on the surface of the formed gate structure 151. This interlayer dielectric layer must completely cover the polysilicon gate electrode 1512 to provide insulation, protection, and support. Subsequently, a pattern window corresponding to the position of the polysilicon gate electrode 1512 is defined using a photolithography process, and then a through-hole 161 is formed on the interlayer dielectric layer using an etching process, ensuring that the bottom of the through-hole 161 exposes the surface of the polysilicon gate electrode 1512.

[0069] A highly conductive metal material is filled into the inner wall of the through-hole 161 using physical vapor deposition or electroplating to form a metal plug. The metal plug contacts the surface of the polysilicon gate electrode 1512 to reduce contact resistance.

[0070] Finally, a metal wiring layer is deposited on the surface of the interlayer dielectric layer, and the metal wiring layer is patterned by etching process, so that the metal wiring layer is connected to the metal plugs corresponding to the two gate structures 151 respectively, realizing the electrical connection of the gate structures 151 of the two power units 150, so as to ensure that the two gate structures 151 can receive the same control voltage signal synchronously.

[0071] Step S500: An electrical connection is formed between the source contact regions 1531 of two adjacent power units 150.

[0072] Specifically, after the source contact region 1531 is formed, an interlayer dielectric layer is first deposited on the surface of the bidirectional power device 100. This interlayer dielectric layer covers the source contact region 1531 to provide insulation protection and support. Subsequently, a pattern window corresponding to the position of the source contact region 1531 is defined by photolithography, and then a through-hole 161 is formed on the interlayer dielectric layer by etching, ensuring that the bottom of the through-hole 161 exposes the surface of the source contact region 1531.

[0073] In the above embodiments, a highly conductive metal material is filled into the inner wall of the through hole 161 using physical vapor deposition or electroplating to form a metal plug. The metal plug contacts the surface of the source contact region 1531 to reduce contact resistance and ensure that charge carriers can pass through efficiently.

[0074] Finally, a metal wiring layer is deposited on the surface of the interlayer dielectric layer. The metal wiring layer is patterned by etching, and then connected to the metal plugs corresponding to the two source contact regions 1531, respectively, to achieve electrical connection between the source contact regions 1531 of the two power units 150. When current flows in from the drain of one of the power units 150, it reaches the source contact region 1531 through its channel and can be directly conducted to the source contact region 1531 of the other power unit 150 through the interconnect path. Then, it flows to the drain of the other power unit 150 through its channel, realizing smooth current flow between the two power units 150 and providing a carrier transport path for bidirectional conduction.

[0075] Step S600: An electrical connection is formed between the body electrode contact areas 1532 of two adjacent power units 150.

[0076] Specifically, after the body electrode contact area 1532 is formed, an interlayer dielectric layer is first deposited on the surface of the bidirectional power device 100. This interlayer dielectric layer covers the body electrode contact area 1532 to provide insulation protection and support. Subsequently, a pattern window corresponding to the position of the body electrode contact area 1532 is defined by photolithography, and then a through-hole 161 is formed on the interlayer dielectric layer by etching, ensuring that the bottom of the through-hole 161 exposes the surface of the body electrode contact area 1532.

[0077] In the above embodiments, a highly conductive metal material is filled into the inner wall of the through hole 161 using physical vapor deposition or electroplating to form a metal plug. The metal plug contacts the surface of the body electrode contact area 1532 to reduce contact resistance and effectively extract the body potential.

[0078] Finally, a metal wiring layer is deposited on the surface of the interlayer dielectric layer. The metal wiring layer is patterned by etching, so that the metal wiring layer is connected to the metal plugs corresponding to the two body electrode contact areas 1532 respectively. This realizes the electrical connection of the body electrode contact areas 1532 of the two power units 150, so that the potentials of the two P-type body regions 153 are consistent and stable. This avoids problems such as threshold voltage drift and unstable channel conductivity caused by floating body regions, and improves the reliability of the bidirectional power device 100.

[0079] Through the above steps, a bidirectional power device 100 is finally fabricated. The specific structure and beneficial effects of the bidirectional power device 100 have been described in detail above and will not be repeated here. This bidirectional power device 100 can achieve bidirectional conductivity while effectively preventing the excessive expansion of the depletion region caused by low-doped regions, thus preventing the formation of a direct conductive path uncontrolled by the gate, and significantly improving device reliability.

[0080] Optionally, in step S300, forming the deep trench isolation structure 142 may include etching the semiconductor layer 130 along a direction perpendicular to the support substrate 110 until it contacts the buried oxide layer 120 to form the deep trench isolation structure 142.

[0081] Specifically, the semiconductor layer 130 is anisotropically etched along a direction perpendicular to the support substrate 110, such as by using deep reactive ion etching, and the etching endpoint is precisely controlled so that the etching process terminates at the surface of the buried oxide layer 120, thereby forming a deep trench isolation structure 142 that exposes the underlying buried oxide layer 120.

[0082] Preferably, a high-density plasma chemical vapor deposition process can be used to fill the deep trench isolation structure 142 with an insulating medium, such as silicon dioxide, and the surface can be planarized by chemical mechanical polishing.

[0083] Similarly, in step S200, forming a deep trench isolation ring 141 in the semiconductor layer 130 may include etching the semiconductor layer 130 along a direction perpendicular to the support substrate 110 until it contacts the buried oxide layer 120 to form the deep trench isolation ring 141.

[0084] In this embodiment, the semiconductor layer 130 is anisotropically etched along a direction perpendicular to the support substrate 110, such as by using deep reactive ion etching, and the etching endpoint is precisely controlled so that the etching process terminates at the surface of the buried oxide layer 120, thereby forming a deep trench isolation ring 141 that exposes the underlying buried oxide layer 120.

[0085] Preferably, a process such as high-density plasma chemical vapor deposition can be used to fill the deep trench isolation ring 141 with an insulating medium, such as silicon dioxide, and the surface can be planarized by chemical mechanical polishing.

[0086] Through the above-described fabrication process, an isolation barrier that extends through the semiconductor layer 130 to the support substrate 110 can be formed, which improves the electrical isolation effect and mechanical strength of the bidirectional power device 100, reduces electric field distortion and punch-through risk under high voltage conditions, and further improves the withstand voltage performance and stability of the bidirectional power device 100.

[0087] The above description is merely an optional embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0088] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable way without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

Claims

1. A bidirectional power device, characterized in that, include: A support substrate, a buried oxide layer, and a semiconductor layer are stacked sequentially. The semiconductor layer is provided with a deep trench isolation ring for enclosing the device region. The semiconductor layer of the device region is provided with at least two symmetrically distributed power units, which are spaced apart from each other by a deep trench isolation structure. The power unit includes an N-type drift region and a P-type body region connected together, and a gate structure located on the junction of the N-type drift region and the P-type body region; The P-type body region has a source contact region and a body electrode contact region on the side away from the buried oxide layer; the N-type drift region has a drain contact region on the side away from the buried oxide layer. The gate structures, source contact regions, and body electrode contact regions of two adjacent power units are electrically connected; the drain contact regions of two adjacent power units are electrically isolated.

2. The bidirectional power device according to claim 1, characterized in that, Along a direction perpendicular to the supporting substrate, the deep trench isolation structure extends to contact the buried oxide layer; Along a direction perpendicular to the supporting substrate, the deep trench isolation ring extends to contact the buried oxide layer.

3. The bidirectional power device according to claim 1, characterized in that, Along an extension direction parallel to the supporting substrate and parallel to the gate structure, the deep trench isolation structure penetrates the device region and is connected to the deep trench isolation ring.

4. The bidirectional power device according to claim 1, characterized in that, Also includes: The semiconductor layer located in the device region is further provided with a shallow trench isolation structure. The shallow trench isolation structure is used to divide the semiconductor layer into multiple active regions. The source contact region, the body electrode contact region and the drain contact region are all formed in the corresponding active regions, and at least one side of the source contact region, the body electrode contact region and the drain contact region is adjacent to the shallow trench isolation structure.

5. The bidirectional power device according to claim 1, characterized in that, Both the source contact region and the drain contact region are heavily doped N+ regions; the bulk electrode contact region is a heavily doped P+ region.

6. The bidirectional power device according to claim 1, characterized in that, The gate structures, source contact regions, and body electrode contact regions of two adjacent power units are electrically connected through interconnection structures. The interconnect structure includes: an interlayer dielectric layer disposed on the gate structure, the source contact region, or the body electrode contact region, and a through-hole located in the interlayer dielectric layer, wherein a metal interconnect is inserted in the through-hole; the gate structures, source contact regions, and body electrode contact regions of two adjacent power units are electrically connected through the metal interconnect.

7. The bidirectional power device according to claim 1, characterized in that, The semiconductor layer is a P-type top silicon layer.

8. The bidirectional power device according to claim 1, characterized in that, The gate structure includes a gate dielectric layer and a polysilicon gate electrode located on the gate dielectric layer.

9. A method for fabricating a bidirectional power device, characterized in that, include: A substrate structure is provided, the substrate structure comprising a support substrate, a buried oxide layer and a semiconductor layer stacked sequentially; A deep trench isolation ring is formed in the semiconductor layer, and the deep trench isolation ring encloses the device region; Within the semiconductor layer of the device region, a deep trench isolation structure is formed to space and form at least two symmetrical power cells, wherein forming each power cell includes: An adjoint N-type drift region and a P-type body region are formed in the semiconductor layer; A gate structure is formed to contact at least a portion of the P-type body region and at least a portion of the N-type drift region; Ion implantation is performed in the semiconductor layer to form a source contact region and a body electrode contact region on top of the P-type body region, and a drain contact region on top of the N-type drift region; An electrical connection is formed between the gate structures of two adjacent power units; An electrical connection is formed between the source contact regions of two adjacent power units; An electrical connection is formed between the body electrode contact areas of two adjacent power units.

10. The method for fabricating a bidirectional power device according to claim 9, characterized in that, The process of forming the deep trench isolation structure includes: etching the semiconductor layer along a direction perpendicular to the supporting substrate until it contacts the buried oxide layer to form the deep trench isolation structure; The process of forming a deep trench isolation ring in the semiconductor layer includes etching the semiconductor layer along a direction perpendicular to the supporting substrate until it contacts the buried oxide layer to form the deep trench isolation ring.

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