Gallium nitride-based integrated bidirectional switching power device with substrate bias diode

Abstract

The invention relates to a gallium nitride-based integrated bidirectional switching power device with substrate bias diodes. An integrated bidirectional switching power device based on gallium nitride includes: a die integrated with a first switching FET transistor and a second switching FET transistor; and a substrate bias network configured to selectively electrically couple the substrate node to source regions of the first and second switching FET transistors at a lower potential. The substrate bias network has first and second diodes coupled in anti-series and formed of field effect diode connected transistors having the same structure as the first and second switching FET transistors in the same conductive layer, contact layer and gate layer.

Description

Technical Field

[0001] This disclosure relates to a gallium nitride-based integrated bidirectional switching power device with a substrate biased diode. Background Technology

[0002] Gallium nitride-based bidirectional switching power devices can be like Figure 1 Formed as shown, and as Figure 2 The diagram illustrates this schematically.

[0003] In detail, Figure 1 A bidirectional switching device 1 is shown, which includes a semiconductor body 2, which is formed by a substrate 3, a first semiconductor layer 4 and a second semiconductor layer 5 stacked on top of each other.

[0004] The substrate 3 may be, for example, single-crystal silicon; the first semiconductor layer 4, which is directly stacked and in contact with the substrate 3, may be a first semiconductor alloy of elements in groups III and V of the periodic table, such as gallium nitride (GaN); and the second semiconductor layer 5, which is directly stacked and in contact with the first semiconductor layer 4, may be a second semiconductor alloy of elements in groups III and V of the periodic table (different from the first semiconductor alloy), such as aluminum gallium nitride (AlGaN).

[0005] The first semiconductor layer 4 forms a channel layer on its upper part, and the second semiconductor layer 5 forms a barrier layer.

[0006] The first semiconductor layer 4 and the second semiconductor layer 5 are, for example, N-type.

[0007] The first gate region 7 and the second gate region 8 of the conductive material extend at a distance from each other above the second semiconductor layer 5. The first gate region 7 and the second gate region 8 are, for example, a third semiconductor alloy of group III and group V elements of the periodic table (different from the first semiconductor alloy and the second semiconductor alloy), such as p-type gallium nitride (p-GaN).

[0008] Metal gate electrodes 9, 10 (in) Figure 1 The gates (G1 and G2) are respectively disposed above and in direct electrical contact with the first gate region 7 and the second gate region 8, and are respectively coupled to the first gate terminal 11 and the second gate terminal 12, which are configured to provide the corresponding gate voltage V. G1 V G2 .

[0009] The bidirectional switching device 1 also includes a first source electrode 15 and a second source electrode 16 located on and in contact with the first semiconductor layer 4. Figure 1 (also indicated by S1 and S2), and is coupled to the first source extremum 17 and the second source extremum 18 respectively.

[0010] In the bidirectional switching device 1, a first semiconductor layer 4 and a second semiconductor layer 5 form a semiconductor heterostructure that allows the generation of a so-called two-dimensional electron gas (2deg) in an electronically controllable manner. This forms a channel region (schematically indicated by 20) and allows current to flow between the first source terminal 17 and the second source terminal 18.

[0011] Specifically, according to Table 1 below, the bidirectional switching device 1 can be controlled in different operating modes depending on the voltages (turn-on voltage and turn-off voltage) applied to the gate terminals 11 and 12: Table 1

[0012] For example, the off voltage can be 0 V, and the on voltage can be 6 V.

[0013] Furthermore, depending on the voltage applied to the source terminals 17 and 18, current can flow from the first source electrode 15 to the second source electrode 16 or in the opposite direction. Therefore, in the case of switching operation, each time, one of the two source terminals 17 and 18 operates as the drain terminal (at a higher voltage), while the other of the two source terminals 17 and 18 operates as the source terminal (at a lower voltage).

[0014] Furthermore, the bidirectional switching device 1 can operate as a diode. In this case, the same voltage is applied to one of the gate terminals 11, 12 and the adjacent source terminals 17, 18. Therefore, each time, one of the two source terminals 17, 18 operates as the anode terminal, while the other of the two source terminals 17, 18 operates as the cathode terminal.

[0015] In the bidirectional switching device 1, the voltage of the substrate 3 ( Figure 1 V SUB The indication is crucial because it can negatively affect the operation of the bidirectional switching device 1, especially during switching operations.

[0016] Specifically, in unidirectional devices, V is clamped here to the minimum voltage in the device (typically the source voltage). SUB It cannot be clamped to the voltage present on one of the source terminals because, as mentioned, each source terminal S1, S2 can operate at a higher voltage than the other source terminal S1, S2 (even in an alternating manner).

[0017] On the other hand, substrate 3 cannot be floated because in this case, a "back gate" phenomenon may occur, in which substrate 3 is at the intermediate voltage between source voltages Vs1 and Vs2 and acts as an additional gate region, resulting in an imbalance between voltages on the device, depletion of the two-dimensional electron gas, and reduced conductivity of the bidirectional switching device 1.

[0018] These situations, such as Figure 3A As shown, under switching operation conditions where the voltage on source terminals 17 and 18 switches between 0 V and 200 V, the substrate voltage V is as follows: when coupled to the grounded substrate 3 (i.e., related to the potential of the terminal at the lower potential, here source terminal 17, line A) and when held floating on the substrate 3 (line B). SUB Related.

[0019] Figure 3B The on-resistance Ron is shown as the stress time t. s The corresponding trend of the function, where line C refers to the case of coupling to the grounded substrate 3, and line D refers to the case of keeping the substrate 3 floating.

[0020] To address this issue, an external circuit could be used to couple the substrate 3 to a lower voltage in the device each time. However, even these solutions are not entirely satisfactory, both because of their complexity and because they cannot guarantee the desired speed and synchronization.

[0021] US 2014 / 0374766A1 and EP 3447917 describe automatic biasing circuits for substrates of gallium nitride-based bidirectional switches using diodes. The diodes can be external or integrated into the same die using different topologies, but they do not always have electrical characteristics (switching time, voltage withstand) suitable for the desired performance. Summary of the Invention

[0022] According to this disclosure, a gallium nitride-based integrated bidirectional switching power device is provided. Embodiments of this disclosure overcome at least some of the disadvantages of the prior art.

[0023] In one embodiment, a gallium nitride-based integrated bidirectional switching power device includes a die. The die includes a semiconductor body integrating a first switching field-effect transistor and a second switching field-effect transistor, the semiconductor body including a semiconductor substrate and a layer stack stacked on the substrate. The layer stack includes a channel layer of a channel semiconductor alloy of group III and group V elements of the periodic table and a gate layer of a gate semiconductor alloy including gallium nitride. The channel layer forms a channel region, and the gate layer is formed above the channel region in a first transistor gate region and a second transistor gate region arranged at a distance from each other. The substrate is electrically coupled to a substrate node. The die includes a first conductive contact region and a second conductive contact region of a first conductive material, arranged side-by-side at a distance from each other on opposite sides of the channel region. The die includes a substrate bias network configured to selectively electrically couple the substrate node to the first conductive contact region and the second conductive contact region at a minimum potential. The substrate bias network includes a first diode and a second diode anti-series coupled and each having a first terminal and a second terminal. The first terminal of the first diode is coupled to the first conductive contact region, the first terminal of the second diode is coupled to the second conductive contact region, and the second terminals of the first diode and the second diode are coupled together and coupled to the substrate node. The first diode is formed by a transistor connected to a first field-effect diode, and the second diode is formed by a transistor connected to a second field-effect diode. The transistor connected to the first and second field-effect diodes has the same structure as the first and second switching field-effect transistors, extending to the sides of both transistors, and includes a corresponding first diode contact region, a corresponding second diode contact region, and a corresponding diode gate region. The first and second diode contact regions are formed of a first conductive material, and the diode gate region is formed of a gate layer.

[0024] In one embodiment, a gallium nitride-based integrated bidirectional switching power device includes a die comprising a semiconductor body including a substrate, a stack of semiconductor layers on the substrate, and a substrate node electrically coupled to a back side of the substrate. The die includes a first switching field-effect transistor integrated in the substrate and including a first gate terminal coupled to the top of the semiconductor layer stack and a first conductive contact region. The die includes a second switching field-effect transistor integrated in the substrate and including a second gate terminal coupled to the top of the semiconductor layer stack and a second conductive contact region. The die includes a substrate bias network configured to selectively electrically couple the substrate node to the first conductive contact region if the first conductive contact region is at a lower potential than the second conductive contact region, and to the second conductive contact region if the second conductive contact region is at a lower potential than the first conductive contact region. The substrate bias network includes first diode-connected transistors and second diode-connected transistors, each coupled to the substrate node.

[0025] In one embodiment, a method includes applying a first gate voltage to a first gate of a first switching field-effect transistor integrated in a semiconductor body, the semiconductor body including a semiconductor substrate and a plurality of semiconductor layers on the semiconductor substrate. A conductive substrate node is coupled to the bottom of the semiconductor substrate. The method includes applying a second gate voltage to a second gate of a second switching field-effect transistor integrated in a semiconductor body, the semiconductor body including a semiconductor substrate and a plurality of semiconductor layers on the semiconductor substrate. The first and second switching field-effect transistors are coupled together as a bidirectional switch. The method includes applying a voltage between a first conductive contact region of the first switching field-effect transistor coupled to the top of a stack of semiconductor layers and a second conductive contact region of the second switching field-effect transistor coupled to the top of the stack of semiconductor layers. The method includes utilizing a substrate biasing network to selectively couple a substrate node to a first conductive contact region if the first conductive contact region is at a lower potential than the second conductive contact region, or to a second conductive contact region if the second conductive contact region is at a lower potential than the first conductive contact region. The substrate biasing network includes first diode-connected transistors and second diode-connected transistors, each coupled to a substrate node. Attached Figure Description

[0026] To better understand this disclosure, embodiments thereof are now described by way of non-limiting example only with reference to the accompanying drawings, wherein:

[0027] Figure 1 This is a schematic cross-section of a known gallium nitride-based bidirectional switch;

[0028] Figure 2 yes Figure 1 The electrical equivalent of a bidirectional switch in the diagram;

[0029] Figure 3A and 3B It shows Figure 1 A graph showing the electrical charge of the bidirectional switch;

[0030] Figure 4 This is a simplified electrical diagram of an embodiment of this bidirectional power switch;

[0031] Figure 5 It shows Figure 4 A graph showing the electrical charge of a bidirectional power switch;

[0032] Figures 6 to 8 A simplified electrical diagram of another bidirectional power switch according to this disclosure is shown;

[0033] Figure 9 The layout of the semiconductor die with an integrated bidirectional power switch according to a first configuration is shown;

[0034] Figure 10 The layout of a semiconductor die with an integrated bidirectional power switch according to another configuration is shown;

[0035] Figure 11 yes Figure 9 Or a portion of the cross-section of a 10-tube die, essentially along Figure 9 The line XI-XI is cut off;

[0036] Figure 12A , 12B And 12C shows Figure 9 or Figure 10 A simplified layout of metal layers in a semiconductor die;

[0037] Figure 13 This is an enlarged cross-section of a possible implementation of a resistor using gallium nitride-based technology;

[0038] Figure 14 It is along Figure 9 The line XIV-XIV intercepted Figure 13 An enlarged cross-section of the possible implementations of the resistor;

[0039] Figure 15 Shown at an enlarged scale Figure 14 Structural details;

[0040] Figure 16 yes Figure 9 or Figure 10 The cross-section of a portion of the die, in a bidirectional switch such as Figure 7 In the case where the electrical diagram is formed as shown, similar to Figure 11 ;

[0041] Figure 17 yes Figure 16 A plan view of a portion of the source-gate connection of a bidirectional switching diode;

[0042] Figure 18 It is along Figure 17 An enlarged longitudinal section taken from line XVIII-XVIII;

[0043] Figure 19 yes Figure 16 A scaled-down schematic plan view of a portion of the first metallization layer of a bidirectional switch;

[0044] Figure 20 yes Figure 9 The cross-section of a portion of the die, in a bidirectional switch such as Figure 8 In the case where the electrical diagram is formed as shown, similar to Figure 16 ;

[0045] Figure 21 yes Figure 20 A magnified plan view of a portion of the source-gate connection of a bidirectional switching diode;

[0046] Figure 22 It is along Figure 21 The longitudinal section taken from line XXII-XXII;

[0047] Figure 23 yes Figure 9 or Figure 10 A perspective view of the possible coupling between the die, lead frame, and its package; and

[0048] Figure 24 yes Figure 9 or Figure 10 The die is coupled to Figure 23 A plan view of the lead frame. Detailed Implementation

[0049] The following description refers to the arrangement shown; therefore, expressions such as “above,” “below,” “upper,” “lower,” “right,” “left,” etc., refer to the accompanying drawings and should not be interpreted in a restrictive manner.

[0050] Figure 4 An electrical diagram of a gallium nitride-based bidirectional switching power device 30 is shown, which integrates a self-biasing network for the substrate, such as to maintain the substrate clamped to the lowest device voltage each time during operation and in the case of switching operation.

[0051] The bidirectional switching power device 30 is schematically represented as a series connection of a first field-effect transistor (FET) 31 and a second FET 32, coupled between a first conductive terminal S1 and a second conductive terminal S2.

[0052] The first FET transistor 31 and the second FET transistor 32 have the following characteristics: Figure 1 The structures shown and illustrated above; in particular, they are referred to as follows: Figure 9 , 10 Implemented as described.

[0053] The bidirectional switching power device 30 has a first gate terminal G1 and a second gate terminal G2, and is configured to receive a corresponding gate voltage V. G1 V G2 .

[0054] The first FET transistor 31 and the second FET transistor 32 are also coupled to each other in a common node indicated by D.

[0055] The conductive terminals S1, S2 and the gate terminals G1, G2 are intended to be connected to the outside of the bidirectional switching power device 30 via suitable leads, as described in detail below.

[0056] The first conductive terminal S1 and the second conductive terminal S2 are also coupled to the substrate node SUB via the substrate bias network 35. The substrate node SUB is typically not accessible from the outside, but can be connected from the outside if needed.

[0057] The substrate bias network 35 here includes: a first diode D1 having a cathode coupled to a first conductive terminal S1 and an anode coupled to a substrate node SUB; a second diode D2 having a cathode coupled to a second conductive terminal S2 and an anode coupled to a substrate node SUB; and a resistor R coupled between a common node D and a substrate node SUB.

[0058] Therefore, the first diode D1 and the second diode D2 are coupled with a common anode configuration.

[0059] The first diode D1 and the second diode D2 are implemented as field-effect transistors using gallium nitride technology, and have the structure of a first FET transistor 31 and a second FET transistor 32, as described in detail below.

[0060] Assuming that the first gate terminal G1 and the second gate terminal G2 are controlled together to switch between the on-state voltage and the off-state voltage, the operation of the bidirectional switching power device 30 is as follows (see also...). Figure 5 Alternatively, the second gate terminal G2 can be coupled to the second conductive terminal S2. In this second case, the second FET 32 is diode-connected. In this case, the reverse conduction (third quadrant) of the diode-connected transistor is utilized.

[0061] Under the first operating condition, the first bias voltage V S1It is applied to the first conductive terminal S1 and is greater than the first bias voltage V. S1 The second bias voltage V S2 It is applied to the second conductive terminal S2. In this case, the first bias voltage V S1 It is the reference voltage (e.g., ground), and the second bias voltage V S2 The bidirectional switching power device 30 is controlled by applying an on or off voltage to the first gate terminal G1 and the second gate terminal G2 (or only to the first gate terminal G1). Figure 5 This allows it to either be turned on or off (in the "on" and "off" phases, respectively).

[0062] For example, in Figure 5 In the switching operation shown, during the turn-off phase, the first gate terminal G1 and the second gate terminal G2 are coupled to ground, and during the turn-on phase, a turn-on voltage is reached, for example, greater than 6 V; and the second bias voltage V S2 High values ​​(e.g., 400 V).

[0063] During the turn-off phase, gate terminals G1 and G2 prevent current from flowing through the bidirectional switching power device 30; during the turn-on phase, the bidirectional switching power device 30 turns on, and the FET enters the linear region, causing current to flow from the second conductive terminal S2 to the first conductive terminal S1. During this turn-on phase, the voltage V across the second conductive terminal S2... S2 The voltage V decreases and almost reaches the voltage V on the first conductive terminal S1 (ground). S1 .

[0064] Under the second operating condition, the bias of the source terminals S1, S2 (and possibly the gate terminals G1, G2, in the case of diode connection) is reversed relative to the first operating condition, such that during the conduction phase, current can flow from the first conductive terminal S1 to the second conductive terminal S2.

[0065] Under the first operating condition, the second diode D2 is reverse biased, thus being open-circuited; during the conduction phase, the first diode D1 conducts and applies the substrate voltage V. SUB The voltage (V) clamped to the first conductive terminal S1 S1 (grounded). During the turn-off phase, the substrate voltage V SUB Keep it low. At this stage, resistor R (with high resistance, such as a few MΩ) conducts a very low, negligible current, while under the first operating condition, the common node D is coupled to the potential of the second source terminal S2, and under the second operating condition, it is coupled to the potential of the first source terminal S1.

[0066] In dual-mode, under the second operating condition, the first diode D1 is open; during the conduction phase, the second diode D2 is open and conducts the substrate voltage V.SUB The voltage V clamped to the second conductive terminal S2 S2 (Grounded). During the shutdown phase, the substrate node SUB remains grounded.

[0067] In fact, the substrate bias network 35 forms a sub-bias control block that clamps the substrate node SUB to the conductive terminals S1 and S2 that are always at the lowest voltage.

[0068] In addition, the substrate bias network 35 maintains the substrate node SUB clamped to ground during both the turn-on and turn-off phases to prevent unwanted transients.

[0069] Figure 6 A bidirectional switching power device 630 is shown, which includes a first FET transistor and a second FET transistor, similar to... Figure 4 The transistors of the bidirectional switching power device 30 are therefore again indicated by 31 and 32.

[0070] Furthermore, the bidirectional switching power device 630 includes a substrate bias network 635, which includes components formed and coupled to... Figure 4 The first and second diodes of the bidirectional switching power device 30 are therefore indicated again by D1 and D2.

[0071] The substrate bias network 635 here includes a first resistor R1 coupled between the substrate node SUB and the first gate terminal G1, and a second resistor R2 coupled between the substrate node SUB and the second gate terminal G2.

[0072] Figure 7 A bidirectional switching power device 730 is shown, which includes a first FET transistor and a second FET transistor, similar to... Figure 4 The transistors of the bidirectional switching power device 30 are therefore indicated again by 31 and 32.

[0073] In addition, the bidirectional switching power device 730 includes a substrate bias network 735, which includes a first bias transistor M1, a second bias transistor M2, a first resistor R1, and a second resistor R2.

[0074] Bias transistors M1 and M2 are coupled by diodes between their respective conductive terminals S1 and S2 and the substrate node SUB, thus forming a configuration similar to... Figure 4 The two diodes are D1 and D2.

[0075] In detail, the source and gate terminals of the first bias transistor M1 are coupled to the first conductive terminal S1, and the drain terminal is coupled to the substrate node SUB.

[0076] The source and gate terminals of the second bias transistor M2 are coupled to the second conductive terminal S2, and the drain terminal is coupled to the substrate node SUB.

[0077] In fact, the substrate bias network 735 provides common drain coupling for bias transistors M1 and M2; since bias transistors M1 and M2 are diode-coupled, this configuration is also referred to as the common anode configuration below.

[0078] exist Figure 7 In the process, the first resistor R1 is coupled between the first conductive terminal S1 and the substrate node SUB.

[0079] The second resistor R2 is coupled between the second conductive terminal S2 and the substrate node SUB.

[0080] Bias transistors M1 and M2 are integrated on their sides into the same semiconductor die as FET transistors 31 and 32; furthermore, they are fabricated using the same technology and have the same structure as FET transistors 31 and 32, as shown in the following reference. Figures 9 to 11 Detailed description.

[0081] The first resistor R1 and the second resistors R1 and R2 are also fabricated on their sides using the same technology and the same layers as the FET transistors 31 and 32 and the bias transistors M1 and M2, as shown in the reference below. Figures 13 to 15 Detailed description.

[0082] exist Figure 7 In the diagram, parasitic diodes P1 and P2 are also shown as being formed by bias transistors M1 and M2, with diode coupling in reverse parallel to the latter.

[0083] Figure 8 It shows something similar to Figure 7 The bidirectional switching power device 730 and the bidirectional switching power device 830, except that the bias transistors M1, M2 (indicated here by 835) of the substrate bias network are arranged in a common source configuration, also referred to below as a common cathode configuration.

[0084] Therefore, components of the bidirectional switching power device 830 that are equivalent to those of the bidirectional switching power device 730 are indicated by the same reference numerals.

[0085] The operation methods and targets of bidirectional switching power devices 630, 730 and 830 Figure 4 The bidirectional switching power device 30 is described similarly.

[0086] Specifically, the bias transistors M1 and M2, which are diode-connected and anti-series coupled common anode or common cathode transistors, provide a current path from the substrate node SUB to the conductive terminals S1 and S2 via corresponding parasitic diodes P1 and P2 inherent in GaN-HEMT technology, with the conductive terminals S1 and S2 always at a lower voltage.

[0087] Resistors R, R1, and R2 are used as discharge paths for the charge stored due to the capacitance effect in the die substrate, which integrate bidirectional switching power devices 630, 730, and 830.

[0088] In this way, substrate bias networks 635, 735, and 835 provide reliable and effective control over the substrate potential.

[0089] Using GaN-HEMT technology to form all components allows for reduced footprint and improved performance, while also lowering manufacturing costs.

[0090] Figures 9 to 11 A possible technical solution is shown for integrating a general-purpose bidirectional switching power device (indicated here by 930) by properly connecting diodes D1, D2 and resistors R, R1, R2, which is applicable to all bidirectional switching power devices 30, 630, 730, 830.

[0091] In particular, Figure 9 This diagram illustrates the layout of a bidirectional switching power device 930 with anode-coupled diodes D1 and D2, which is typically used in... Figure 4 , 6 The embodiments of 8 depend on the connection between resistors R, R1, R2 and FET transistors 30, 31, and Figure 10 This diagram illustrates the layout of a bidirectional switching power device 930 with diodes D1 and D2 having coupled cathodes, which is typically used in... Figure 8 This is one embodiment, but it can also be used with diodes D1 and D2 in opposite coupling. Figure 4 and 6 The configuration appropriately forms the connection between resistors R, R1, R2 and FET transistors 30, 31.

[0092] Therefore, in Figure 9 and 10 In this document, the connection of one or more resistors R, R1, R2 is not shown, but it will be obvious to those skilled in the art, and this is also based on the following description of embodiments of bidirectional switching power devices 730, 830.

[0093] For details, please refer to Figure 9 and 11The bidirectional switching power device 930 (hereinafter referred to as device 930) is integrated into die 40, wherein Figure 9 The layout of the Cartesian coordinate system XYZ in the XY plane is shown, which has a first horizontal axis X, a second horizontal axis Y, and a vertical axis Z. Figure 11 The cross section is shown in the plane of the Cartesian coordinate system XYZ.

[0094] Figure 9 The active region 68 forming FET transistors 31, 32 and diodes D1, D2 is schematically shown.

[0095] In the considered embodiment, the first FET transistor 31 is formed by a plurality of first power elements 31A adjacent to each other; the second FET transistor 32 is formed by a plurality of second power elements 32A adjacent to each other. Each first power element 31A is coupled in series to a corresponding second power element 32A to form a basic branch 33; the basic branches 33 are coupled in parallel to each other.

[0096] Furthermore, each of the first power elements 31A is integrated adjacent to the second power element 32A, such as Figure 11 As can be seen in, Figure 11 The integration of a single first power element 31A and a single second power element 32A in the same basic branch 33 is shown.

[0097] Diodes D1 and D2 are arranged near one side of the active region 68, on the side of the FET transistors 31 and 32, and are preferably integrated to extend one diode to the side of the other diode.

[0098] Figure 9 The locations of resistors R1 and R2 are also shown (they may be connected in parallel to form a...). Figure 4 The bidirectional switching power device 30 has a single resistor R), which is transverse to the active region 68, and here transverse to diodes D1 and D2.

[0099] Figure 9 The possible arrangement of the pads for the conductive terminals S1, S2 (source pads 57, 58), gate terminals G1, G2 (gate pads 59, 60), and substrate node SUB (substrate pad 61) formed in the upper metallization layer is also schematically shown, as referenced below. Figure 12C Detailed description.

[0100] The following will refer to Figure 11 Describe the possible integration of FET transistors 31 and 32 and diodes D1 and D2 in die 40.

[0101] In particular, Figure 11An integration of a single first power element 31A, a single second power element 32A, and a single diode (e.g., first diode D1) is shown; as indicated above, another diode (second diode D2) that can be arranged to the side of the first diode D1 has the same structure.

[0102] Here, the first diode D1 (similar to the second diode D2, not shown) is a transistor (indicated by M1, and...). Figure 7 and 8 (Similarly), it is made using the same technology as the first power element 31A and the second power element 32A, and has the same structure, wherein the source and gate regions are electrically connected using the two metallization layers already present in the FET transistors 31 and 32, as explained below.

[0103] The die 40 includes a semiconductor body 41. In the illustrated embodiment, the semiconductor body 41 includes a substrate 42, a first semiconductor layer 43, a second semiconductor layer 44, and a third conductive layer 45 stacked on each other in the direction of the vertical axis Z.

[0104] The semiconductor body 41 has an upper surface 41A and a lower surface 41B, and may be, for example, monocrystalline silicon.

[0105] The first semiconductor layer 43, which is directly stacked and in contact with the substrate 42, may consist of a series of sublayers formed from different alloys of elements of Group III and Group V of the periodic table, including gallium nitride (GaN).

[0106] In particular, Figure 11 In the first semiconductor layer 43, there are a first sublayer 43.1 formed by different combinations of AlGaN / GaN / AlN alloys; a second sublayer 43.2 of GaN forming a buffer layer; and a third sublayer 43.3 of GaN forming a channel layer.

[0107] The second semiconductor layer 44, which is directly stacked and in contact with the first semiconductor layer 43, can be a different semiconductor alloy of group III and group V elements of the periodic table, such as aluminum gallium nitride (AlGaN), and forms a barrier layer.

[0108] The first semiconductor layer 43 and the second semiconductor layer 44 are, for example, N-type.

[0109] The third semiconductor layer 45 is another semiconductor alloy of Group III and Group V elements of the periodic table, and is generally different from the alloys of the first semiconductor layer 43 and the second semiconductor layer 44. The third semiconductor layer 45 is, for example, p-type gallium nitride (p-GaN) and forms multiple gate conductive regions that extend at intervals above the second semiconductor layer 44 along a direction parallel to the second horizontal axis Y. Therefore, in the following text, the third semiconductor layer 45 is also referred to as the gate layer 45.

[0110] In particular, Figure 11 The first gate conductive region 45A, the second gate conductive region 45B, and the third gate conductive region 45, respectively, belonging to the first power element 31A, the second power element 31B, and the diode D1, are shown. Figure 11 In the cross-section, each gate conductive region 45A to 45C is divided into two parts.

[0111] The first gate metallization region 49A, the second gate metallization region 49B, and the third gate metallization region 49C belonging to the gate metallization layer 49 are in direct contact with the first gate conductive region 45A, the second gate conductive region 45B, and the third gate conductive region 45C, respectively.

[0112] Specifically, the first gate metallization region 49A and the second gate metallization region 49B are coupled to the first gate terminal G1 and the second gate terminal G2, respectively, while the third gate metallization region 49C is coupled to the lower cathode contact region 56C.

[0113] Specifically, and in a manner not shown, the first gate metallization region 49A and the second gate metallization region 49B are formed by strips extending perpendicular to the plane of the sheet and parallel to the second horizontal axis Y, forming "gate fingers".

[0114] As discussed below, the gate metallization regions 49A and 49B are coupled at their ends, in a manner not shown, to gate contact regions formed in the same layer as the lower conductive contact portions 51A, 51B, 51C, and 51D, as referenced below. Figure 12A Described.

[0115] The bidirectional switching power device 930 also includes ohmic contact regions to obtain low resistivity contacts between conductive terminals S1, S2 and the first semiconductor layer 43, between the first conductive terminal S1 and the first semiconductor layer, and between the substrate node SUB and the first semiconductor layer 43.

[0116] In detail, Figure 11 The diagram shows a first ohmic contact region 50A belonging to the first power element 31A; a second ohmic contact region 50B belonging to the second power element 31B; and a third ohmic contact region 50C and a fourth ohmic contact region 50D belonging to the diode D1.

[0117] Ohmic contact regions 50A, 50B, 50C and 50D are in direct electrical contact with the first semiconductor layer 43 (more precisely, with the channel layer 43.3) of the semiconductor body 41, and are formed, for example, by a Ti / AlCu / TiN multilayer.

[0118] The channel layer 43.3 forms a channel region schematically indicated by 65 between the first ohmic contact region 50A and the second ohmic contact region 50B.

[0119] Ohmic contact regions 50A, 50B, 50C, and 50D are part of a conductive contact structure, which also includes a first conductive metallized region 51A, a second conductive metallized region 51B, a third conductive metallized region 51C, and a fourth conductive metallized region 51D. These regions are stacked and directly electrically contact the first ohmic contact region 50A, the second ohmic contact region 50B, the third ohmic contact region 50C, and the fourth ohmic contact region 50D.

[0120] Specifically, the first ohmic contact region 50A, the second ohmic contact region 50B, the third ohmic contact region 50C, and the fourth ohmic contact region 50D (together with the corresponding conductive metallization regions 51A, 51B, 51C, and 51D) form the corresponding lower source contact portions of the first power element 31A and the second power element 31B, as well as the lower source and drain contact portions of the transistor M1 (forming the first diode D1). Therefore, in the following text, they are also referred to as the first lower transistor source contact region 56A, the second lower transistor source contact region 56B, the lower cathode contact region 56C, and the lower anode contact region 56D.

[0121] Conductive metallization regions 51A, 51B, 51C, and 51D are formed in a metal layer called the first interconnect metallization layer 70, such as Figure 12A As shown, it is shaped to form a field plate. Figure 11 In the illustrated embodiment, the conductive metallization regions 51A, 51B, and 51C are also in direct electrical contact with the field plate structure. The field plate structure includes a thin metal region 52 formed in a thin metal layer 55 (also referred to as layer 0) and an auxiliary metal region 53 formed in the same layer as the gate metallization regions 49A to 49C (gate metallization layer 49). The field plate structures 52 to 53 may exist on both sides of the conductive metallization regions 51A, 51B, and 51C, or may be completely absent.

[0122] like Figure 11 The illustration is shown in the image, and reference is made to the image. Figure 17 , 18 right Figure 7 The bidirectional switching power device 730 is described in detail and referenced. Figure 21 , 22 right Figure 8The bidirectional switching power device 830 is described in detail, wherein the third lower conductive contact portion 51C of the first interconnect metallization layer 70 is electrically coupled to the third gate metallization region 49C to form a diode D1. In this way, the third ohmic contact region 50C (the source contact of the first bias transistor M1) forms the cathode terminal of the diode D1, and the fourth ohmic contact region 50D (the drain contact of the first bias transistor M1) forms the anode terminal of the diode D1.

[0123] An insulating layer, typically indicated by 54 and typically formed of multiple stacked insulating layers (e.g., silicon oxide), covers the upper surface 41A of the semiconductor body 41 and embeds gate conductive regions 45A to 45C, gate metallization regions 49A to 49C, ohmic contact regions 50A to 50D, lower conductive contact portions 51A to 51D, and field plate structures 52 to 53.

[0124] A via (not shown) extends through insulating layer 54 and couples lower conductive contact portions 51A to 51D to upper metallization layer, allowing connection to external terminals and forming a connection for device 930, as described below for... Figure 7 , 8 The bidirectional switching power devices 730 and 830 are discussed in detail.

[0125] In particular, such as Figure 11 As schematically shown, the first conductive metallization region 51A is coupled to the first conductive terminal S1; the second metallization region 51B is coupled to the second conductive terminal S2; the third metallization region 51C is coupled to the third gate conductive region 45C and one of the first conductive terminal S1 and the substrate node SUB (depending on whether the device 930 forms a bidirectional switching power device 30, 630, 730 or 830); and the fourth metallization region 51D is coupled to the other of the first conductive terminal S1 and the substrate node SUB.

[0126] As described in detail below, the post-metallization layer 67 coupled to the substrate node SUB extends on the lower surface 41B of the semiconductor body 41.

[0127] Die 40 also accommodates resistors R, R1, and R2 on the sides of diodes D1 and D2. Figure 11 The figure is not shown in the figure and will be described in detail below with reference to Figures 12 to 14.

[0128] Figure 10 The layout of a bidirectional switching power device (indicated here by 930') with cathode-coupled diodes D1 and D2 is shown. This layout is similar to... Figure 9 Completely similar, and referenced above. Figure 9 and 11 The described layout also applies Figure 10The configuration, except that the two diodes D1 and D2 are at the cathode terminal instead of the anode terminal ( Figure 11 The connections between the conductive terminals S1 and S2 (which are not visible in the middle) and between the conductive terminals S1 and S2 and the anode and cathode terminals are interchangeable.

[0129] Figures 9 to 11 The components of the devices 930 and 930' shown are interconnected using three interconnect metallization layers stacked on the gate metallization layer 49 and layer 0 (thin metal layer 55), as shown. Figure 11 It is visible in the text.

[0130] Specifically, devices 930 and 930' include three interconnect metallization layers, which are connected to... Figure 9 Device 930 and Figure 10 The device 930' has a similar configuration and differs substantially only in the interconnection between different layers.

[0131] exist Figures 12A to 12C The diagram shows three metallization layers for two devices 930 and 930', including a first interconnect metallization layer 70 (in...). Figure 11 This can also be seen in the text, and in Figure 12A (shown in detail); second interconnect metallization layer 71 ( Figure 11 Invisible in the middle, and in Figure 12B (shown in detail); and the third interconnect metallization layer 72 (shown in detail); Figure 11 Invisible in the middle, and in Figure 12C (See details in the text).

[0132] In particular, Figure 12A In the illustrated embodiment, the first interconnect metallization layer 70 formed above the thin metal layer 55 includes: First lower gate contact portion 74; Second lower gate contact portion 75; Multiple first conductive metallization regions 51A (one of which is such as Figure 11 (as shown) Multiple second conductive metallization regions 51B (one of which is such as Figure 11 (as shown) Two third conductive metallization regions 51C; and Two fourth conductive metallization regions 51D.

[0133] The first lower gate contact portion 74 includes a first lower gate metal connection portion 74A and a first vertical portion 74B.

[0134] The second lower gate contact portion 75 includes a second lower gate metal connection portion 75A and a second longitudinal portion 75B.

[0135] The first lower gate metal connection portion 74A and the second lower gate metal connection portion 75A are allowed to be connected to the second interconnect metallization layer 71 through vias (not shown) to form the first gate terminal G1 and the second gate terminal G2, respectively.

[0136] The first longitudinal portion 74B and the second longitudinal portion 75B have elongated shapes (here along a direction parallel to the first horizontal axis X), and are respectively connected to... Figure 11 The first gate metallization region 49A and the second gate metallization region 49B in the gate metallization layer 49 are coupled.

[0137] The first conductive metallized region and the second conductive metallized region 51B have an elongated shape in a direction parallel to the second horizontal axis Y, and extend between the longitudinal portions 74B and 75B (but are electrically insulated from them).

[0138] The first conductive metallization region 51A and the second conductive metallization region 51B essentially form source fingers that intersect with each other.

[0139] Each third conductive metallized region 51C is adjacent to a corresponding fourth conductive metallized region 51D; the third conductive metallized region 51C and the fourth conductive metallized region 51D have an elongated shape, extend parallel to the first lower conductive contact portion 51A and the second lower conductive contact portion 51B, and extend laterally for approximately the same length, as shown below. Figure 16 and 20 The manner shown and described in detail is connected to the second interconnect metallization layer 71 to form a coupled anode or cathode configuration.

[0140] Furthermore, here, the first interconnect layer forms contact metal portions 80, 81 (schematically shown) for resistors R, R1, R2; see below for reference. Figures 13 to 15 Describe in detail these metal contact parts 80 and 81.

[0141] Figure 12B An example layout of the second interconnect metallization layer 71 is shown.

[0142] In detail, Figure 12B In the middle, the second interconnect metallization layer 71 is formed: The first intermediate gate contact portion 93 is coupled to the first lower gate contact portion 74A through a lower gate metal connection (e.g., a via) not shown; The second intermediate gate contact portion 94 is coupled to the second lower gate contact portion 75A through a via (not shown); Multiple first intermediate conductive contact portions 90A, each first intermediate conductive contact portion 90A is covered with a corresponding first lower conductive contact portion 51A, and is electrically in contact with it through a via not shown; Multiple second intermediate conductive contact portions 90B, each second intermediate conductive contact portion 90B covered by a corresponding second lower conductive contact portion 51B, and electrically contacted therewith through a via not shown; A third intermediate conductive contact portion 91 extends transversely to the first intermediate conductive contact portion 90A and is in electrical contact with it at one end. Here, the third intermediate conductive contact portion 91 extends, for example, in a direction parallel to the first horizontal axis X; A fourth intermediate conductive contact portion 92 extends transversely to the second intermediate conductive contact portion 90B and is in electrical contact with it at one end. Here, the fourth intermediate conductive contact portion 92 extends, for example, in a direction parallel to the first horizontal axis X; and The intermediate substrate contact portion 95, depending on the configuration and coupling of diodes D1 and D2, is selectively coupled to either the third lower conductive contact portion 51C or the fourth lower conductive contact portion 51D, as shown in the following reference. Figures 16 to 21 Detailed description.

[0143] The intermediate substrate contact portion 95 extends parallel to the first intermediate conductive contact portion 90A and the second intermediate conductive contact portion 90B on its longitudinal side, and is covered by either the first lower conductive contact portion 51C or the second lower conductive contact portion 51D selectively connected thereto, depending on the connection configuration of diodes D1 and D2, such as, for example Figures 16 to 22 See details below.

[0144] The intermediate substrate contact portion 95 also extends above the contact metal portions 80 and 81, through... Figure 14 and 15 The via shown is electrically connected to the contact metal portion.

[0145] Figure 12C An example layout of the third interconnect metallization layer 72 is shown.

[0146] In detail, Figure 12C In the middle, the third interconnect metallization layer 72 is formed: Multiple first upper conductive contact portions 100A, each first upper conductive contact portion 100A is covered with a corresponding first intermediate conductive contact portion 90A, and is electrically in contact with it through a via not shown; Multiple second upper conductive contact portions 100B, each second upper conductive contact portion 100B is covered with a corresponding second intermediate conductive contact portion 90B, and is electrically in contact with it through a via not shown; The third upper conductive contact portion 101 is coupled to the third intermediate conductive contact portion 91 through a via (not shown); The fourth upper conductive contact portion 102 is coupled to the fourth intermediate conductive contact portion 92 through a via (not shown); The first upper gate contact portion 103 is coupled to the first intermediate gate contact portion 93 through a via (not shown); The second upper gate contact portion 104 is coupled to the second intermediate gate contact portion 94 through a via (not shown); and The upper substrate contact portion 105 is coupled to the middle substrate contact portion 95, such as... Figure 14 As shown below, and will be described in detail below.

[0147] Figure 12C Also shown are pads formed directly on or above the third interconnect metallization layer 72 and including gate pads 59 and 60 that are in direct electrical contact with the first upper gate contact portion 103 and the second upper gate contact portion 104, respectively; conductive pads 57 and 58 that are in direct electrical contact with the third upper conductive contact portion 101 and the fourth upper conductive contact portion 102, respectively; and substrate pad 61 that is in direct electrical contact with the upper substrate contact connection 104.

[0148] Figure 13 Possible embodiments of resistors R, R1, and R2 are shown, which utilize the presence of a third semiconductor layer 45 of p-GaN, which forms, for example... Figure 11 The gate conductive regions 45A to 45C are included. In fact, the third semiconductor layer 45 allows the two-dimensional electron gas 2deg formed in the lower layer (third sublayer 43.3, channel sublayer) to be partially depleted, thus increasing the resistivity of this region.

[0149] exist Figure 13 In the p-GaN depletion region 110 is stacked on the body 111, which includes, for example, a silicon substrate 112, a channel layer 113 of a GaN alloy, and an AlGaN barrier layer 114 that may be covered by one or more GaN layers.

[0150] For example, substrate 112 may include substrate 42, Figure 11 The first sublayer 43.1 and the second sublayer 43.2; the channel layer 113 may include Figure 11 The third sublayer 43.3; and the barrier layer 114 may include Figure 11 The second semiconductor layer 44.

[0151] As indicated, the depletion region 110 is stacked on the barrier layer 114 and is disposed between the first ohmic contact 115 and the second ohmic contact 116. For example, the first ohmic contact 115 and the second ohmic contact 116 can be coupled with... Figure 11 The ohmic contact areas 50A to 50D are formed in the same layer in a similar manner.

[0152] Insulation layer 118 covers the depleted area 110 here.

[0153] The presence of the depletion layer 110 increases the resistivity of the channel layer 113 portion between the two ohmic contacts 115, 116, forming resistors R / R1 / R2 (resistor portion 119) in the channel layer 13. In this way, a resistor with reduced length can be obtained by direct integration into the die 40.

[0154] Figure 14 and 15 It shows the use of Figure 13 Technical solutions and Figures 12A to 12C The three interconnecting metallization layers 70 to 72 shown implement resistors R, R1, and R2 in die 40.

[0155] Specifically, here, the insulating layer separating the first interconnect metallization layer 70 from the second interconnect metallization layer 71 is designated as the first insulating layer 54A, and the insulating layer separating the second interconnect metallization layer 71 from the third interconnect metallization layer 72 is designated as the second insulating layer 54B.

[0156] Specifically, each resistor R / R1 / R2 extends between the fifth ohmic contact region 50E and the sixth ohmic contact region 50F, these ohmic contact regions being formed with... Figure 11 In the same layer as the ohmic contact regions 50A to 50D, on the first semiconductor layer 43 of the semiconductor body 41 and in direct electrical contact with it (more precisely, with the third sublayer 43.3, the channel sublayer).

[0157] The fifth ohmic contact region 50E and the sixth ohmic contact region 50F are respectively contacted by corresponding contact metal portions 80 and 81 formed in the first interconnect metallization layer. Figure 12A ).

[0158] Contact metal portions 80 and 81 (forming a first contact metal portion 80 and a second contact metal portion 81) are coupled to an intermediate substrate contact portion 95 and another intermediate contact portion 96 (both belonging to the second interconnect metallization layer 71) respectively through a metal substrate via 97 extending in the first insulating layer 54A.

[0159] In fact, the fifth ohmic contact region 50E, the first contact metal portion 80 and the corresponding substrate via 97 form a lower substrate intermetallic connection 120, which electrically couples the first end of resistors R / R1 / R2 to the intermediate substrate contact portion 95 and the semiconductor body 41.

[0160] The sixth ohmic contact region 50F, the second contact metal portion 81, and the corresponding substrate via 97 form a resistor connection 121, which, depending on the topology of the substrate bias networks 35, 635, 735, 835, couples the second end of resistors R / R1 / R2 to... Figure 11 The device 930 comprises (multiple) components. For example, in Figure 7 , 8 In the case of substrate bias networks 735 and 835, another intermediate contact portion 96 can be Figure 12B The third intermediate conductive contact portion 91 is used to couple the second end of the first resistor R1 to the first conductive terminal S1.

[0161] exist Figure 7 , 8 In the case of substrate bias networks 735 and 835, a biasing network is provided for the second resistor R2. Figure 14 A completely similar structure. In this case, another intermediate contact portion 96 is formed by... Figure 12B The fourth intermediate conductive contact portion 92 is formed.

[0162] exist Figure 4 In the case of substrate bias network 35, by connecting the second terminal of resistor R to common node D, Figure 14 Another intermediate contact portion 96 can be coupled to a portion (not shown) of the first interconnect metallization layer 70, which is connected via an ohmic contact. Figure 11 The third sublayer 43.3 (not shown) between the first ohmic contact region 50A and the second ohmic contact region 50B.

[0163] exist Figure 6 In the case of substrate bias network 635, Figure 14 Another intermediate contact portion 96 can be coupled to, in a manner not shown but obvious to those skilled in the art, to Figure 12A The first lower gate contact portion 74 (for the first resistor R1) and the second lower gate contact portion 75 (for the second resistor R2).

[0164] Figure 14 The upper substrate inter-metal connection 122 is also shown, formed by a plurality of metal vias extending through a second insulating layer 54B between a second interconnect metallization layer 71 and a third interconnect metallization layer 72, and connecting an intermediate substrate contact portion 95 in the second interconnect metallization layer 71. Figure 12B Electrically coupled to the upper substrate contact portion 105 in the third interconnect metallization layer 72 ( Figure 12C ).

[0165] In fact, the lower substrate metal connection 120, the intermediate substrate contact portion 95, the upper substrate metal connection 122 and the upper substrate contact portion 105 enable the upper substrate contact portion 105 (therefore the substrate pad 61 which is not visible here) to contact the first semiconductor layer 43, and thus achieve contact with the substrate 42.

[0166] Another intermediate contact portion 96 is electrically coupled to another upper contact portion 124 formed in the third interconnect metallization layer 72 by another upper metallization connection 123 formed by a plurality of metal vias extending through the second insulating layer 54B between the second interconnect metallization layer 71 and the third interconnect metallization layer 72.

[0167] For example, in Figure 7 , 8 In the case of substrate biasing networks 735 and 835, another upper contact portion 124 is the third upper conductive contact portion 101.

[0168] In fact, in this case, another intermetallic connection 123 will Figure 12B , 12C The third intermediate conductive contact portion 91 and the third upper conductive contact portion 101 are electrically coupled.

[0169] Other contact portions can also extend directly between these portions 91 and 101 on the long side of the die 40.

[0170] In addition, Figure 12A A similar connection using suitable vias between the first lower conductive contact portion 51A, the third intermediate conductive contact portion 91A, and the third upper conductive contact portion 101A allows for the third sublayer 43.3 (in Figure 11 Electrical connection between the first ohmic contact area 50A and the first source pad 57.

[0171] Similarly, Figure 12A The second lower conductive contact portion 51B can be connected to the second source pad 58, such as, for example Figure 16 and 20 As shown.

[0172] The passivation layer 125 (e.g., formed of multiple stacked insulating layers) extends over the third interconnect metallization layer 72 in a known manner and has openings at pads 57 to 61.

[0173] Figures 16 to 19 It shows Figure 7 An embodiment of the device 730.

[0174] In particular, Figure 16 It shows something similar to Figure 11 The cross-section of the first power element 31A is not shown, but portions of the second interconnect metallization layer 71 and the third interconnect metallization layer 72 of the second power element 32A and diode D1 are visible.

[0175] For clarity, Figures 16 to 19 The use of Figures 11 to 15 The same reference numerals are used in the accompanying drawings, and the common parts are no longer described.

[0176] In detail, Figure 16 A first anode interconnect 128 (formed by a via extending through the insulating layer 54) is shown, which couples the lower anode contact region 56D to the intermediate substrate contact portion 95, and an upper substrate intermetallic connection 122 connects the intermediate substrate contact portion 95 to the upper substrate contact portion 105 (see also...). Figure 14 ), forming the anode of diode D1 and Figure 7 The connection of the substrate node SUB.

[0177] also, Figure 16 This diagram illustrates a lower transistor source metal-to-metal connection 230 (formed here by a via) coupling the second lower transistor source contact region 56B to the corresponding second intermediate conductive contact portion 90B, and an upper transistor source metal-to-metal connection 231 (formed here by a via) coupling the second intermediate conductive contact portion 90B to the corresponding second upper conductive contact portion 100B. Figure 7 In the case of device 730, with Figure 14 Another metal-to-metal connection 123 is similar and connected in parallel.

[0178] As indicated above, here, the third gate conductive region 45C (the gate region of the first diode D1) is electrically coupled to the third lower conductive contact portion 51C (the source / cathode contact of the first transistor D1) to connect the transistor M1 coupled to the first bias diode, thereby forming the first diode D1, as shown. Figure 17 and 18 As shown, for clarity, the second interconnect metallization layer 71 and the third interconnect metallization layer 71, as well as the interconnect structure, are not shown.

[0179] In detail, Figure 17 A portion of the die 40 is shown near one end of the source finger of the first diode D1. The second semiconductor layer 44 is interrupted at the third ohmic contact region 50C and is in direct contact with the first semiconductor layer 43.

[0180] Figure 17 The shape of the third gate metallization region 49C is shown, which surrounds the third gate conductive region 45C and has an elongated portion 240 (see also...). Figure 18 The elongated portion 240 is also formed in the gate metallization layer 49 and extends beyond the second semiconductor layer 44 thereon.

[0181] A portion of the first insulating layer 54A, separating the gate metallization layer 49 from the first interconnect metallization layer 70, is removed over the elongated portion 240 of the third gate conductive region 45C, thereby forming a direct electrical contact between the elongated portion 240 and the third metallization region 51C. Figure 18 It is visible in the text.

[0182] In this way, refer again Figure 16 The third ohmic contact region 50C (i.e., the source contact of the first bias transistor M1) is short-circuited with the third gate conductive region 45C (i.e., the gate region of the first bias transistor M1) to form diode D1.

[0183] Figure 19 The interconnection between diodes D1 and D2 and the second interconnect metallization layer 71 is shown in a scaled-down and schematic manner.

[0184] Specifically, for each diode D1, D2, Figure 19 This diagram illustrates a first cathode interconnect 241 connecting each third metallization region 51C to a corresponding third intermediate conductive contact portion 91, and a fourth metallization region 51D connecting each diode D1, D2 to... Figure 12B and 16 The first anode interconnect 128 of the intermediate substrate contact portion 95.

[0185] Figures 20 to 22 It shows Figure 8 An embodiment of the device 830; in particular, Figure 20 and Figure 16 Similarly, and along the same cross-section, Figure 21 and Figure 17 Similarly, and Figure 22 and Figure 18 similar.

[0186] As from Figures 20 to 22 With simulation Figures 16 to 18 The comparison mentioned, Figures 20 to 22 The structure of device 830 and Figures 16 to 19 The structure of the device 730 is completely similar, and the only difference is that the connection between the third metallization region 51C and the fourth metallization region 51D and the second interconnect metallization layer 71 is interchangeable.

[0187] Therefore, no further description will be given. Figures 20 to 22 Device 830 and Figures 16 to 19 The common part of the device 730.

[0188] In detail, Figure 20 and 21 In this configuration, the third metallization region 51C (the source / cathode contact of the first diode D1) is coupled to the intermediate substrate contact portion 95 via a second cathode interconnect 245, which is formed by a via extending between the first interconnect metallization layer 70 and the second interconnect metallization layer 71, extending through the first insulating layer 54A. In this configuration, the upper substrate intermetallic connection 122 provides coupling from the cathode terminal of the diode D1 to the substrate node SUB.

[0189] Figure 20 A second anode interconnect 246, which couples the fourth metallization region 51D to the first intermediate conductive contact portion 91, is also shown.

[0190] Alternatively, the second anode interconnect 246 may be formed only at the end (not visible) of the fourth metallization region 51D, and the intermediate substrate contact portion 95 may also extend on the fourth metallization region 51D to form a field plate, similar to Figure 16 As shown (but with the opposite coupling).

[0191] Figure 22 The connection between the third ohmic contact region 50C and the third gate conductive region 45C is shown; the third ohmic contact region 50C, which serves as the source contact for the first bias transistor M1, is short-circuited to the third gate conductive region 45C. As mentioned, this connection is related to... Figure 18 It is exactly the same as the one in the previous one, so it will not be described further.

[0192] Bidirectional switching power devices 30, 630, 730, 830, 930, and 930' can be packaged in TOLT (TOp-side lead-cooled package) type housings, such as... Figure 23 and 24 As shown.

[0193] In detail, die 40 is attached to lead frame 130, and post-metallization layer 67 ( Figure 11 The source and gate pads 57 to 60 are bonded to the support portion 131 of the lead frame 130; the wiring 132 couples the source and gate pads 57 to 60 to the corresponding leads 133 of the lead frame 131.

[0194] In the illustrated embodiment, die 40 has two substrate pads, indicated by 61A and 61B, coupled to support portion 131 via corresponding wiring 134.

[0195] An insulating housing 135 (e.g., resin) is embedded in the support portion 131, the core 40, the wiring 132, 134, and the initial portion of the lead 133 in a manner known per se.

[0196] With the help of Figure 23 , 24 The arrangement shown, and reference Figure 11 The lower surface 41B of the semiconductor body 41 (and the substrate 42) can be electrically connected to the upper surface 41A, thereby electrically connected to the substrate node SUB.

[0197] In this way, the substrate 42 is connected to the substrate terminal (SUB) 61 in a simple manner, as discussed above, and the substrate terminal 61 maintains the lowest potential coupled to the die 40 each time.

[0198] Finally, it is obvious that modifications and variations can be made to the bidirectional switching power devices described and illustrated herein without departing from the scope of this disclosure, as defined in the appended claims. For example, the different embodiments described can be combined to provide other technical solutions.

[0199] In addition, the electrical connection between the substrate terminal SUB and the substrate 42 can be achieved in different ways, either by direct coupling or by a conductive via through the semiconductor body 41.

[0200] Furthermore, the resistor can be formed differently, for example, by appropriately locally doped channel layer 43.3 or without providing it. Figure 9 The depletion region 110 is appropriately selected by utilizing the non-zero resistivity of the two-dimensional gas, with the distance between the ohmic contacts 115 and 116 appropriately chosen. Alternatively, the resistor can be formed in the upper interconnect metal layers 71 and 72 using a high resistivity material (e.g., SiCr and TaN).

[0201] Ohmic contacts 50A to 50F, 115, and 116 can be formed to contact barrier layers 44 and 114, or partially recessed into barrier layers 44 and 114, or even completely recessed into them, and directly contact channel layers 43, 32, and 112.

[0202] In one embodiment, a gallium nitride-based integrated bidirectional switching power device (30; 630; 730; 830; 930; 930') includes a die (40) comprising: a semiconductor body (41) integrating a first switching field-effect transistor and a second switching field-effect transistor (31, 32), the semiconductor body including a semiconductor substrate (42) and a layer stack (43 to 45) stacked on the substrate (42), the layer stack including a channel layer (43.3) of a channel semiconductor alloy of group III and group V elements of the periodic table and a gate layer (45) including a gate semiconductor alloy of gallium nitride, wherein the channel layer (43.3) A channel region (65) is formed, and a gate layer (45) is formed above the channel region, with a first transistor gate region and a second transistor gate region (45A, 45B) arranged at a distance from each other. A substrate (42) is electrically coupled to a substrate node (SUB, 61). A first conductive contact region and a second conductive contact region (50A, 50B) of a first conductive material are arranged side by side at a distance from each other on opposite sides of the channel region (65). A substrate bias network (35; 635; 735; 835) is configured to selectively electrically couple the substrate node (SUB, 61) to the first conductive contact region and the second conductive contact region (50A, 50B) at a minimum potential. 0B), substrate bias network (35; 635; 735; 835) includes a first diode and a second diode (D1, D2) anti-series coupled and each having a first terminal and a second terminal, wherein the first terminal of the first diode is coupled to a first conductive contact region (50A), the first terminal of the second diode is coupled to a second conductive contact region (50B), and the second terminals of the first diode and the second diode are coupled together and coupled to a substrate node (SUB), wherein the first diode (D1) is formed by a transistor (M1) connected to a field-effect diode, and the second diode (D2) is formed by a transistor (M2) connected to a second field-effect diode. The transistors connected to the first and second field-effect diodes (M1, M2) have the same structure as the first and second switching field-effect transistors (31, 32), extending to the sides of the first and second switching field-effect transistors, and including a corresponding first diode contact region (50C), a corresponding second diode contact region (50D), and a corresponding diode gate region (45C), wherein the first and second diode contact regions (50C, 50D) are formed of a first conductive material, and the diode gate region (45C) is formed of a gate layer (45).

[0203] The channel semiconductor alloy comprises gallium nitride of a first conductivity type, and the gate semiconductor alloy is of a second conductivity type.

[0204] The first lower conductive contact portion, the second lower conductive contact portion, and the third lower conductive contact portion (51A, 51B, 51C) form a field plate.

[0205] The device includes at least one first interconnect metal layer (70) overlying a semiconductor body (41) and forming: a first lower conductive contact portion (51A) electrically contacting a first conductive contact region (50A); a second lower conductive contact portion (51B) electrically contacting a second conductive contact region (50B); a third lower conductive contact portion and a fourth lower conductive contact portion (51C, 51D) for each diode (D1, D2), wherein the third lower conductive contact portion (51C) of each diode is directly electrically contacting a corresponding first diode contact region (50C), and the fourth lower conductive contact portion (51D) of each diode is directly electrically contacting a corresponding second diode contact region (50D). For each diode, the device also includes a diode gate metallization region (49C, 140) under the first interconnect metal layer (70) and directly electrically contacting a corresponding diode gate region (45C) and a corresponding third metallization region (51C).

[0206] The device also includes a gate metallization layer (49) forming a diode gate metallization region (49C, 140) and a first transistor gate metallization region and a second transistor gate metallization region (49A, 49B); the first transistor gate metallization region and the second transistor gate metallization region (49A, 49B) are respectively disposed above the first transistor gate region and the second transistor gate region (45A, 45B) and are in direct electrical contact with them; and the first transistor gate metallization region and the second transistor gate metallization region (49A, 49B) are respectively coupled to a first lower gate metal connection portion and a second lower gate metal connection portion (74, 75) formed by the first interconnect metal layer (70).

[0207] The device also includes a second interconnect metal layer (71) overlying the first interconnect metal layer (70) and separated by a first insulating layer (54A); the second interconnect metal layer (71) is formed with: a first intermediate conductive contact portion and a second intermediate conductive contact portion (90A, 91, 90B, 92) respectively, which are partially overlying and electrically coupled to the first lower conductive contact portion and the second lower conductive contact portion (51A, 51B) through a lower conductive intermetallic connection (230); a first intermediate gate contact portion and a second intermediate gate contact portion (93, 94) respectively, which are overlying and electrically coupled to the first lower gate metal connection portion and the second lower gate metal connection portion (74, 75) through a lower gate intermetallic connection; and an intermediate substrate contact portion (95) overlying and electrically and selectively coupled to a third conductive metallization region or a fourth conductive metallization region (51C, 51D), the intermediate substrate contact portion (95) also being ohmically coupled to the substrate (42) and electrically connected to the substrate node (SUB, 61).

[0208] The device also includes a third interconnect metal layer (72), which covers the second interconnect metal layer (71) and is separated by a second insulating layer (54B); the third interconnect metal layer (72) is formed with: a first upper gate contact portion and a second upper gate contact portion (103, 104), respectively, which are covered and electrically coupled to a first lower gate metal connection portion and a second lower gate metal connection portion (74, 75) through an upper gate metal connection; a first upper conductive contact portion and a second upper conductive contact portion (101, 102), respectively, which are covered and electrically coupled to a first intermediate conductive contact portion and a second intermediate conductive contact portion (90A, 91, 90B, 92) through corresponding upper conductive metal connections (231); and an upper substrate contact portion (105), which is covered and electrically coupled to an intermediate substrate contact portion (95) through an upper substrate metal connection (122), the upper substrate contact portion (105) forming a substrate node (SUB).

[0209] The stacked layers (43 to 45) further include a first sublayer (43.1) stacked on the substrate (42) and comprising a first GaN alloy; a buffer layer (43.2) stacked on the first sublayer (43.1) and below the channel layer (43.3) and comprising a second GaN alloy; and a barrier layer (44) stacked on the channel layer (43.3) and comprising aluminum gallium nitride, wherein the channel semiconductor alloy is a third GaN alloy, and the barrier layer (44) and the channel layer (43.3) form a heterostructure; wherein a first transistor gate region (45A), a second transistor gate region (45B) and a diode gate region (45C) of each diode (D1, D2) are disposed above the barrier layer (44) and comprise a fourth GaN alloy with a conductivity opposite to that of the channel layer (43.3) and the barrier layer (44).

[0210] The substrate (42) of the semiconductor body (41) is bonded to the support portion (131) of the lead frame (130), and the connecting wire (134) couples the substrate node (SUB, 61) to the support portion of the lead frame (130).

[0211] The die (40) and lead frame (130) are encapsulated in an electrically insulating housing (135) and form a TOLT-Top side lead cooling package.

[0212] The substrate bias network (35; 635; 735; 835) also includes at least one first resistor (R, R1, R2) having a first resistor terminal coupled to a substrate node (SUB, 61) and a second resistor terminal coupled to a region selected from: i) a portion of the channel region (65) disposed between a first conductive contact region 50A and a second conductive contact region 50B, ii) a first transistor gate region (45A), and

[0213] iii) A first conductive contact region (50A), wherein a first resistor (R, R1, R2) is formed by a resistive portion of the channel layer (43.3) transverse to the channel region (65).

[0214] The resistive portion (119) is covered by the depletion region (110) formed by the gate layer (45).

[0215] The resistive portion (119) has one end ohmically coupled to the substrate (42) and ohmically coupled to the substrate node (SUB, 61).

[0216] The first resistor (R1) is coupled to the first transistor gate region (45A). The device also includes a second resistor (R2) coupled to the second transistor gate region (45B). The second resistor (R2) is formed by another resistive portion of the channel layer (43.3) transverse to the channel region (65). The other resistive portion (119) has one end ohmically coupled to the substrate (42) and ohmically coupled to the substrate node (SUB, 61).

[0217] The first resistor (R1) is coupled to the first conductive contact region (50A). The device also includes a second resistor (R2) coupled to the second conductive contact region (50B). The second resistor (R2) is formed by another resistive portion of the channel layer (43.3) transverse to the channel region (65). The other resistive portion (119) has one end ohmically coupled to the substrate (42) and ohmically coupled to the substrate node (SUB, 61).

[0218] In one embodiment, a gallium nitride-based integrated bidirectional switching power device includes a die comprising a semiconductor body including a substrate, a stack of semiconductor layers on the substrate, and a substrate node electrically coupled to a back side of the substrate. The die includes a first switching field-effect transistor integrated in the substrate and including a first gate terminal coupled to the top of the semiconductor layer stack and a first conductive contact region. The die includes a second switching field-effect transistor integrated in the substrate and including a second gate terminal coupled to the top of the semiconductor layer stack and a second conductive contact region. The die includes a substrate bias network configured to selectively electrically couple the substrate node to the first conductive contact region if the first conductive contact region is at a lower potential than the second conductive contact region, and to the second conductive contact region if the second conductive contact region is at a lower potential than the first conductive contact region. The substrate bias network includes first diode-connected transistors and second diode-connected transistors, each coupled to the substrate node.

[0219] In one embodiment, a method includes applying a first gate voltage to a first gate of a first switching field-effect transistor integrated in a semiconductor body, the semiconductor body including a semiconductor substrate and a plurality of semiconductor layers on the semiconductor substrate. A conductive substrate node is coupled to the bottom of the semiconductor substrate. The method includes applying a second gate voltage to a second gate of a second switching field-effect transistor integrated in a semiconductor body, the semiconductor body including a semiconductor substrate and a plurality of semiconductor layers on the semiconductor substrate. The first and second switching field-effect transistors are coupled together as a bidirectional switch. The method includes applying a voltage between a first conductive contact region of the first switching field-effect transistor coupled to the top of a stack of semiconductor layers and a second conductive contact region of the second switching field-effect transistor coupled to the top of the stack of semiconductor layers. The method includes utilizing a substrate biasing network to selectively couple a substrate node to a first conductive contact region if the first conductive contact region is at a lower potential than the second conductive contact region, or to a second conductive contact region if the second conductive contact region is at a lower potential than the first conductive contact region. The substrate biasing network includes first diode-connected transistors and second diode-connected transistors, each coupled to a substrate node.

[0220] In view of the detailed description above, these and other changes may be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in this specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents to which such claims are conferred. Therefore, the claims are not limited to this disclosure.

Claims

1. An integrated bidirectional switching power device based on gallium nitride, comprising a die, the die comprising: A semiconductor body integrating a first switching field-effect transistor and a second switching field-effect transistor, the semiconductor body comprising a semiconductor substrate and a layer stack stacked on the substrate, the layer stack comprising a channel layer of a channel semiconductor alloy of group III and group V elements of the periodic table, and a gate layer comprising a gate semiconductor alloy of gallium nitride. The channel layer forms a channel region, and the gate layer forms a first transistor gate region and a second transistor gate region arranged at a distance from each other above the channel region, and the substrate is electrically coupled to a substrate node. The first conductive contact area and the second conductive contact area of ​​the first conductive material are arranged side by side at a distance from each other on opposite sides of the channel region. A substrate biasing network is configured to selectively electrically couple the substrate nodes to the first conductive contact region and the second conductive contact region at minimum potential. The substrate bias network includes a first diode and a second diode, which are anti-series coupled and each has a first terminal and a second terminal. The first terminal of the first diode is coupled to a first conductive contact region, the first terminal of the second diode is coupled to a second conductive contact region, and the second terminals of the first diode and the second diode are coupled together and coupled to the substrate node. The first diode is formed by a transistor connected to a field-effect diode, and the second diode is formed by a transistor connected to a second field-effect diode. The transistors connected to the first and second field-effect diodes have the same structure as the first and second switching field-effect transistors, extending to the sides of the first and second switching field-effect transistors, and include a corresponding first diode contact region, a corresponding second diode contact region, and a corresponding diode gate region, wherein the first and second diode contact regions are formed of the first conductive material, and the diode gate region is formed of the gate layer.

2. The device of claim 1, wherein the channel semiconductor alloy comprises gallium nitride of a first conductivity type, and the gate semiconductor alloy is of a second conductivity type.

3. The device according to claim 1, wherein the first lower conductive contact portion, the second lower conductive contact portion and the third lower conductive contact portion form a field plate.

4. The device of claim 1, comprising at least one first interconnect metal layer, wherein the semiconductor body is covered by the at least one first interconnect metal layer and formed with: The first lower conductive contact portion is in electrical contact with the first conductive contact area; The second lower conductive contact portion is in electrical contact with the second conductive contact area; Each diode has a third lower conductive contact portion and a fourth lower conductive contact portion, wherein the third lower conductive contact portion of each diode is in direct electrical contact with the corresponding first diode contact area, and the fourth lower conductive contact portion of each diode is in direct electrical contact with the corresponding second diode contact area. For each diode, the device further includes a diode gate metallization region below the first interconnect metal layer and in direct electrical contact with the corresponding diode gate region and the corresponding third metallization region.

5. The device of claim 4, further comprising a gate metallization layer forming the diode gate metallization region, the first transistor gate metallization region, and the second transistor gate metallization region; the first transistor gate metallization region and the second transistor gate metallization region being disposed above the first transistor gate region and the second transistor gate region, respectively, and in direct electrical contact with the first transistor gate region and the second transistor gate region; and the first transistor gate metallization region and the second transistor gate metallization region being coupled to a first lower gate metal connection portion and a second lower gate metal connection portion formed by the first interconnect metal layer, respectively.

6. The device of claim 4, further comprising a second interconnect metal layer, the second interconnect metal layer covering the first interconnect metal layer and separated by a first insulating layer; the second interconnect metal layer is formed as follows: The first intermediate conductive contact portion and the second intermediate conductive contact portion are respectively partially covered and electrically coupled to the first lower conductive contact portion and the second lower conductive contact portion through the lower conductive metal connection; The first intermediate gate contact portion and the second intermediate gate contact portion are respectively covered and electrically coupled to the first lower gate metal connection portion and the second lower gate metal connection portion through the lower gate metal connection; as well as The intermediate substrate contact portion is covered and electrically and selectively coupled to the third conductive metallization region or the fourth conductive metallization region, and the intermediate substrate contact portion is also ohmically coupled to the substrate and electrically connected to the substrate node.

7. The device of claim 6, further comprising a third interconnect metal layer, the third interconnect metal layer covering the second interconnect metal layer and separated from the second interconnect metal layer by a second insulating layer; the third interconnect metal layer is formed as follows: The first upper gate contact portion and the second upper gate contact portion are respectively covered and electrically coupled to the first lower gate metal connection portion and the second lower gate metal connection portion through the upper gate metal connection; The first upper conductive contact portion and the second upper conductive contact portion are respectively covered and electrically coupled to the first intermediate conductive contact portion and the second intermediate conductive contact portion through corresponding upper conductive metal inter-connection; as well as The upper substrate contact portion is covered and electrically coupled to the middle substrate contact portion through an intermetallic connection of the upper substrate, and the upper substrate contact portion forms the substrate node.

8. The device of claim 1, wherein the layer stack further comprises a first sublayer stacked on the substrate and comprising a first GaN alloy; a buffer layer stacked on the first sublayer and below the channel layer and comprising a second GaN alloy; and a barrier layer stacked on the channel layer and comprising aluminum gallium nitride, wherein the channel semiconductor alloy is a third GaN alloy, and the barrier layer forms a heterostructure with the channel layer; wherein the first transistor gate region, the second transistor gate region, and the diode gate region of each diode are disposed above the barrier layer and comprise a fourth GaN alloy with a conductivity opposite to that of the channel layer and the barrier layer.

9. The device of claim 1, wherein the substrate of the semiconductor body is bonded to a support portion of the lead frame, and a connecting wire couples the substrate node to the support portion of the lead frame.

10. The device of claim 9, wherein the die and the lead frame are encapsulated in an electrically insulating housing and form a TOLT-Top side lead-cooled package.

11. The device of claim 1, wherein the substrate bias network further comprises at least one first resistor having a first resistor terminal coupled to the substrate node and a second resistor terminal coupled to a region selected from: i) The portion of the channel region disposed between the first conductive contact region 50A and the second conductive contact region 50B. ii) the gate region of the first transistor, and iii) the first conductive contact area, and The first resistor is formed by the resistive portion of the channel layer transversely to the channel region.

12. The device of claim 11, wherein the resistive portion is covered by a depletion region formed by the gate layer.

13. The device of claim 11, wherein the resistive portion has one end ohmically coupled to the substrate and ohmically coupled to the substrate node.

14. The device of claim 11, wherein the first resistor is coupled to the first transistor gate region, the device further comprising a second resistor coupled to the second transistor gate region, the second resistor being formed laterally to the channel region by another resistive portion of the channel layer, the other resistive portion having one end ohmically coupled to the substrate and ohmically coupled to the substrate node.

15. The device of claim 11, wherein the first resistor is coupled to the first conductive contact region, the device further comprising a second resistor coupled to the second conductive contact region, the second resistor being formed transversely to the channel region by another resistive portion of the channel layer, the other resistive portion having one end ohmically coupled to the substrate and ohmically coupled to the substrate node.

16. An integrated bidirectional switching power device based on gallium nitride, comprising a die, the die comprising: A semiconductor body, comprising a substrate and a stack of semiconductor layers on the substrate; Substrate nodes are electrically coupled to the back side of the substrate; A first switching field-effect transistor is integrated in the substrate and includes a first gate terminal and a first conductive contact region coupled to the top of the semiconductor layer stack; A second switching field-effect transistor is integrated in the substrate and includes a second gate terminal and a second conductive contact region coupled to the top of the semiconductor layer stack; A substrate biasing network is configured to selectively electrically couple the substrate node to the first conductive contact region if the first conductive contact region is at a lower potential than the second conductive contact region, and selectively electrically couple the substrate node to the second conductive contact region if the second conductive contact region is at a lower potential than the first conductive contact region, the substrate biasing network including a first diode-connected transistor and a second diode-connected transistor respectively coupled to the substrate node.

17. The device of claim 16, wherein a first terminal of the transistor connected to the first diode is coupled to the first conductive contact region, a first terminal of the transistor connected to the second diode is coupled to the second conductive contact region, and the second terminals of the first diode and the second diode are coupled together and coupled to the substrate node.

18. The device of claim 16, wherein the first field-effect diode-connected transistor and the second field-effect diode-connected transistor have the same structure as the first switching field-effect transistor and the second switching field-effect transistor, extend on the side of the first switching field-effect transistor and the second switching field-effect transistor, and include a corresponding first diode contact region, a corresponding second diode contact region, and a corresponding diode gate region, wherein the first diode contact region and the second diode contact region are formed of the first conductive material, and the diode gate region is formed of the gate layer.

19. A method comprising: A first gate voltage is applied to the first gate of a first switching field-effect transistor, the first switching field-effect transistor being integrated in a semiconductor body, the semiconductor body including a semiconductor substrate and a plurality of semiconductor layers on the semiconductor substrate, and a conductive substrate node coupled to the bottom of the semiconductor substrate; A second gate voltage is applied to the second gate of a second switching field-effect transistor, the second switching field-effect transistor being integrated in a semiconductor body, the semiconductor body including a semiconductor substrate and a plurality of semiconductor layers on the semiconductor substrate, the first switching field-effect transistor and the second switching field-effect transistor being coupled together as a bidirectional switch; A voltage is applied between a first conductive contact region of the first switching field-effect transistor coupled to the top of the semiconductor layer stack and a second conductive contact region of the second switching field-effect transistor coupled to the top of the semiconductor layer stack; Using a substrate biasing network, if the first conductive contact region is at a lower potential than the second conductive contact region, the substrate node is selectively coupled to the first conductive contact region, and if the second conductive contact region is at a lower potential than the first conductive contact region, the substrate node is selectively coupled to the second conductive contact region. The substrate biasing network includes transistors with first diode connections and transistors with second diode connections, each coupled to the substrate node.

20. The method of claim 19, wherein the top layer of the semiconductor layer stack is a channel layer of a semiconductor alloy of group III and group V elements of the periodic table.

Images