Coil device

Abstract

The coil device includes: a first base film having a first main surface and a second main surface, the second main surface being a surface facing the first main surface; a first wiring disposed on the first main surface; and a second wiring disposed on the second main surface. The first wiring has a first coil portion, and the first coil portion is configured from a portion of the first wiring wound in a coil shape in plan view. The second wiring has a second coil portion, and the second coil portion is configured from a portion of the second wiring wound in a coil shape in plan view. When viewed in a cross-section orthogonal to a direction in which a portion of a first wiring constituting the first coil portion extends, the first coil portion extends. A value obtained by dividing a positional shift amount between a portion of the first wiring constituting the first coil portion and a portion of the second wiring constituting the second coil portion by 1 / 2 of a pitch of the portion of the first wiring constituting the first coil portion is 0.06 or more and less than 0.50.

Description

Technical Field

[0001] This disclosure relates to coil devices. This application claims priority based on Japanese Application No. 2023-182036, filed on October 23, 2023, and incorporates the entire contents of the aforementioned Japanese application. Background Technology

[0002] For example, Japanese Patent Application Publication No. 2021-197408 (Patent Document 1) discloses a coil device. The coil device described in Patent Document 1 includes a first base film, a second base film, a first wiring, a second wiring, a third wiring, and an adhesive layer. The first base film has a first main surface and a second main surface. The first wiring and the second wiring are respectively disposed on the first main surface and the second main surface. The first wiring has a first planar coil portion that is wound into a coil shape when viewed from above. The second wiring has a second planar coil portion that is wound into a coil shape when viewed from above. The second base film has a third main surface. The third main surface faces the first main surface. The third wiring is disposed on the third main surface. The third wiring has a third planar coil portion that is wound into a coil shape when viewed from above. The adhesive layer is located between the first main surface and the third main surface, bonding the first base film and the second base film together.

[0003] When viewed in a cross section orthogonal to the direction in which the first wiring portion constituting the first planar coil portion extends, the portion of the first wiring portion constituting the first planar coil portion overlaps with the portion of the second wiring portion constituting the second planar coil portion in the thickness direction, and the portion of the first wiring portion constituting the first planar coil portion overlaps with the portion of the third wiring portion constituting the third planar coil portion. That is, when viewed in a cross section orthogonal to the direction in which the first wiring portion constituting the first planar coil portion extends, the positional offset between the portion of the first wiring portion constituting the first planar coil portion and the portion of the second wiring portion constituting the second planar coil portion, and the positional offset between the portion of the first wiring portion constituting the first planar coil portion and the portion of the third wiring portion constituting the third planar coil portion, are both 0.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2021-197408 Summary of the Invention

[0007] The coil device disclosed herein includes: a first base film having a first main surface and a second main surface, the second main surface being the surface opposite to the first main surface; a first wiring disposed on the first main surface; and a second wiring disposed on the second main surface. The first wiring has a first coil portion, which is composed of a portion of the first wiring wound into a coil shape when viewed from above. The second wiring has a second coil portion, which is composed of a portion of the second wiring wound into a coil shape when viewed from above. When viewed in a cross section orthogonal to the direction in which the portion of the first wiring constituting the first coil portion extends, the value obtained by dividing the positional offset between the portion of the first wiring constituting the first coil portion and the portion of the second wiring constituting the second coil portion by half the pitch of the portion of the first wiring constituting the first coil portion is 0.06 or more and less than 0.50. Attached Figure Description

[0008] Figure 1A This is a top view of the coil device 100, omitting the adhesive layer 60 and the base film 70.

[0009] Figure 1B From and Figure 1A A top view of the coil assembly 100, shown from the opposite side, omitting the adhesive layer 61 and the base film 71.

[0010] Figure 2A This is a top view of the coil device 100, omitting the illustrations of adhesive layer 30, base film 40, wiring 50, adhesive layer 60, and base film 70.

[0011] Figure 2B From and Figure 2A A top view of the coil device 100, viewed from the opposite side, omitting the illustrations of adhesive layer 31, base film 41, wiring 51, adhesive layer 61, and base film 71.

[0012] Figure 3 yes Figure 1A The cross-sectional view at point III-III.

[0013] Figure 4A This is a top view of the coil device 200A.

[0014] Figure 4B This is a top view of the coil device 200B.

[0015] Figure 5 This is a manufacturing process diagram of the coil device 100.

[0016] Figure 6 This is a cross-sectional view illustrating the conductive processing step S2.

[0017] Figure 7 This is a cross-sectional view illustrating the resist pattern formation process S3.

[0018] Figure 8 This is a cross-sectional diagram illustrating the electroplating process S4.

[0019] Figure 9 This is a cross-sectional view illustrating the resist pattern removal process S5.

[0020] Figure 10 This is a cross-sectional view illustrating etching process S6.

[0021] Figure 11 This is a cross-sectional view illustrating the base film bonding process S7.

[0022] Figure 12 This is a cross-sectional view illustrating the conductive processing step S8.

[0023] Figure 13 This is a cross-sectional view illustrating the resist pattern formation process S9.

[0024] Figure 14 This is a cross-sectional diagram illustrating the electroplating process S10.

[0025] Figure 15 This is a cross-sectional view illustrating the resist pattern removal process S11.

[0026] Figure 16 This is a cross-sectional view illustrating etching process S12.

[0027] Figure 17 This is a cross-sectional view of the coil device 100 involved in the modified example.

[0028] Figure 18 This is a graph showing the simulation results of the temperature rise at the main surface 70b when the first position offset is changed.

[0029] Figure 19 It is a graph showing the simulation results of the relationship between the current value that can flow through the wiring and the first position offset when the temperature at the main surface 70b rises to 65°C.

[0030] Figure 20 This is a graph showing the relationship between the thermal stress at the interface between the main surface 71a and the adhesive layer 61 and the value obtained by dividing the first position offset by 1 / 2 of the pitch P1 in the simulations of Tables 3 and 4.

[0031] Figure 21 This is a graph showing the relationship between the temperature rise in the simulations of Tables 5 and 6 and the value obtained by dividing the first position offset by half of the pitch P1.

[0032] Figure 22 This is an enlarged cross-sectional view of the coil device 100 involved in the modified example.

[0033] Figure 23It is Figure 1A The enlarged portion of the cross-sectional view at point III-III is an attached diagram used to illustrate the positional offset.

[0034] Figure 24 This is a cross-sectional view of the area surrounding the first through hole.

[0035] Figure 25 This is a cross-sectional view of the area around the second blind hole.

[0036] Figure 26 This is a cross-sectional view of the area around the third blind hole. Detailed Implementation

[0037] [The technical problem this disclosure aims to solve]

[0038] In the coil device described in Patent Document 1, since the aforementioned positional offset is 0, the heat generated in each wiring is easily transferred along the thickness direction, exhibiting good heat dissipation. In the coil device described in Patent Document 1, when the temperature rises due to reflow soldering, the thermal stress at the interface between the adhesive layer and the base film (first base film, second base film) increases, and the base film may peel off from the adhesive layer due to thermal stress.

[0039] This disclosure provides a coil device capable of suppressing the peeling of the base film from the adhesive layer when the temperature rises, while maintaining heat dissipation. Here, "when the temperature rises" refers, for example, to the temperature rise during reflow soldering during installation.

[0040] [The Effects of This Disclosure]

[0041] According to the coil device disclosed herein, it is possible to maintain heat dissipation while suppressing the base film from peeling off from the adhesive layer when the temperature rises.

[0042] [Description of embodiments of this disclosure]

[0043] First, embodiments of this disclosure will be described.

[0044] (1) The coil device according to the embodiment includes: a first base film having a first main surface and a second main surface, the second main surface being the surface opposite to the first main surface; a first wiring disposed on the first main surface; and a second wiring disposed on the second main surface. The first wiring has a first coil portion, which is composed of a portion of the first wiring wound into a coil shape when viewed from above. The second wiring has a second coil portion, which is composed of a portion of the second wiring wound into a coil shape when viewed from above. When viewed in a cross section orthogonal to the direction in which the portion of the first wiring constituting the first coil portion extends, the value obtained by dividing the positional offset between the portion of the first wiring constituting the first coil portion and the portion of the second wiring constituting the second coil portion by half the pitch of the portion of the first wiring constituting the first coil portion is 0.06 or more and less than 0.50.

[0045] According to the coil device described in (1) above, it is possible to maintain heat dissipation while suppressing the peeling of the base film from the adhesive layer when the temperature rises. Here, "when the temperature rises" refers, for example, to the temperature rise during reflow soldering during installation.

[0046] (2) Alternatively, the coil device of (1) above may further include: a first adhesive layer disposed on a first main surface in a manner covering the first wiring; a second base film disposed on the first adhesive layer and having a third main surface and a fourth main surface, the third main surface being opposite to the first adhesive layer and the fourth main surface being the surface opposite to the third main surface; and a third wiring disposed on the fourth main surface. Alternatively, the third wiring may have a third coil portion, which is composed of a portion of the third wiring that is wound into a spiral shape when viewed from above. Alternatively, when viewed in a section orthogonal to the direction in which the portion of the first wiring constituting the first coil portion extends, the positional offset between the portion of the first wiring constituting the first coil portion and the portion of the third wiring constituting the third coil portion divided by half the pitch of the portion of the first wiring constituting the first coil portion is a value of 0.06 or more and less than 0.50.

[0047] According to the coil device described in (2) above, it is possible to maintain heat dissipation while suppressing the base film from peeling off from the adhesive layer when the temperature rises.

[0048] (3) Alternatively, the coil device of (2) above may further include: a second adhesive layer disposed on the second main surface in a manner covering the second wiring; a third base film disposed on the second adhesive layer and having a fifth main surface and a sixth main surface, the fifth main surface being opposite to the second adhesive layer and the sixth main surface being the surface opposite to the fifth main surface; and a fourth wiring disposed on the sixth main surface. Alternatively, the fourth wiring may have a fourth coil portion, which is composed of a portion of the fourth wiring wound into a coil shape when viewed from above. Alternatively, when viewed in a section orthogonal to the direction in which the portion of the first wiring constituting the first coil portion extends, the positional offset between the portion of the second wiring constituting the second coil portion and the portion of the fourth wiring constituting the fourth coil portion divided by half the pitch of the portion of the second wiring constituting the second coil portion is a value of 0.06 or more and less than 0.50.

[0049] According to the coil device described in (3) above, it is possible to maintain heat dissipation while suppressing the base film from peeling off from the adhesive layer when the temperature rises.

[0050] (4) Alternatively, the coil device of (3) above may further include: a third adhesive layer disposed on the fourth main surface in a manner covering the third wiring; a fourth base film disposed on the third adhesive layer; the fourth adhesive layer disposed on the sixth main surface in a manner covering the fourth wiring; and a fifth base film disposed on the fourth adhesive layer. Alternatively, the fourth base film may have a seventh main surface and an eighth main surface, the seventh main surface being opposite to the third adhesive layer, and the eighth main surface being the surface opposite to the seventh main surface. Alternatively, when a current of 0.43 amperes flows through the first wiring, the second wiring, the third wiring, and the fourth wiring and reaches a stable state, the temperature rise at the eighth main surface is less than 65°C, and the thermal stress generated at the interface between the third adhesive layer and the fourth base film as the temperature rises is less than 46 MPa.

[0051] According to the coil device described in (4) above, it is possible to maintain heat dissipation while suppressing the base film from peeling off from the adhesive layer when the temperature rises.

[0052] (5) In any of the coil devices in (1) to (4) above, the first wiring and the second wiring may each have: a seed layer disposed on the first main surface; a conductive layer disposed on the seed layer; and an electroplating layer disposed on the conductive layer.

[0053] (6) Another embodiment of the coil device includes: a first base film having a first main surface and a second main surface, the second main surface being the surface opposite to the first main surface; a first wiring disposed on the first main surface; a first adhesive layer disposed on the first main surface to cover the first wiring; a second base film disposed on the first adhesive layer and having a third main surface and a fourth main surface, the third main surface being opposite to the first adhesive layer and the fourth main surface being the surface opposite to the third main surface; and a third wiring disposed on the fourth main surface. The first wiring has a first coil portion, which is composed of a portion of the first wiring wound into a coil shape when viewed from above. The third wiring has a third coil portion, which is composed of a portion of the third wiring wound into a coil shape when viewed from above. When viewed in a cross section orthogonal to the direction in which the portion of the first wiring constituting the first coil portion extends, the value obtained by dividing the positional offset between the portion of the first wiring constituting the first coil portion and the portion of the third wiring constituting the third coil portion by half the pitch of the portion of the first wiring constituting the first coil portion is 0.06 or more and less than 0.50.

[0054] According to the coil device described in (6) above, it is possible to maintain heat dissipation while suppressing the base film from peeling off from the adhesive layer when the temperature rises.

[0055] [Details of the embodiments of this disclosure]

[0056] Next, with reference to the accompanying drawings, details of the embodiments of this disclosure will be described. In the following drawings, the same or equivalent parts will be labeled with the same reference numerals, and repeated descriptions will not be given. The coil device involved in the embodiments will be referred to as coil device 100.

[0057] (Composition of coil device 100)

[0058] The configuration of the coil device 100 will be described below.

[0059] Figure 1A This is a top view of the coil device 100, omitting the adhesive layer 60 and the base film 70. Figure 1A Is Figure 3 The diagram shows the wiring 50 viewed from the base film 70 toward the base film 71. Figure 1B From and Figure 1A A top view of the coil assembly 100, shown from the opposite side, omitting the adhesive layer 61 and the base film 71. Figure 2A This is a top view of the coil device 100, omitting the illustrations of adhesive layer 30, base film 40, wiring 50, adhesive layer 60, and base film 70. Figure 2A Is Figure 3 The diagram shows the wiring 20 viewed from the base film 70 toward the base film 71. Figure 2B From and Figure 2AA top view of the coil device 100, viewed from the opposite side, omitting the illustrations of adhesive layer 31, base film 41, wiring 51, adhesive layer 61, and base film 71. Figure 3 yes Figure 1A The cross-sectional view at point III-III. (See diagram below.) Figures 1A to 3 As shown, the coil device 100 includes a base film 10, wiring 20, wiring 21, adhesive layer 30, adhesive layer 31, base film 40, base film 41, wiring 50, wiring 51, adhesive layer 60, adhesive layer 61, base film 70, and base film 71.

[0060] The base film 10 is made of a flexible, electrically insulating material. Polyimide is a specific example of the base film 10. The base film 10 has a main surface 10a and a main surface 10b. Main surfaces 10a and 10b are end faces in the thickness direction of the base film 10. Main surface 10b is the surface opposite to main surface 10a.

[0061] Wiring 20 is disposed on main surface 10a. Wiring 20 has a coil portion 20a. The coil portion 20a is formed by a portion of wiring 20. When viewed from above, the coil portion 20a is wound into a coil shape. Wiring 20 has a pad 20b at a first end and a pad 20c at a second end. Pad 20b and pad 20c are located at the outermost and innermost peripheries of the coil portion 20a, respectively.

[0062] Wiring 21 is disposed on the main surface 10b. Wiring 21 has a coil portion 21a. The coil portion 21a is formed by a portion of wiring 21. When viewed from above, the coil portion 21a is wound into a coil shape. Wiring 21 has a pad 21b at a first end and a pad 21c at a second end. Pad 21b and pad 21c are located at the outermost and innermost peripheries of the coil portion 21a, respectively. When viewed from above, pad 21b overlaps with pad 20b.

[0063] Wiring 20 and wiring 21 each have a seed layer 22, a conductive layer 23, and an electroplated layer 24. The seed layer 22 of wiring 20 is disposed on the main surface 10a. The seed layer 22 of wiring 21 is disposed on the main surface 10b. The constituent material of the seed layer 22 can be, for example, a copper-based metal, but from the perspective of weather resistance, it can also be a nickel-chromium alloy. In the seed layer 22, copper formed by sputtering or the like may also be present on top of the nickel-chromium alloy.

[0064] The conductive layer 23 is disposed on the seed layer 22. For example... Figure 24 As shown, a first through-hole is formed in the base film 10, the seed layer 22 of the pad 20b, and the seed layer 22 of the pad 21b. A conductive layer 23 is also disposed on the inner wall surface of the first through-hole. The conductive layer 23 is, for example, an electroless plating layer (a layer formed by electroless plating). The constituent material of the conductive layer 23 is, for example, copper.

[0065] An electroplated layer 24 is disposed on the conductive layer 23. The electroplated layer 24 is made of, for example, copper. The wiring 20 and wiring 21 are electrically connected to each other through the conductive layer 23 disposed on the inner wall surface of the first through hole and the electroplated layer 24 disposed on the conductive layer 23.

[0066] Adhesive layer 30 is disposed on main surface 10a in a manner that covers wiring 20. Adhesive layer 31 is disposed on main surface 10b in a manner that covers wiring 21. The constituent materials of adhesive layer 30 and adhesive layer 31 are, for example, thermosetting adhesives.

[0067] A base film 40 is disposed on an adhesive layer 30. The base film 40 has a main surface 40a and a main surface 40b. Main surfaces 40a and 40b are end faces of the base film 40 in the thickness direction. Main surface 40a faces the adhesive layer 30. Main surface 40b is the surface opposite to main surface 40a. The base film 40 is made of a flexible, electrically insulating material. Polyimide is a specific example of the material constituting the base film 40.

[0068] A base film 41 is disposed on an adhesive layer 31. The base film 41 has a main surface 41a and a main surface 41b. Main surfaces 41a and 41b are end faces of the base film 41 in the thickness direction. Main surface 41a faces the adhesive layer 31. Main surface 41b is the surface opposite to main surface 41a. The base film 41 is made of a flexible, electrically insulating material. Polyimide is a specific example of the material constituting the base film 41.

[0069] Wiring 50 is disposed on main surface 40b. Wiring 50 has a coil portion 50a, which is composed of a portion of wiring 50 wound into a coil shape when viewed from above. Wiring 50 has a pad 50b at a first end and a pad 50c at a second end. Pad 50b and pad 50c are located at the outermost and innermost peripheries of coil portion 50a, respectively. Pad 50c overlaps with pad 20c when viewed from above and is connected through a second blind via, which will be described below.

[0070] Wiring 51 is disposed on main surface 41b. Wiring 51 has a coil portion 51a, which is composed of a portion of wiring 51 wound into a coil shape when viewed from above. Wiring 51 has a pad 51b at a first end and a pad 51c at a second end. Pad 51b and pad 51c are located at the outermost and innermost peripheries of the coil portion 51a, respectively. Pad 51c overlaps with pad 21c when viewed from above and is connected through a third blind via, which will be described below.

[0071] Wiring 50 and wiring 51 each have a seed layer 52, a conductive layer 53, and an electroplated layer 54. The seed layer 52 of wiring 50 is disposed on the main surface 40b. The seed layer 52 of wiring 51 is disposed on the main surface 41b. The constituent material of the seed layer 52 can be, for example, a copper-based metal, but for weather resistance considerations, it can also be a nickel-chromium alloy. In the seed layer 52, copper formed by sputtering or the like may also be present on top of the nickel-chromium alloy.

[0072] The conductive layer 53 is disposed on the seed layer 52. For example... Figure 25 As shown, a second blind via is formed in the seed layer 52 of the adhesive layer 30, the base film 40, and the pad 50c by having a through hole extending in the thickness direction. The pad 20c is located below (inside) the second blind via. Figure 26 As shown, a third blind via is formed in the seed layer 52 of the adhesive layer 31, the base film 41, and the pad 51c by having a through hole extending in the thickness direction. The pad 21c is located above (inside) the third blind via. A conductive layer 53 is also disposed on the inner wall surface of the second blind via, on the pad 20c located below the second blind via, on the inner wall surface of the third blind via, and on the pad 21c located above the third blind via. The conductive layer 53 is, for example, an electroless plating layer. The constituent material of the conductive layer 53 is, for example, copper.

[0073] An electroplated layer 54 is disposed on the conductive layer 53. The constituent material of the electroplated layer 54 is, for example, copper. Wiring 50 and wiring 20 are electrically connected to each other through the conductive layer 53 and the electroplated layer 54 disposed on the inner wall surface of the second blind via and on the pad 20c located below the second blind via. Wiring 51 and wiring 21 are electrically connected to each other through the conductive layer 53 and the electroplated layer 54 disposed on the inner wall surface of the third blind via and on the pad 21c located above the third blind via. For this purpose, by applying a voltage between pads 50b and 51b, current flows in a coil shape in coil sections 50a, 20a, 21a, and 51a, generating magnetic flux.

[0074] Adhesive layer 60 is disposed on main surface 40b in a manner that covers wiring 50. Adhesive layer 61 is disposed on main surface 41b in a manner that covers wiring 51. The constituent materials of adhesive layer 60 and adhesive layer 61 are, for example, thermosetting adhesives.

[0075] A base film 70 is disposed on an adhesive layer 60. The base film 70 has a main surface 70a and a main surface 70b. Main surfaces 70a and 70b are end faces of the base film 70 in the thickness direction. Main surface 70a faces the adhesive layer 60. Main surface 70b is the surface opposite to main surface 70a. The base film 70 is made of a flexible, electrically insulating material. Polyimide is a specific example of a material constituting the base film 70.

[0076] A base film 71 is disposed on an adhesive layer 61. The base film 71 has a main surface 71a and a main surface 71b. Main surfaces 71a and 71b are end faces of the base film 71 in the thickness direction. Main surface 71a faces the adhesive layer 61. Main surface 71b is the surface opposite to main surface 71a. The base film 71 is made of a flexible, electrically insulating material. Polyimide is a specific example of the material constituting the base film 71.

[0077] The width of the portion of the wiring 20 constituting the coil section 20a is defined as width L1. The height of the portion of the wiring 20 constituting the coil section 20a is defined as height H1. The spacing between adjacent portions of the wiring 20 constituting the coil section 20a is defined as spacing SP1. The pitch between adjacent portions of the wiring 20 constituting the coil section 20a is defined as pitch P1. Pitch refers to the distance between the first center and the second center of each portion of adjacent wirings in the width direction of the wiring. Pitches other than pitch P1 are also defined in the same way.

[0078] The width of the portion of the wiring 21 constituting the coil section 21a is set to width L2. The height of the portion of the wiring 21 constituting the coil section 21a is set to height H2. The spacing between adjacent portions of the wiring 21 constituting the coil section 21a is set to spacing SP2. The pitch between adjacent portions of the wiring 21 constituting the coil section 21a is set to pitch P2.

[0079] The width of the portion of wiring 50 constituting coil section 50a is set to width L3. The height of the portion of wiring 50 constituting coil section 50a is set to height H3. The spacing between adjacent portions of wiring 50 constituting coil section 50a is set to spacing SP3. The pitch between adjacent portions of wiring 50 constituting coil section 50a is set to pitch P3.

[0080] The width of the portion of wiring 51 constituting coil section 51a is set to width L4. The height of the portion of wiring 51 constituting coil section 51a is set to height H4. The spacing between adjacent portions of wiring 51 constituting coil section 51a is set to spacing SP4. The pitch between adjacent portions of wiring 51 constituting coil section 51a is set to pitch P4.

[0081] The thickness of the base film 10 is set to thickness T1. The thickness of the base film 40 is set to thickness T2, and the thickness of the base film 41 is set to thickness T3. The thickness of the base film 70 is set to thickness T4, and the thickness of the base film 71 is set to thickness T5. The thickness of the adhesive layer 30 between the wiring 20 and the base film 40 is set to thickness T6, and the thickness of the adhesive layer 31 between the wiring 21 and the base film 41 is set to thickness T7. The thickness of the adhesive layer 60 between the wiring 50 and the base film 70 is set to thickness T8, and the thickness of the adhesive layer 61 between the wiring 51 and the base film 71 is set to thickness T9.

[0082] Reference Figure 23 A cross-sectional view is defined as an observation taken at a cross section orthogonal to the direction in which the wiring 20 constituting the coil section 20a extends. During the cross-sectional view, the positional offset between the portion of wiring 20 constituting the coil section 20a and the portion of wiring 21 constituting the coil section 21a is defined as a first positional offset. Figure 23 In this diagram, the position offset is represented by D. The shadow lines in the cross-sectional view are omitted to indicate the position offset D. In the cross-sectional view, the direction in which the wiring 20 constituting the coil section 20a is arranged is defined as the arrangement direction. In the cross-sectional view, one of the wiring 20 constituting the coil section 20a is designated as the first part, and one of the wiring 21 constituting the coil section 21a is designated as the second part. In the cross-sectional view, the distance in the arrangement direction between the center of the first part and the center of the second part is defined as the first position offset. The second part selected to determine the first position offset is the portion of the wiring 21 constituting the coil section 21a that is closer to the first part in the arrangement direction than other parts of the wiring 21 in the cross-sectional view.

[0083] In cross-sectional view, the positional offset between the portion of wiring 20 constituting coil section 20a and the portion of wiring 50 constituting coil section 50a is defined as the second positional offset. One of the portions of wiring 50 constituting coil section 50a is defined as the third portion. In cross-sectional view, the distance in the arrangement direction between the center of the first portion and the center of the third portion is defined as the second positional offset. The third portion selected to determine the distance is the portion of wiring 50 constituting coil section 50 that is closer to the first portion in the arrangement direction than other portions of wiring 50 in cross-sectional view.

[0084] In cross-sectional view, the positional offset between the portion of wiring 21 constituting coil section 21a and the portion of wiring 51 constituting coil section 51a is defined as the third positional offset. One of the portions of wiring 51 constituting coil section 51a is defined as the fourth portion. In cross-sectional view, the distance in the arrangement direction between the center of the second portion and the center of the fourth portion is defined as the third positional offset. The fourth portion selected to determine the distance is the portion of wiring 51 constituting coil section 51 that is closer to the first portion in the arrangement direction than other portions of wiring 51 in cross-sectional view.

[0085] The coil device involved in the first reference example is designated as coil device 200A, and the coil device involved in the second reference example is designated as coil device 200B. Figure 4A This is a top view of the coil device 200A. Figure 4BThis is a top view of the coil device 200B. (Example) Figure 4A As shown, coil devices 200A and 200B have a base film 110, wiring 120, and wiring 121. Wiring 120 and wiring 121 are respectively disposed on a first main surface and a second main surface of the base film 110. Figure 4A China and Figure 4B In the diagram, the center position of the wiring 121 in the width direction (arrangement direction) is marked with a dashed line.

[0086] Wiring 120 has a coil portion 120a, which is composed of a portion of wiring 120 wound into a coil shape when viewed from above. Wiring 121 has a coil portion 121a wound into a coil shape when viewed from above. From the perspective of improving magnetic force, wiring 120 and wiring 121 are arranged overlapping in the thickness direction. On the other hand, the direction of the magnetic flux generated by the current flowing through the coil portion 120a needs to be consistent with the direction of the magnetic flux generated by the current flowing through the coil portion 121a. For this purpose, the winding direction of wiring 120 when viewed along the normal direction of the first main surface of the base film 110 is opposite to the winding direction of wiring 121 when viewed along the normal direction of the second main surface of the base film 110. As a result, wiring 121 includes a portion with a pitch different from the other portions. The section used to measure the position offset (the section orthogonal to the portion of wiring 20 constituting the coil portion 20a) is a section excluding the portion with a pitch different from the other portions.

[0087] The value obtained by dividing the first position offset by half of the pitch P1 is greater than or equal to 0.06 and less than 0.50, or greater than or equal to 0.13 and less than 0.50, or greater than or equal to 0.16 and less than 0.50.

[0088] Furthermore, the value obtained by dividing the second position offset by half of the pitch P1 can be greater than or equal to 0.06 and less than 0.50, greater than or equal to 0.13 and less than 0.50, or greater than or equal to 0.16 and less than 0.50. Similarly, the value obtained by dividing the third position offset by half of the pitch P2 can be greater than or equal to 0.06 and less than 0.50, greater than or equal to 0.13 and less than 0.50, or greater than or equal to 0.16 and less than 0.50.

[0089] Widths L1, L2, L3, and L4 can be equal or different. Heights H1, H2, H3, and H4 can be equal or different. Spacings SP1, SP2, SP3, and SP4 can be equal or different.

[0090] Pitches P1, P2, P3, and P4 can be equal or different from each other. Thicknesses T1, T2, T3, T4, and T5 can be equal or different from each other. Thicknesses T6, T7, T8, and T9 can be equal or different from each other.

[0091] Pitches P1, P2, P3, and P4 are, for example, 35 μm or more and 60 μm or less. Spacing SP1, SP2, SP3, and SP4 are, for example, 5 μm or less and 30 μm or less. Heights H1, H2, H3, and H4 are, for example, 45 μm or more and 65 μm or less. Thicknesses T1, T2, T3, T4, and T5 are, for example, 2.5 μm or more and 7.5 μm or less. Thicknesses T6, T7, T8, and T9 are, for example, 2.5 μm or more and 7.5 μm or less.

[0092] When a current of 0.43 amps flows through wirings 20, 21, 50, and 51 and reaches a steady state, the temperature rise at the main surface 70b is, for example, 65°C or less. The thermal stress generated at the interface between the adhesive layer 61 and the base film 71 due to the temperature rise during reflow soldering during installation is, for example, 46 MPa or less. The temperature during the temperature rise is, for example, 240°C. Therefore, it is possible to suppress the temperature rise when using the coil device 100 while also suppressing the peeling of the base film from the adhesive layer due to the thermal stress caused by the temperature rise.

[0093] (Manufacturing method of coil device 100)

[0094] The manufacturing method of the coil device 100 will be described below.

[0095] Figure 5 This is a manufacturing process diagram of the coil device 100. (For example...) Figure 5 As shown, the manufacturing method of the coil device 100 includes a preparation step S1, a conductive treatment step S2, a resist pattern forming step S3, an electroplating step S4, a resist pattern removal step S5, an etching step S6, a base film bonding step S7, a conductive treatment step S8, a resist pattern forming step S9, an electroplating step S10, a resist pattern removal step S11, an etching step S12, and a base film bonding step S13.

[0096] In preparation step S1, a base film 10 is prepared. In the base film 10 prepared in preparation step S1, seed layers 22 are disposed on the main surface 10a and the main surface 10b. After preparation step S1, a conductivity treatment step S2 is performed. After preparation step S1 and before conductivity treatment step S2, a first through-hole is formed in the base film 10, the seed layer 22 on the main surface 10a, and the seed layer 22 on the main surface 10b. The formation of the first through-hole is, for example, performed by laser processing.

[0097] Figure 6 This is a cross-sectional view illustrating the conductive processing step S2. For example... Figure 6 As shown, in the conductive processing step S2, a conductive layer 23 is formed on the seed layer 22, for example, by electroless plating. In the conductive processing step S2, the conductive layer 23 is also formed on the inner wall surface of the first through-hole. After the conductive processing step S2, a resist patterning step S3 is performed.

[0098] Figure 7 This is a cross-sectional view illustrating the resist pattern formation process S3. For example... Figure 7 As shown, in the resist pattern forming process S3, a resist pattern 80 is formed on the conductive layer 23. The resist pattern 80 has an opening 80a. The conductive layer 23 is partially exposed from the opening 80a. The resist pattern 80 is formed, for example, by adhering a dry film resist to the conductive layer 23 and exposing and developing the adhering dry film resist. After the resist pattern forming process S3, an electroplating process S4 is performed.

[0099] Figure 8 This is a cross-sectional diagram illustrating the S4 electroplating process. For example... Figure 8 As shown, in the electroplating process S4, an electroplated layer 24 is formed on the conductive layer 23 exposed from the opening 80a by electroplating. After the electroplating process S4, a resist pattern removal process S5 is performed. Figure 9 This is a cross-sectional view illustrating the resist pattern removal process S5. For example... Figure 9 As shown, in the resist pattern removal step S5, the resist pattern 80 is removed from the conductive layer 23. After the resist pattern removal step S5, the etching step S6 is performed.

[0100] Figure 10 This is a cross-sectional view illustrating etching process S6. For example... Figure 10 As shown, in etching step S6, the conductive layer 23 and seed layer 22 beneath the resist pattern 80 are removed by etching. This forms wiring 20 and wiring 21. After etching step S6, a base film bonding step S7 is performed.

[0101] Figure 11 This is a cross-sectional view illustrating the base film bonding process S7. For example... Figure 11As shown, in the base film bonding process S7, the base film 40 is bonded using the adhesive layer 30. Additionally, in the base film bonding process S7, the base film 41 is bonded using the adhesive layer 31. In the base film bonding process S7, firstly, base film 40 and base film 41 are prepared. In the base film 40 prepared in the base film bonding process S7, an uncured adhesive layer 30 is disposed on the main surface 40a, and a seed layer 52 is disposed on the main surface 40b. In the base film 41 prepared in the base film bonding process S7, an uncured adhesive layer 31 is disposed on the main surface 41a, and a seed layer 52 is disposed on the main surface 41b.

[0102] Second, a base film 40 is disposed on the main surface 10a through an adhesive layer 30, and a base film 41 is disposed on the main surface 10b through an adhesive layer 31. Third, the base film 40 and base film 41 are heated and pressurized towards the base film 10. As a result, the adhesive layers 30 and 31 are cured, thus bonding the base film 40 and base film 41. After the base film bonding step S7, a conductive treatment step S8 is performed. After the base film bonding step S7 and before the conductive treatment step S8, a second blind hole is formed penetrating the seed layer 52 and the base film 40 and reaching at least the surface of the electroplated layer 24. After the base film bonding step S7 and before the conductive treatment step S8, a third blind hole penetrating the seed layer 52 and the base film 41 and reaching at least the surface of the electroplated layer 24 is formed. The formation of the second and third blind holes is performed, for example, by laser processing.

[0103] Figure 12 This is a cross-sectional view illustrating the conductive processing step S8. For example... Figure 12 As shown, in the conductive processing step S8, a conductive layer 53 is formed on the seed layer 52, for example, by electroless plating. In the conductive processing step S8, the conductive layer 53 is also formed on the inner wall surfaces of the second and third blind holes. After the conductive processing step S8, a resist patterning step S9 is performed.

[0104] Figure 13 This is a cross-sectional view illustrating the resist pattern formation process S9. For example... Figure 13 As shown, in the resist pattern forming step S9, a resist pattern 81 is formed on the conductive layer 53. The resist pattern 81 has an opening 81a. The conductive layer 53 is partially exposed from the opening 81a. The resist pattern 81 is formed, for example, by adhering a dry film resist to the conductive layer 53 and exposing and developing the adhering dry film resist. After the resist pattern forming step S9, an electroplating step S10 is performed.

[0105] Figure 14 This is a cross-sectional diagram illustrating the electroplating process S10. For example... Figure 14As shown, in the electroplating process S10, an electroplated layer 54 is formed on the conductive layer 53 exposed from the opening 81a by electroplating. After the electroplating process S10, a resist pattern removal process S11 is performed. Figure 15 This is a cross-sectional view illustrating the resist pattern removal process S11. For example... Figure 15 As shown, in the resist pattern removal process S11, the resist pattern 81 is removed from the conductive layer 53. After the resist pattern removal process S11, the etching process S12 is performed.

[0106] Figure 16 This is a cross-sectional view illustrating etching process S12. For example... Figure 16 As shown, in the etching process S12, the conductive layer 53 and the seed layer 52 located under the resist pattern 81 are removed by etching. This forms wiring 50 and wiring 51. After the etching process S12, the base film bonding process S13 is performed.

[0107] In the base film bonding process S13, the base film 70 is bonded via the adhesive layer 60, and the base film 71 is bonded via the adhesive layer 61. In the base film bonding process S13, firstly, the base film 70 and the base film 71 are prepared. In the base film 70 prepared in the base film bonding process S13, an uncured adhesive layer 60 is disposed on the main surface 70a. In the base film 71 prepared in the base film bonding process S7, an uncured adhesive layer 61 is disposed on the main surface 71a.

[0108] Second, a base film 70 is disposed on the main surface 40a through an adhesive layer 60, and a base film 71 is disposed on the main surface 41a through an adhesive layer 31. Third, the base film 70 and base film 71 are heated and pressurized towards the base film 10. As a result, the adhesive layers 60 and 61 cure and adhere the base film 70 and base film 71, forming... Figures 1A to 3 The structure of the coil device 100 shown.

[0109] <Variation Example>

[0110] Figure 17 This is a cross-sectional view of the coil device 100 involved in the modified example. For example... Figure 17 As shown, wiring 21 can also be configured on main surface 41a instead of main surface 10b. Wiring 51 can also be configured on main surface 71a instead of main surface 41b. That is, Figure 3 The diagram shows a coil device 100 consisting of two single-sided panels sandwiching a double-sided panel, but the coil device 100 may also have multiple single-sided panels (in...) Figure 17 The example shows a configuration consisting of four single-sided panels stacked in the thickness direction. The number of single-sided panels stacked can be four, five or more, or even six or more.

[0111] (Effect of coil device 100)

[0112] The effects of the coil device 100 will be explained below.

[0113] Table 1 shows the simulation results (two-dimensional steady-state temperature analysis) of the temperature rise at the main surface 70b when the first position offset changes. In the simulation in Table 1, the second and third position offsets are set to be equal to the first position offset, simulating the state of cooling the main surface 71b by contacting the metal plate.

[0114] In the simulations in Table 1, widths L1, L2, L3, and L4 are set to 30 μm. Heights H1, H2, H3, and H4 are set to 50 μm. Spacings SP1, SP2, SP3, and SP4 are set to 30 μm. Thicknesses T1, T2, T3, T4, and T5 are set to 5 μm. Thicknesses T6, T7, T8, and T9 are set to 5 μm. Pitches P1, P2, P3, and P4 are set to 60 μm. The thermal conductivity of wiring 20, wiring 21, wiring 50, and wiring 51 is set to 400 W / m·K. In the simulations in Table 1, the thermal conductivity of base films 10, 40, 41, 70, and 71 was set to 0.1 W / m·K. In the simulations in Table 1, the thermal conductivity of adhesive layers 30, 31, 60, and 61 was also set to 0.1 W / m·K.

[0115]

[0116] Figure 18 This is a graph showing the simulation results of the temperature rise at the main surface 70b when the first position offset is changed. Figure 18 The curves were created based on Table 1 (heat generation is 2W / mm). 3 As shown in Table 1 and Figure 18 As shown, as the offset of the first position increases, the temperature rise at the main surface 70b also increases.

[0117] Table 2 shows the simulation (thermal expansion analysis) results of the equivalent stress at the interface between the main surface 71a and the adhesive layer 61 when the first position offset changes. The simulation in Table 2 simulates... Figure 17 The structure was determined, and the thermal stress during the temperature rise (240°C) generated during reflow soldering was calculated.

[0118] In the simulations in Table 2, widths L1, L2, L3, and L4 are set to 30 μm. Heights H1, H2, H3, and H4 are set to 50 μm. Spacings SP1, SP2, SP3, and SP4 are set to 30 μm. Thicknesses T1, T2, T3, T4, and T5 are set to 5 μm. Thicknesses T6, T7, T8, and T9 are set to 5 μm. Pitches P1, P2, P3, and P4 are set to 60 μm. The thermal conductivity of wiring 20, wiring 21, wiring 50, and wiring 51 is set to 400 W / m·K. In the simulations in Table 2, the thermal conductivity of base films 10, 40, 41, 70, and 71 was set to 0.1 W / m·K. In the simulations in Table 2, the thermal conductivity of adhesive layers 30, 31, 60, and 61 was also set to 0.1 W / m·K.

[0119] In the simulation in Table 2, the coefficients of thermal expansion of wiring 20, wiring 21, wiring 50, and wiring 51 are set to 16.8 × 10⁻⁶. -6 / K. In the simulation in Table 2, the coefficients of thermal expansion of base film 10, base film 40, base film 41, base film 70, and base film 71 are set to 13.0 × 10⁻⁶. -6 / K. In the simulation in Table 2, the coefficients of thermal expansion of adhesive layers 30, 31, 60, and 61 are set to 45.0 × 10⁻⁶. -6 / K.

[0120]

[0121] As shown in Table 2, as the first position offset increases, the equivalent stress at the interface between the main surface 71a and the adhesive layer 61 decreases.

[0122] Thus, if the first position offset becomes larger, the heat dissipation decreases, while on the other hand, the thermal stress at the interface between the main surface 71a and the adhesive layer 61 decreases. In the coil device 100, by dividing the first position offset by half of the pitch P1, the value is set to be greater than or equal to 0.06 and less than 0.50, thereby maintaining heat dissipation while suppressing the peeling of the base film 70 (base film 71) from the adhesive layer 60 (adhesive layer 61).

[0123] Figure 19 This is a graph showing the simulation results of the relationship between the current flowing through the wiring and the first position offset when the temperature at the main surface 70b rises to 65°C. Figure 19 In the simulation, widths L1, L2, L3, and L4 were set to 30 μm. Figure 19In the simulation, heights H1, H2, H3, and H4 were set to 50 μm, intervals SP1, SP2, SP3, and SP4 were set to 30 μm, and pitches P1, P2, P3, and P4 were set to 60 μm. Additionally, in Figure 19 In the simulation, the total length of wires 20, 21, 50 and 51 is set to 666.3 mm, and the total resistance of wires 20, 21, 50 and 51 is set to 9.9 Ω.

[0124] like Figure 19 As shown, when the first position offset is less than 15 μm (when the value obtained by dividing the first position offset by 1 / 2 of the pitch P1 is less than 0.50), the temperature at the main surface 70b can be raised to below 65°C when a current of 0.43 amperes flows through it.

[0125] The simulation results of the equivalent stress at the interface between the main surface 71a and the adhesive layer 61 when the pitch P1, spacing SP1, height H1, thickness T1, and thickness T6 are varied are shown in Tables 3 and 4. It should be noted that in the simulations in Tables 3 and 4, conditions other than those shown in Tables 3 and 4 are set to be the same as those in Table 2. In samples 1 to 6 shown in Tables 3 and 4, the pitches P1 to P4 are equal, the heights H1 to H4 are equal, the thicknesses T1 to T5 are equal, and the thicknesses T6 to T9 are equal. In Table 3, L1 represents the wiring width, which is the value obtained by subtracting the spacing SP1 from the pitch P1 (width L1 = pitch P1 - spacing SP1).

[0126]

[0127] Figure 20 This is a graph showing the relationship between the thermal stress at the interface between the main surface 71a and the adhesive layer 61 and the value obtained by dividing the first position offset by half of the pitch P1 in the simulations shown in Tables 3 and 4. The values ​​obtained by dividing the first position offset by half of the pitch P1 are set to 0, 0.066, 0.167, 0.333, and 0.5. Figure 20 As shown, the smaller the thicknesses T1 and T6, the greater the thermal stress at the interface between the main surface 71a and the adhesive layer 61. When the height H1 is greater than or less than 50 μm, the thermal stress at the interface between the main surface 71a and the adhesive layer 61 increases. The smaller the spacing SP1, the smaller the thermal stress at the interface between the main surface 71a and the adhesive layer 61. Figure 20As shown in Tables 3 and 4, if the value obtained by dividing the first position offset by half of the pitch P1 is greater than or equal to 0.06 and less than 0.50, it is possible to reduce the thermal stress generated at the interface between the adhesive layer 61 and the base film 71 as the temperature rises to less than 46 MPa, while reducing the temperature at the main surface 70b to less than 65°C when a current of 0.43 amperes flows through it.

[0128] The simulation results of temperature rise when pitch P1, spacing SP1, height H1, thickness T1, and thickness T6 are varied are shown in Tables 5 and 6. It should be noted that in the simulations in Tables 5 and 6, conditions other than those shown in Tables 5 and 6 are set to be the same as those in Table 1. However, in the simulations in Tables 5 and 6, the heat generation is set to 2.0 W / mm². 3 In samples 1 to 6 shown in Tables 5 and 6, the pitches P1 to P4 are equal, the heights H1 to H4 are equal, the thicknesses T1 to T5 are equal, and the thicknesses T6 to T9 are equal. In Table 5, L1 represents the wiring width, which is the value obtained by subtracting the interval SP1 from the pitch P1 (width L1 = pitch P1 - interval SP1).

[0129]

[0130] Figure 21 This is a graph showing the relationship between the temperature rise in the simulations shown in Tables 5 and 6 and the values ​​obtained by dividing the first position offset by half of the pitch P1. The values ​​obtained by dividing the first position offset by half of the pitch P1 are set to 0, 0.066, 0.167, 0.333, 0.5, and 1.0. Figure 21 As shown, the smaller the thicknesses T1 and T6, the smaller the temperature rise. Furthermore, if the interval SP1 decreases, the temperature rise increases. Figure 21 In the curve graph, since it largely overlaps with sample 5, the illustrations of samples 1 and 6 are omitted. That is, the height H1 has no effect on the temperature rise.

[0131] (Variation example)

[0132] Figure 22 This is an enlarged cross-sectional view of the coil device 100 involved in the modified example. For example... Figure 22 As shown, wiring 20 and wiring 21 (in Figure 22 (Not shown in the figure) It may also have an electroplated layer 25. The electroplated layer 25 covers the side surface of the seed layer 22, the side surface of the conductive layer 23, the side surface of the electroplated layer 24, and the upper surface of the electroplated layer 24. The electroplated layer 25 is formed by electroplating after the etching step S6 and before the base film bonding step S7.

[0133] Although not illustrated, wiring 50 and wiring 51 may also have an electrolytic plating layer different from the electrolytic plating layer 54, which covers the side surfaces of the seed layer 52, the conductive layer 53, the electrolytic plating layer 54, and the upper surface of the electrolytic plating layer 54. This different electrolytic plating layer is formed by electrolytic plating after the etching process S12 and before the base film bonding process S13.

[0134] It should be understood that the embodiments disclosed herein are illustrative in all respects and not restrictive. The scope of the invention is set forth not by the above embodiments but by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0135] Explanation of reference numerals in the attached figures

[0136] 10, 40, 41, 70, 71, 110 base films

[0137] 10a, 10b, 40a, 40b, 41a, 41b, 70a, 70b, 71a, 71b (Main face)

[0138] 20, 21, 50, 51, 120, 121 wiring

[0139] 20a, 21a, 50a, 51a, 120a, 121a coil section

[0140] 20b, 20c, 21b, 21c, 50b, 50c, 51b, 51c pads

[0141] Seed layers 22 and 52

[0142] 23, 53 conductive layers

[0143] 24, 54 Electrolytic plating

[0144] 25 Electrolytic plating

[0145] 30, 31, 60, 61 adhesive layers

[0146] 80, 81 Resist Pattern

[0147] 80a, 81a openings

[0148] 100, 200A, 200B Coil Devices

[0149] D position offset

[0150] Heights of H1, H2, H3, and H4

[0151] Widths of L1, L2, L3, and L4

[0152] P1, P2, P3, P4 pitch

[0153] S1 Preparation Process

[0154] S2 and S8 conductive treatment processes

[0155] S3 and S9 resist patterning processes

[0156] S4 and S10 electroplating processes

[0157] S5 and S11 Resist Pattern Removal Process

[0158] S6 and S12 etching processes

[0159] S7 and S13 Base Film Bonding Process

[0160] SP1, SP2, SP3, SP4 intervals

[0161] Thicknesses T1, T2, T3, T4, T5, T6, T7, T8, and T9.

Claims

1. A coil device comprising: The first base film has a first main surface and a second main surface, wherein the second main surface is the surface opposite to the first main surface; The first wiring is configured on the first main surface; as well as The second wiring is configured on the second main surface. The first wiring has a first coil portion, which is composed of a portion of the first wiring that is wound into a coil shape when viewed from above. The second wiring has a second coil portion, which is composed of a portion of the second wiring that is wound into a coil shape when viewed from above. When viewed in a cross section orthogonal to the direction in which the portion of the first wiring constituting the first coil portion extends, the positional offset between the portion of the first wiring constituting the first coil portion and the portion of the second wiring constituting the second coil portion, divided by half the pitch of the portion of the first wiring constituting the first coil portion, yields a value of 0.06 or more and less than 0.

50.

2. The coil device according to claim 1, wherein, The coil device also includes: A first adhesive layer is disposed on the first main surface in a manner that covers the first wiring; The second base film is disposed on the first adhesive layer and has a third main surface and a fourth main surface, wherein the third main surface is opposite to the first adhesive layer and the fourth main surface is the surface opposite to the third main surface; as well as The third wiring is configured on the fourth main surface. The third wiring has a third coil portion, which is composed of a portion of the third wiring that is wound into a coil shape when viewed from above. When viewed in a cross section orthogonal to the direction in which the portion of the first wiring constituting the first coil portion extends, the positional offset between the portion of the first wiring constituting the first coil portion and the portion of the third wiring constituting the third coil portion, divided by half the pitch of the portion of the first wiring constituting the first coil portion, yields a value of 0.06 or more and less than 0.

50.

3. The coil device according to claim 2, wherein, The coil device also includes: A second adhesive layer is disposed on the second main surface in a manner that covers the second wiring; A third base film, disposed on the second adhesive layer, has a fifth main surface and a sixth main surface, the fifth main surface being opposite to the second adhesive layer, and the sixth main surface being opposite to the fifth main surface; and The fourth wiring is configured on the sixth main surface. The fourth wiring has a fourth coil portion, which is composed of a portion of the fourth wiring that is wound into a coil shape when viewed from above. When viewed in a cross section orthogonal to the direction in which the portion of the first wiring constituting the first coil portion extends, the positional offset between the portion of the second wiring constituting the second coil portion and the portion of the fourth wiring constituting the fourth coil portion, divided by half the pitch of the portion of the second wiring constituting the second coil portion, yields a value of 0.06 or more and less than 0.

50.

4. The coil device according to claim 3, wherein, The coil device also includes: A third adhesive layer is disposed on the fourth main surface in a manner that covers the third wiring; The fourth base film is disposed on the third adhesive layer; A fourth adhesive layer is disposed on the sixth main surface in such a way as to cover the fourth wiring; as well as The fifth base film is disposed on the fourth adhesive layer. The fourth base film has a seventh main surface and an eighth main surface. The seventh main surface is opposite to the third adhesive layer, and the eighth main surface is the surface opposite to the seventh main surface. When a current of 0.43 amperes flows through the first wiring, the second wiring, the third wiring, and the fourth wiring and reaches a stable state, the temperature rise at the eighth main surface is less than 65°C, and the thermal stress generated at the interface between the third adhesive layer and the fourth base film as the temperature rises is less than 46 MPa.

5. The coil device according to any one of claims 1 to 4, wherein, The first wiring and the second wiring respectively have: A seed layer is disposed on the first main surface; A conductive layer is disposed on the seed layer; and An electrolytic plating layer is disposed on the conductive layer.

6. A coil device comprising: The first base film has a first main surface and a second main surface, wherein the second main surface is the surface opposite to the first main surface; The first wiring is configured on the first main surface; A first adhesive layer is disposed on the first main surface in a manner that covers the first wiring; The second base film is disposed on the first adhesive layer and has a third main surface and a fourth main surface, wherein the third main surface is opposite to the first adhesive layer and the fourth main surface is the surface opposite to the third main surface; as well as The third wiring is configured on the fourth main surface. The first wiring has a first coil portion, which is composed of a portion of the first wiring that is wound into a coil shape when viewed from above. The third wiring has a third coil portion, which is composed of a portion of the third wiring that is wound into a coil shape when viewed from above. When viewed in a cross section orthogonal to the direction in which the portion of the first wiring constituting the first coil portion extends, the positional offset between the portion of the first wiring constituting the first coil portion and the portion of the third wiring constituting the third coil portion, divided by half the pitch of the portion of the first wiring constituting the first coil portion, yields a value of 0.06 or more and less than 0.50.

Images