Semiconductor device and porous plate

Abstract

The present technology relates to a semiconductor device and a perforated plate that make it possible to reduce the number of connection terminals. The semiconductor device includes: an MEA including an electrode array unit formed of a plurality of electrodes and configured to output one or more pieces of first digital data obtained by measurement using the electrode array unit; and a first multiplexing unit configured to multiplex N pieces of first digital data output from the plurality of MEAs, and output M pieces of second digital data less than N. The present technology can be applied to a perforated plate.

Description

Technical Field

[0001] This technology relates to a semiconductor device and a perforated plate, and more particularly, to a semiconductor device and a perforated plate that can reduce the number of connection terminals. Background Technology

[0002] Microelectrode arrays (MEAs) can obtain information about the cell’s response to a compound by measuring the cell’s active potential.

[0003] For example, as an MEA, one known configuration involves forming multiple electrodes by depositing electrode material on an insulating substrate such as glass, and capturing the cell's activity potential through the electrodes to detect the signal using an external amplifier and analog-to-digital (AD) converter. In the following text, an MEA with this configuration is also referred to as a prior art MEA.

[0004] For example, as a technology related to existing MEAs, a technology has been proposed in which multiple transparent MEAs integrally formed with culture wells are arranged in an array to form a culture plate (see, for example, Patent Document 1).

[0005] In contrast, MEAs (also referred to below as CMOS-MEAs) using so-called complementary metal oxide semiconductor (CMOS) technology have been developed.

[0006] In existing MEAs, it is difficult to reduce the spacing between electrodes, but in CMOS technology, by using semiconductor photolithography, it is possible to form electrodes that are finer than those in existing MEAs.

[0007] Furthermore, the use of CMOS technology to amplify and convert active potentials detected by electrodes within the chip reduces the impact of external noise and enables MEAs with more electrodes than existing MEAs. Citation List Patent documents

[0008] Patent Document 1: JP 2016-529889 A Summary of the Invention Technical issues

[0009] A porous plate with multiple holes inside is known.

[0010] For example, consider a perforated plate in which one MEA is placed in each hole.

[0011] In this case, if the existing type of MEA is set in the hole, then for each MEA in the multi-hole plate, a connection terminal (output terminal) is required to read the signal of the measurement result in the electrode. The number of connection terminals is equal to the number of electrodes included in the MEA.

[0012] Therefore, as the number of holes and electrodes increases, the number of connection terminals in the perforated board also increases, and the spacing between the connection terminals becomes narrower. Additionally, numerous amplifiers and AD converters are required on the external device side connected to the perforated board.

[0013] Therefore, when using existing MEA technology, it is difficult to achieve porous plates with a large number of holes.

[0014] Similarly, even when CMOS-MEA is configured for vias, the number of connection terminals (output terminals) in the via board increases with the number of vias and electrodes. Therefore, it is desirable to use CMOS-MEA to reduce the number of connection terminals in the via board.

[0015] This technology was proposed in view of this situation, and its purpose is to make it possible to reduce the number of connection terminals. Solution to the problem

[0016] A semiconductor device according to a first aspect of the present invention includes: an MEA comprising an electrode array unit formed of a plurality of electrodes and configured to output one or more first digital data obtained by measuring using the electrode array unit; and a first multiplexing unit configured to multiplex N first digital data output from the plurality of MEAs and output M second digital data less than N.

[0017] In a first aspect of the present technology, the semiconductor device is provided with: an MEA including an electrode array unit formed by a plurality of electrodes, and outputting one or more first digital data obtained by measuring using the electrode array unit; and a first multiplexing unit that multiplexes N first digital data output from the plurality of MEAs, and outputs M second digital data less than N.

[0018] The perforated plate according to the second aspect of the present invention is a perforated plate that includes a semiconductor device according to the first aspect of the present invention. Attached Figure Description

[0019] Figure 1 This is a diagram illustrating an example of the structure of a conventional MEA. Figure 2 This is a conceptual diagram of a measurement system that utilizes existing MEA technology. Figure 3This is a diagram showing an example of the configuration of a CMOS-MEA. Figure 4 This is a diagram showing the appearance of a CMOS-MEA. Figure 5 This is a diagram showing an example of CMOS-MEA installation. Figure 6 This is a conceptual diagram of a measurement system using CMOS-MEA. Figure 7 This is a diagram showing an example of a perforated plate. Figure 8 This is a diagram showing an image of a perforated plate using a conventional MEA. Figure 9 This is a diagram used to illustrate this technology. Figure 10 This is a diagram illustrating an example of the configuration of a measurement system to which this technology is applicable. Figure 11 This is a diagram illustrating an example of the configuration of a semiconductor device. Figure 12 This is a diagram showing an example of the configuration of a CMOS-MEA chip. Figure 13 This is a diagram illustrating an example of the configuration of a multiplexing IC. Figure 14 This is a diagram illustrating an example of the configuration of a semiconductor device. Detailed Implementation

[0020] The following description, with reference to the accompanying drawings, illustrates the applicable implementation scheme for this technology.

[0021] First Implementation Plan This technology This technology reduces the number of connection terminals in a perforated board by providing multiplexing (synthesis) of digital data from each output of multiple CMOS-MEAs.

[0022] Figure 1 This is a diagram illustrating an example of the structure of a conventional MEA.

[0023] In this example, the prior art MEA 11 includes a substrate 21 made of glass or the like, and microelectrodes 22 formed on the substrate 21 in a 4 × 4 array, for a total of 16 electrodes.

[0024] Additionally, the connection terminals (output terminals) are electrically connected to each electrode via wiring. For example, connection terminal 24 is connected to electrode 22 via wiring 23, and signals such as cell activity potential detected by electrode 22 are output to an external device connected to connection terminal 24 via wiring 23 and connection terminal 24.

[0025] In the following text, for ease of understanding, the electrodes, wiring and connection terminals provided on the prior art MEA 11 are also referred to as electrode 22, wiring 23 and connection terminal 24, without any special distinction between them.

[0026] Figure 2 Is using Figure 1 The diagram shows a conceptual representation of the existing MEA 11 measurement system.

[0027] In this example, in the measurement system, a prior art MEA 11 is connected to the top of the device housing 51, and cell culture wells 52 are formed on the prior art MEA 11.

[0028] Specifically, here, each connection terminal 24 provided on the existing technology type MEA 11 is connected to each connection terminal 53 provided on the device side of the housing 51.

[0029] Furthermore, in the measurement system, the conventional MEA 11 is positioned at the bottom of the cell culture well 52, such that each electrode 22 of the conventional MEA 11 is contained within the cell culture well 52. The cells to be tested are cultured inside the cell culture well 52. Specifically, the cells in the cell culture well 52 are cultured to contact the electrodes 22.

[0030] In the measurement system, external device 54 is electrically connected to the housing 51 of the device via a signal transmission line, and data acquisition system 55 is also connected to external device 54. External device 54 includes an amplifier and an AD converter.

[0031] During measurement, the activity potential of cells cultured in cell culture well 52 is detected by electrode 22. Then, an analog signal indicating the detected activity potential is read out to housing 51 via wiring 23, connection terminal 24 and connection terminal 53, and the read signal is further transmitted from housing 51 to external device 54 via signal transmission line.

[0032] The signal read from housing 51 is amplified and converted by an analog-to-digital converter in external device 54. The resulting digital data is supplied to data acquisition system 55 and recorded as a measurement result.

[0033] In the measurement system described above, the number of connection terminals 24 on the MEA 11 side and the number of connection terminals 53 on the device housing 51 side need to correspond to the number of electrodes 22 provided on the MEA 11 in the prior art. Similarly, the number of signal transmission lines connecting the device housing 51 and the external device 54 also needs to be the same as the number of electrodes 22 provided on the MEA 11.

[0034] Figure 3An example of a CMOS-MEA configuration is shown.

[0035] In this example, the CMOS-MEA 81 includes a semiconductor substrate 91, and an electrode array unit 92, a row selection circuit 93, an AD conversion circuit 94, and an output circuit 95 are formed on the semiconductor substrate 91.

[0036] In electrode array unit 92, in the row direction ( Figure 3 (horizontal direction) and column direction ( Figure 3 Multiple electrodes, including microelectrodes 101, are arranged (i.e., in a matrix) in the vertical direction. Specifically, in this example, with... Figure 1 As in the example shown, a total of 16 electrodes in a 4 × 4 array are formed on the semiconductor substrate 91.

[0037] Each electrode within the electrode array unit 92 is connected to the vertical signal line via an amplifying transistor and a selecting transistor. For example, electrode 101 is connected to the gate of amplifying transistor 102. Furthermore, amplifying transistor 102 is connected to the vertical signal line 104 via selecting transistor 103. Vertical signal line 104 is connected to the AD conversion circuit 94.

[0038] In the following text, for ease of understanding, the electrodes, amplifying transistors, selecting transistors, and vertical signal lines disposed in the electrode array unit 92 are also referred to as electrodes 101, amplifying transistors 102, selecting transistors 103, and vertical signal lines 104, without any particular distinction between them. Multiple electrodes 101 arranged in the row direction are also referred to as electrode rows, and multiple electrodes 101 arranged in the column direction are also referred to as electrode columns.

[0039] For example, when the row selection circuit 93 supplies a control signal to the selection transistor 103 of each electrode 101 connected to a predetermined electrode row and the selection transistor 103 is turned on (in the on state), the electrode row is in the selection state.

[0040] Subsequently, a signal indicating the cell activity potential detected by each electrode 101 constituting the electrode row set to the selected state is output from the electrode 101 to the AD conversion circuit 94 via the amplifying transistor 102, the selecting transistor 103 and the vertical signal line 104.

[0041] The AD conversion circuit 94 performs AD conversion on the analog signal indicating the cell's activity potential and outputs the resulting digital data to the outside of the CMOS-MEA 81 via the output circuit 95.

[0042] Figure 4 An image showing the appearance of the CMOS-MEA 81 is displayed.

[0043] In this example, in addition to the electrode array unit 92, a plurality of pads, including pads 131, are provided along the long side of the semiconductor substrate 91 on the surface of the semiconductor substrate 91. In the following description, pads similar to the pads 131 provided on the semiconductor substrate 91 are also referred to as pads 131, without any special distinction between them.

[0044] Pad 131 is used to supply power, clock, control signals, etc., to operate various circuits such as row selection circuit 93 disposed inside the semiconductor substrate 91, and to output digital data from the output circuit 95 to external devices. That is, circuits disposed inside the semiconductor substrate 91 are connected to pad 131 via wiring (not shown). Pad 131 is connected to substrates outside the CMOS-MEA 81 via gold wires, etc.

[0045] For example, such as Figure 5 As shown, the CMOS-MEA 81 can be mounted on the substrate 161. In this example, for example, a semiconductor substrate 91 on which an electrode array unit 92 is formed is mounted on the substrate 161 to form a package, and this package can be considered as a CMOS-MEA.

[0046] In substrate 161, for example, semiconductor substrate 91 is electrically connected to substrate 161 via wire bonding or the like. Semiconductor substrate 91 may be housed in a package and mounted on substrate 161.

[0047] Cell culture wells 162 are formed on a semiconductor substrate 91. That is, the semiconductor substrate 91 is disposed on the bottom surface portion of the cell culture wells 162, such that each electrode 101 of the electrode array unit 92 is contained within the cell culture wells 162.

[0048] Furthermore, the substrate 161 is provided with a plurality of connection terminals, including connection terminals 163 which serve as terminals for connection to external devices, etc. Hereinafter, these connection terminals are also referred to as connection terminals 163 without any particular distinction.

[0049] For example, pads 131 provided on semiconductor substrate 91 are connected to connection terminals 163 via wiring formed in substrate 161. Therefore, for example, digital data output from output circuit 95 is output to external devices, etc., via pads 131, wiring in substrate 161 and connection terminals 163.

[0050] Figure 6 This is a conceptual diagram of a measurement system that uses CMOS-MEA 81 to acquire digital data indicating the active potential.

[0051] In this example, Figure 5The substrate 161 shown is mounted on the housing 191 of a predetermined device. Specifically, the substrate 161 and the housing 191 (device) are electrically connected via connection terminals 163 connecting the substrate 161 and connection terminals including connection terminals 192 provided on the housing 191. In the following text, the connection terminals on the housing 191 side are also referred to as connection terminals 192 without any particular distinction.

[0052] As described above, the semiconductor substrate 91 is mounted on the substrate 161, and the cell culture well 162 is formed in a portion of the electrode array unit 92 in the semiconductor substrate 91.

[0053] The data acquisition system 193 is connected to the housing 191 of the device via a transmission line.

[0054] For example, the data acquisition system 193 supplies clock, power, GND power (ground power), control signals, etc. to the semiconductor substrate 91 via transmission lines, wiring and circuits in the housing 191, connection terminals 192 and 163, wiring and circuits in the substrate 161, and pads 131.

[0055] Furthermore, various digital data, such as digital data indicating the measurement result of the active potential output from the semiconductor substrate 91, are supplied to the data acquisition system 193 via wiring and circuitry within the substrate 161, connection terminals 163 and 192, wiring and circuitry within the housing 191, and transmission lines. Note that the number of transmission lines connecting the housing 191 and the data acquisition system 193 varies depending on the amount and format of the digital data to be transmitted.

[0056] As mentioned above, existing MEA or CMOS-MEA technologies are used to measure the activity potential of cells in cell culture wells.

[0057] Various applications and methods are used to perform experiments using cell culture wells.

[0058] In particular, a so-called multi-well plate was prepared to observe the cell response while changing various conditions.

[0059] Figure 7 An example of a perforated plate is shown. In this example, each cylindrical section is a hole, and the perforated plate is provided with a total of 96 holes in an 8 × 12 array.

[0060] Typically, a multi-well plate with 6, 12, 24, 48, 96, 384, or 1536 wells is prepared, along with devices for adding the medicine into each well and observation devices, etc., depending on the size of the multi-well plate.

[0061] Therefore, the multiwell plates have standard dimensions as specified by the American National Standards Institute (ANSI) / Society for Biomolecular Screening (SBS). Specifically, the length is 127.13 mm to 83 mm, the width is 85.23 mm to 85.73 mm, and the height is 14.1 mm to 14.6 mm.

[0062] In perforated plates including MEA, the dimensions of the perforated plate also need to be set according to the above standard dimensions.

[0063] Therefore, it is necessary to consider the technical issues of porous plates, including MEAs, under the assumption that porous plates are implemented in standard sizes.

[0064] For perforated plates that include holes with MEAs, consider porous structures.

[0065] First, we will consider the use of existing technology-based MEAs.

[0066] For example, in the case of a porous plate with 96 holes in which 4 × 4 = 16 electrodes are formed in one hole, 16 × 96 = 1536 connection terminals (output terminals) are needed to read the electrical signal indicating the measurement result from the porous plate.

[0067] Since the bottom surface of the standard orifice plate is 127.5 mm × 85.5 mm, the outer perimeter of the bottom surface is 426 mm.

[0068] Therefore, the spacing between adjacent electrodes is 426 mm ÷ 1536 = 0.28 mm. When the electrodes are arranged in two or three rows, the spacing becomes two or three times, but the spacing is still very narrow (microscopic).

[0069] When the number of holes in the porous plate is further increased to 384, the spacing becomes even more pronounced. Furthermore, as the number of electrodes in each hole increases, the spacing also narrows, making it difficult to achieve a porous structure.

[0070] Figure 8 An image of a porous plate formed using a prior art MEA is shown, which includes 16 electrodes in one hole and a total of 96 holes.

[0071] In this example, the part indicated by arrow Q11 is Figure 1 The example shown is a prior art MEA, and 4 × 4 electrodes are formed in the MEA.

[0072] In addition, the connection terminals (output terminals) used to read signals from each electrode are drawn along the edge portion of the perforated plate, but since not all connection terminals can be drawn here, some connection terminals are omitted from the illustration. In particular, a rectangle drawn on the edge portion represents a connection terminal.

[0073] from Figure 8 The examples show that it is difficult to achieve porous plates with a large number of holes when using existing MEA technology.

[0074] Furthermore, when using existing MEAs, the device side connected to the perforated board requires connection terminals for connecting to the perforated board side, as well as circuitry for amplifying and converting the signals read from the connection terminals using AD conversion. For example, in Figure 8 In the example, 1536 connection terminals are required on the device side.

[0075] As mentioned above, even if it is not impossible, it is not easy to realize a porous plate using existing MEA technology.

[0076] Even if such a perforated plate and the device connected to it can be realized, when the number of holes is changed, the number of connection terminals on the device side must also be changed to cope with the change, and it is not easy to increase the number of connection terminals.

[0077] Similar to the existing MEA technology described above, it is difficult to form a porous structure even when using a CMOS-MEA.

[0078] For example, in a via including a CMOS-MEA, if there are eight channels of digital output (differential output) for a via, then 16 connection terminals are required for a via.

[0079] If there are 96 such holes in the perforated plate, then the perforated plate needs 16 × 96 = 1536 connection terminals (output terminals) to read the signal obtained from the electrodes.

[0080] When using CMOS-MEA, terminals are also required for power, clock, etc. Even if shared terminals are used for all 96 holes, a large number of connection terminals are still needed.

[0081] Even if a porous board utilizing a CMOS-MEA and a device connected to that porous board are implemented, when the number of holes in the porous board changes, the number of connection terminals on the device side must also change to accommodate this change, which is the same as in the case of existing MEA technology.

[0082] As mentioned above, in order to realize a porous board using CMOS-MEA, a number of connection terminals (output terminals) corresponding to the number of holes are needed to read out the signals (digital data) obtained from the electrodes, making it difficult to realize a porous structure.

[0083] Here, in this technology, by setting a function to multiplex the output of digital data from the CMOS-MEA set (installed) in each hole, the number of connection terminals (output terminals) that previously needed to be multiplied by the number of holes can be reduced.

[0084] Reference Figure 9 This technology is explained. Figure 9 In order to facilitate understanding and explanation, the structure has been simplified.

[0085] exist Figure 9 In the example shown, the perforated board is provided with a total of four CMOS-MEAs in a 2 × 2 array. Specifically, the perforated board is provided with CMOS-MEAs 221-1 to CMOS-MEAs 221-4.

[0086] Note that in the following text, when there is no need to make a special distinction between CMOS-MEA 221-1 to CMOS-MEA 221-4, they are also referred to as CMOS-MEA 221.

[0087] In this example, a CMOS-MEA 221 is configured on the bottom portion of a hole formed in a porous plate.

[0088] For example, with Figure 3 As in the example shown, each CMOS-MEA 221 includes multiple electrodes and outputs digital data obtained by measuring using the multiple electrodes as measurement data. Specifically, the measurement data output from CMOS-MEA 221-1 to CMOS-MEA 221-4 are represented as measurement data D1 to measurement data D4.

[0089] The perforated board includes a multiplexing circuit 222 formed by multiplexing integrated circuits (ICs) and the like.

[0090] Measurement data D1 to D4 output from CMOS-MEA 221-1 to CMOS-MEA 221-4 are input to multiplexing circuit 222. Multiplexing circuit 222 implements the multiplexing function to multiplex these measurement data.

[0091] That is, the multiplexing circuit 222 multiplexes (synthesizes) the measurement data supplied from each CMOS MEA 221, and outputs a digital data as a result as measurement data to the later stage.

[0092] Specifically, for example, the multiplexing circuit 222 outputs each of the measurement data D1, measurement data D2, measurement data D3, and measurement data D4 sequentially to a signal line, thereby realizing the multiplexing function. In other words, the measurement data D1, measurement data D2, measurement data D3, and measurement data D4 are arranged sequentially and combined into one measurement data.

[0093] As an example, assume that measurement data D1 to measurement data D4 are output from the CMOS-MEA 221 at a data rate of N [bps].

[0094] In this configuration, the multiplexing circuit 222 outputs a single measurement data, formed from measurement data D1 to measurement data D4, at a data rate of 4N bps, which is four times N bps. This reduces the number of connection terminals required to one-quarter.

[0095] Note that the number of wirings used to output digital data (measurement data) from each CMOS-MEA 221 is not necessarily limited to one, and it is also possible to consider connecting a CMOS-MEA 221 and the multiplexing circuit 222 through multiple wirings.

[0096] In this configuration, multiple (two or more) digital data inputs are fed from a CMOS-MEA 221 to the multiplexing circuit 222. However, the number of connection terminals can be reduced by setting the number of data outputs from the multiplexing circuit 222 to be less than the total number of digital data inputs to the multiplexing circuit 222.

[0097] Typically, more than M digital data items (M=4 in this example) are input to the multiplexing circuit 222 from multiple N CMOS-MEAs 221 (N=4 in this example). The multiplexing circuit 222 multiplexes the input M digital data items and outputs M' digital data items (less than M) as a result of the multiplexing.

[0098] Each CMOS-MEA 221 can be formed from an independent Si chip (silicon chip), that is, a semiconductor chip.

[0099] In this configuration, for example, each semiconductor chip, serving as a CMOS-MEA 221, is chip-bonded onto a substrate formed of ceramic or organic material. Each semiconductor chip (CMOS-MEA 221) is connected to a multiplexing circuit 222 disposed on the substrate via wiring formed on the substrate.

[0100] Furthermore, for example, each CMOS-MEA 221 may not be an independent semiconductor chip, and some CMOS-MEA 221s may be formed on the same semiconductor chip (Si chip). In other words, CMOS-MEA 221s disposed in each of multiple holes can be formed (mounted) on the same semiconductor chip.

[0101] For example, CMOS-MEA 221-1 and CMOS-MEA 221-2 can be formed on one semiconductor chip, and CMOS-MEA 221-3 and CMOS-MEA 221-4 can be formed on another semiconductor chip.

[0102] Furthermore, for example, all of CMOS-MEA 221-1 to CMOS-MEA 221-4 can be formed on a single semiconductor chip (Si chip).

[0103] In this case, the multiplexing circuit 222 can be located inside the semiconductor chip on which all CMOS-MEA 221 are located, or it can be located outside the semiconductor chip on which all CMOS-MEA 221 are located.

[0104] exist Figure 9 For ease of understanding, the following example is provided, in which the perforated plate includes a total of four CMOS-MEAs in a 2 × 2 array.

[0105] However, in reality, the number of holes is even greater. For example, in a typical porous plate, the number of holes is 96, 384, etc.

[0106] In this context, for example, the application of this technology is advantageous when the number of connection terminals used to transmit digital data (measurement data) from the 96-hole output (i.e., from the 96 CMOS-MEA221 outputs) can be reduced.

[0107] As a specific example, when using 8 multiplexer circuits 222, each multiplexer circuit 222 generates one output for 12 inputs, reducing the number of connection terminals that would normally be 96 to 8.

[0108] Furthermore, for example, four multiplexing circuits 222 can be used, each multiplexing circuit 222 producing one output for four inputs. Additionally, multiplexing circuits 222 can be used that utilize the outputs from the four multiplexing circuits 222 as inputs and produce one output for those inputs. In this case, 4 × 4 = 16 inputs (digital data) can be converted into one output (digital data).

[0109] Multiple CMOS-MEAs and one or more multiplexing circuits can be arbitrarily configured to reduce the number of connection terminals.

[0110] That is, the combination of CMOS-MEA and multiplexing circuit can be appropriately determined based on the number and array of holes in the perforated board, the number and array of connection terminals on the device side connected to the perforated board, etc.

[0111] This not only reduces the number of connection terminals in perforated plates or devices, but also allows for easy adaptation to changes in the number of holes.

[0112] For example, multiple perforated plates with different numbers of holes and different hole arrays can be connected to the same device and used, thereby improving convenience.

[0113] exist Figure 9 In the examples shown, when the outputs (measurement data) from multiple CMOS-MEA 221s are combined (combined) into one measurement data by multiplexing circuit 222, it may be impossible to determine which of the measurement data constituting the measurement data is the measurement data of which hole (which CMOS-MEA 221).

[0114] To prevent this, the ID information inherent to the aperture (CMOS-MEA 221) can be stored in the measurement data output from the CMOS-MEA 211.

[0115] In other words, identification information such as an ID number (ID information) that can uniquely identify the aperture (CMOS-MEA 221) means that the output source of the measurement data can be assigned to the measurement data output from the CMOS-MEA 211.

[0116] In this case, for example, the inherent ID information of the aperture, i.e., the ID information used to identify the aperture, is stored (assigned) in the header data portion of the measurement data header within a predetermined period, such as a frame output from the CMOS-MEA 221. This makes it possible to identify which measurement data was obtained from which aperture (CMOS-MEA 221).

[0117] Example of a measurement system configuration Figure 10 This is a diagram illustrating an example of the configuration of a measurement system to which this technology is applicable.

[0118] Figure 10 The measurement system shown includes a perforated plate 251, an external device 252, and a data acquisition system 253.

[0119] A multi-well plate 251 is a plate having multiple wells, including wells 261. For example, wells 261 are cell culture wells (biological culture wells) for culturing cells to be observed.

[0120] Here, the perforated plate 251 includes a total of 96 holes in an 8 × 12 array, but the number of holes set in the perforated plate 251 can be any number.

[0121] In the following text, the holes provided in the perforated plate 251 are also referred to simply as holes 261, without any special distinction between them.

[0122] The perforated plate 251 includes a semiconductor device 262 formed from a semiconductor substrate or the like, and the semiconductor device 262 is disposed on the bottom portion (bottom) of the perforated plate 251, that is, on the surface portion of the perforated plate 251 on the side of the external device 252.

[0123] Semiconductor device 262 includes a plurality of CMOS-MEAs (not shown), and the CMOS-MEAs are configured to be included within a hole 261.

[0124] More specifically, for example, an electrode array unit having multiple electrodes is disposed in a CMOS-MEA in semiconductor device 262 and is fixed to the bottom (bottom portion) of hole 261 such that the electrode array unit is included within a hole 261.

[0125] Here, an example in which the CMOS-MEA is set as the MEA will be described. However, the MEA set in the semiconductor device 262 is not limited to this example, and can be any MEA, as long as the MEA outputs one or more digital data (measurement data) indicating the measurement result; in other words, as long as the MEA has AD conversion function.

[0126] In each well 261, the cells to be tested (observed) are cultured. At this time, the cells are cultured such that they are positioned (in contact) with at least one or more electrodes disposed in the electrode array unit.

[0127] Note that although the following example illustrates a CMOS-MEA configured for a single aperture 261, a CMOS-MEA can also be configured for multiple apertures 261. In this case, for example, multiple electrode array cells, such as 2 × 2 electrode array cells, are configured in a CMOS-MEA, and one electrode array cell is included at the bottom of an aperture 261.

[0128] In this measurement system, a perforated plate 251 is disposed on an external device 252, and a connection terminal (not shown) provided on the perforated plate 251 and a plurality of connection terminals including connection terminal 263 in the external device 252 are connected to each other. As a result, the perforated plate 251 and the external device 252 are electrically connected via the connection terminals.

[0129] In the following text, the connection terminals provided in the external device 252 for connecting to the perforated plate 251 are simply referred to as connection terminals 263, without any particular distinction between them.

[0130] Furthermore, although the accompanying drawings show the perforated plate 251 not configured on the external device 252 for ease of understanding, the perforated plate 251 is actually used when configured on the external device 252.

[0131] The data acquisition system 253 is connected to the external device 252 via one or more transmission lines. For example, the data acquisition system 253 may consist of a computer or the like.

[0132] For example, the data acquisition system 253 supplies clock, power, GND power (ground power), control signals, etc. to the semiconductor device 262 via transmission lines, wiring and circuits in the external device 252 and connection terminals 263.

[0133] Furthermore, various digital data, such as digital data indicating active potential, output from semiconductor device 262, are supplied to data acquisition system 253 via connection terminal 263, wiring and circuitry within external device 252, and transmission lines. Note that the number of transmission lines connecting external device 252 and data acquisition system 253 varies depending on the amount and format of the digital data to be transmitted.

[0134] For example, the semiconductor device 262 disposed at the bottom of the porous plate 251 has Figure 11 The structure shown.

[0135] exist Figure 11 In the example shown, multiple CMOS-MEA chips, including CMOS-MEA chip 292, arranged in an array are chip-bonded (configured) on a single substrate 291, such as a substrate formed of ceramic, organic material, or a semiconductor substrate. Each CMOS-MEA chip is formed from an independent semiconductor chip.

[0136] In this example, although 6 × 5 = 30 CMOS-MEA chips are shown for ease of understanding of the accompanying drawings, the actual number of CMOS-MEA chips provided corresponds to the number of vias 261 in the entire semiconductor device 262. For example, the same number of CMOS-MEA chips as standard numbers of vias such as 6, 12, 96, or 1536 can be provided in the entire semiconductor device 262.

[0137] For example, the CMOS-MEA chip 292 is a semiconductor chip formed from a silicon substrate (semiconductor substrate) and is used as a CMOS-MEA. That is, the CMOS-MEA chip 292 includes an electrode array unit formed from multiple electrodes and outputs one or more measurement data (digital data) obtained by measuring using the electrode array unit.

[0138] The CMOS-MEA chip 292 can be mounted on the substrate 291 by any method. For example, the CMOS-MEA chip 292 can be bonded to the substrate 291 via gold wire leads. That is, the CMOS-MEA chip 292 can be connected to the substrate 291 via wires such as gold wires. The CMOS-MEA chip 292 can be connected to the substrate 291 via solder bumps or the like.

[0139] In the following text, the CMOS-MEA chip disposed on the substrate 291 is also referred to as CMOS-MEA chip 292, without making any special distinction between them.

[0140] The multiplexing IC 293, which serves as a multiplexing circuit, is also mounted on the substrate 291, and each CMOS-MEA chip 292 is connected to the multiplexing IC 294 via wiring 294 formed on the substrate 291.

[0141] Therefore, measurement data, which is digital data obtained by measurement in each CMOS-MEA chip 292, is supplied to the multiplexing IC 293 via wiring 294.

[0142] Circuits that perform certain signal processing on the digital data output from the CMOS-MEA chip 292 can be connected between the CMOS-MEA chip 292 and the multiplexing IC 293.

[0143] One or more digital data points (measurement data) obtained through measurement are supplied from a CMOS-MEA chip 292 to a multiplexing IC 293. That is, two or more digital data points can be supplied from the CMOS-MEA chip 292 to the multiplexing IC 293.

[0144] Basically, in the porous plate 251, a CMOS-MEA chip 292 is disposed for each hole 261. For example, the CMOS-MEA chip 292 is provided with an electrode array unit including multiple electrodes, and the electrode array unit is disposed at the bottom (bottom portion) of the hole 261 so as to be contained within the hole 261. The electrode array unit referred to here is described later. Figure 12 Electrode array unit 322 in the middle.

[0145] On the other hand, multiple electrode array units can be disposed within a single CMOS-MEA chip 292. In this case, for example, multiple electrode array units can be configured within multiple holes 261 that are different from each other. That is, a single CMOS-MEA chip 292 can be configured at the bottom of the multiple holes 261.

[0146] In cases where the CMOS-MEA chip 292 includes multiple electrode array units, the CMOS-MEA chip 292 can output digital data (measurement data) obtained through measurement to the multiplexing IC 293 for each electrode array unit. In particular, in this case, the number of wiring 294 connecting the CMOS-MEA chip 292 and the multiplexing IC 293 can be the same as the number of output digital data.

[0147] The multiplexing IC 293 multiplexes the digital data (measurement data) supplied from each of the multiple CMOS-MEA chips 292 via wiring 294, and outputs the resulting digital data (measurement data) to the connection terminal 295 via wiring, etc.

[0148] exist Figure 11 In the example, the CMOS-MEA chip 292 and the multiplexing IC 293 correspond to respectively Figure 9 The CMOS-MEA chip 221 and multiplexing circuit 222 are shown.

[0149] The connection terminal 295 is a terminal (output terminal) formed on the substrate 291. For example, the connection terminal 295 is directly connected to the connection terminal 263 of the external device 252, or indirectly connected to the connection terminal 263 via circuits, wiring, etc. provided in the semiconductor device 262.

[0150] The connection terminal 295 supplies digital data (measurement data) output from the multiplexer IC 293 to the external device 252 via the connection terminal 263.

[0151] A circuit that performs some kind of signal processing on the measurement data can be located between the connection terminal 295 and the multiplexing IC 293.

[0152] The circuit that performs signal processing on the measurement data can be located between the connection terminal 295 and the connection terminal 263 on the substrate 291, between the connection terminal 263 and the connection terminal 295 in the external device 252, or at the rear end of the connection terminal 263 in the external device 252.

[0153] The digital data output from the multiplexer IC 293 is not limited to the example of transmitting to the external device 252 via the connection terminal 295, and can be supplied to the external device 252 by other methods.

[0154] For example, digital data (measurement data) output from the multiplexing IC 293 can be transmitted to the external device 252 via an IC or the like, which is provided on the substrate 291 and has a transceiver function that enables the digital data to be transmitted to the external device 252 (i.e., can be connected to the external device 252).

[0155] Furthermore, while an example is shown here in which one digital data (multiplexed measurement data) is output from the multiplexing IC 293 to the connection terminal 295, it is also possible for the multiplexing IC 293 to output two or more digital data. In this case, for example, the substrate 291 includes a number of connection terminals 295 corresponding to the number of digital data to be output, and the digital data is output from the multiplexing IC 293 to multiple connection terminals 295.

[0156] Typically, it is assumed that a total of N digital data (measurement data) are supplied (output) from multiple CMOS-MEA chips 292 to the multiplexing IC 293. In this case, the multiplexing IC 293 multiplexes the N digital data to be input to generate M digital data (where M is greater than or equal to 1), and outputs the M data (measurement data) obtained through multiplexing to the connection terminal 295.

[0157] Semiconductor device 262 includes at least one substrate 291 on which a CMOS-MEA chip 292 and a multiplexing IC 293 are disposed.

[0158] In other words, the semiconductor device 262 can be composed of one substrate 291 or more substrates 291.

[0159] In addition, for example, various configurations can be provided, each of which includes a plurality of CMOS-MEA chips 292 disposed on a substrate 291, a multiplexer IC 293 connected to the CMOS-MEA chips 292, and a connection terminal 295.

[0160] In addition, various configurations can be provided, each of which includes a plurality of CMOS-MEA chips 292 disposed on substrate 291 and a multiplexing IC 293 connected to the CMOS-MEA chips 292, and also includes a multiplexing IC for multiplexing digital data output from the plurality of multiplexing ICs 293.

[0161] In this case, the multiplexing IC multiplexes a total of P (where P is 2 or more) of digital data output from multiple multiplexing ICs 293, and outputs Q (where Q is 1 or more) of digital data less than P to the connection terminal 295, etc.

[0162] A multiplexing IC can also be configured to multiplex measurement data (digital data) output from one or more multiplexing ICs 293 with measurement data output from one or more CMOS-MEA chips 292, and output one or more measurement data lines with fewer input measurement data than the multiplexed measurement data.

[0163] Furthermore, multiple substrates 291 can be mounted on other substrates, and a multiplexing IC that multiplexes digital data (measurement data) output from multiple substrates 291 (multiplexing IC 293) can be disposed on other substrates.

[0164] For example, the CMOS-MEA chip 292 used as a CMOS-MEA can be as follows: Figure 12 The structure shown is as described.

[0165] exist Figure 12 In the example, the CMOS-MEA chip 292 includes a semiconductor substrate 321. Electrode array unit 322, row selection circuit 323, AD conversion circuit 324, ID allocation unit 325 and output circuit 326 are formed on the semiconductor substrate 321.

[0166] In electrode array unit 322, in the row direction ( Figure 12 (horizontal direction) and column direction ( Figure 12 Multiple electrodes, including microelectrodes 331, are arranged in a matrix along the vertical direction.

[0167] Here, a total of 16 electrodes in the 4 × 4 array are formed on the semiconductor substrate 321, but the number of electrodes forming the electrode array unit 322 can be any number.

[0168] Each electrode within the electrode array unit 322 is connected to the vertical signal line via an amplifying transistor and a selecting transistor. For example, electrode 331 is connected to the gate of amplifying transistor 332. Furthermore, amplifying transistor 332 is connected to the vertical signal line 334 via selecting transistor 333. Vertical signal line 334 is connected to the AD conversion circuit 324.

[0169] In the following text, the electrodes, amplifying transistors, selecting transistors, and vertical signal lines disposed in the electrode array unit 322 are also referred to as electrode 331, amplifying transistor 332, selecting transistor 333, and vertical signal line 334, without making any special distinction between them.

[0170] Electrode array unit 322 is disposed at the bottom within a well 261. For example, when cells are cultured within the well 261 to bring them into contact with the electrodes 331 of electrode array unit 322, the cell activity potential observed at the electrodes 331 changes due to the electrical activity of the cells.

[0171] Therefore, a signal corresponding to the cell's activity potential is supplied from electrode 331 to the gate of amplifying transistor 332. Consequently, a signal corresponding to the signal supplied to the gate, i.e., a signal corresponding to the cell's activity potential, is output from amplifying transistor 332 to selecting transistor 333. The signal supplied from amplifying transistor 332 to selecting transistor 333 is an analog signal indicating the measurement result of the activity potential, i.e., an analog signal obtained by measuring the activity potential.

[0172] In electrode array unit 322, selection transistor 333 is connected to electrode 331 via amplification transistor 332. The gate of the selection transistor 333 connected to each electrode 331 constituting the electrode row is connected to a signal line arranged along the electrode row, and the end of the signal line is connected to row selection circuit 323.

[0173] When the row selection circuit 323 supplies a control signal via a signal line to the gate of each selection transistor 333 of the electrode row for setting the electrode row to the selection state, the selection transistor 333 connected to the electrode 331 constituting the electrode row is set to the on state (conducting state), that is, the selection state.

[0174] When the select transistor 333 is turned on, an analog signal indicating the measurement result output from the amplifier transistor 332 is output (supplied) to the AD conversion circuit 324 via the select transistor 333 and the vertical signal line 334.

[0175] The selection transistors 333 connected to each electrode 331 constituting the electrode row are connected to the vertical signal line 334. For example, the row selection circuit 323 sequentially selects each electrode row and only turns on the selection transistors 333 of the selected electrode row, so that the analog signals of the electrodes 331 constituting the selected electrode row are sequentially output to the AD conversion circuit 324.

[0176] The AD conversion circuit 324 performs AD conversion on the analog signal supplied from the amplifying transistor 332 via the vertical signal line 334 and the selection transistor 333, and supplies the digital data obtained as a result of the AD conversion to the ID allocation unit 325. The digital data supplied to the ID allocation unit 325 in this way is measurement data obtained by measuring the cell's activity potential using the electrode 331 (electrode array unit 322).

[0177] The ID allocation unit 325 is formed by digital circuitry including a memory and maintains (records) ID information that can uniquely identify the hole 261 containing the electrode array unit 322.

[0178] For example, the ID information held by the ID allocation unit 325 is identification information such as information indicating the hole number inherent in the hole 261 containing the electrode array unit 322.

[0179] When measurement data (digital data) is supplied from the AD conversion circuit 324, the ID allocation unit 325 allocates (adds) the held ID information to the measurement data and supplies the measurement data with the allocated ID information to the output circuit 326.

[0180] For example, ID allocation unit 325 assigns ID information to a frame of measurement data. At this time, for example, the ID information inherent to the aperture is stored (assigned) in the header data portion at the beginning of the measurement data of a frame. Therefore, it is possible to determine which of the measurement data output from the CMOS-MEA chip 292 (semiconductor substrate 321) is the data indicating the measurement result of which CMOS-MEA chip 292 (i.e., which aperture 261).

[0181] The output circuit 326 outputs the measurement data (digital data) supplied by the ID allocation unit 325 to the outside of the semiconductor substrate 321. More specifically, it outputs the measurement data that has been assigned ID information to the outside of the semiconductor substrate 321.

[0182] For example, such as Figure 11 As shown, the measurement data output from the output circuit 326 is supplied to the multiplexing IC 293 via wiring 294.

[0183] As described above, ID information is assigned (stored) in the header of the measurement data. Therefore, in the multiplexed measurement data output from the multiplexing IC 293, by referring to the ID information, it is possible to identify which data containing that ID information belongs to which aperture 261.

[0184] exist Figure 12 The following example illustrates an electrode array unit 322 formed on a semiconductor substrate 321 on which a CMOS-MEA chip 292 is formed. However, this configuration is not limited to this example, and two or more electrode array units 322 may be formed on the semiconductor substrate 321.

[0185] In this case, for example, one of the electrode array units 322 is disposed within one of the holes 261. Furthermore, when multiple electrode array units 322 are formed on the semiconductor substrate 321, a drive circuit, such as a row selection circuit 323, can be formed for each electrode array unit 322 to drive the electrode array unit 322, or a shared drive circuit, such as a row selection circuit 323, can be formed for multiple electrode array units 322. Additionally, circuitry that performs some signal processing on the measurement data can be provided in the front or back section of the ID allocation unit 325.

[0186] Figure 13 It shows Figure 11 The example configuration of the multiplexer IC 293 is shown.

[0187] exist Figure 13 In the example shown, the multiplexing IC 293 includes buffers 361-1 to 361-4 and selection circuit 362.

[0188] Measurement data (digital data) output from CMOS-MEA chip 292 is supplied to buffers 361-1 to 361-4 via wiring 294.

[0189] In the following text, when there is no need to specifically distinguish between buffers 361-1 to 361-4, buffers 361-1 to 361-4 are also referred to as buffer 361.

[0190] The measurement data, which includes ID information and is output from different CMOS-MEA chips 292, and more specifically from different output circuits 326, is supplied to each buffer 361.

[0191] The buffer 361 temporarily holds the measurement data supplied from the CMOS-MEA chip 292 (output circuit 326) and then supplies the measurement data to the selection circuit 362.

[0192] Specifically, in the following text, the measurement data supplied to buffers 361-1 to 361-4 are specifically referred to as measurement data DT1 to measurement data DT4.

[0193] Although for ease of understanding the accompanying diagram, the number of measurement data inputs to the multiplexing IC 293 is shown as 4, in fact... Figure 11 In the example, at least 30 measurement data points are actually input to the multiplexing IC 293.

[0194] The selection circuit 362 achieves multiplexing by sequentially selecting and outputting measurement data supplied from each of the multiple buffers 361.

[0195] That is, the selection circuit 362 multiplexes the supplied measurement data DT1 to measurement data DT4 and outputs a single measurement data formed by measurement data DT1 to measurement data DT4 to the connection terminal 295. Therefore, in this example, a multiplexing IC 293 in which four inputs obtain one output is implemented.

[0196] Selection circuit 362 includes switches 371-1 to 371-4.

[0197] For example, switches 371-1 to 371-4 are formed by transistors and are turned on or off according to a selection signal supplied from circuitry within the substrate 291. That is, switches 371-1 to 371-4 are turned on (conductive state) or off (non-conductive state) according to the selection signal.

[0198] When each of switches 371-1 to 371-4 is turned on, the respective measurement data DT1 to DT4 held in each of buffers 361-1 to 361-4 are output to the connection terminal 295 of the downstream section.

[0199] For example, in selection circuit 362, switches 371-1 to 371-4 are selected sequentially, and when one switch is in the ON state, the other three switches are in the OFF state. As a result, the measurement data of each hole 261 are output sequentially.

[0200] Note that in the following text, unless otherwise specified, switches 371-1 to 371-4 are also referred to as switch 371.

[0201] A specific example of multiplexing measurement data DT1 to DT4 will be provided.

[0202] For example, suppose that each of the measurement data DT1 to DT4 is simultaneously or approximately simultaneously input to buffers 361-1 to 361-4 at D Hz. In this case, new measurement data is input to each buffer 361 every 1 / D second.

[0203] For example, first, switch 371-1 is selected (turned on) by a selection signal, and the measurement data DT1 is held in buffer 361-1 at a frequency of 4 × D Hz. In this case, the output measurement data DT1 takes 1 / (4 × D) seconds.

[0204] Then, switches 371-2, 371-3, and 371-4 are selected sequentially using the selection signal in the same manner. As a result, measurement data DT2, measurement data DT3, and measurement data DT4 are output sequentially from each switch 371.

[0205] Similar to the case of measurement data DT1, each of the output measurement data DT2, measurement data DT3, and measurement data DT4 requires 1 / (4 × D) seconds.

[0206] By sequentially selecting switch 371 in this manner, a digital data is output from selection circuit 362 by sequentially arranging (combining) measurement data DT1 to measurement data DT4.

[0207] Since each of the measurement data DT1 to DT4 requires 1 / (4 × D) seconds to output, the total time required to output all measurement data DT1 to DT4 is 1 / D seconds. In other words, all measurement data can be output within 1 / D seconds. Therefore, the four measurement data can be multiplexed without causing delay, and the multiplexed data can be output as a single measurement data.

[0208] The configuration of the multiplexing IC 293 is not limited to... Figure 13 The configuration shown can be any configuration, as long as it can achieve the multiplexing function.

[0209] The above explains the above. Figure 11 The substrate 291 shown is an example of a semiconductor device 262 disposed at the bottom of a perforated plate 251.

[0210] However, the configuration of semiconductor device 262 is not limited to Figure 11 The example shown can be any other configuration. As an example, the configuration of semiconductor device 262 can include... Figure 14 The semiconductor substrate 401 shown is configured as follows. Figure 14 In, with Figure 11 Corresponding parts are given the same reference numerals, and their descriptions will be omitted as appropriate.

[0211] exist Figure 14In the example shown, multiple CMOS-MEAs, including CMOS-MEA 402, are formed on a semiconductor substrate 401 made of a silicon substrate or the like.

[0212] In this example, with Figure 11 Similarly, although 6 × 5 = 30 CMOS-MEAs are shown in the accompanying drawings for ease of understanding, the actual number of CMOS-MEAs corresponds to the number of holes 261 in the entire semiconductor device 262.

[0213] For example, CMOS-MEA 402 includes Figure 12 The electrode array unit 322, row selection circuit 323, AD conversion circuit 324, ID allocation unit 325 and output circuit 326 are shown, and the CMOS-MEA 402 is integrated into the semiconductor substrate 401.

[0214] Therefore, in this example, a semiconductor chip (silicon chip) is formed on a semiconductor substrate 401 on which a plurality of CMOS-MEAs, including CMOS-MEAs 402, are formed. In other words, a plurality of CMOS-MEAs are disposed in a semiconductor chip.

[0215] In the following text, the CMOS-MEA formed on the semiconductor substrate 401 is also referred to as CMOS-MEA 402, without making any special distinction between them.

[0216] exist Figure 11 In the example shown, multiple CMOS-MEA chips 292, as individual semiconductor chips, are mounted on a substrate 291. In contrast, in... Figure 14 In the example shown, each CMOS-MEA 402 is formed on a semiconductor substrate 401 that forms a semiconductor chip.

[0217] Multiple CMOS-MEAs 402 are formed in an array on a semiconductor substrate 401, and the output circuits 326 within the CMOS-MEAs 402, in particular, are connected to a multiplexer IC 293 via wiring 294 formed on the semiconductor substrate 401. The multiplexer IC 293 is connected to a connection terminal 295 via wiring on the semiconductor substrate 401.

[0218] Therefore, in this example, the measurement data output from the output circuits 326 of each CMOS-MEA 402 is input to the multiplexing IC 293 via wiring 294. The measurement data is then multiplexed in the multiplexing IC 293, and one measurement data obtained through multiplexing is output from the multiplexing IC 293 to the connection terminal 295.

[0219] The semiconductor device 262 includes at least one semiconductor substrate 401 as the semiconductor chip described above. That is, the semiconductor device 262 may be formed from one semiconductor substrate 401 or from two or more semiconductor substrates 401.

[0220] According to the above-described technology, even in the case of a multi-hole structure, the number of connection terminals (output terminals) can be reduced. That is, even in the case of a multi-hole structure, it is not necessary to increase the number of connection terminals.

[0221] This eliminates the need for circuitry, etc., in the measurement system setup to receive (acquire) a number of measurement data corresponding to a multiple of the number of holes in the perforated plate, and furthermore, the perforated plate can be installed at a mounting location determined by the physical dimensions with actual dimensions.

[0222] Furthermore, according to this technology, even when using perforated plates with different numbers of holes, the same number of connection terminals can be used to form a system for perforated plates with different numbers of holes and external devices connected to the perforated plates.

[0223] That is, in systems that use perforated plates with different numbers of holes depending on the application, the number of connection terminals on the system side can be shared, regardless of the type of holes (number of holes, arrangement of holes, etc.).

[0224] Note that the implementation scheme of this technology is not limited to the above implementation scheme, and can be modified within the scope of the key points of this technology.

[0225] In addition, this technology may also have the following configuration.

[0226] (1) A semiconductor device, comprising: MEA, comprising an electrode array unit formed by multiple electrodes, and configured to output one or more first digital data points obtained by measuring using the electrode array unit; and The first multiplexing unit is configured to multiplex N first digital data outputs from multiple MEAs and output M second digital data less than N. (2) The semiconductor device according to (1), wherein, The MEA is a CMOS-MEA. (3) The semiconductor device according to (1) or (2), wherein, The electrode array unit is disposed within the holes of the porous plate. (4) The semiconductor device according to (3), wherein, The MEA output is assigned first digital data that allows identification information to be recognized by the hole. (5) The semiconductor device according to any one of (1) to (4), wherein, Each of the plurality of MEAs is formed by a corresponding one of the plurality of semiconductor chips. (6) The semiconductor device according to (5), wherein, The plurality of semiconductor chips are configured on a substrate. (7) The semiconductor device according to (6), wherein, The semiconductor chip is connected to the substrate via solder bumps or wires. (8) The semiconductor device according to any one of (1) to (4), wherein, Multiple MEAs are disposed on a single semiconductor chip. (9) The semiconductor device according to any one of (1) to (8), wherein, The MEA includes multiple electrode array units, and Each of the electrode array units is disposed in a different hole of the porous plate. (10) The semiconductor device according to any one of (1) to (9) further includes: The second multiplexing unit is configured to multiplex P pieces of second digital data output from multiple first multiplexing units and output Q pieces of third digital data less than P. (11) A porous plate comprising a plurality of holes, the porous plate comprising: A semiconductor device is disposed at the bottom of the porous plate, wherein, The semiconductor device includes: MEA, comprising an electrode array unit formed by a plurality of electrodes disposed within the aperture, and configured to output one or more first digital data points obtained by measuring using the electrode array unit; and The multiplexing unit is configured to multiplex N first digital data outputs from multiple MEAs and output M second digital data less than N. List of reference numerals

[0227] 251 Perforated Plate 252 External devices 253 Data Acquisition System 261 holes 262 Semiconductor Devices 263 Connection Terminal 291 substrate 292 CMOS-MEA chip 293 Multiplexing IC 295 Connection Terminal 322 electrode array units 325 ID Allocation Unit 401 Semiconductor Substrate 402 CMOS-MEA.

Claims

1. A semiconductor device, comprising: MEA, which includes an electrode array unit formed by multiple electrodes, and is configured to output one or more first digital data obtained by measuring using the electrode array unit; and The first multiplexing unit is configured to multiplex N first digital data outputs from multiple MEAs and output M second digital data less than N.

2. The semiconductor device according to claim 1, wherein, The MEA is a CMOS-MEA.

3. The semiconductor device according to claim 1, wherein, The electrode array unit is disposed within the holes of the porous plate.

4. The semiconductor device according to claim 3, wherein, The MEA output is assigned first digital data that allows identification information to be recognized by the hole.

5. The semiconductor device according to claim 1, wherein, Each of the plurality of MEAs is formed by a corresponding one of the plurality of semiconductor chips.

6. The semiconductor device according to claim 5, wherein, The plurality of semiconductor chips are configured on a substrate.

7. The semiconductor device according to claim 6, wherein, The semiconductor chip is connected to the substrate via solder bumps or wires.

8. The semiconductor device according to claim 1, wherein, Multiple MEAs are disposed on a single semiconductor chip.

9. The semiconductor device according to claim 1, wherein, The MEA includes multiple electrode array units, and Each of the electrode array units is disposed in a different hole of the porous plate.

10. The semiconductor device of claim 1, further comprising: The second multiplexing unit is configured to multiplex P pieces of second digital data output from multiple first multiplexing units and output Q pieces of third digital data less than P.

11. A porous plate comprising a plurality of holes, the porous plate comprising: A semiconductor device is disposed at the bottom of the porous plate, wherein, The semiconductor device includes: MEA, comprising an electrode array unit formed by a plurality of electrodes disposed within the aperture, and configured to output one or more first digital data points obtained by measuring using the electrode array unit; and The multiplexing unit is configured to multiplex N first digital data outputs from multiple MEAs and output M second digital data less than N.

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