Stacked quantum chip supporting structure
By setting cutoff layers and limiting pillars between chips, the problem of uneven force distribution in the multi-layer stacking process of three-dimensional superconducting quantum chips is solved, achieving chip gap consistency and stability, and improving chip performance and the safety of external circuits.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- YANGTZE DELTA IND INNOVATION CENT OF QUANTUM SCI & TECH
- Filing Date
- 2024-11-22
- Publication Date
- 2026-05-22
AI Technical Summary
In existing technologies, during the multi-layer stacking process of three-dimensional superconducting quantum chips, uneven stress on the interconnect metals leads to inconsistencies between the chip gaps and design requirements, resulting in compression deformation and tilting. This affects the quantum bit frequency and coupling capacitance, and the spillover of interconnect metals also affects the external circuit structure.
A cutoff layer is set between the chips, and multiple sets of limiting posts are set on the cutoff layer. The chips are aligned and bonded to form a stacked structure by the limiting posts. The limiting posts are made of superconducting metal or low-loss junction dielectric material to support and limit the chips, ensure uniform force, prevent interconnect metal overflow, and precisely control the chip gap.
This achieves uniform stress distribution during multi-layer chip stacking, avoids deformation and tilting, ensures consistent chip spacing, improves the performance and stability of quantum chips, and prevents interconnect metals from affecting external circuits.
Smart Images
Figure CN122072845A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of superconducting quantum computing chip technology, and in particular to a stacked quantum chip support structure. Background Technology
[0002] In the development of superconducting quantum computing, as the number of qubits increases, quantum chips are gradually transitioning from two-dimensional planar structures to three-dimensional structures, further improving chip integration. However, because the interconnect metals need to be superconducting materials, and because high-melting-point metals can cause annealing of the Josephson junction during thermal bonding, thus affecting qubit performance, soft metals (such as indium) are more commonly used as interconnect metals in the field of superconducting quantum chips to achieve flip-chip interconnection.
[0003] With the development of three-dimensional structure technology, flip-chip bonding equipment is needed to bond two chips together. Flip-chip bonding technology uses a bonding material under certain pressure and temperature to press two chips together to form a single chip. Currently, metal plating often uses thermal evaporation processes, resulting in uneven metal spheres. During interconnection, uneven stress can lead to chip gaps that do not meet design requirements, and can easily cause significant compression deformation and tilting at a certain angle. As the number of qubits increases, when chips need to be stacked in multiple layers, each bonding step is affected by multiple flip-chip bonding processes. This leads to a gradual increase in gap deviation and self-capacitance deviation, which in turn changes the qubit frequency, the coupling capacitance between the XY line and the qubit, and the capacitance between the readout resonant cavity and the qubit. This affects the readout conditions and the Purcell decay limit applied to the qubit, ultimately impacting chip performance. Furthermore, the indium metal, due to heat leakage, can also affect the surrounding circuit structure. Summary of the Invention
[0004] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0005] The purpose of this invention is to address the shortcomings of existing technologies by proposing a stacked quantum chip support structure.
[0006] To achieve the above objectives, the present invention adopts the following technical solution: a stacked quantum chip support structure, comprising:
[0007] First chip and second chip;
[0008] A cutoff layer is provided between the first chip and the second chip. The cutoff layer is provided with multiple sets of limiting posts. The first chip and one or more second chips are aligned and bonded through the limiting posts to form a stacked structure.
[0009] In some embodiments, the cutoff layer is provided with one or more layers.
[0010] In some embodiments, the limiting post is disposed on the cutoff layer of the first chip or the second chip.
[0011] In some embodiments, the limiting post is disposed on the cutoff layer of the first chip and the second chip.
[0012] In some embodiments, the limiting post is a solid and / or hollow column.
[0013] In some embodiments, a group of limiting posts may be surrounded by a ring of multiple sets of limiting posts of the same and / or different shapes.
[0014] In some embodiments, the limiting post includes a first support portion, and the first support portion is provided with multiple sets around the first chip and / or the second chip.
[0015] In some embodiments, the limiting post further includes a second support portion disposed at the center of the first chip and / or the second chip.
[0016] In some embodiments, one set of the limiting posts is provided with a covering cavity, and the outer contour of the other set of limiting posts is fitted with the inner contour of the covering cavity.
[0017] In some embodiments, the limiting post having a covering cavity covers the outside of the limiting post without a covering cavity, and the limiting post is bonded to form a collar.
[0018] In some embodiments, the limiting posts on the two stop layers are made of different materials.
[0019] The present invention has the following beneficial effects:
[0020] 1. This invention sets multiple sets of limiting posts at the corresponding positions of one or more cut-off layers between chips, which can better balance stress without affecting chip wiring, ensuring that the chips are subjected to more uniform stress and will not deform during flip-chip soldering or stacking design. Furthermore, the size of the chip gap can be determined by controlling the height of the limiting posts, ensuring that the gap is consistent with the design. This effectively solves the problems of tilting and collapse after multi-layer chip stacking, and realizes the stacking design and processing of two or more layers of chips.
[0021] 2. The present invention employs a structure in which two sets of limiting posts are interlocked and connected through a covering cavity to form a collar, which further improves the support stability, effectively prevents the overflow of interconnect metal from affecting the external circuit structure, and precisely controls the gap distance between chips. Attached Figure Description
[0022] Figure 1 A schematic diagram of the stacked quantum chip support structure provided in the embodiments of this application. Figure 1 ;
[0023] Figure 2 A schematic diagram of a dual-layer chip design scheme provided in an embodiment of this application. Figure 2 ;
[0024] Figure 3 A schematic diagram of a dual-layer chip design scheme provided in an embodiment of this application. Figure 1 ;
[0025] Figure 4 A schematic diagram of a dual-layer chip design scheme provided in an embodiment of this application. Figure 2 ;
[0026] Figure 5 This is a schematic diagram of a multilayer chip design scheme provided in an embodiment of this application;
[0027] Figure 6 This is a structural schematic diagram of a support column collar design provided in one embodiment of this application.
[0028] Legend:
[0029] 1. First chip; 2. Second chip; 3. Cut-off layer; 31. Limiting post; 311. First support part; 312. Second support part. Detailed Implementation
[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0031] This application provides a stacked quantum chip support structure, solving the problem in existing technologies where, during flip-chip bonding or multilayer processes, the use of relatively soft interconnect metals leads to uneven stress during bonding, causing chip tilting and repeated compression, resulting in uncontrollable gaps and significant deviations between the designed and fabricated gaps of the coupling capacitors, ultimately leading to poor chip performance. This application addresses this issue by setting limiting posts between the chips, providing support and limiting for the chip structure, thus enabling the design and fabrication of stacked two- or multi-layer chips.
[0032] Please refer to the following examples for details:
[0033] See Figures 1-6 As shown, this invention provides an embodiment of a stacked quantum chip support structure, specifically comprising: a first chip 1 and a second chip 2. A cutoff layer 3 is disposed between the first chip 1 and the second chip 2; the cutoff layer 3 is provided with multiple sets of vapor-deposited limiting posts 31, allowing the first chip 1 and one or more second chips 2 to be aligned and bonded through the limiting posts 31 to form a stacked structure, thereby providing support and limiting for the chip structure, ultimately realizing the stacked design and fabrication of two or more layers of chips.
[0034] It is understandable that the cutoff layer 3 can be optionally set to one or more layers, and the specific number of layers is selected according to the processing parameters such as the spacing during chip stacking.
[0035] Furthermore, the limiting post 31 is arranged around the cutoff layer 3 of the first chip 1 and / or the second chip 2. For example, the limiting post 31 can be set at the center and the four edges of the first chip 1 or the second chip 2, thereby avoiding the wiring area of the chip, ensuring that the circuit structure of the chip is not affected, and adapting different stacking structures and stacking spacings according to different stacking schemes when performing flip-chip bonding or multi-layer stacking.
[0036] Meanwhile, the limiting posts 31 in different positions and in different numbers can divide the large wiring area on the end face of the first chip 1 and the second chip 2 into multiple small wiring areas. Different wiring areas can improve the reliability and stability of the chip as needed. By rationally planning the double-row pin settings on each edge of the wiring layer and connecting these pins to the control line port array and read cavity port array of the core area of the wiring layer, automated and efficient wiring can be achieved, thereby improving the overall performance and reliability of the quantum chip.
[0037] Furthermore, the limiting post 31 can be a solid or hollow post, which can be flexibly selected for different stacking design schemes;
[0038] In addition, multiple sets of the same and / or different shapes of limit posts can be arranged around a set of limit posts 31, which can be flexibly selected and adapted according to the routing scheme of different chips.
[0039] Specifically, the limiting posts can be prisms, cylinders, or frustums, and the limiting posts at different positions can be the same or different shapes, thus adapting to regular / irregular chip layouts.
[0040] Furthermore, the limiting post 31 includes a first support portion 311, and the first support portion 311 is provided with multiple sets around the first chip 1 and / or the second chip 2, which can be flexibly arranged on the superposition surface between the corresponding two sets of chips according to the superposition scheme.
[0041] Alternatively, the limiting post 31 may further include a second support portion 312, and the second support portion 312 is disposed at the center of the first chip 1 and / or the second chip 2.
[0042] For example, the first support portion 311 can be symmetrically arranged at equal intervals in areas such as the four periphery of the first chip 1 or the second chip 2, and a plurality of second support portions 312 are symmetrically arranged relative to the center point of the first support portion 311. By setting limiting posts 31 at the center, periphery and edges of the support area, the stress between the chips can be better balanced, ensuring that the chips are subjected to more uniform stress during flip-chip bonding or stacking design, and preventing deformation and tilting. Furthermore, the size of the chip gap can be determined by controlling the height of the limiting posts 31, ensuring that the gap is consistent with the gap of the coupling capacitor design.
[0043] Furthermore, when the cutoff layer 3 has multiple layers, the limiting posts 31 on two adjacent sets of cutoff layers 3 can be bonded to each other, and the gap distance between the chips during bonding can be determined according to the height of the limiting posts 31.
[0044] For example, when two cut-off layers 3 are provided between the first chip 1 and the second chip 2, one set of limiting posts 31 has a covering cavity at its end, and the outer contour of the other set of limiting posts 31 that are bonded to it fits the inner contour of the covering cavity. The limiting posts 31 with covering cavities and the limiting posts 31 without covering cavities are made of different materials. In this way, when the chips are bonded, the limiting posts 31 with covering cavities can cover the outside of the other set of limiting posts 31. By bonding, a collar is formed, which can effectively prevent the interconnect metal from overflowing and affecting the external circuit structure, and accurately control the gap distance between the chips.
[0045] Current metal plating processes often employ thermal evaporation, resulting in unevenly formed metal spheres. During interconnection, this uneven stress can lead to inconsistent chip gaps compared to design requirements, and can also cause significant compression deformation and tilting. To overcome these technical problems, refer to... Figure 2As shown, in one specific embodiment, limiting posts 31 are deposited on the surface of the superconducting quantum chip to be bonded, which is fabricated by wafer fabrication. The limiting posts 31 are located at the center and periphery of the superconducting quantum chip's cutoff layer 3. The limiting posts 31 are made of superconducting metals or superconducting materials with low-loss junction dielectrics, such as hard-conducting metals (Sn, Al, and Au, etc.) or hard compounds (SiO2, TiN, and SiN, etc.). These materials possess high mechanical strength and stability, effectively supporting and fixing the structure of the superconducting quantum chip. Their good thermal conductivity helps manage and disperse the heat generated in the quantum chip, while their high oxidation resistance and chemical stability enable long-term stable operation in the superconducting quantum computing environment, improving the chip's stability and performance.
[0046] For example, the limiting post 31 is formed by evaporating material after photolithography patterning. The shape of the limiting post 31 can be a square post, a circular post, or other regular or irregular shapes. Its specific shape depends on the chip wiring space and actual processing requirements.
[0047] See Figure 3 As shown, in another specific embodiment, for a dual-layer chip design, when the height range of a single-layer limiting post 31 can meet the gap height requirement, the first chip 1 can be without a limiting post 31, while the second chip 2 can be equipped with a limiting post 31. The first chip 1 and the second chip 2 are aligned and bonded together to form a stacked structure by flip-chip bonding. The gap height is determined by the height of one layer of limiting post 31. The limiting post 31 can play a supporting and limiting role, ensuring that the chip gap distance and the gap of the coupling capacitor design are consistent.
[0048] See Figure 4 As shown, in another specific embodiment, for a dual-layer chip design, when the height range of a single-layer limiting post 31 cannot meet the gap height requirement, limiting posts 31 can be set on the first chip 1 and the second chip 2. The first chip 1 and the second chip 2 are aligned and bonded together to form a stacked structure by flip-chip bonding. The gap height is determined by the height of the two limiting posts 31. The limiting posts 31 can play a supporting and limiting role, ensuring that the chip gap distance and the gap of the coupling capacitor design are consistent.
[0049] See Figure 5As shown, in another specific embodiment, for a multi-layer chip stacking design, the first chip 1 does not have a limiting post 31, while the second chip 2 does. The first chip 1 and the second chip 2 are aligned and bonded together using a flip-chip method to form a stacked structure. Subsequently, multiple sets of second chips 2 are sequentially bonded to the stacked structure. During this process, the first chip 1 and the second chip 2 bonded first at the bottom are continuously subjected to pressure and compression. After alignment and bonding through the limiting post 31, their upper and lower support posts can be well aligned, and the gap distance can be determined based on the height of the limiting post 31. For chips with three or more layers, the stacked structure, after multiple bonding operations, is continuously compressed. The limiting component effectively prevents tilting and collapse after multiple stacking operations, thus preventing damage to the chips.
[0050] See Figure 6 As shown, in another specific embodiment, the limiting post 31 of the first chip 1 is provided with a covering cavity, the inner contour of which fits the limiting post 31 of the second chip 2; and the limiting post 31 of the first chip 1 can be a superconducting metal or a superconducting material with low-loss junction dielectric (Sn, Al, Au, SiO2, TiN, and SiN, etc.), while the limiting post 31 of the second chip 2 can be an existing interconnect metal (In, etc.). In this way, during bonding, the top limiting post 31 can completely cover the outside of the bottom limiting post 31 to form a collar design, which can effectively prevent the interconnect metal from overflowing and affecting the external circuit structure, and precisely control the gap distance between the chips.
[0051] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A stacked quantum chip support structure, characterized in that, include: First chip (1) and second chip (2); A cutoff layer (3) is provided between the first chip (1) and the second chip (2). The cutoff layer (3) is provided with multiple sets of limiting posts (31). The first chip (1) and one or more second chips (2) are aligned and bonded through the limiting posts (31) to form a stacked structure.
2. The stacked quantum chip support structure according to claim 1, characterized in that, The cutoff layer (3) has one or more layers.
3. The stacked quantum chip support structure according to claim 2, characterized in that, The limiting post (31) is disposed on the cutoff layer (3) of the first chip (1) or the second chip (2).
4. The stacked quantum chip support structure according to claim 2, characterized in that, The limiting post (31) is disposed on the cutoff layer (3) of the first chip (1) and the second chip (2).
5. A stacked quantum chip support structure according to claim 4, characterized in that, The limiting post (31) is a solid and / or hollow post.
6. A stacked quantum chip support structure according to claim 4, characterized in that, A group of limiting posts (31) may be surrounded by multiple groups of limiting posts (31) of the same and / or different shapes.
7. A stacked quantum chip support structure according to claim 4, characterized in that, The limiting post (31) includes a first support part (311), and the first support part (311) is provided with multiple sets around the first chip (1) and / or the second chip.
8. A stacked quantum chip support structure according to claim 4, characterized in that, The limiting post (31) further includes a second support part (312), which is disposed at the center of the first chip (1) and / or the second chip.
9. A stacked quantum chip support structure according to claim 4, characterized in that, One set of the limiting posts (31) is provided with a covering cavity, and the outer contour of the other set of limiting posts (31) fits the inner contour of the covering cavity.
10. A stacked quantum chip support structure according to claim 9, characterized in that, The limiting post (31) with a covering cavity covers the outside of the limiting post (31) without a covering cavity, and the limiting post (31) is bonded to form a collar.
11. A stacked quantum chip support structure according to claim 1, characterized in that, The limiting posts (31) on the two cutoff layers (3) are made of different materials.