Repairing circuit, memory and method for repairing memory

Abstract

Embodiments of the present application provide a repair circuit, a memory and a repair method of the memory. The repair circuit comprises a fuse array, a failure matching circuit and a failure processing circuit. The fuse array comprises a normal fuse array, a failure fuse array and a redundant fuse array. The fuses in the normal fuse array have first address information and are configured to store second address information. The fuses in the failure fuse array are configured to store fourth address information. The fuses in the redundant fuse array are configured to store sixth address information. The failure matching circuit is connected to the failure fuse array and is configured to compare the first address information with the fourth address information and output a matching flag signal according to the comparison result. The failure processing circuit is configured to receive the second address information, the sixth address information and the matching flag signal and select to output the second address information or the sixth address information based on the matching flag signal.

Description

Technical Field

[0001] This application relates to the field of memory, and in particular to a repair circuit and repair method for memory. Background Technology

[0002] During the manufacturing process of large-scale integrated circuits, due to physical limitations and process defects, some defective cells may appear on the chip, such as damaged memory cells or interconnects. Fuse redundancy technology allows these defective cells to be replaced with pre-installed spare cells, thereby improving the chip yield.

[0003] However, fuses themselves also have a chance of error. For example, when burning a fuse, there is a risk of burning failure or incorrect burning. An erroneous fuse can lead to incorrect redundant address mapping and a loss of yield. Summary of the Invention

[0004] This application provides a method for repairing a circuit, a memory, and a memory, which at least helps to solve the problem of redundancy technology errors caused by fuse failures.

[0005] According to some embodiments of this application, one aspect of this application provides a repair circuit, including a fuse array, a failure matching circuit, and a failure handling circuit. The fuse array includes a conventional fuse array, a failed fuse array, and a redundant fuse array. The failed fuse array is configured to store address information of failed fuses in the conventional fuse array. The fuses in the conventional fuse array have first address information and are configured to store second address information. The fuses in the failed fuse array have third address information and are configured to store fourth address information. The fuses in the redundant fuse array have fifth address information and are configured to store sixth address information. The failure matching circuit, connected to the failed fuse array, is configured to compare the first address information with the fourth address information and output a matching flag signal based on the comparison result. The failure handling circuit, connected to the conventional fuse array, the redundant fuse array, and the failure matching circuit, is configured to receive the second address information, the sixth address information, and the matching flag signal, and select to output either the second address information or the sixth address information based on the matching flag signal.

[0006] According to some embodiments of this application, another aspect of this application also provides a memory, the memory including the aforementioned repair circuit, the memory further including a memory array, and the second address information being the address information of a failed memory cell in the memory array.

[0007] According to some embodiments of this application, another aspect of this application provides a memory repair method, including: broadcasting a fuse array to read out the address information of the failed fuses stored in the failed fuse array and the address information of the fuses in the conventional fuse array; comparing the read out address information of the failed fuses with the address information of the fuses in the conventional fuse array and outputting a matching result; and, based on the matching result, selecting to output the address information stored in the fuses in the conventional fuse array or the address information stored in the replaced fuses in the redundant fuse array.

[0008] The repair circuit and method provided in this application's embodiments store the address information of failed fuses by setting some fuses in the fuse array, setting some fuses as spare fuses, and matching the read fuse addresses with the addresses of faulty fuses during use. This allows the identification of faulty fuses, and the replacement of faulty fuses with spare fuses. This enables the memory to correctly utilize redundant resources for memory cell repair, avoiding redundant address mapping errors and yield losses. Furthermore, by employing staggered storage and alternating read / write methods, more time margin is provided for the fuse array sensitive amplifier circuit while maintaining normal fuse data reading without affecting broadcast timing. Attached Figure Description

[0009] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0010] Figure 1 This is a schematic diagram of a repair circuit provided in an embodiment of the present disclosure;

[0011] Figure 2 This is a schematic diagram of the structure of a counting circuit provided in an embodiment of the present disclosure;

[0012] Figure 3 A schematic diagram of the register circuit of a failure matching circuit provided in an embodiment of this disclosure;

[0013] Figure 4 A schematic diagram of the structure of a comparison circuit for a failure matching circuit provided in an embodiment of this disclosure;

[0014] Figure 5 A schematic diagram illustrating an encoding method for fourth and seventh address information provided in an embodiment of this disclosure;

[0015] Figure 6 This is a schematic diagram of a memory provided in an embodiment of the present disclosure. Detailed Implementation

[0016] Hereinafter, exemplary embodiments of the invention will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily practice the invention. As will be appreciated by those skilled in the art, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. For example, the exemplary embodiments provided herein are thought to be implementable by combining them, in whole or in part. Specifically, an element described in a particular exemplary embodiment, even if not described in another exemplary embodiment, can be understood as a description relating to another exemplary embodiment, unless a contrary or contradictory description is provided therein.

[0017] Throughout this specification, when any part is referred to as being “connected” to another part, it includes cases where any part and another part are “indirectly connected” to each other due to the presence of another part between them, as well as cases where any part and another part are “directly connected” to each other. For example, it should be understood that when an element is referred to as being “connected” or “attached” or “on another element” to another element, it may be directly connected or attached to or on that other element, or there may be an intermediate element present. Conversely, when an element is referred to as being “directly connected” or “directly attached” to another element, or referred to as being “in contact” or “in contact” with another element, there is no intermediate element at the point of contact.

[0018] Furthermore, "electrical connection" conceptually includes both physical connection and physical disconnection. It is understood that when an element is referred to using terms such as "first" and "second," the element is not limited in this respect. These terms may be used only to distinguish the element from other elements and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

[0019] The memory has storage rows and columns composed of storage cells, forming a storage array. For memories equipped with redundancy technology, redundant storage rows and columns are also provided to replace faulty storage rows and / or columns, thus repairing the memory. During product testing, the address information of the faulty storage row and / or column is written to the fuse array. Upon power-up, this address information is broadcast to a local redundancy register. Then, during read / write operations, the address of the faulty storage row / column is remapped to the address of the redundant storage row / column, replacing the storage resource.

[0020] In the aforementioned technology, the fuse array is used to store the address information of damaged (i.e., faulty, failed) memory rows / columns in the memory array. This allows redundant resources (i.e., redundant memory cells) to replace the damaged memory cells, enabling the memory to function normally. However, fuses in the fuse array can also fail. For example, a fuse that should be programmed may not be successfully programmed (unblown), or a fuse that should not be programmed may be mistakenly programmed (misblown), resulting in unsuccessful mapping of redundant resources and a decrease in memory yield.

[0021] The repair circuit and method provided in this application's embodiments store the address information of failed fuses by setting some fuses in the fuse array, setting some fuses as spare fuses, and matching the read fuse addresses with the addresses of faulty fuses during use. This allows the identification of faulty fuses, and the replacement of faulty fuses with spare fuses. This enables the memory to correctly utilize redundant resources for memory cell repair, avoiding redundant address mapping errors and yield losses. Furthermore, by employing staggered storage and alternating read / write methods, more time margin is provided for the fuse array sensitive amplifier circuit while maintaining normal fuse data reading without affecting broadcast timing.

[0022] Figure 1 This is a schematic diagram of a repair circuit provided in an embodiment of this application. Figure 1A repair circuit 10 is shown, including a fuse array 100, a failure matching circuit 200, and a failure handling circuit 300. The fuse array 100 includes a conventional fuse array 110, a failed fuse array 120, and a redundant fuse array 130. The failed fuse array 120 is configured to store address information of failed fuses in the conventional fuse array 110. The redundant fuse array 130 is used to redundantly replace failed fuses in the conventional fuse array 110. The fuses in the conventional fuse array 110 have first address information. The fuses in array 110 are configured to store second address information, the fuses in the failed fuse array 120 have third address information, and the fuses in the failed fuse array 120 are configured to store fourth address information; the fuses in the redundant fuse array 130 have fifth address information, and the fuses in the redundant fuse array 130 are configured to store sixth address information; the failure matching circuit 200, connected to the failed fuse array 120, is configured to compare the first address information with the fourth address information, and output a matching flag signal Fuse match based on the comparison result; the failure processing circuit 300, connected to the conventional fuse array 110, the redundant fuse array 130, and the failure matching circuit 200, is configured to receive the second address information, the sixth address information, and the matching flag signal Fuse match, and select to output either the second address information or the sixth address information based on the matching flag signal Fuse match.

[0023] Specifically, the fuse array 100 includes a conventional fuse array 110, a failover fuse array 120, and a redundant fuse array 130. The conventional fuse array 110 stores the row or column address information of failed memory cells in the memory array. The failover fuse array 120 stores the address information of failed fuses in the conventional fuse array 110. The redundant fuse array replaces the failed fuse addresses in the conventional fuse array 110 with the correct fuse addresses. A failed fuse is, for example, a fuse that failed to successfully write the row or column address information of a failed memory cell, or a fuse that incorrectly wrote the row or column address information of a failed memory cell. The address replacement in the redundant fuse array 130 includes, for example, replacing the failed memory cell with redundant row or column address information of a memory cell that is the same as the redundant row or column address information stored at the failed fuse address, or replacing the failed memory cell with redundant row or column address information of a memory cell that is different from the redundant row or column address information stored at the failed fuse address. The former can repair defects in fuse addresses, while the latter can simultaneously repair defects in fuse addresses and redundant resources in memory cells. Specifically, the fuses in the conventional fuse array 110 have first address information, which is the address information of the fuses in the conventional fuse array 110 within the fuse array 100, i.e., the address information of the fuses themselves in the conventional fuse array 110. The fuses in the conventional fuse array 110 are used to store second address information, such as the row address information or column address information of a failed memory cell in the memory array. The fuses in the failed fuse array 120 have third address information, which is the address information of the fuses in the failed fuse array 120 within the fuse array 100. The address information in 0 refers to the address information of the fuses themselves in the failed fuse array 120. The fuses in the failed fuse array 120 are configured to store fourth address information, which is the address information related to the failed fuses in the conventional fuse array 110. The fuses in the redundant fuse array 130 have fifth address information, which is the address information of the fuses themselves in the redundant fuse array 130. The fuses in the redundant fuse array 130 are configured to store sixth address information, which is the address information related to the spare fuses used to replace the failed fuses. The conventional fuse array 110 is configured to receive the first address information and, based on the received first address information, output the corresponding second address information. The failed fuse array 120 is configured to receive the third address information and, based on the received third address information, output the corresponding fourth address information. The redundant fuse array 130 is configured to receive the fifth address information and, based on the received fifth address information, output the corresponding sixth address information.

[0024] In some embodiments, the second address information and the sixth address information can be the same address information. That is, the redundant resources of the same storage unit are used to repair the failed storage unit. In other words, the failed storage unit is replaced with the redundant row or column address information of the storage unit that is the same as the redundant row or column address information stored at the failed fuse address. Thus, when the fuse address fails, the storage unit can be repaired by simply replacing the fuse address without modifying the redundant storage unit, saving storage unit area. In other embodiments, the second address information and the sixth address information can be different address information. That is, the redundant resources of different storage units are used to repair the failed storage unit. In other words, the failed storage unit is replaced with the redundant row or column address information of the storage unit that is different from the redundant row or column address information stored at the failed fuse address. Thus, by using other fuse addresses and the redundant resources of other storage units, the defects of both the fuse address and the redundant resources of the storage unit can be repaired simultaneously.

[0025] In some embodiments, the fuse array can be composed of fuses, such as metal fuses or laser fuses; the fuse array can also be composed of antifuses, such as semiconductor antifuses. This application uses antifuses to form the fuse array as an example. When an antifuse is not programmed, it is in a high-resistance state and can be used to represent the data "0"; after programming, it is in a low-resistance state and can be used to represent the data "1". One antifuse unit can be used to store 1 bit of data. For an antifuse group composed of multiple antifuses, multiple bits of data can be stored together. For example, for the row address of a storage unit, which is typically multiple bits of data (e.g., 17 bits, <17:0>), an antifuse group composed of 17 antifuse units can be used to store the row address. For example, the second address information can be 17 bits of data. It should be understood that fuses can also form the fuse array of this application. For ease of explanation, the terms antifuse and fuse will not be distinguished below.

[0026] In some embodiments, the fuse array has multiple fuse subarrays, such as 32 or 64. Some of these fuse subarrays are used to form a conventional fuse array 110, some to form a failed fuse array 120, and some to form a redundant fuse array 130. For example, for a fuse array containing 64 fuse subarrays, one or two fuse subarrays can be used to form the failed fuse array 120, and two or four fuse subarrays can be used to form the redundant fuse array 130. The remaining fuse subarrays are used to store address information related to failed memory cells, or address information related to failed memory cells and test mode information. It should be understood that the above figures are for illustrative purposes only and do not constitute a limitation of this application.

[0027] Furthermore, the repair circuit 10 also includes a failure matching circuit 200, which is connected to the failure fuse array 120 and is used to compare the first address information with the fourth address information, and output a matching flag signal Fuse match based on the comparison result.

[0028] The repair circuit 10 also includes a failure handling circuit 300, which is connected to the conventional fuse array 110, the redundant fuse array 130 and the failure matching circuit 200. It is configured to receive second address information, sixth address information and matching flag signal Fusematch, and select to output the second address information or the sixth address information based on the matching flag signal Fusematch.

[0029] Specifically, when the comparison result shows that the first address information is the same as the fourth address information, the matching flag signal Fuse match output by the failure matching circuit 200 is at the first level (e.g., high level 1), and the failure processing circuit 300 selects to output the sixth address information based on the first level of the matching flag signal Fuse match; when the comparison result shows that the first address information is different from the fourth address information, the matching flag signal Fuse match output by the failure matching circuit 200 is at the second level (e.g., low level 0), and the failure processing circuit 300 selects the second address information as the output signal FuseOut based on the second level of the matching flag signal Fuse match. Figure 1 Taking a second address information containing 17 bits as an example, the output signal is FuseOut<17:0>).

[0030] In some embodiments, the failure handling circuit 300 can be a two-to-one multiplexer, with the two data input terminals of the multiplexer receiving second address information and sixth address information respectively, and the selection input terminal of the multiplexer receiving a match flag signal Fuse match.

[0031] However, this application is not limited thereto. It should be understood that other circuits capable of performing selection functions, such as combinational logic circuits, may also be used.

[0032] exist Figure 1 In this embodiment, the matching flag signal Fuse match is a single bit of data. Figure 2 In this embodiment, the matching flag signal Fuse match is a two-bit data, including a first matching flag signal (fuse match high) and a second matching flag information (fuse match low). This application does not limit this; the matching flag signal Fuse match can be a one-bit or multi-bit data, depending on the amount of data stored in the second address information.

[0033] Therefore, the repair circuit provided in this application provides a method to store the address information of failed fuses by setting some fuses in the fuse array, setting some fuses as spare fuses, and matching the read fuse address with the erroneous fuse address during use. This allows the circuit to identify the erroneous fuse and replace it with a spare fuse. This enables the memory to correctly use redundant resources to repair the memory cells, thereby avoiding redundant address mapping errors and yield loss.

[0034] In some embodiments, the failure matching circuit 200 is also connected to the redundant fuse array 130, and the failure matching circuit 200 also outputs redundancy selection information RedSeg based on the comparison result. Figure 1 Taking the redundancy selection information containing 2 bits as an example, i.e. RedSeg<1:0>); the redundant fuse array 130 is configured to receive the redundancy selection information RedSeg and select to output the sixth address information based on the redundancy selection information.

[0035] Therefore, based on the comparison results of the failure matching circuit, when the redundant fuse array 130 has a large capacity and many addresses, the corresponding redundant fuse address can be selected in the redundant fuse array 130 through the redundancy selection information RedSeg. This enables flexible selection and correspondence of redundant fuse array addresses, thereby achieving more flexible selection of redundant resources and repair of failed fuse addresses.

[0036] In some embodiments, the repair circuit 10 further includes a counting circuit 400. The repair circuit 10 broadcasts the count value output by the counting circuit to the conventional fuse array 110 and the failed fuse array 120; wherein, the counting circuit 400 is connected to the conventional fuse array 110, the failed fuse array 120, the redundant fuse array 130, and the failure matching circuit 200, and the counting circuit is used to provide first address information and third address information for the currently broadcast fuses. The conventional fuse array 110 is configured to receive the first address information and output corresponding second address information based on the received first address information; the failed fuse array 120 is configured to receive the third address information and output corresponding fourth address information based on the received third address information; the redundant fuse array 130 is configured to receive the count information and redundancy selection information RedSeg output by the counting circuit, and select and output sixth address information based on the received information.

[0037] During broadcasting, the fuses in the fuse array are scanned. A counting circuit is used to provide fuse addresses for the scan. Figure 2An example of a counting circuit 400 is provided, comprising three sub-counting circuits 410, 420, and 430, but this number does not constitute a limitation of this application. The counting circuit may also include fewer than three sub-counting circuits or more than three sub-counting circuits, depending on the size of the fuse array, the scanning rules, and the address hierarchy of the fuse array.

[0038] Taking the three-level address of the fuse array as an example: row address, column address, and segment address, the corresponding counting circuit includes three counting sub-circuits, which are used to count the row address, column address, and segment address respectively, and scan the row address, column address, and segment address according to the count value, so as to read out the address information stored in the failed fuse array and the conventional fuse array in sequence.

[0039] Figure 2 In the circuit, the counting circuit includes a first counting sub-circuit 410, a second counting sub-circuit 420, and a third counting sub-circuit 430; the clock Clk is used as the trigger signal for the counting circuit, and the counting value of the counting circuit is incremented by 1 each time the clock Clk jumps. Figure 2 The counting circuit is divided into three stages. When the counting value of the previous stage is full, the counting of the next stage will begin. Figure 2 In the example, the segment address Seg is used as the lowest level counting circuit, and scanning starts from the segment address Seg. When all segment addresses Seg are scanned (that is, for 32-bit segment addresses Seg[31:0], the count value reaches 31), the column address Yadd count value is incremented by 1. When all column addresses Yadd are scanned (that is, for 32-bit column addresses Yadd[31:0], the count value reaches 31), the row address Xadd count value is incremented by 1. In this way, all fuse addresses in the fuse array are scanned (that is, for 32-bit row addresses Xadd[31:0], the count value reaches 31), and all information of the fuse array is read out. In other embodiments, the row address can also be used as the counting object of the lowest level counting circuit 410, scanning starts from the row address, then scans the column address (or segment address), and then scans the segment address (or column address). In some other embodiments, the column address can be used as the counting object of the lowest-level counting circuit 410, scanning starting from the column address, then scanning the row address (or segment address), and then scanning the segment address (or row address). This application does not impose a mandatory requirement on the scanning order. The following will refer to... Figure 2 Take the scanning order of segment address-column address-row address from low to high (from first to last) as an example.

[0040] In some embodiments, the first counting sub-circuit 410, the second counting sub-circuit 420, and the third counting sub-circuit 430 can all be constructed from counters. The counters can output count values ​​before and / or after decoding. Figure 2Seg[31:0], Yadd[31:0], and Xadd[31:0] shown are the decoded decimal count values, which are used in circuits (such as...). Figure 1 , 2 In the circuit, it can also be an undecoded 5-bit or 4-bit binary count value. For example, Seg[31:0] (count value from 0 to 31) can also be Seg<5:0> in the circuit, Yadd[31:0] (count value from 0 to 31) can also be Yadd<4:0> in the circuit, and Xadd[31:0] (count value from 0 to 31) can also be Xadd<4:0> in the circuit. The failure matching circuit 200 is used to compare the binary address with the address information stored in the failure fuse array. Furthermore, since their actual meanings are equivalent, this paper does not make a special distinction between the decoded value and the undecoded value.

[0041] For an address Xadd, Yadd, Seg (e.g., Xadd = 0, Yadd = 0, Seg = 0), a set (multi-bit) of fuse data can be read. This set of fuse data is also an address information, such as the address information for storing a row / column. Each time the broadcast scans an address, the entirety of that address (e.g., Xadd = 0, Yadd = 0, Seg = 0) can be the aforementioned first and third address information. The fuse array then sends out a set of fuse data, namely the aforementioned second, fourth, and sixth address information. Figure 1 and Figure 2 In the embodiment, the second address information Fuse2[16:0] is 17 bits of data, the fourth address information Fuse4[16:0] is 17 bits of data, and the sixth address information Fuse6[16:0] is 17 bits of data.

[0042] By grouping addresses, errors can be detected and stored on a single-address basis (e.g., segment addresses as an example below), thereby reducing the number of fuse bits required to store erroneous addresses. In some embodiments, the broadcast scans one address at a time, and a portion of that address (e.g., Xadd=0, Yadd=0, Seg=0) can be the aforementioned first address information, third address information, and fifth address information. For example, only the segment address (Seg address) can be used as the first address information. For instance, when scanning in the order of segment address-column address-row address, only the segment address information of the broadcast to the regular fuse array can be compared and processed with the segment address information in the failed fuse array. When the row address Xadd and column address Yadd are the same, or when the row address Xadd and column address Yadd have a fixed correspondence, the row address Xadd and column address Yadd can be omitted, and only the segment address (Seg address) is used for processing. For example, the redundant fuse array 130 is configured to receive redundancy selection information RedSeg and determine segment address information Seg based on the redundancy selection information RedSeg. Combined with the information of the currently broadcast row address Xadd and column address Yadd output by the received counting circuit 400, the sixth address information is selected for output.

[0043] In some embodiments, the faulty fuse array and the conventional fuse array can be encoded with segment addresses separately. For example, the segment addresses of the faulty fuse array can be encoded from 0 to 1, while the segment addresses of the conventional fuse array can be re-encoded from 0 to 57. This allows the faulty fuse array and the conventional fuse array to broadcast and compare data immediately. However, the row address Xadd and column address Yadd of the faulty fuse array and the conventional fuse array can correspond to each other. Thus, the fault matching circuit 200 connects the faulty fuse array 120 and the counting circuit 400, comparing the segment address information in the binary count value (i.e., the first address information) output by the counting circuit 400 with the segment address information in the data stored in the faulty fuse array 120 (i.e., the fourth address information).

[0044] With the above settings, during broadcasting, the failed fuse array 120 and the conventional fuse array 110 can be scanned sequentially to obtain their own address information and stored address information (i.e., the first to fourth address information). This allows for the comparison of the first and fourth address information. The redundancy selection information RedSeg is output through the failure matching circuit 200 to obtain partial address information (such as segment address information) of the redundant fuse array 130. Combined with the address information of the current broadcast output by the counting circuit, the corresponding fifth address information can be obtained, thereby selecting and outputting the corresponding sixth address information.

[0045] In some embodiments, the row address Xadd and column address Yadd of the failed fuse array and the conventional fuse array can be stored in a staggered manner and fixedly repaired to save the storage area occupied by the address Xadd and column address Yadd information, and match the normal broadcast timing. Specifically, for example, in the first batch of broadcasts (referred to as CLK0), all segment address information Seg[31:0] of Xadd=0 and Yadd=0 is first sent to the conventional fuse array 110 and the failed fuse array 120. The failed fuse array 120 reads out the segment address information of the fuses that failed when Xadd=0 and Yadd=0 stored in it, and sends it as the fourth address information to the failure matching circuit 200 for storage. The failure matching circuit 200 writes the fourth address information of this time into the register. In the next batch of broadcasts (referred to as CLK1), all segment address information Seg[31:0] for Xadd=0 and Yadd=1 is sent to the regular fuse array 110, the failed fuse array 120, and the failure matching circuit 200. The failed fuse array 120 reads out the segment address information of the fuses that failed when Xadd=0 and Yadd=1, and sends it again as the fourth address information to the failure matching circuit 200. The failure matching circuit 200 writes the fourth address information of the current broadcast into its register for storage. At this time, the failure matching circuit 200 stores the failed fuse segment address information written at CLK0 and receives the segment address information broadcast at CLK1. The failure matching circuit 200 compares the failed fuse segment address information (Xadd=0 and Yadd=0) written at CLK0 with the segment address information (Xadd=0 and Yadd=1) broadcast at CLK1 and outputs the comparison result. Simultaneously, the failure matching circuit 200 writes the failed fuse segment address information at CLK1, to be compared during the next batch broadcast (CLK2, Xadd=0 and Yadd=2). Thus, the failure matching circuit reads and stores the failed segment address information of Xadd=0 and Yadd=0 at CLK0, and compares the stored Xadd=0 and Yadd=0 failed segment address information with the broadcast segment address information of Xadd=0 and Yadd=1 at CLK1, forming a misalignment correction with a fixed mapping relationship between Xadd and Yadd. Therefore, there is no need to store row address Xadd and column address Yadd information, saving significant storage space and allowing more failed fuses to be stored using the same storage space. Furthermore, since the failure matching circuit 200 reads and writes simultaneously, and compares the segment address information written during the previous broadcast, it does not affect the broadcast timing at all.

[0046] In this scheme, the fuse address information in the conventional fuse array read at CLK0 has not been repaired by the failed fuse array. Therefore, the fuse address information in the conventional fuse array can be directly output at CLK0. Alternatively, no data can be stored in the conventional fuse array (Xadd=0 and Yadd=0) read at CLK0, thereby avoiding the incorrect mapping of redundant resources.

[0047] In some embodiments, due to misalignment repair, when CLK0 is read, the segment address information stored in the failed fuse array 120 with Xadd=0 and Yadd=0 can be that of the failed fuses with Xadd=0 and Yadd=1 in the conventional fuse array 120.

[0048] In this embodiment, such as Figure 3 As shown, the failure matching circuit 200 includes a register circuit 210 connected to the failed fuse array 120. The register circuit 210 is configured to receive and store the fourth address information Fuse4<16:0>. The register circuit 210 includes a first register circuit 211 and a second register circuit 212. When one of the first register circuit 211 and the second register circuit 212 reads data, the other register circuit writes data.

[0049] Because two sets of register circuits are used, and one set of register circuits reads data while the other writes data, misaligned data storage and retrieval can be performed, thereby correcting misaligned addresses of failed fuses.

[0050] refer to Figure 3 The failure matching circuit 200 also includes a first OR logic circuit 213. The two input terminals of the first OR logic circuit 213 are connected to the output terminals of the first register circuit 211 and the second register circuit 212. The first OR logic circuit 213 outputs the data output by the first register circuit 211 or the data output by the first register circuit 212 as the seventh address information Fuse7<16:0>.

[0051] refer to Figure 3 The first register circuit 211 includes a first flip-flop DFF1 and a first AND gate AND1. The data receiving terminal of the first flip-flop DFF1 receives the fourth address information Fuse4<16:0>, and the clock receiving terminal of the first flip-flop DFF1 receives the first write enable signal Write enable. <0> The output of the first flip-flop DFF1 is connected to the first input of the first AND gate AND1, and the second input of the first AND gate AND1 receives the first read enable signal. <0> ;

[0052] The second register 212 includes a second flip-flop DFF2 and a second AND gate AND2. The data receiving terminal of the second flip-flop DFF2 receives the fourth address information Fuse4<16:0>, and the clock receiving terminal of the second flip-flop DFF2 receives the second write enable signal Write enable. <1> The output of the second flip-flop DFF2 is connected to the first input of the second AND gate AND2, and the second input of the second AND gate AND2 receives the second read enable signal. <1> ;

[0053] The first read enable signal is Read enable. <0> With the second read enable signal Read enable <1> Not valid at the same time, the first write enable signal is Write enable. <0> The second write enable signal <1> They are not valid at the same time.

[0054] It should be understood that triggers and latches function similarly, and the triggers in this application can also be latches.

[0055] In some embodiments, the first read enable signal is shown. <0> With the second read enable signal Readenable <1> The signal is inverted; the first write enable signal is `Write enable`. <0> The second write enable signal <1> It is obtained from the inverted signal.

[0056] refer to Figure 3 The failure matching circuit 200 also includes a generation circuit for a first read enable signal, a second read enable signal, a first write enable signal, and a second write enable signal. The first read enable signal is... <0> With the second read enable signal Read enable <1> The generation circuit can be a third flip-flop DFF3. The third flip-flop DFF3 is a counter whose inverting output is connected to the data input. The clock input of the third flip-flop DFF3 receives the count completion signal Cnt flag. When a batch of broadcasts is completed (i.e., CLK0 ends, meaning all segment addresses under the same row address Xadd and column address Yadd have been read), the count completion signal Cnt flag is pulled high (generating a pulse signal), causing the count value of the third flip-flop DFF3 to increment by 1, and the first read enable signal Read enable is activated. <0> With the second read enable signal Read enable <1> One of them transitions to a low level (0), while the other transitions to a high level (1).

[0057] First write enable signal: Write enable <0> The second write enable signal <1> The generation circuit can be a third AND gate (AND3) and a fourth AND gate (AND4). For example... Figure 3One input of the third AND gate AND3 receives the first read enable signal. <0> The other input receives the segment address information of the currently read failed fuse subarray. Figure 3 China-Israel Seg <0> Example), for the currently read failed fuse subarray, its segment address information Seg <0> If the signal is high, then the corresponding output of the third AND gate, AND3, will be the second write enable signal (Write enable). <1> Correspondingly, one input of the fourth AND gate, AND4, receives the second read enable signal. <1> The other input receives the segment address information of the currently read failed fuse subarray. Figure 3 China-Israel Seg <0> Example), for the currently read failed fuse subarray, its segment address information Seg <0> If the signal is high, then the corresponding first write enable signal (Write enable) will be output from the fourth AND gate (AND4). <0> .

[0058] In some embodiments, for a limited array of failed fuse subarrays, such as when the failed fuse array has only one failed fuse subarray, the processing logic for the segment address information in the third AND gate AND3 and the fourth AND gate AND4 can also be removed. That is, the first write enable signal Write enable <0> This can be the second read enable signal. <1> After a delay, the second write enable signal is obtained directly. <1> This can be the first read enable signal. <0> The delay is applied directly. In other embodiments, the delay can be skipped, and the first write enable signal Writeenable can be used directly. <0> As the second read enable signal <1> Use the second write enable signal directly. <1> As the first read enable signal <0> .

[0059] In other embodiments, for cases with multiple failed fuse subarrays, each failed fuse subarray has a corresponding first write enable signal (Write enable) corresponding to different segment address signals (Seg). <0> Generation circuit, second write enable signal (Write enable) <1> The circuit includes a generation circuit, a first register circuit 211, a second register circuit 212, and a first OR logic circuit 213.

[0060] Therefore, through the above circuit design, register circuit 210 can achieve read-write alternation. When the second register circuit 212 writes data to CLK1, the first register circuit 211 can read data from CLK0; when the first register circuit 211 writes data to CLK2, the second register circuit 212 can read data from CLK1. Furthermore, by using identical register circuits, read enable signal generation circuits, and write enable signal generation circuits, data path delay matching under different clock cycles is achieved. And, by employing the first OR logic circuit 213, the first register circuit 211 and the second register circuit 212 can alternately output data.

[0061] Figure 4 This is a schematic diagram of the comparison circuit structure of a failure matching circuit provided in an embodiment of this application. (Reference) Figure 4 The failure matching circuit 200 also includes a comparison circuit 220, which is connected to the output of the first OR logic circuit 210 and receives the seventh address information Fuse7<16:0> output by the OR logic circuit. The comparison circuit is configured to compare the seventh address information Fuse7<16:0> with the first address information currently broadcast. The first address information can be obtained from the count value Seg<4:0> currently broadcast.

[0062] Figure 5 A schematic diagram illustrating the encoding methods for fourth and seventh address information is provided. It should be understood that the fourth and seventh address information carry the same information, differing only in timing. The following explanation will focus on the fourth address information. Figure 5 As shown, the first row represents the position of each data bit, and the second row represents the encoding meaning of each data bit. The fourth address information includes at least two fourth sub-address information (Resource A Fail Fuse Seg<4:0> and Resource B Fail Fuse Seg<4:0>). The failure matching circuit 200 compares the first address information with the fourth address information. Specifically, the failure matching circuit 200 compares the first address information (the count value output by the counting circuit, such as the segment address count value Seg<4:0> output by the first counting circuit 410) with one fourth sub-address information (Resource A Fail Fuse Seg<4:0> or Resource B Fail Fuse Seg<4:0>).

[0063] Therefore, considering that the address bits required to store a failed fuse may be 5 bits (e.g., Figure 5 As shown in FA0-FA4, or FA8-FA12), the fourth address information may be 17 bits (e.g., Figure 5As shown in FA0-FA16, the fourth address information can store the address information of multiple failed fuses (multiple fourth sub-address information), thus maximizing the utilization of the bits in the fourth address information. Furthermore, the fourth address information can store only part of the address information of the failed fuse, such as only storing the segment address information of the failed fuse, without storing the row address information and column address information. In this way, by using misaligned Xadd and Yadd addresses for repair, an appropriate number of segment addresses can be selected from all segment addresses to repair the remaining fuses. This allows for a trade-off between the increased area caused by repair and the repair capability, maintaining a large repair capability with a smaller area increase, maximizing the cost-effectiveness of the area loss.

[0064] In other embodiments, the multiple fourth sub-address information stored in the fourth address information can also be the row address Xadd or column address Yadd of the failed fuse. Furthermore, the fourth address information is not limited to including two sub-address information; it can also include three or four sub-address information, flexibly selected based on the number of bits in the sub-address information.

[0065] Continue to refer to Figure 5 In some embodiments, the fourth address information further includes a first flag bit (EN AB), which is used to indicate whether the fourth address information is valid. Figure 5 When the fourth address information contains multiple fourth sub-address information, if all of the multiple fourth sub-address information is invalid (e.g., all are damaged, or no faulty fuse address information is stored), it indicates that no valid repair information is stored in the fourth address information, and the first flag bit is in the first state (e.g., 1); if at least one of the multiple fourth sub-address information is valid, it indicates that valid repair information is stored in the fourth address information, and the first flag bit is in the second state (e.g., 0).

[0066] The fourth address information also includes at least two second flag bits (such as...). Figure 5 In the EN A and EN B section, the number of second flag bits is the same as the number of fourth sub-address information bits. Each second flag bit corresponds one-to-one with each fourth sub-address information bit. The second flag bit is used to indicate whether the corresponding fourth sub-address information is valid. If the second flag bit is in the first state (e.g., 1), it means that the corresponding fourth sub-address information has stored information and has stored valid address information; if the second flag bit is in the second state (e.g., 0), it means that the corresponding fourth sub-address information has not stored information, or it has stored information, but the fourth sub-address information is corrupted.

[0067] Therefore, by setting the first and second flag bits, the availability of the fourth address information and the fourth sub-address information can be determined by detecting the flag bits, thereby avoiding incorrect mapping of redundant fuse resources.

[0068] Continue to refer to Figure 5 In some embodiments, the fourth address information also includes a third flag bit (e.g., Figure 5 In the RedSeg A and RedSeg B arrays, the number of third flag bits is the same as the number of fourth sub-address information bits. Each third flag bit corresponds one-to-one with each fourth sub-address information bit. The third flag bit is used to indicate the segment address of the redundant resource corresponding to the corresponding fourth sub-address information, and is used to select the corresponding fuse in the redundant fuse array 130. For embodiments where the third flag bit contains two bits of data, such as RedSeg A containing two bits of data ResSeg<1:0>, then one fuse sub-array can be selected from the four redundant fuse sub-arrays.

[0069] refer to Figure 4 When the seventh address information includes two seventh sub-address information, the seventh sub-address information is compared one by one with the first address information. At this time, the comparison circuit 220 performs two address comparisons, one for the seventh sub-address information (Fuse7). <0> -Fuse7 <4> The information is compared with the first address information Seg<4:0>, and simultaneously the second flag bit (Fuse7) of the seventh sub-address information is used. <7> ) and the first flag (Fuse7) <16> Determine if the seventh sub-address information is valid (if invalid, disable); simultaneously, another seventh sub-address information (Fuse7) is checked. <8> -Fuse7 <12> Another set of comparisons is also performed with the first address information Seg<4:0>, and simultaneously with the second flag bit (Fuse7) of this seventh sub-address information. <15> ) and the first flag (Fuse7) <16> The system determines whether the seventh sub-address information is valid (if invalid, it is disabled). If the currently read first address information matches the seventh sub-address information, and the second and first flag bits of the seventh sub-address information indicate that the seventh sub-address information is valid, the corresponding intermediate match flag signal (match 0 or match 1) is output. Specifically, if the currently read first address information matches the first seventh sub-address information, and the seventh sub-address information is valid, the corresponding intermediate match flag signal (match 0) is in the first state (e.g., high level 1); if the currently read first address information matches the second seventh sub-address information, and the seventh sub-address information is valid, the corresponding intermediate match flag signal (match 1) is in the first state (e.g., high level 1). If there is no match or the seventh sub-address information is invalid, the corresponding intermediate match flag signal (match 0 or match 1) is in the second state (e.g., low level 0).

[0070] Specifically, such as Figure 4In the circuit shown, each bit of the seventh sub-address information and each bit of the first address information are subjected to an XOR operation, and the result is then processed by a NAND gate. The result of the NAND gate processing is then subjected to a NOR operation with the second flag bit and the first flag bit corresponding to the seventh sub-address information to obtain the intermediate match flag signal (match 0 or match 1).

[0071] Then, the intermediate match flag signal (match 0 or match 1) is passed through an OR gate and directly output as the match flag signal Fuse match. Furthermore, the intermediate match flag signal (match 0 or match 1) is also ANDed with the third flag bit of the corresponding seventh sub-address information to select the corresponding redundant resource address. Specifically, the first seventh sub-address information (Fuse7...) <0> -Fuse7 <4> The intermediate match flag signal (match 0) is ANDed with its corresponding third flag bit (Fuse7<6:5>) to select the corresponding redundant resource segment address; the second seventh sub-address information (Fuse7) is used. <8> -Fuse7 <12> The intermediate match flag signal (match 1) is ANDed with its corresponding third flag bit (Fuse7<14:13>) to select the corresponding redundant resource segment address. The redundant fuse array 130 receives the redundant resource segment address RedSeg<1:0> output by the comparator circuit 220 and the currently broadcast row address Xadd and column address Yadd to obtain the fifth fuse address information, and obtains the sixth fuse address information Fuse<16:0> through the fifth fuse address information.

[0072] Therefore, the repair circuit of this application stores the address information of failed fuses by setting some fuses in the fuse array, sets some fuses as spare fuses, and matches the read fuse address with the erroneous fuse address during use. This allows the identification of the erroneous fuse and replacement of it with a spare fuse. This enables the memory to correctly utilize redundant resources for memory cell repair, avoiding redundant address mapping errors and yield loss. Furthermore, because the above circuit implements misaligned storage and alternating read / write operations, it provides more time margin for the fuse array sensitive amplifier circuit while maintaining normal fuse data reading without affecting broadcast timing.

[0073] In an embodiment where the failure handling circuit 300 includes a selector, when the first address information matches the fourth address information and all flag bits indicate that the fourth address information is valid, the matching flag signal Fuse match is in a first state (e.g., 1). Based on this first state, the failure handling circuit 300 selects the sixth address information Fuse6<16:0> for output. At this time, the memory performs a secondary address mapping based on the sixth address information Fuse6<16:0> output by the repair circuit, and either re-uses the redundant resource for repair or replaces it with another redundant resource. When the first address information does not match the fourth address information, the matching flag signal Fuse match is in a second state (e.g., 0). Based on this second state, the failure handling circuit 300 selects the second address information Fuse2<16:0> for output.

[0074] Therefore, the failure matching circuit 200 can store the fourth address information read from the failed fuse array. During broadcast scanning of the fuse array, the fourth address information read in advance from the failed fuse array is stored beforehand, and then compared with the first address information generated from the subsequent broadcast scanning of the regular fuse array. This allows for a comparison of the address information of the failed and regular fuse arrays in a single broadcast. Furthermore, by setting at least two sets of failed address comparisons in the comparison circuit, the capacity of the failed fuse array can be fully utilized. The failure matching circuit 200 also includes processing logic for the first and second flag bits. When the fourth address information is invalid, its use can be avoided, improving the correct utilization rate of redundant resources.

[0075] Figure 6 A schematic diagram illustrating a memory 1 provided in an embodiment of this application is shown. For example... Figure 6 The memory 1 includes the repair circuit 10 provided in any of the foregoing embodiments. The memory also includes a memory array 20, which may consist of multiple memory rows and columns, each composed of multiple memory cells. A memory cell may, for example, consist of a capacitor and a transistor. Accordingly, the memory 1 is a dynamic random access memory (DRAM). In other embodiments, the memory may also be, for example, NAND flash memory, ferroelectric memory, or other similar memory. This application does not limit the type of memory.

[0076] The second address information is the address information of the failed memory cell in the memory array 20. For example, the second address information can be the row address information or column address information of the failed memory cell in the memory array 20.

[0077] In some embodiments, this application also provides a method for repairing a memory, comprising:

[0078] S1. Broadcast the fuse array to read the address information of the failed fuses stored in the failed fuse array and the address information of the fuses in the normal fuse array;

[0079] S2. Compare the read-out faulty fuse address information with the address information of fuses in the conventional fuse array, and output the matching result;

[0080] S3. Based on the matching result, select to output the address information of the fuses stored in the regular fuse array, or the address information of the fuses stored in the redundant fuse array.

[0081] The repair method can employ the repair circuit 10 provided in any of the foregoing embodiments.

[0082] Specifically, step S1 can be broadcasting to the fuse array 100 according to, as follows: Figure 2 The counting circuit 400 shown scans the fuse array 100 sequentially, reading the failed fuse address information (i.e., the aforementioned fourth address information) stored in the failed fuse array 120. Figure 1 and 2 The address information of the fuses in the conventional fuse array 110 (also known as the first address information mentioned above, which is given by the counting circuit 400) is stored in the Fuse4<16:0> array and the address information of the fuses in the conventional fuse array 110. The failed fuse array 120 is used to store the address information of the failed fuses in the conventional fuse array 110.

[0083] Step S2 can be based on the appendix Figure 1 , 3 The failure matching circuit shown in Figure 4 reads the address information of the failed fuse (i.e., the aforementioned fourth address information, attached). Figure 1 and 2 The address information of the fuses in the conventional fuse array (i.e., the first address information mentioned above, given by the counting circuit 400) is compared with the address information of the fuses in the conventional fuse array, and the matching result (i.e., Fusematch) is output.

[0084] Step S3 can be based on the appendix Figure 1As shown, based on the matching result, the circuit selects to output either the address information stored in the conventional fuse array or the address information stored in the replacement fuse in the redundant fuse array. If the matching result indicates that the currently read first address information matches the fourth address information, meaning the currently read fuse in the conventional fuse array is a failed fuse, the failure handling circuit outputs the address information stored in the replacement fuse in the redundant fuse array, thereby repairing the failed fuse and improving yield. If the matching result indicates that the currently read first address information does not match the fourth address information, meaning the currently read fuse in the conventional fuse array is a normal, undamaged fuse, the failure handling circuit normally outputs the address for normal repair of the storage array.

[0085] Therefore, this method can identify faulty fuses by storing and matching faulty fuse addresses, and by matching read fuse addresses with faulty fuse addresses. By replacing the faulty fuse resource with a redundant one, the memory can repair the faulty fuse address, thus avoiding redundant address mapping errors and yield loss. Furthermore, by storing only partial address information of the faulty fuse and employing staggered storage and alternating read / write methods, more time margin is provided for the fuse array sensitive amplifier circuit while minimizing area overhead and ensuring normal fuse data readout without affecting broadcast timing.

[0086] In some embodiments, step S2 compares the read-out faulty fuse address information with the address information of fuses in a conventional fuse array, specifically:

[0087] The address information of the failed fuse read in the i-th time is compared with the address information of the fuses in the conventional fuse array read in the (i+1)-th time; where i is a positive integer greater than 0 and less than the number of addresses in the conventional fuse array.

[0088] Specifically, the i-th read includes, for example, when row address Xadd = 0 and column address Yadd = 0, the address of the failed fuse segment read once or multiple times; the (i+1)-th read includes, for example, when row address Xadd = 0 and column address Yadd = 1, the address of the failed fuse segment read once or multiple times; and the failed fuse segment addresses read in these two reads are compared. That is, misaligned storage and fixed repair of row address Xadd and column address Yadd are used. Xadd = 0 and Yadd = 1 are used to repair Xadd = 0 and Yadd = 0, thereby saving storage space occupied by address Xadd and column address Yadd information and matching the normal broadcast timing.

[0089] In some embodiments of the repair method that can employ the aforementioned repair circuit embodiments, the memory 1 includes a failure matching circuit 200, and the failure matching circuit includes a register circuit 210; the repair method specifically includes:

[0090] During the i-th read, the address information of the failed fuse read in the i-th read is stored in the register circuit 210;

[0091] During the (i+1)th read, the address information of the fuses in the conventional fuse array read in the (i+1)th read is compared with the address information of the failed fuse read in the (i)th read. At the same time, the address information of the failed fuse read in the (i+1)th read is stored in the register circuit 210.

[0092] During the (i+2)th read, the address information of the fuses in the conventional fuse array read in the (i+2)th read is compared with the address information of the failed fuses read in the (i+1)th read. At the same time, the address information of the failed fuses read in the (i+2)th read is stored in the register circuit.

[0093] Repeat the above steps until all addresses of the conventional fuse array have been read.

[0094] Specifically, for example, in the first batch of broadcasts (abbreviated as CLK0, i.e. i=1), all segment address information Seg[31:0] for Xadd=0 and Yadd=0 is sent sequentially to the conventional fuse array 110 and the failed fuse array 120. The failed fuse array 120 reads out the segment address information of the fuses that failed when Xadd=0 and Yadd=0 stored in it, and sends it as the fourth address information to the failure matching circuit 200 for storage. The failure matching circuit 200 writes the fourth address information of this time into the register circuit 210. In the next batch of broadcasts (referred to as CLK1, i.e., i=2), all segment address information Seg[31:0] for Xadd=0 and Yadd=1 is sequentially sent to the regular fuse array 110, the failed fuse array 120, and the failure matching circuit 200. The failed fuse array 120 reads out the segment address information of the fuses that failed when Xadd=0 and Yadd=1, and sends it again as the fourth address information to the failure matching circuit 200. The failure matching circuit 200 writes the fourth address information of the current broadcast into the register circuit 210 for storage. At this time, the failure matching circuit 200 stores the failed fuse segment address information written at CLK0 and receives the segment address information broadcast at CLK1. The failure matching circuit 200 compares the failed fuse segment address information (Xadd=0 and Yadd=0) written at CLK0 with the segment address information (Xadd=0 and Yadd=1) broadcast at CLK1 and outputs the comparison result. Simultaneously, the failure matching circuit 200 writes the failed fuse segment address information at CLK1, to be compared during the next batch broadcast (CLK2, Xadd=0 and Yadd=2). Thus, the failure matching circuit reads and stores the failed segment address information of Xadd=0 and Yadd=0 at CLK0, and compares the stored Xadd=0 and Yadd=0 failed segment address information with the broadcast segment address information of Xadd=0 and Yadd=1 at CLK1, forming a misalignment correction with a fixed mapping relationship between Xadd and Yadd. Therefore, there is no need to store row address Xadd and column address Yadd information, saving significant storage space and allowing more failed fuses to be stored using the same storage space. Furthermore, since the failure matching circuit 200 reads and writes simultaneously, and compares the segment address information written during the previous broadcast, it does not affect the broadcast timing at all.

[0095] At CLK2, i.e., i=3, all segment address information Seg[31:0] for Xadd=0 and Yadd=2 is sequentially sent to the conventional fuse array 110, the failed fuse array 120, and the failure matching circuit 200. The failed fuse array 120 reads the segment address information of the fuses that failed when Xadd=0 and Yadd=2, and sends it again as the fourth address information to the failure matching circuit 200. The failure matching circuit 200 writes the currently broadcast fourth address information into the register circuit 210 for storage. At this time, the failure matching circuit 200 stores the failed fuse segment address information written at CLK1 and receives the segment address information broadcast at CLK2. The failure matching circuit 200 compares the failed fuse segment address information (Xadd=0 and Yadd=1) written at CLK1 with the segment address information (Xadd=0 and Yadd=2) broadcast at CLK2 and outputs the comparison result. Simultaneously, the failure matching circuit 200 writes the failed fuse segment address information at CLK2 into the register circuit 210 for comparison during the next batch broadcast (CLK3, Xadd=0 and Yadd=3). After reading all segment addresses of a row address Xadd and column address Yadd, the next Yadd address is switched, and the above steps are repeated until all addresses of the conventional fuse array have been read.

[0096] In this scheme, the fuse address information in the conventional fuse array read at CLK0 has not been repaired by the failed fuse array. Therefore, the fuse address information in the conventional fuse array can be directly output at CLK0. Alternatively, no data can be stored in the conventional fuse array (Xadd=0 and Yadd=0) read at CLK0, thereby avoiding the incorrect mapping of redundant resources.

[0097] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A repair circuit, characterized in that, This includes fuse arrays, failure matching circuits, and failure handling circuits, among which... The fuse array includes a conventional fuse array, a failed fuse array, and a redundant fuse array. The failed fuse array is configured to store address information of failed fuses in the conventional fuse array. Specifically, the fuses in the conventional fuse array have first address information, and the fuses in the conventional fuse array are configured to store second address information. The fuses in the failed fuse array have third address information, and the fuses in the failed fuse array are configured to store fourth address information. The fuses in the redundant fuse array have fifth address information, and the fuses in the redundant fuse array are configured to store sixth address information. The failure matching circuit, connected to the failure fuse array, is configured to compare the first address information with the fourth address information and output a matching flag signal based on the comparison result. The failure handling circuit, connected to the conventional fuse array, the redundant fuse array, and the failure matching circuit, is configured to receive the second address information, the sixth address information, and the matching flag signal, and select to output the second address information or the sixth address information based on the matching flag signal.

2. The repair circuit according to claim 1, characterized in that, The failure matching circuit is also connected to the redundant fuse array, and based on the comparison result, the failure matching circuit outputs redundancy selection information. The redundant fuse array is configured to receive the redundancy selection information and, based on the redundancy selection information, select and output the sixth address information.

3. The repair circuit according to claim 2, characterized in that, The repair circuit also includes a counting circuit, which broadcasts the count value output by the counting circuit to the conventional fuse array and the failed fuse array. The counting circuit is connected to the conventional fuse array, the failed fuse array, the redundant fuse array and the failure matching circuit. The counting circuit is used to provide the first address information and the third address information of the currently broadcast fuse. The conventional fuse array is configured to receive the first address information and output the corresponding second address information based on the received first address information. The failed fuse array is configured to receive the third address information and output the corresponding fourth address information based on the received third address information. The redundant fuse array is configured to receive the counting information and redundancy selection information output by the counting circuit and select and output the sixth address information based on the received information.

4. The repair circuit according to any one of claims 1-3, characterized in that, The failure matching circuit includes a register circuit connected to the failed fuse array, and the register circuit is configured to receive and store the fourth address information; The register circuit includes a first register circuit and a second register circuit; when one register circuit reads data, the other register circuit writes data.

5. The repair circuit according to claim 4, characterized in that, The failure matching circuit further includes a first OR logic circuit, which is connected to the output terminals of the first register circuit and the second register circuit. The first OR logic circuit outputs the data output by the first register circuit or the data output by the first register circuit as the seventh address information. The failure matching circuit further includes a comparison circuit connected to the first OR logic circuit, and the comparison circuit is configured to compare the seventh address information with the first address information.

6. The repair circuit according to claim 4, characterized in that, The first register circuit includes a first flip-flop and a first AND gate. The data receiving terminal of the first flip-flop receives the fourth address information, the clock receiving terminal of the first flip-flop receives a first write enable signal, the output terminal of the first flip-flop is connected to the first input terminal of the first AND gate, and the second input terminal of the first AND gate receives a first read enable signal. The second register includes a second flip-flop and a second AND gate. The data receiving end of the second flip-flop receives the fourth address information, the clock receiving end of the second flip-flop receives the second write enable signal, the output end of the second flip-flop is connected to the first input end of the second AND gate, and the second input end of the second AND gate receives the second read enable signal. Specifically, the first read enable signal and the second read enable signal are not valid at the same time, and the first write enable signal and the second write enable signal are not valid at the same time.

7. A memory, characterized in that, The memory includes a repair circuit as described in any one of claims 1-6, and the memory further includes a storage array, wherein the second address information is the address information of a failed storage cell in the storage array.

8. A method for repairing a memory, comprising: Broadcast the fuse array to read the address information of the failed fuses stored in the failed fuse array and the address information of the fuses in the normal fuse array; The read address information of the failed fuse is compared with the address information of the fuses in the conventional fuse array, and the matching result is output. Based on the matching results, the output can be either the address information stored in the conventional fuse array or the address information stored in the replacement fuse in the redundant fuse array.

9. The repair method according to claim 8, characterized in that, The step of comparing the read address information of the failed fuse with the address information of the fuses in the conventional fuse array specifically involves: The address information of the failed fuse read in the i-th time is compared with the address information of the fuses in the conventional fuse array read in the (i+1)-th time; where i is a positive integer greater than 0 and less than the number of addresses in the conventional fuse array.

10. The repair method according to claim 9, characterized in that, The memory includes a failure matching circuit, which includes a register circuit; the repair method specifically includes: During the i-th read, the address information of the failed fuse read in the i-th read is stored in the register circuit; During the (i+1)th read, the address information of the fuses in the conventional fuse array read in the (i+1)th read is compared with the address information of the failed fuse read in the ith read. At the same time, the address information of the failed fuse read in the (i+1)th read is stored in the register circuit. During the (i+2)th read, the address information of the fuses in the conventional fuse array read in the (i+2)th read is compared with the address information of the failed fuse read in the (i+1)th read. At the same time, the address information of the failed fuse read in the (i+2)th read is stored in the register circuit. Repeat the above operation until all the address numbers of the conventional fuse array have been read.

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