Repair circuit, memory and memory repair method

Abstract

The embodiment of the invention provides a repairing circuit, a memory and a repairing method of the memory, the repairing circuit comprises a fuse array, a failure matching circuit and a failure processing circuit, the fuse array comprises a conventional fuse array and a failure fuse array, and the failure fuse array is configured to store address information of failure fuses in the conventional fuse array; wherein fuses in the conventional fuse array have first address information, the fuses in the conventional fuse array are configured to store second address information, and the fuses in the failure fuse array are configured to store fourth address information; the failure matching circuit is connected with the failure fuse array and is configured to compare the first address information with the fourth address information and output a matching mark signal according to a comparison result; and the failure processing circuit is connected with the failure matching circuit and the conventional fuse array, and is configured to receive the matching flag signal and the second address information, and selectively output the second address information or invalid address information based on the matching flag signal.

Description

Technical Field

[0001] This application relates to the field of memory, and in particular to a repair circuit and repair method for memory. Background Technology

[0002] During the manufacturing process of large-scale integrated circuits, due to physical limitations and process defects, some defective cells may appear on the chip, such as damaged memory cells or interconnects. Fuse redundancy technology allows these defective cells to be replaced with pre-installed spare cells, thereby improving the chip yield.

[0003] However, fuses themselves also have a chance of error. For example, when burning a fuse, there is a risk of burning failure or incorrect burning. An erroneous fuse can lead to incorrect redundant address mapping and a loss of yield. Summary of the Invention

[0004] This application provides a method for repairing a circuit, a memory, and a memory, which at least helps to solve the problem of redundancy technology errors caused by fuse failures.

[0005] According to some embodiments of this application, one aspect of this application provides a repair circuit, including a fuse array, a failure matching circuit, and a failure handling circuit. The fuse array includes a conventional fuse array and a failed fuse array. The failed fuse array is configured to store address information of failed fuses in the conventional fuse array. The fuses in the conventional fuse array have first address information, are configured to store second address information, and the fuses in the failed fuse array have third address information and are configured to store fourth address information. The failure matching circuit, connected to the failed fuse array, is configured to compare the first address information with the fourth address information and output a matching flag signal based on the comparison result. The failure handling circuit, connected to the failure matching circuit and the conventional fuse array, is configured to receive the matching flag signal and the second address information, and, based on the matching flag signal, selectively output the second address information or invalid address information.

[0006] According to some other embodiments of this application, the repair circuit further includes a counting circuit that broadcasts a count value output by the counting circuit to the conventional fuse array and the failed fuse array; wherein the counting circuit is connected to the conventional fuse array and the failed fuse array, and the counting circuit is used to provide first address information and third address information of the currently broadcast fuse; the conventional fuse array is configured to receive the first address information and output corresponding second address information based on the received first address information, and the failed fuse array is configured to receive the third address information and output corresponding fourth address information based on the received third address information; the failure matching circuit includes a register circuit connected to the failed fuse array, and the register circuit is configured to receive and store the fourth address information.

[0007] According to some other embodiments of this application, the second address information includes a first flag bit and a second flag bit; when the first flag bit and the second flag bit are not both 1, the second address information is valid address information, and when the first flag bit and the second flag bit are both 1, the second address information is invalid address information; the failure processing circuit is configured to select outputting the second address information or invalid address information based on the matching flag signal, including: the failure processing circuit is configured to select outputting the second address information or address information where the first flag bit and the second flag bit are both 1 based on the matching flag signal.

[0008] According to some other embodiments of this application, the second address information includes second row address information and second column address information, each second row address information includes at least one row address information, and each second column address information includes at least two column address information; each row address information and each column address information includes a first flag bit and a second flag bit.

[0009] According to some other embodiments of this application, the fourth address information includes at least two fourth sub-address information, and the failure matching circuit is configured to compare the first address information with the fourth address information, specifically: the failure matching circuit is configured to compare the first address information with one of the fourth sub-address information.

[0010] According to some other embodiments of this application, the fourth address information further includes a third flag bit, which is used to indicate whether the fourth address information is valid; the fourth address information further includes at least two fourth flag bits, each of which corresponds one-to-one with each of the fourth sub-address information, and the fourth flag bit is used to indicate whether the corresponding fourth sub-address information is valid.

[0011] According to some other embodiments of this application, each of the second address information includes at least two second sub-address information, and each of the fourth sub-address information corresponds to the at least two second sub-address information; each of the fourth sub-address information is further provided with a corresponding fifth flag bit, the fifth flag bit being used to indicate the information of the second sub-address information corresponding to the fourth sub-address information.

[0012] According to some embodiments of this application, another aspect of this application also provides a memory, the memory including the repair circuit described in any of the foregoing embodiments, the memory further including a memory array, and the second address information being the address information of a failed memory cell in the memory array.

[0013] According to some embodiments of this application, another aspect of this application also provides a method for repairing a memory, including:

[0014] Broadcast the fuse array to read the address information of the failed fuses stored in the failed fuse array and the address information of the fuses in the normal fuse array;

[0015] The address information of the failed fuse is compared with the address information of the fuses in the conventional fuse array, and the matching result is output.

[0016] Based on the matching result, the output may be either the address information stored in the conventional fuse array or an invalid address information.

[0017] According to some other embodiments of this application, the step of broadcasting the fuse array and reading the address information of the failed fuses stored in the failed fuse array and the address information of the fuses in the conventional fuse array includes: during the broadcasting of the fuse array, reading the address information of the failed fuses stored in the failed fuse array and temporarily storing the address information of the failed fuses in a register circuit; continuing to broadcast the fuse array and sequentially reading the address information of the fuses in the conventional fuse array; the step of comparing the address information of the failed fuses with the address information of the fuses in the conventional fuse array includes: comparing the address information of the failed fuses in the register circuit with the address information of the fuses in the conventional fuse array read out one by one.

[0018] The technical solution provided in this application has at least the following advantages:

[0019] The repair circuit and method provided in this application's embodiments store the address information of failed fuses by setting some fuses in the fuse array. During use, the read fuse addresses are matched with the addresses of erroneous fuses to identify the faulty fuses. By replacing the stored address information of the erroneous fuse with invalid address information, the faulty fuse is disabled. This allows the memory to use other redundant resources to repair memory cells, thus avoiding redundant address mapping errors and yield loss. Furthermore, by storing only the address information of failed fuses and disabling them, and by replacing them with redundant resources, the yield loss caused by errors in writing memory row or column addresses via fuses can be improved with minimal area overhead. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0021] Figure 1 This is a schematic diagram of a repair circuit provided in an embodiment of the present disclosure;

[0022] Figure 2 A schematic diagram of another repair circuit provided in an embodiment of this disclosure;

[0023] Figure 3 This is a schematic diagram of the structure of a counting circuit provided in an embodiment of the present disclosure;

[0024] Figure 4 A schematic diagram illustrating an encoding method for second address information provided in an embodiment of this disclosure;

[0025] Figure 5 A schematic diagram illustrating an encoding method for fourth address information provided in an embodiment of this disclosure;

[0026] Figure 6 This is a schematic diagram of a failure matching circuit provided in an embodiment of the present disclosure;

[0027] Figure 7 This is a schematic diagram of another failure matching circuit provided in an embodiment of the present disclosure;

[0028] Figure 8 This is a schematic diagram of a memory provided in an embodiment of the present disclosure. Detailed Implementation

[0029] Hereinafter, exemplary embodiments of the invention will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily practice the invention. As will be appreciated by those skilled in the art, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. For example, the exemplary embodiments provided herein are thought to be implementable by combining them, in whole or in part. Specifically, an element described in a particular exemplary embodiment, even if not described in another exemplary embodiment, can be understood as a description relating to another exemplary embodiment, unless a contrary or contradictory description is provided therein.

[0030] Throughout this specification, when any part is referred to as being “connected” to another part, it includes cases where any part and another part are “indirectly connected” to each other due to the presence of another part between them, as well as cases where any part and another part are “directly connected” to each other. For example, it should be understood that when an element is referred to as being “connected” or “attached” or “on another element” to another element, it may be directly connected or attached to or on that other element, or there may be an intermediate element present. Conversely, when an element is referred to as being “directly connected” or “directly attached” to another element, or referred to as being “in contact” or “in contact” with another element, there is no intermediate element at the point of contact.

[0031] Furthermore, "electrical connection" conceptually includes both physical connection and physical disconnection. It is understood that when an element is referred to using terms such as "first" and "second," the element is not limited in this respect. These terms may be used only to distinguish the element from other elements and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

[0032] The memory has storage rows and columns composed of storage cells, forming a storage array. For memories equipped with redundancy technology, redundant storage rows and columns are also provided to replace faulty storage rows and / or columns, thus repairing the memory. During product testing, the address information of the faulty storage row and / or column is written to the fuse array. Upon power-up, this address information is broadcast to a local redundancy register. Then, during read / write operations, the address of the faulty storage row / column is remapped to the address of the redundant storage row / column, replacing the storage resource.

[0033] In the aforementioned technology, the fuse array is used to store the address information of damaged (i.e., faulty, failed) memory rows / columns in the memory array. This allows redundant resources (i.e., redundant memory cells) to replace the damaged memory cells, enabling the memory to function normally. However, fuses in the fuse array can also fail. For example, a fuse that should be programmed may not be successfully programmed (unblown), or a fuse that should not be programmed may be mistakenly programmed (misblown), resulting in unsuccessful mapping of redundant resources and a decrease in memory yield.

[0034] The repair circuit, memory, and repair method provided in this application can identify the read faulty fuse address by storing the faulty fuse address and matching the read fuse address with the faulty fuse address during use. By disabling the faulty fuse address, the memory can use other redundant resources to repair the memory cell, thereby avoiding redundant address mapping errors and yield loss.

[0035] Figure 1 This is a schematic diagram of a repair circuit provided in an embodiment of this application. Figure 1 A repair circuit 10 is shown, including a fuse array 100, a failure matching circuit 200, and a failure handling circuit 300. The fuse array 100 includes a conventional fuse array 110 and a failed fuse array 120. The failed fuse array 120 is configured to store address information of the failed fuses in the conventional fuse array 110. The fuses in the conventional fuse array 110 have first address information and are configured to store second address information. The fuses in the failed fuse array 120 have third address information and are configured to store fourth address information. The failure matching circuit 200, connected to the failed fuse array 120, is configured to compare the first address information with the fourth address information and output a matching flag signal (Fusematch) based on the comparison result. The failure handling circuit 300, connected to the failure matching circuit 200 and the conventional fuse array 110, is configured to receive the matching flag signal (Fusematch) and the second address information, and based on the matching flag signal (Fusematch),... The `match` option selects to output either the second address information or invalid address information (Invalid data).

[0036] Specifically, the fuse array 100 includes a conventional fuse array 110 and a faulty fuse array 120. The conventional fuse array 110 is used to store the row address or column address information of the failed memory cells in the memory array. The faulty fuse array 120 is used to store the address information of the failed fuses in the conventional fuse array 110. For example, a faulty fuse is a fuse that failed to successfully write the row address or column address information of the failed memory cell, or a fuse that incorrectly wrote the row address or column address information of the failed memory cell. The fuses in the conventional fuse array 110 have first address information, which is the address information of the fuses in the conventional fuse array 110 in the fuse array 100, that is, the address information of the fuses in the conventional fuse array 110 themselves; the fuses in the conventional fuse array 110 are used to store second address information, which is, for example, the row address information or column address information of the failed memory cell in the storage array; the fuses in the failed fuse array 120 have third address information, which is the address information of the fuses in the failed fuse array 120 in the fuse array 100, that is, the address information of the fuses in the failed fuse array 120 themselves; the fuses in the failed fuse array 120 are configured to store fourth address information, which is the relevant address information of the failed fuses in the conventional fuse array 110. The conventional fuse array 110 is configured to receive first address information and output corresponding second address information based on the received first address information; the faulty fuse array 120 is configured to receive third address information and output corresponding fourth address information based on the received third address information.

[0037] In some embodiments, the fuse array can be composed of fuses, such as metal fuses or laser fuses; the fuse array can also be composed of antifuses, such as semiconductor antifuses. This application uses antifuses to form the fuse array as an example. When an antifuse is not programmed, it is in a high-resistance state and can be used to represent the data "0"; after programming, the antifuse is in a low-resistance state and can be used to represent the data "1". One antifuse unit can be used to store 1 bit of data. For an antifuse group composed of multiple antifuses, multiple bits of data can be stored together. For example, for the row address of a storage unit, which is typically multiple bits of data (e.g., 17 bits), an antifuse group composed of 17 antifuse units can be used to store the row address. For example, the second address information can be 17 bits of data. It should be understood that fuses can also form the fuse array of this application. For ease of explanation, the terms antifuse and fuse will not be distinguished below.

[0038] In some embodiments, the fuse array has multiple fuse subarrays, such as 64. Some of these fuse subarrays are used to form the failed fuse array 110, and some are used to form the conventional fuse array 120. For example, for a fuse array containing 64 fuse subarrays, one or two fuse subarrays can be used to form the failed fuse array 120, and the remaining 63 or 62 fuse subarrays can be used to store address information related to failed memory cells, or address information related to failed memory cells and test mode information. It should be understood that the above figures are for illustrative purposes only and do not constitute a limitation of this application.

[0039] Furthermore, the repair circuit 10 also includes a failure matching circuit 200, which is connected to the failure fuse array 120 and is used to compare the first address information with the fourth address information, and output a matching flag signal Fuse match based on the comparison result.

[0040] The failure handling circuit 300 is connected to the failure matching circuit 200 and the conventional fuse array 110. It receives the matching flag signal Fuse match and the second address information, and selects to output the second address information or invalid address information Invalid data based on the matching flag signal Fuse match.

[0041] Specifically, when the comparison result shows that the first address information and the fourth address information are the same, the matching flag signal Fusematch output by the failure matching circuit 200 is at the first level (e.g., high level 1), and the failure processing circuit 300 selects to output invalid address information Invalid data based on the first level of the matching flag signal Fusematch. When the comparison result shows that the first address information and the fourth address information are different, the matching flag signal Fusematch output by the failure matching circuit 200 is at the second level (e.g., high level 0), and the failure processing circuit 300 selects the second address information as the output signal FuseOut based on the second level of the matching flag signal Fusematch.

[0042] Figure 1 The example of the failure handling circuit 300 is a two-to-one multiplexer, but this application is not limited thereto. It should be understood that other circuits capable of implementing the selection function, such as combinational logic circuits, may also be used.

[0043] exist Figure 1 In this embodiment, the matching flag signal Fuse match is a single bit of data. Figure 2In this embodiment, the matching flag signal Fuse match is a two-bit data, including a first matching flag signal (fuse match high) and a second matching flag information (fuse match low). This application does not limit this; the matching flag signal Fuse match can be a one-bit or multi-bit data, depending on the amount of data stored in the second address information.

[0044] Therefore, the repair circuit provided in this application stores the address information of failed fuses by setting some fuses in the fuse array. During use, it matches the read fuse addresses with the addresses of erroneous fuses to identify the erroneous fuses. By replacing the stored address information of the erroneous fuse with invalid address information, the erroneous fuse is disabled. This allows the memory to use other redundant resources to repair memory cells, thus avoiding redundant address mapping errors and yield loss. Furthermore, by storing only the address information of failed fuses and disabling them, and by replacing redundant resources, the yield loss caused by errors in writing memory row or column addresses can be improved with minimal area overhead.

[0045] In some embodiments, Figure 1 and Figure 2 The repair circuit 10 also includes a counting circuit. The repair circuit 10 broadcasts the count value output by the counting circuit to the conventional fuse array 110 and the failed fuse array 120; wherein, the counting circuit is connected to the conventional fuse array 110 and the failed fuse array 120, and the counting circuit is used to provide the first address information and the third address information of the currently broadcast fuse.

[0046] During broadcasting, the fuses in the fuse array are scanned. A counting circuit is used to provide fuse addresses for the scan. Figure 3 An example of a counting circuit 400 is provided, comprising three sub-counting circuits 410, 420, and 430, but this number does not constitute a limitation of this application. The counting circuit may also include fewer than three sub-counting circuits or more than three sub-counting circuits, depending on the size of the fuse array, the scanning rules, and the address hierarchy of the fuse array.

[0047] Taking the three-level address of the fuse array as an example: row address, column address, and segment address, the corresponding counting circuit includes three counting sub-circuits, which are used to count the row address, column address, and segment address respectively, and scan the row address, column address, and segment address according to the count value, so as to read out the address information stored in the failed fuse array and the conventional fuse array in sequence.

[0048] Figure 3In the circuit, the counting circuit includes a first counting sub-circuit 410, a second counting sub-circuit 420, and a third counting sub-circuit 430; the clock Clk is used as the trigger signal for the counting circuit, and the counting value of the counting circuit is incremented by 1 each time the clock Clk jumps. Figure 3 The counting circuit is divided into three stages. When the counting value of the previous stage is full, the counting of the next stage will begin. Figure 3 In the example, the segment address Seg is used as the lowest level counting circuit, and scanning starts from the segment address Seg. When all segment addresses Seg are scanned (that is, for 64-bit segment addresses Seg[63:0], the count value reaches 63), the column address Yadd count value is incremented by 1. When all column addresses Yadd are scanned (that is, for 32-bit column addresses Yadd[31:0], the count value reaches 31), the row address Xadd count value is incremented by 1. In this way, all fuse addresses in the fuse array are scanned (that is, for 32-bit row addresses Xadd[31:0], the count value reaches 31), and all information of the fuse array is read out. In other embodiments, the row address can also be used as the counting object of the lowest level counting circuit 410, scanning starts from the row address, then scans the column address (or segment address), and then scans the segment address (or column address). In some other embodiments, the column address can be used as the counting object of the lowest-level counting circuit 410, scanning starting from the column address, then scanning the row address (or segment address), and then scanning the segment address (or row address). This application does not impose a mandatory requirement on the scanning order. The following will refer to... Figure 3 Take the scanning order of segment address-column address-row address from low to high (from first to last) as an example.

[0049] By grouping addresses, errors can be detected and stored on a single address basis (for example, segment addresses will be used as an example later), thereby reducing the number of fuse bits required to store erroneous addresses.

[0050] In some embodiments, the first counter circuit 410, the second counter circuit 420, and the third counter circuit 430 can all be composed of counters.

[0051] For an address Xadd, Yadd, Seg (e.g., Xadd = 0, Yadd = 0, Seg = 0), a set (multi-bit) of fuse data can be read. This set of fuse data is also an address information, such as the address information for storing a row / column. Each time the broadcast scans an address, the address itself (e.g., Xadd = 0, Yadd = 0, Seg = 0) contains the aforementioned first and third address information. The fuse array then sends out a set of fuse data, namely the aforementioned second and fourth address information. Figure 1 and Figure 2In the embodiment, the second address information Fuse2[16:0] is 17 bits of data, and the fourth address information Fuse4[16:0] is 17 bits of data.

[0052] Figure 3 The values ​​Seg[63:0], Yadd[31:0], and Xadd[31:0] shown are for ease of understanding of the decimal count values ​​displayed. In circuits (such as...) Figure 1 , 2 In section 4), it is represented by a 5-bit or 4-bit binary number. For example, Seg[63:0] (count values ​​from 0 to 63) is actually Seg[5:0] in the circuit, Yadd[31:0] (count values ​​from 0 to 31) is actually Yadd[4:0] in the circuit, and Xadd[31:0] (count values ​​from 0 to 31) is actually Xadd[4:0] in the circuit. The failure matching circuit 200 is used to compare the binary address with the address information stored in the failed fuse array.

[0053] In some embodiments, the failed fuse array is stored in the fuse array of the lower-order address range, such as Seg0 and Seg1, while the conventional fuse array is stored in the higher-order address range, such as Seg2-Seg63. The failure matching circuit 200 connects the failed fuse array 120 and the counting circuit 400, and compares the binary count value output by the counting circuit 400 (i.e., the first address information) with the data stored in the failed fuse array 120 (i.e., the fourth address information).

[0054] With the above settings, during broadcasting, the failed fuse array 120 and the conventional fuse array 110 can be scanned sequentially to obtain their own address information and stored address information (i.e., the first to fourth address information), thereby enabling the comparison of the first and fourth address information and the selective output of the second address information.

[0055] In some embodiments, the second address information includes a first flag bit and a second flag bit; when the first flag bit and the second flag bit are not both 1, the second address information is valid address information, and when the first flag bit and the second flag bit are both 1, the second address information is invalid address information.

[0056] The failure handling circuit is configured to select to output second address information or invalid address information based on the matching flag signal, including: the failure handling circuit is configured to select to output second address information or address information in which both the first flag bit and the second flag bit are 1 based on the matching flag signal.

[0057] Figure 4 A schematic diagram of an encoding method for second address information is shown. By defining encoding rules, valid and invalid addresses can be distinguished in the second address information. For example, Figure 4 The second address information shown includes 17 bits (FA0-FA16), and may include a first flag bit ( Figure 4 Taking FA0 as an example) and the second flag bit (e.g., FA6), when the first flag bit and the second flag bit are not both 1 (the XOR result is 1), the second address information is valid address information; when the first flag bit and the second flag bit are both 1, the second address information is invalid address information.

[0058] The failure handling circuit 300 selects to output either second address information or invalid address information based on the matching flag signal Fuse match. Specifically, the failure handling circuit 300 is configured to select to output either second address information or address information where both the first and second flag bits are 1, based on the matching flag signal Fuse match. That is, since both the first and second flag bits are 1, it indicates that the second address information is invalid. Therefore, invalid address information can be output by programming the first and second flag bits to 1, or by programming all second address information bits to 1.

[0059] In other words, by defining encoding rules, the second address information can be distinguished as valid or invalid. The example above uses two flag bits, where the XOR result of the two flag bits is 1, to represent valid address information. In other embodiments, the number of flag bits is not limited to two; it can be one, three, or more flag bits. Furthermore, the encoding rule is not limited to an XOR result of 1. For example, a single flag bit being 1 indicates an invalid address; two or more flag bits being XORed with 1 indicates valid address information, or other encoding rules may apply.

[0060] Continue to refer to Figure 4 In some embodiments, the second address information may include second row address information and second column address information. Each second row address information includes at least one row address information (e.g., ROW0), and each row includes 17-bit address information RA0-RA16. Each second column address information includes at least two column address information (e.g., COL0 and COL1). Each row address information and each column address information includes a first flag bit and a second flag bit. Figure 4 In the second row address information, ROW0 includes the first flag FA0 and the second flag FA6. One column address information, COL0, includes the first flag Fn4 and the second flag Fn5. The other column address information, COL1, also includes the first flag Fn4 and the second flag Fn5. When neither the first nor the second flag is 1 (the XOR result is 1), the second address information is valid. When both the first and second flags are 1, the second address information is invalid.

[0061] In other embodiments, each second row address information may include two row address information (not shown), and the two row address information share all the bits of the second row address information (e.g., the two second row address information have a total of 16 bits, and one row address information occupies 8 bits); each second column address information may include three column address information (not shown), and the three column address information share all the bits of the second column address information (e.g., the three column address information have a total of 15 bits, and each column address occupies 5 bits).

[0062] Therefore, the data length of a set of fuses can be matched with the data length of row or column addresses. For row addresses with longer address information, one row address (or other number) can be set in a set of fuse data; for column addresses with shorter address information, two column addresses (or other number) can be set in a set of fuse data. Thus, the number of row / column addresses in the second address information can be flexibly set according to the length of the row / column address information, maximizing the utilization of fuse resources. Furthermore, each row / column address has a first flag bit and a second flag bit, allowing each row / column address to work independently and independently determine the validity of each address. Row and column errors are distinguished when storing error addresses, thereby implementing different resource discard strategies.

[0063] Figure 5 A schematic diagram illustrating a method for encoding fourth address information is provided. For example... Figure 5 As shown, the first row represents the position of each data bit, and the second row represents the encoding meaning of each data bit. The fourth address information includes at least two fourth sub-address information (Resource A Fail Fuse Seg[5:0] and Resource B Fail Fuse Seg[5:0]). The failure matching circuit 200 compares the first address information with the fourth address information. Specifically, the failure matching circuit 200 compares the first address information (the count value output by the counting circuit, such as the segment address count value Seg[5:0] output by the first counting circuit 410) with one fourth sub-address information (Resource A Fail Fuse Seg[5:0] or Resource B Fail Fuse Seg[5:0]).

[0064] Therefore, considering that the address bits required to store a failed fuse may be 6 bits (e.g., Figure 5 As shown in FA7-FA7, or FA10-FA15), the fourth address information may be 17 bits (e.g., Figure 5As shown in FA0-FA16, the fourth address information can store the address information of multiple failed fuses (multiple fourth sub-address information), thus maximizing the utilization of the bits in the fourth address information. Furthermore, the fourth address information can store only part of the address information of the failed fuse, such as only storing the segment address information of the failed fuse, without storing the row address information and column address information. In this way, by using the same Xadd and Yadd addresses for repair, an appropriate number of segment addresses can be selected from all segment addresses to repair the remaining fuses. This allows for a trade-off between the increased area caused by repair and the repair capability, maintaining a large repair capability with a smaller area increase, maximizing the cost-effectiveness of the area loss.

[0065] In other embodiments, the multiple fourth sub-address information stored in the fourth address information can also be the row address Xadd or column address Yadd of the failed fuse. Furthermore, the fourth address information is not limited to including two sub-address information; it can also include three or four sub-address information, flexibly selected based on the number of bits in the sub-address information.

[0066] Continue to refer to Figure 5 In some embodiments, the fourth address information further includes a third flag bit (EN AB), which is used to indicate whether the fourth address information is valid. Figure 5 When the fourth address information contains multiple fourth sub-address information, if all of the multiple fourth sub-address information is invalid (e.g., all are damaged, or no faulty fuse address information is stored), it indicates that no valid repair information is stored in the fourth address information, and the third flag bit is in the first state (e.g., 1); if at least one of the multiple fourth sub-address information is valid, it indicates that valid repair information is stored in the fourth address information, and the third flag bit is in the second state (e.g., 0).

[0067] The fourth address information also includes at least two fourth flag bits (such as...). Figure 5 In the EN A and EN B sections, the number of fourth flag bits is the same as the number of fourth sub-address information bits. Each fourth flag bit corresponds one-to-one with each fourth sub-address information bit. The fourth flag bit is used to indicate whether the corresponding fourth sub-address information is valid. If the fourth flag bit is in the first state (e.g., 1), it means that the corresponding fourth sub-address information has stored information and has stored valid address information; if the fourth flag bit is in the second state (e.g., 0), it means that the corresponding fourth sub-address information has not stored information, or it has stored information, but the fourth sub-address information is corrupted.

[0068] Therefore, by setting the third and fourth flag bits, the availability of the fourth address information and the fourth sub-address information can be determined by detecting the flag bits, thereby avoiding incorrect mapping of redundant fuse resources.

[0069] Comprehensive reference Figure 4 and Figure 5 In some embodiments, each second address information includes at least two second sub-address information, and each fourth sub-address information corresponds to one second address information; therefore, each fourth sub-address information corresponds to at least two second sub-address information. Each fourth sub-address information also includes a corresponding fifth flag bit (e.g., ...). Figure 5 In the ACol High and BCol High, the fifth flag bit is used to indicate the information of the second sub-address corresponding to the fourth sub-address information.

[0070] like Figure 4 Each second address information includes two second sub-address information (column addresses COL0 and COL1), and the address information stored in each fourth sub-address information (such as Resource AFail Fuse Seg[5:0]) corresponds to at least two second sub-address information (sharing the first address information COL0 and COL1). Each fourth sub-address information also has a corresponding fifth flag bit (such as...). Figure 5 In the configuration, the fifth flag (ACol High) indicates the information of the second sub-address corresponding to the fourth sub-address, such as whether the fourth sub-address stores COL0 or COL1 information. For example, if the fourth sub-address information Resource AFail Fuse Seg[5:0] matches the first address information, it means that the currently read first address information is the address information of a failed fuse. If ACol High is in the first state (e.g., 1), it means that the second sub-address information COL1 is failed; if ACol High is in the second state (e.g., 0), it means that the second sub-address information COL0 is failed. Thus, the corresponding second sub-address information can be converted into invalid address information, thereby disabling the redundant storage column corresponding to the failed second sub-address and replacing other redundant storage columns to repair the failed storage column.

[0071] In other embodiments, when the second address information includes multiple second sub-address information, the fifth flag bit can be multiple bits to indicate the corresponding second sub-address information. For example, if the second address information contains three or four second sub-address information, the fifth flag bit can be two bits (such as FA1 and FA2). The number of bits in the fifth flag bit is related to the number of second sub-address information in the second address information.

[0072] Therefore, in the case where multiple second sub-addresses are stored in the second address information, a fifth flag is set to indicate (select) the second sub-address information, so as to make full use of the number of bits of the second address information and ensure the correct replacement or invalidation of multiple second sub-addresses.

[0073] Figure 6 This is a schematic diagram of a failure matching circuit provided in an embodiment of this application. Figure 7 This is a schematic diagram of another failure matching circuit provided in an embodiment of this application. The failure matching circuit 200 includes a register circuit (DFF0-DFF16 in the figure), which is connected to the failure fuse array 120, receives and stores the fourth address information Fuse4[16:0], and outputs Fail Fuse Add[16:0]. Figure 6 In this configuration, the register circuit can consist of multiple D flip-flops (DFFs).

[0074] The failure matching circuit 200 also includes a buffer, which receives the first address information Seg[5:0] and outputs the buffered first address information Segment[5:0].

[0075] The failure matching circuit 200 also includes a comparison circuit connected to the counting circuit 400 or the buffer, and receiving buffered first address information Segment[5:0] or directly receiving the first address information Seg[5:0]; the comparison circuit is also connected to a register and receives cached fourth address information Fail Fuse Add[16:0]; the comparison circuit is configured to compare the first address information and the fourth address information.

[0076] refer to Figure 6 and Figure 7When the fourth address information includes two fourth sub-address information, the fourth sub-address information is compared with the first address information one by one. At this time, the failure matching circuit includes two sets of comparison circuits. One fourth sub-address information (Fail Fuse Add[2]-Fail Fuse Add[7]) is compared with the first address information Segment[5:0], and the fourth flag bit (Fail Fuse Add[0]) of the fourth sub-address information is used to determine whether the fourth sub-address information is valid (if invalid, it is disabled); at the same time, the other fourth sub-address information (Fail Fuse Add

[10] -Fail Fuse Add

[15] ) is also compared with the first address information Segment[5:0] through another set of comparison circuits, and the fourth flag bit (Fail Fuse Add[8]) of the fourth sub-address information is used to determine whether the fourth sub-address information is valid (if invalid, it is disabled). If the currently read first address information matches the fourth sub-address information, and the fourth flag bit of the fourth sub-address information indicates that the fourth sub-address information is valid, the corresponding intermediate match flag signal (Fuse match A or Fuse match B) is output. Specifically, if the currently read first address information matches the first fourth sub-address information, and the fourth sub-address information is valid, the corresponding intermediate match flag signal (Fuse match A) is in the first state (e.g., high level 1); if the currently read first address information matches the second fourth sub-address information, and the fourth sub-address information is valid, the corresponding intermediate match flag signal (Fuse match B) is in the first state (e.g., high level 1). If there is no match or the fourth sub-address information is invalid, the corresponding intermediate match flag signal (Fuse match A or Fuse match B) is in the second state (e.g., low level 0).

[0077] Specifically, such as Figure 6 and Figure 7 In the circuit shown, each bit of the fourth sub-address information and each bit of the first address information are processed by an XOR gate, and the result is processed by a NAND gate. Then, the result of the NAND gate processing and the fourth flag bit corresponding to the fourth sub-address information are processed by a NOR gate to obtain the intermediate match flag signal (Fuse match A or Fuse match B).

[0078] Then, the intermediate match flag signal is judged by the third flag bit (Fail Fuse Add

[16] ). When the third flag bit indicates that the fourth address information is valid, the failure match circuit 200 will allow the output of the intermediate match flag signal. Specifically, as shown in the figure... Figure 6As shown, the intermediate matching flag signals Fuse match A and Fuse match B are processed by an NOR gate, and their results are then processed by an NOR gate with the third flag bit (Fail Fuse Add

[16] ) to obtain the matching flag signal Fusematch.

[0079] like Figure 1 As shown, the failure handling circuit 300 may include a selector, for example. When the first address information matches the fourth address information, and all flag bits indicate that the fourth address information is valid, the matching flag signal Fuse match is in a first state (e.g., 1). The failure handling circuit 300 selects invalid address information Invalid data to output based on this first state. Invalid address information Invalid data can be data where both the first and second flag bits are 1, for example, all data bits are 1. In this case, the data FuseOut[16:0] output by the repair circuit is invalid address information, and the memory performs a secondary address mapping, using other redundant resources for replacement and repair. When the first address information does not match the fourth address information, or all flag bits indicate that the fourth address information is invalid, the matching flag signal Fuse match is in a second state (e.g., 0). The failure handling circuit 300 selects second address information to output based on this second state.

[0080] When the second address information includes two second sub-address information, the failure matching circuit 200 also includes a low-order enable circuit and a high-order enable circuit, and the matching flag signal also includes two matching flag signals (low-order matching flag signal Fusematch low and high-order matching flag signal Fusematch high). Figure 7 As shown, the low-order enable circuit and the high-order enable circuit determine whether the high-order (COL1) or the second-order (COL0) of the second sub-address information corresponding to the fourth sub-address information is invalid based on the fifth flag bit (Fail Fuse Add[1] and Fail Fuse Add[9], and their inverted signals Fail Fuse Add[1]B and Fail Fuse Add[9]B). When the high-order second sub-address information (COL1) in the second address information is invalid, FA1 or FA9 is in the first state (e.g., 1), and at this time, the high-order match flag signal Fuse match high outputs the first state (e.g., 1). When the low-order second sub-address information (COL0) in the second address information is invalid, FA1 or FA9 is in the second state (e.g., 0), and at this time, the low-order match flag signal Fuse match low outputs the first state (e.g., 1).

[0081] like Figure 2As shown, the failure handling circuit 300 may include, for example, two selectors. The selection terminal of one selector receives the low-bit match flag signal Fuse match low, and the two input terminals receive the low-bit address information Fuse2[7:0] and invalid address information in the second address information Fuse2[16:0], respectively. The selection terminal of the other selector receives the high-bit match flag signal Fuse match high, and the two input terminals receive the high-bit address information Fuse2[16:8] and invalid address information in the second address information Fuse2[16:0], respectively.

[0082] When the first address information matches the fourth address information, and all flag bits indicate that the fourth address information is valid, and the fifth flag bit indicates that the lower-order address information in the second address information Fuse2[16:0] is invalid (the lower-order match flag signal Fuse match low is 1), the failure processing circuit 300 selects the invalid lower-order address information Invalid data for output. The invalid lower-order address information Invalid data can be data where both the first and second flag bits are 1, for example, all data bits are 1. At this time, the lower-order data FuseOut[7:0] in the data FuseOut[16:0] output by the repair circuit is invalid address information, and the memory performs a secondary address mapping, using other redundant resources for replacement and repair.

[0083] When the first address information matches the fourth address information, and all flag bits indicate that the fourth address information is valid, and the fifth flag bit indicates that the high-order address information in the second address information Fuse2[16:0] is invalid (the high-order match flag signal Fuse match high is 1), the failure processing circuit 300 selects invalid high-order address information Invalid data to output. Invalid high-order address information Invalid data can be data where both the first and second flag bits are 1, for example, all data bits are 1. At this time, the high-order data FuseOut[16:8] in the data FuseOut[16:0] output by the repair circuit is invalid address information, and the memory performs secondary address mapping and uses other redundant resources for replacement and repair.

[0084] When the first address information does not match the fourth address information, or when each flag bit indicates that the fourth address information is invalid, the low-bit match flag signal Fuse match low and the high-bit match flag signal Fuse match high are both in the second state (e.g., 0). The failure processing circuit 300 directly selects the second address information Fuse2[16:0] for output based on the second state.

[0085] In other embodiments, the failure matching circuit 200 may also include other enable circuits to provide more than two enable circuits corresponding to more than two fifth flag bits.

[0086] Therefore, the failure matching circuit 200 can store the fourth address information read from the failed fuse array. During broadcast scanning of the fuse array, the fourth address information read in advance from the failed fuse array is stored beforehand, and then compared with the first address information generated from the subsequent broadcast scanning of the regular fuse array. This allows for a comparison of the address information of the failed and regular fuse arrays in a single broadcast. Furthermore, by configuring at least two sets of comparison circuits, at least two fourth sub-address information can be stored, thereby fully utilizing the capacity of the failed fuse array. Additionally, by configuring high-bit and low-bit enable circuits, at least two second sub-address information can be stored and selected, thereby fully utilizing the capacity of the regular fuse array. Moreover, the failure matching circuit 200 also includes processing logic for a third flag bit. When the fourth address information is invalid, its use can be avoided, improving the correct utilization rate of redundant resources.

[0087] Figure 8 A schematic diagram illustrating a memory 1 provided in an embodiment of this application is shown. For example... Figure 8 The memory 1 includes the repair circuit 10 provided in any of the foregoing embodiments. The memory also includes a memory array 20, which may consist of multiple memory rows and columns, each composed of multiple memory cells. A memory cell may, for example, consist of a capacitor and a transistor. Accordingly, the memory 1 is a dynamic random access memory (DRAM). In other embodiments, the memory may also be, for example, NAND flash memory, ferroelectric memory, or other similar memory. This application does not limit the type of memory.

[0088] The second address information is the address information of the failed memory cell in the memory array. For example, the second address information can be the row address information or the column address information of the failed memory cell in the memory array.

[0089] In some embodiments, this application also provides a method for repairing a memory, comprising:

[0090] S1. Broadcast the fuse array to read the address information of the failed fuses stored in the failed fuse array and the address information of the fuses in the normal fuse array;

[0091] S2. Compare the address information of the failed fuse with the address information of the fuses in the conventional fuse array, and output the matching result;

[0092] S3. Based on the matching result, choose to output the address information of the fuse storage in the conventional fuse array, or output invalid address information.

[0093] Specifically, step S1 can be broadcasting to the fuse array 100 according to, as follows: Figure 3 The counting circuit 400 shown scans the fuse array 100 sequentially, reading the failed fuse address information (i.e., the aforementioned fourth address information) stored in the failed fuse array 120. Figure 1 and 2 The address information of the fuses in the conventional fuse array 110 (also known as the first address information mentioned above, which is given by the counting circuit 400) is stored in the Fuse4[16:0] and the conventional fuse array 110. The failed fuse array 120 is used to store the address information of the failed fuses in the conventional fuse array 110.

[0094] Step S2 can be based on the appendix Figure 1 , 2 The failure matching circuit shown in 6 and 7 will store the address information of the failed fuse (i.e., the aforementioned fourth address information, attached) Figure 1 and 2 The address information of the fuses in the conventional fuse array (Fuse4[16:0]) is compared with the address information of the fuses in the conventional fuse array (i.e., the aforementioned first address information, given by the counting circuit 400), and the matching result is output (i.e. Figure 1 The Fusematch shown, or Figure 2 (The examples shown are Fuse match high and Fuse match low).

[0095] Step S3 can be based on the appendix Figure 1 and 2 As shown, based on the matching result, the circuit selects to output either the address information stored in the conventional fuse array or invalid address information. If the matching result indicates that the currently read first address information matches the fourth address information, meaning the currently read fuse in the conventional fuse array is a failed fuse, the failure handling circuit outputs invalid address information, enabling (disable) the failed fuse. This allows for the replacement of row / column redundant resources for the failed fuse, improving yield. If the matching result indicates that the currently read first address information does not match the fourth address information, meaning the currently read fuse in the conventional fuse array is a normal, undamaged fuse, the failure handling circuit normally outputs the address for normal repair of the storage array.

[0096] Therefore, this method can identify faulty fuses by storing and matching faulty fuse addresses, and by matching read fuse addresses with faulty fuse addresses. By replacing the stored address information of the faulty fuse with invalid address information, the faulty fuse is disabled. This allows the memory to use other redundant resources to repair memory cells, thus avoiding redundant address mapping errors and yield loss. Furthermore, by storing only the address information of faulty fuses and disabling them, and by replacing them with redundant resources, the yield loss caused by faulty fuse row or column address writing can be improved with minimal area overhead.

[0097] In some embodiments, step S1, which involves broadcasting the fuse array and reading the address information of the failed fuses stored in the failed fuse array and the address information of the fuses in the conventional fuse array, specifically includes:

[0098] S11. During the broadcasting process of fuse array 100, the address information of the failed fuses stored in the failed fuse array 120 (i.e., the aforementioned fourth address information, appended) is read out. Figure 1 and 2 In Fuse4[16:0]), the address information of the failed fuse is temporarily stored in the register circuit (e.g., Fuse4[16:0]). Figure 6 and Figure 7 (as shown)

[0099] S12. Continue broadcasting to the fuse array and read out the address information of the fuses in the conventional fuse array in sequence;

[0100] The address information of the failed fuse is compared with the address information of fuses in the conventional fuse array, including:

[0101] The address information of the failed fuse in the register circuit is compared one by one with the address information of the fuses in the conventional fuse array read out sequentially.

[0102] Specifically, for step S11, with Figure 1 and Figure 2 The fuse array 100 shown contains 64 segment addresses (Seg[63:0]), 32 row addresses (XAdd[31:0]), and 32 column addresses (YAdd[31:0]), with the failed fuse addresses stored in the fuse array where segment address Seg=0. During power-on broadcast, the fuses at addresses Xadd=0, Yadd=0, and Seg=0 are read first; at this time, the fourth address information Fuse 4[16:0] is read, these seventeen bits containing the segment addresses of the failed fuses among the other 63 segment addresses where X=0 and Y=0. The fourth address information Fuse 4[16:0] is then sent to... Figure 6 and Figure 7In the register circuit shown.

[0103] The broadcast continues to the fuse array, sequentially reading the second address information Fuse2[16:0] stored in the other fuses with addresses X=0, Y=0, and segments 1 to 63. Each time it is read, the segment address output by the counting circuit before decoding, Seg[5:0], is sent to the failure matching circuit 200 and compared with the address information stored in the register circuit using XNOR or XOR. If they match, it means that the fuse corresponding to the currently read segment address is a failure fuse, and the matching flag signal Fuse match corresponding to the level state is output.

[0104] After the conventional fuse array 110 determines whether a fuse is faulty based on its segment address, the failure handling circuit 300 determines whether to output the corresponding second address information based on the matching flag signal "Fuse match" corresponding to the level state. If the matching result indicates that the currently read first address information matches the fourth address information, meaning the fuse in the conventional fuse array is faulty, the failure handling circuit outputs invalid address information, enabling (disable) the faulty fuse. This allows for the replacement of row / column redundant resources for the faulty fuse, improving yield. If the matching result indicates that the currently read first address information does not match the fourth address information, meaning the fuse in the conventional fuse array is normal and undamaged, the failure handling circuit normally outputs the address for normal repair of the memory array.

[0105] After reading all segment addresses of a row address Xadd and column address Yadd, switch to the next Yadd address and repeat the above process until the broadcast of the fuse array is completed.

[0106] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A repair circuit, characterized in that, This includes fuse arrays, failure matching circuits, and failure handling circuits, among which... The fuse array includes a conventional fuse array and a failed fuse array. The failed fuse array is configured to store address information of failed fuses in the conventional fuse array. The fuses in the conventional fuse array have first address information, are configured to store second address information, and the fuses in the failed fuse array have third address information and are configured to store fourth address information. The failure matching circuit, connected to the failure fuse array, is configured to compare the first address information with the fourth address information and output a matching flag signal based on the comparison result. The failure handling circuit, connected to the failure matching circuit and the conventional fuse array, is configured to receive the matching flag signal and the second address information, and based on the matching flag signal, select to output the second address information or invalid address information.

2. The repair circuit according to claim 1, characterized in that, The repair circuit also includes a counting circuit, which broadcasts the count value output by the counting circuit to the conventional fuse array and the failed fuse array. The counting circuit is connected to the conventional fuse array and the failed fuse array, and the counting circuit is used to provide the first address information and the third address information of the currently broadcast fuse; The conventional fuse array is configured to receive the first address information and output the corresponding second address information based on the received first address information; the failed fuse array is configured to receive the third address information and output the corresponding fourth address information based on the received third address information. The failure matching circuit includes a register circuit connected to the failed fuse array, and the register circuit is configured to receive and store the fourth address information.

3. The repair circuit according to claim 1, characterized in that, The second address information includes a first flag bit and a second flag bit; when the first flag bit and the second flag bit are not both 1, the second address information is valid address information, and when the first flag bit and the second flag bit are both 1, the second address information is invalid address information. The failure handling circuit is configured to select to output the second address information or invalid address information based on the matching flag signal, including: the failure handling circuit is configured to select to output the second address information or address information in which both the first flag bit and the second flag bit are 1 based on the matching flag signal.

4. The repair circuit according to claim 3, characterized in that, The second address information includes second row address information and second column address information. Each second row address information includes at least one row address information, and each second column address information includes at least two column address information. Each row address information and each column address information includes a first flag bit and a second flag bit.

5. The repair circuit according to claim 1, characterized in that, The fourth address information includes at least two fourth sub-address information. The failure matching circuit is configured to compare the first address information with the fourth address information. Specifically, the failure matching circuit is configured to compare the first address information with one of the fourth sub-address information.

6. The repair circuit according to claim 5, characterized in that, The fourth address information also includes a third flag bit, which is used to indicate whether the fourth address information is valid. The fourth address information also includes at least two fourth flag bits, each of which corresponds one-to-one with each of the fourth sub-address information. The fourth flag bits are used to indicate whether the corresponding fourth sub-address information is valid.

7. The repair circuit according to claim 6, characterized in that, Each of the second address information includes at least two second sub-address information, and each of the fourth sub-address information corresponds to the at least two second sub-address information; Each fourth sub-address information is also provided with a corresponding fifth flag bit, which is used to indicate the information of the second sub-address information corresponding to the fourth sub-address information.

8. A memory, characterized in that, The memory includes a repair circuit as described in any one of claims 1-7, and the memory further includes a storage array, wherein the second address information is the address information of a failed storage cell in the storage array.

9. A method for repairing a memory, comprising: Broadcast the fuse array to read the address information of the failed fuses stored in the failed fuse array and the address information of the fuses in the normal fuse array; The address information of the failed fuse is compared with the address information of the fuses in the conventional fuse array, and the matching result is output. Based on the matching result, the output may be either the address information stored in the conventional fuse array or an invalid address information.

10. The repair method according to claim 9, characterized in that, The broadcasting of the fuse array and reading the address information of the failed fuses stored in the failed fuse array and the address information of the fuses in the normal fuse array includes: During the broadcasting of the fuse array, the address information of the failed fuses stored in the failed fuse array is read out and the address information of the failed fuses is temporarily stored in the register circuit. Continue broadcasting to the fuse array, and read out the address information of the fuses in the conventional fuse array in turn; The step of comparing the address information of the failed fuse with the address information of the fuses in the conventional fuse array includes: The address information of the failed fuse in the register circuit is compared one by one with the address information of the fuses in the conventional fuse array read out sequentially.

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