System and method for slow branch control in totem-pole power factor correction converter

Abstract

The invention relates to a system and method for slow branch control in totem-pole power factor correction converters. Embodiments include a totem-pole power factor correction (PFC) converter. An example embodiment includes a method for operating a PFC converter including: conducting, by an inductor, a current between a first AC input node and a fast branch switch node; a DC output voltage is generated by a fast branch between a positive output node and a negative output node by selectively conducting current between a fast branch switching node and each of: a positive output node and a negative output node; selectively conducting current between the second AC input node and the positive output node by a slow branch high side switch; selectively conducting current between the second AC input node and the negative output node by a slow branch low side switch; and operating a field effect transistor in at least one of the slow branch low side switch or the slow branch high side switch in a saturation mode to gradually vary the voltage on the second AC input node.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 723,989, filed November 22, 2024, entitled “Totem Pole Power Factor Correction, Slow Leg Control”. That provisional application is incorporated herein by reference as reproduced entirely below. Background Technology

[0003] A power factor correction (PFC) converter can be configured to receive an AC line voltage at its input and generate a regulated DC voltage at its output. The PFC circuitry can perform power conversion using a switch that switches back and forth at a pulse width modulation (PWM) frequency, and may also include circuitry for rectification. The rectification circuitry may include a switch that switches back and forth according to the polarity of the AC line voltage. A PFC converter with switches for both power conversion and rectification is called a totem-pole PFC converter.

[0004] At the zero-crossing point of the input voltage, the rectifier switches (also known as slow leg switches) each change between a conducting and a non-conducting state. However, conventional operation of slow leg switches can cause transient currents and / or surge input voltages, which can lead to common-mode noise and / or EMI (electromagnetic interference). Attached Figure Description

[0005] To describe the example implementation in detail, reference will now be made to the accompanying drawings, in which:

[0006] Figure 1 A schematic diagram of a totem pole PFC system according to aspects of this disclosure is shown;

[0007] Figure 2 An example is shown. Figure 1 A graph showing the operation of the totem pole PFC converter;

[0008] Figure 3 A schematic block diagram of a first slow branch switch according to an aspect of this disclosure is shown;

[0009] Figure 4 An example is shown with Figure 3 A graph showing the operation of the slow branch bridge in the totem pole PFC of the first slow branch switch;

[0010] Figure 5 A schematic block diagram of a second slow branch switch according to an aspect of this disclosure is shown;

[0011] Figure 6 An example is shown with Figure 5 A graph showing the operation of the slow branch bridge in the totem pole PFC of the second slow branch switch;

[0012] Figure 7 Aspects according to this disclosure are shown Figure 5 A schematic diagram of the current source for the second slow branch switch;

[0013] Figure 8 A diagram showing the method steps according to at least some implementation schemes is provided.

[0014] definition

[0015] Various terms are used to refer to specific system components. Different companies may use different names to refer to a component—this document is not intended to distinguish between components with different names but the same function. In the following discussion and in the claims, the terms "comprising" and "including" are used in an open form, and therefore, these terms should be interpreted as meaning "including, but not limited to,...". Additionally, the term "coupled" is intended to mean either an indirect connection or a direct connection. Thus, if a first device is coupled to a second device, the connection can be made either directly or indirectly via other devices and connections.

[0016] "Controller" should be used individually or in combination to mean a single circuit component configured to read inputs and drive outputs in response to those inputs, an application-specific integrated circuit (ASIC), a microcontroller with control software, a reduced instruction set computer (RISC) with control software, a digital signal processor (DSP), a processor with control software, a programmable logic device (PLD), a field-programmable gate array (FPGA), or a programmable system-on-a-chip (PSOC).

[0017] In the context of electrical equipment, the terms "input" and "output" refer to electrical connections to the electrical equipment and should not be considered as verbs requiring operation. For example, a controller may have a gate output and one or more sensing inputs. Detailed Implementation

[0018] The following discussion relates to various embodiments of the invention. While one or more of these embodiments may be preferred, the disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is intended only as an example of that embodiment and is not intended to imply that the scope of this disclosure, including the claims, is limited to that embodiment.

[0019] The example embodiments relate to methods and systems for power factor correction (PFC) converters with a slow branch switch driver configured to gradually change the slow branch voltage at the slow branch node over a time period to reduce or eliminate transient currents that could otherwise be caused by switching the slow branch switch at the zero-crossing point of the input voltage. Therefore, the methods and systems of this disclosure can reduce or eliminate undesirable effects such as surges in the input current, common-mode noise, and / or EMI (electromagnetic interference).

[0020] A method has been proposed to operate the fast branch switch in a totem-pole PFC converter at a relatively high switching frequency to achieve line voltage V AC An alternative solution involves gradually changing the slow branch voltage at the slow branch node over a period of time near the zero-crossing point. However, such a solution may cause undesirable effects. For example, and referring to... Figure 1 Fastleg switches 121 and 122 are in operation at line voltage V. AC High-speed operation around the zero crossing point can induce inductor current through inductor 104 and AC power source 102 to reach the second AC input node 125, causing the slow branch voltage V on the second AC input node 125 to... SL This can be achieved via fast branch switches 121 and 122. This can be referred to as indirect V. SL The switch is driven, and may require additional switching logic in the controller 150 to implement. Additionally, due to the induced current in the inductor 104, this indirect V... SL The conversion drive may cause the input current I IN Unexpected distortion.

[0021] Figure 1 A schematic diagram of a PFC system 100 for converting AC power to DC power is shown. The PFC system 100 includes an AC power source 102. For example, the AC power source 102 may be a line voltage (e.g., 120VAC at 60Hz, 230VAC at 50Hz, etc.). The AC power source 102 defines an AC line voltage V between a first AC input node 124 and a second AC input node 125. AC .

[0022] The PFC system 100 also includes a load 103. The load 103 is represented as a resistor. However, the load 103 may include a combination of resistive and / or reactive components. The load 103 may include, for example, a DC-DC converter, such as those used in battery charging systems. The PFC system 100 also includes a PFC converter 101 configured to convert the AC voltage (VAC) (i.e., line voltage) at its input to a DC voltage (VDC) (e.g., 400V) at its output. While the DC voltage is adjustable, the current supplied to the load 103 may vary based on load conditions.

[0023] The PFC converter 101 has a totem-pole topology including multiple switches that can be controlled to be turned on / off. The PFC system 100 also includes a controller 150 configured to generate switch signals to control the on / off state of each of the multiple switches. The multiple switches can be configured by the switch signals to form different circuit configurations that change over time to perform VAC to VDC conversion.

[0024] The conversion may include a boost conversion process. The PFC converter 101 can use a boost conversion process to output a DC level higher than the peak input voltage. For example, for an input line voltage V in the range of 90VAC to 264VAC. AC The PFC converter 101 can generate a DC output voltage V of approximately 400VDC (e.g., 395VDC). OUT To support the boost conversion process, the PFC converter 101 includes an inductor 104 connected between the first AC input node 124 and the fast branch switching node 123 of the PFC converter 101. Additionally, the PFC converter 101 may include an inductor with a capacitor C. L And the output capacitor 105 is connected in parallel with the load 103 between the positive output node 131 and the negative output node 132.

[0025] exist Figure 1 In the diagram, PFC converter 101 is shown as including inductor 104 and output capacitor 105. The boundaries shown (i.e., dashed lines) illustrate the functional groups to aid understanding and are not intended to limit possible physical implementations. For example, in an actual implementation of PFC converter 101, inductor 104 and / or output capacitor 105 may be discrete components.

[0026] The PFC converter 101 can be operated by a switching signal to perform a boost conversion process. The boost conversion process may repeatedly include: (i) charging the inductor 104 to increase the inductor current passing through it, and (ii) discharging the inductor 104 to charge the output capacitor 105 in order to generate a DC output voltage V for the load 103. OUT(iii) Discharge the output capacitor 105 to maintain the DC output voltage V applied to the load 103. OUT At the same time, inductor 104 is recharged for the next cycle.

[0027] To perform the boost conversion process, switching signals from controller 150 can switch one or more switches in PFC converter 101 at a pulse width modulation (PWM) switching frequency. The PWM switching frequency can be higher than the source frequency (i.e., line frequency) of AC power source 102. Therefore, these switching signals can be referred to as high-frequency switching signals (i.e., PWM switching signals, boost switching signals).

[0028] The PFC converter 101 can be further configured to perform a rectification process via a switching signal from the controller 150. The rectification process may include switching nodes coupled to the AC power source 102. Therefore, the switching signal used for the rectification process can be switched at the line frequency and is thus referred to as a low-frequency or slow-switching signal.

[0029] As mentioned, the PFC converter 101 includes multiple switches. The multiple switches in the PFC converter 101 can be implemented using transistors of various technologies (such as metal-oxide-semiconductor field-effect transistors (MOSFETs)) and various types of transistors (such as N-type). In some specific implementations, one or more of the multiple switches may require low reverse recovery and therefore wide bandgap (WBG) technology can be utilized. For example, WBG switches can be implemented using GaN HEMT or SiC FET technology. These switch examples are not intended to be limiting, as the disclosed techniques can be applied to any switch suitable for control by signals transmitted from the controller 150 (e.g., voltage signals, current signals).

[0030] PFC converter 101 includes a slow branch 110 for rectifying AC power from AC power source 102. Slow branch 110 includes a slow branch high-side switch 111 configured to selectively conduct current between a second AC input node 125 and a positive output node 131 of PFC converter 101. The slow branch high-side switch 111 includes a field-effect transistor (FET) controllable by a first synchronous rectification signal SR1 at its gate terminal. Slow branch 110 also includes a slow branch low-side switch 112 configured to selectively conduct current between the second AC input node 125 and a negative output node 132 of PFC converter 101. The slow branch low-side switch 112 includes a FET controllable by a second synchronous rectification signal SR2 at its gate terminal. The synchronous rectification signals SR1 and SR2 may also be referred to as low-frequency signals because they operate at a relatively low frequency relative to the AC power from AC power source 102.

[0031] The PFC converter 101 also includes a fast tributary 120, which may also be referred to as a fast tributary branch. The fast tributary 120 includes a high-side fast tributary switch 121 configured to selectively conduct current between the fast tributary switch node 123 and the positive output node 131 of the PFC converter 101. The high-side fast tributary switch 121 includes a FET that can be controlled to turn on / off by a first high-frequency signal (S1) at its gate terminal. The fast tributary 120 also includes a low-side fast tributary switch 122 configured to selectively conduct current between the fast tributary switch node 123 and the negative output node 132 of the PFC converter 101. The low-side fast tributary switch 122 includes a FET that can be controlled to turn on / off by a second high-frequency signal (S2) at its gate terminal.

[0032] Fast branch 120 can be configured to turn on / off at the PWM frequency. In other words, switching signals S1 and S2 can be switched at the PWM frequency to generate a DC output voltage V between the positive output node 131 and the negative output node 132. OUT Switching the high-side fast branch switch 121 and the low-side fast branch switch 122 allows the fast branch 120 to perform power transmission (i.e., boost conversion) and facilitates power factor correction.

[0033] Slow branch 110 is configured to turn on / off at a frequency corresponding to AC power source 102. For example, low-frequency switching signals SR1 and SR2 can be switched at twice the AC line frequency to operate slow branch high-side switch 111 and slow branch low-side switch 112 for synchronous rectification. IN This provides a high-efficiency conduction path back to the AC power source 102. Synchronous rectification using switches eliminates the need for a diode bridge. Therefore, the PFC converter 101 can be referred to as a bridgeless PFC converter or a totem-pole PFC converter. During half a cycle of the line voltage (VAC), the slow branch high-side switch 111 or the slow branch low-side switch 112 is driven to turn on, and one of the slow branch high-side switches 111 or 112 driven to turn on can be based on the line voltage (V). AC The polarity of ) alternates.

[0034] like Figure 1 As shown, the controller 150 can be configured to sense the voltage between the first AC input node 124 and the second AC input node 125 in order to determine the line voltage V. ACThe polarity, when the polarity change occurs, and / or the type of polarity change (e.g., positive to negative, negative to positive). For example, the controller can be configured to determine whether the AC power source 102 is in a positive VAC half-cycle or a negative VAC half-cycle. Based on this determination, the controller 150 can determine the polarity of the line voltage V. AC The polarity is used to adjust the control of switches 111, 112, 121, and 122. During implementation, the controller 150 can also be configured to operate at line voltage V. AC The switching signal (i.e., the drive signal) is disabled before and / or after the zero-crossing point. For example, controller 150 can disable both the slow branch high-side switch 111 and the slow branch low-side switch 112 at AC line voltage V. AC The dead zone is disconnected during the time period around the zero crossing point in order to avoid causing a short circuit between the positive output node 131 and the negative output node 132, which may occur when both the high-side switch 111 and the low-side switch 112 of the slow branch are simultaneously conducting.

[0035] Figure 2 An example is shown. Figure 1 A first graph 200 illustrating the operation of the PFC converter 101. The first graph 200 includes several curves 202, 204, and 206 illustrating various signals or conditions on a common time scale. The first graph 200 also includes a graph showing the AC line voltage V between the first AC input node 124 and the second AC input node 125. AC The first curve 202. The first curve 200 also includes a diagram showing the slow branch voltage V on the second AC input node 125. SL The second curve 204. The first curve 200 also includes an illustration of the input current I supplied to the PFC converter 101. IN The third curve is 206. (For example...) Figure 2 As shown, at AC line voltage V AC At each zero crossing point, the slow branch voltage V SL At zero volts and DC output voltage V OUT The switching occurs rapidly. This rapid switching is a result of the switching states of the high-side switch 111 and the low-side switch 112 of the slow branch to perform synchronous rectification. The slow branch voltage V... SL This rapid switching may cause transient currents, which can lead to surges in input current and / or input voltage, common-mode noise, and / or EMI (electromagnetic interference). Curve 206 shows the AC line voltage V. AC The input current I around the zero crossing point IN The positive and negative spikes in the data, and the positive and negative spikes are caused by the slow branch voltage V. SL This is caused by rapid changes. Curve 206 can represent the input current I. INThis is a simplified version of the actual spike, and this simplified version may not be scaled. Input current I IN The slow branch voltage V SL The actual magnitude and duration of the spikes caused by rapid changes can vary based on consideration of many practical factors, such as the physical characteristics of the equipment of the PFC system 100.

[0036] In conventional totem pole PFC designs (such as, Figure 1 In the PFC converter 101, the FETs of the slow branch high-side switch 111 and the slow branch low-side switch 112 can be directly driven between a non-conductive state and a conductive state by applying digital control signals. As described, this switching operation may cause undesirable effects such as common-mode noise and / or EMI.

[0037] This disclosure provides a system and method for a totem-pole power factor correction (PFC) converter, the method comprising operating one or more FETs in saturation mode to progressively change the slow branch voltage V on a second AC input node 125. SL Gradually change the voltage V of the slow branch. SL This may include keeping the slow branch voltage V for a period of time substantially longer than the near-instantaneous change. SL At zero volts and DC output voltage V OUT The change between these states was originally achieved by directly switching the FETs of the high-side switch 111 and the low-side switch 112 of the slow branch between non-conductive and conductive states using digital control signals. This is achieved by gradually changing the slow branch voltage V. SL The system and method disclosed herein can reduce or eliminate AC line voltage V AC The input current I around the zero crossing point IN The spikes in the signal can potentially cause undesirable effects. In saturation mode (also known as active mode), the FET can act as a constant current source instead of a switch. In saturation mode, the FET can be effectively used as a voltage amplifier to make the slow branch voltage Vo a constant current source for a period of time. SL Gradually changing.

[0038] Figure 3A schematic block diagram of the first slow branch switch 300 of this disclosure is shown. The first slow branch switch 300 can be used as a slow branch low-side switch 112 and / or as a slow branch high-side switch 111 in the PFC converter 101. However, for the sake of simplicity, the first slow branch switch 300 is shown and described as a low-side switch configured to selectively conduct current between the second AC input node 125 and the negative output node 132 of the PFC converter 101. The current description of the first slow branch switch 300 includes several references to voltages at different terminals. The described voltages may each be relative to the negative output node 132, which may be connected to ground.

[0039] The first slow branch switch 300 includes a first rectifier FET 310 having a drain terminal, a source terminal, and a gate terminal, respectively labeled D, S, and G. The drain terminal D of the first rectifier FET 310 is connected to a second AC input node 125, and the source terminal S of the first rectifier FET 310 is connected to a negative output node 132. The first rectifier FET 310 is configured to conduct current between the second AC input node 125 and the negative output node 132 based on a voltage applied to the gate terminal G. The first slow branch switch 300 is configured to operate the first rectifier FET 310 in saturation mode to gradually change the voltage on the second AC input node 125.

[0040] like Figure 3 As shown, the first slow branch switch 300 includes a first voltage scaler 312 connected between the second AC input node 125 and the negative output node 132. The first voltage scaler 312 is configured to operate based on the slow branch voltage V on the second AC input node 125. SL To generate a sensed voltage signal V at the first sensor terminal 318 S . Figure 3 The first voltage scaler 312 shown includes a resistive voltage divider having a first resistor 314 connected in series with a second resistor 316 and defining a first sensor terminal 318 between the first resistor and the second resistor. However, other types of voltage scalers, such as capacitive voltage dividers, can be used. The sensed voltage signal V S It can be the slow branch voltage V SL It is a part of the resistance ratio of the first resistor 314 to the second resistor 316.

[0041] The first slow branch switch 300 also includes a first driver circuit 320 configured to apply a voltage to the gate G of the first rectifier FET 310 to control the operation of the first rectifier FET 310 to conduct current between the second AC input node 125 and the negative output node 132. The first driver circuit 320 defines an input terminal 321 coupled to the controller 150 for receiving a second synchronous rectified signal SR2. The first driver circuit 320 includes a reference signal generator 322 defining a reference output terminal 324. The reference signal generator 322 is coupled to the input terminal 321 and configured to gradually change a reference signal REF on the reference output terminal 324 in response to a digital input signal. For example, the reference signal generator 322 may reduce the voltage of the reference output terminal 324 linearly (e.g., by transitioning from a low-level condition to a high-level condition) in response to the second synchronous rectified signal SR2 being asserted. After the gradual change is complete, such as when the reference signal REF has reached its final value, the reference signal generator 322 may maintain the reference signal REF on the reference output terminal 324. For example, such as Figure 3 As shown, as long as the second synchronous rectified signal SR2 remains high, the reference signal generator 322 can maintain the reference signal REF in a zero-voltage state. The reference signal generator 322 can reset the reference signal REF on the reference output terminal 324 in response to the second synchronous rectified signal SR2 being deasserted (e.g., by transitioning from a high-level condition to a low-level condition).

[0042] The first slow branch switch 300 also includes an amplifier 330 defining a first input terminal 332, a second input terminal 334, and an output terminal 336 connected to the gate G of the first rectifier FET 310. The first input terminal 332 is configured as an inverting (-) input, and the second input terminal 334 is configured as a non-inverting (+) input. However, the configurations of the first input terminal 332 and the second input terminal 334 may differ. The first input terminal 332 of the amplifier 330 is connected to the reference output terminal 324 of the reference signal generator 322, and the second input terminal 334 is connected to the first sensor terminal 318 of the first voltage scaler 312. The amplifier 330 may include, for example, configurations based on a sensed voltage signal V. S The operational amplifier (op-amp) uses the difference between the output signal 330 and the reference signal REF to generate the drive voltage DRV at the output terminal 336. Therefore, amplifier 330 serves as a source for the sensed voltage signal V. SA controller adjusts the voltage applied to the gate G of the first rectifier FET 310 based on the difference between the reference signal REF and the reference signal REF. Therefore, the first slow branch switch 300 can operate the first rectifier FET 310 in saturation mode to gradually change the slow branch voltage V on the second AC input node 125 during the time period during which the reference signal REF on the reference output terminal 324 changes due to the reference signal generator 322. SL .

[0043] The first slow branch switch 300 can also be configured to respond to the slow branch voltage V on the second AC input node 125. SL Because the first rectifier FET 310 operates in saturation mode, reaching the target voltage drives the first rectifier FET 310 to a low-impedance state (which may be referred to as a conducting state). For example, the reference signal generator 322 can drive the reference signal REF on the reference output terminal 324 to zero volts or a negative voltage after the gradual change is complete (such as when the reference signal REF has reached its final value). When the slow branch voltage V on the second AC input node 125... SL When the target voltage of zero volts is reached, the sensed voltage signal V is measured because the first rectifier FET 310 operates in saturation mode. S It also reaches zero. Then, amplifier 330 can sense the voltage signal V. S The signal is compared with a reference signal REF. When the sensed voltage signal V... S When the impedance reaches zero, amplifier 330 can apply a predetermined maximum voltage to the gate G of the first rectifier FET 310, which is sufficient to drive the first rectifier FET 310 to a low-impedance state and maintain it until the second synchronous rectification signal SR2 is deasserted. By operating the first rectifier FET 310 in a low-impedance state, resistive power loss in the first rectifier FET 310 can be significantly reduced.

[0044] Figure 4 An example with is shown. Figure 3 The second curve 350 shows the operation of the slow branch bridge in the totem pole PFC of the first slow branch switch 300. The second curve 350 includes several curves 352, 354, 356, 358, and 360 illustrating various signals or conditions on a common time scale. The second curve 350 also includes a diagram showing the slow branch voltage V at the second AC input node 125. SL The first curve 352. The second curve 350 also includes a second curve 354 showing the first synchronous rectified signal SR1 used to control the operation of the slow branch high-side switch 111. The second curve 350 also includes the gate-source voltage V of the slow branch high-side switch 111. GS(SWSL-H)The third curve 356. The second curve 350 also includes a fourth curve 358 showing the operation of the second synchronous rectification signal SR2 used to control the operation of the first slow branch switch 300, which acts as the slow branch low-side switch 112. The second curve 350 also includes the gate-source voltage V of the first rectifier FET 310 in the first slow branch switch 300, which acts as the slow branch low-side switch 112. GS(SWSL-L) The fifth curve is 360.

[0045] At the initial time t0, the first synchronous rectified signal SR1 is in an assertion state, the high-side switch 111 of the slow branch is conductive, and the first curve 352 shows the slow branch voltage V. SL Equal to the DC output voltage V at positive output node 131 OUT When the AC line voltage V AC When the value is negative, the initial time t0 corresponds to the negative half-cycle. Subsequently, at time t1, the first synchronous rectified signal SR1 is deasserted, thus transitioning from a high-level condition to a low-level condition. This corresponds to the AC line voltage V. AC Corresponding to the zero-crossing point. At time t1, the gate-source voltage V of the high-side switch 111 in the slow branch is... GS(SWSL-H) The voltage drops to zero, thus indicating that the high-side switch 111 of the slow branch switches to a non-conductive state. Subsequently, at time t2, the second synchronous rectifier signal SR1 is asserted and transitions from a low-level condition to a high-level condition. When the AC line voltage V... AC When it is positive, this corresponds to the positive half-cycle.

[0046] From time t2 and continuing for a period of time until the subsequent time t3, the first rectifier FET 310 operates in saturation mode. The first rectifier FET 310 is also referred to as the slow branch low switch (SW). SL-L During the time period from t2 to t3, the gate-source voltage V of the first rectifier FET 310... GS(SWSL-L) The voltage is driven and maintained at an intermediate value between the highest and lowest values. Therefore, during this period between time t2 and t3, the first rectifier FET 310 operates in saturation mode to gradually change the slow branch voltage V on the second AC input node 125. SL The first curve 352 shows the slow branch voltage V. SL DC output voltage V at time t2 OUT It gradually changes and slopes back to zero volts at time t3.

[0047] At time t3, when the slow branch voltage V SL When the target voltage of zero volts is reached, curve 360 ​​shows the gate-source voltage V of the first rectifier FET 310. GS(SWSL-L)The value is at a higher level corresponding to the first rectifier FET 310 being driven to a low impedance state. Subsequently, after time t3, the fourth curve 358 shows that the second synchronous rectifier signal SR2 is deasserted at time t4, thus transitioning from a high-level condition to a low-level condition. This corresponds to the AC line voltage V. AC Corresponding to the zero-crossing point. The fifth curve 360 ​​also shows the deassertion of the synchronous rectification signal SR2 at time t4, thereby causing the gate-source voltage V of the first rectifier FET 310 to... GS(SWSL-L) The voltage drops to zero, thus putting the first rectifier FET 310 into a non-conductive state.

[0048] Figure 5 A schematic block diagram of the second slow branch switch 400 of this disclosure is shown. The second slow branch switch 400 can be used as a slow branch low-side switch 112 and / or as a slow branch high-side switch 111 in the PFC converter 101. However, for the sake of simplicity, the second slow branch switch 400 is shown and described as a low-side switch configured to selectively conduct current between the second AC input node 125 and the negative output node 132 of the PFC converter 101. The current description of the second slow branch switch 400 includes several references to voltages at different terminals. The described voltages may each be relative to the negative output node 132, which may be connected to ground.

[0049] The second slow branch switch 400 includes a second rectifier FET 410 having a drain terminal, a source terminal, and a gate terminal, respectively labeled D, S, and G. The drain terminal D of the second rectifier FET 410 is connected to the second AC input node 125, and the source terminal S of the second rectifier FET 410 is connected to the negative output node 132. The second rectifier FET 410 is configured to selectively conduct current between the second AC input node 125 and the negative output node 132 in response to a control voltage applied to the gate terminal G.

[0050] The second slow branch switch 400 also includes a second voltage scaler 412 connected between the second AC input node 125 and the negative output node 132. The second voltage scaler 412 is configured to operate based on the slow branch voltage V on the second AC input node 125. SL To generate the sensed voltage signal V at the second sensor terminal 418 S . Figure 5 The second voltage scaler 412 shown includes a resistive voltage divider having a third resistor 414 connected in series with a fourth resistor 416 and defining a second sensor terminal 418 between the third resistor and the fourth resistor. However, other types of voltage scalers, such as capacitive voltage dividers, can be used. The sensed voltage signal V S It can be the slow branch voltage V SLIt is a part of the resistance ratio of the third resistor 414 to the fourth resistor 416.

[0051] The second slow branch switch 400 also includes a second driver circuit 420 configured to apply a voltage to the gate G of the second rectifier FET 410 to control the operation of the second rectifier FET 410 to conduct current between the second AC input node 125 and the negative output node 132. The second driver circuit 420 defines an input terminal 421 coupled to the controller 150 for receiving a second synchronous rectified signal SR2. The second driver circuit 420 includes a current source 422 coupled to the input terminal 421 for receiving the second synchronous rectified signal SR2 as a digital input signal. The current source 422 is configured to conduct a constant current I between the second AC input node 125 and the negative output node 132 in response to the second synchronous rectified signal SR2. HV See below for reference. Figure 7 As described, the current source 422 includes operations in saturation mode to conduct a constant current I between the second AC input node 125 and the negative output node 132. HV The second FET 472.

[0052] The second driver circuit 420 of the second slow branch switch 400 includes a gate driver 424 defining an output terminal 426 and an input terminal 428. The output terminal 426 of the gate driver 424 is connected to the gate G of the second rectifier FET 410. The gate driver 424 can be used as a buffer or amplifier to apply a voltage to the gate G of the second rectifier FET 410, and this voltage is sufficient to drive the second rectifier FET 410 to a low-impedance state in response to a high level at the input terminal 428 or an assertion condition, wherein the signal at the input terminal 428 has a different voltage level and / or the current supply capability is insufficient to drive the second rectifier FET 410 to a low-impedance state.

[0053] The second driver circuit 420 of the second slow branch switch 400 also includes a comparator 430. As described below, the comparator 430 determines the sensed voltage signal V at the second sensor terminal 418. SThe voltage is lower than the target voltage because the second FET 472 of the current source 422 operates in saturation mode, and then the second rectifier FET 410 is driven to a low-impedance state. Comparator 430 defines a first input terminal 432, a second input terminal 434, and an output terminal 436. The first input terminal 432 is configured as an inverting (-) input, and the second input terminal 434 is configured as a non-inverting (+) input. However, the configurations of the first input terminal 432 and the second input terminal 434 can differ. The first input terminal 432 of comparator 430 is connected to the second sensor terminal 418 of the second voltage scaler 412, and the second input terminal 434 is connected to the reference node defining the target voltage. Figure 5 The second driver circuit 420 shown includes a reference node serving as ground (GND) to define a zero-volt target voltage. However, another voltage source can be used to define a non-zero target voltage. The comparator 430 can be configured to respond to a sensed voltage signal V at the second sensor terminal 418. S The output terminal 436 is energized with a voltage lower than the target voltage. For example, comparator 430 may include a voltage signal V sensed at the first input terminal 432. S An operational amplifier (op-amp) that drives output terminal 436 to a high-level condition (also known as the power-on state or assertion state) by a voltage less than or equal to the ground GND level voltage on the second input terminal 434.

[0054] The second driver circuit 420 of the second slow branch switch 400 further includes a set-reset (SR) latch 440 defining a set input 442, a reset input 444, and a latch output 446. The set input 442 is coupled to the output terminal 436 of the comparator 430. The reset input 444 is active low and coupled to the input terminal 421 for receiving the second synchronous rectified signal SR2. The latch output 446 is coupled to the second rectifier FET 410 to maintain the second rectifier FET 410 in a low-impedance state from the moment the output terminal 436 of the comparator 430 is energized until the second synchronous rectified signal SR2 is deasserted.

[0055] In some implementations, the latched output 446 is indirectly coupled to the second rectifier FET 410 via the gate driver 424. For example, as Figure 5 As shown, the latch output 446 of the SR latch 440 is directly coupled to the input terminal 428 of the gate driver 424. Alternatively, and if the SR latch 440 has sufficient capacity, the latch output 446 of the SR latch 440 may be directly coupled to the gate G of the second rectifier FET 410.

[0056] Figure 6 An example is shown with Figure 5The third curve 450 illustrates the operation of the slow branch bridge in the totem pole PFC of the second slow branch switch 400. The third curve 450 includes several curves 452, 454, 456, 458, and 460 illustrating various signals or conditions on a common time scale. The third curve 450 also includes a diagram showing the slow branch voltage V at the second AC input node 125. SL The first curve 452. The third curve 450 also includes a second curve 454 showing the first synchronous rectified signal SR1 used to control the operation of the slow branch high-side switch 111. The third curve 450 also includes a gate-source voltage V of the slow branch high-side switch 111. GS(SWSL-H) The third curve 456. The third curve 450 also includes a fourth curve 458 showing the second synchronous rectification signal SR2 used to control the operation of the second slow branch switch 400, which acts as the slow branch low-side switch 112. The third curve 450 also includes the gate-source voltage V of the second rectifier FET 410 in the second slow branch switch 400, which acts as the slow branch low-side switch 112. GS(SWSL-L) The fifth curve is 460.

[0057] At the initial time t0, the first synchronous rectified signal SR1 is in an assertion state, the high-side switch 111 of the slow branch is conducting, and the first curve 452 shows the slow branch voltage V. SL Equal to the DC output voltage V at positive output node 131 OUT When the AC line voltage V AC When the value is negative, the initial time t0 corresponds to the negative half-cycle. Subsequently, at time t1, the first synchronous rectified signal SR1 is deasserted, thus transitioning from a high-level condition to a low-level condition. This corresponds to the AC line voltage V. AC Corresponding to the zero-crossing point. At time t1, the gate-source voltage V of the high-side switch 111 in the slow branch is... GS(SWSL-H) The voltage drops to zero, thus indicating that the slow branch high-side switch 111 switches to the non-conductive state. The slow branch high-side switch 111 is also known as the slow branch high switch (SW). SL-H Subsequently, at time t2, the second synchronous rectified signal SR1 is asserted and transitions from a low-level condition to a high-level condition. When the AC line voltage V AC When it is positive, this corresponds to the positive half-cycle.

[0058] Current source 422 is activated starting at time t2 and remains activated for a period of time until a subsequent time t3, thereby enabling the second FET 472 to operate in saturation mode to conduct a constant current I between the second AC input node 125 and the negative output node 132. HV The first curve 452 shows the slow branch voltage V due to the current conducted by current source 422. SL DC output voltage V at time t2OUT It gradually changes and slopes back to zero volts at time t3.

[0059] At time t3, when the slow branch voltage V SL When the target voltage of zero volts is reached, curve 460 shows the gate-source voltage V of the energized second rectifier FET 410 corresponding to the second rectifier FET 410 being driven to a low-impedance state. GS(SWSL-L) The second rectifier FET 410 is also known as the slow branch low switch (SW). SL-L Subsequently, after time t3, the fourth curve 458 shows that the second synchronous rectified signal SR2 is deasserted at time t4, thus transitioning from a high-level condition to a low-level condition. This corresponds to the AC line voltage V. AC Corresponding to the zero-crossing point. The fifth curve 460 also shows the deassertion of the synchronous rectifier signal SR2 at time t4, causing the SR latch 440 to de-energize the latched output 446, and thereby reducing the gate-source voltage V of the second rectifier FET 410. GS(SWSL-L) The voltage drops to zero, thereby putting the second rectifier FET 410 into a non-conductive state.

[0060] Figure 7 It shows Figure 5 A schematic diagram of the current source 422 of the second slow branch switch 400. Figure 7 The schematic diagram shown illustrates the selective conduction of a constant current I between the second AC input node 125 and the negative output node 132 of the PFC converter 101. HV The simplified example circuit is shown below. However, other circuit designs can be used to form the current source 422.

[0061] Current source 422 includes a switch to selectively enable current source 422 to conduct a constant current I between the second AC input node 125 and the negative output node 132 of PFC converter 101. HV The first FET 470 defines a drain terminal, a source terminal, and a gate terminal, respectively labeled D, S, and G. The gate terminal G of the first FET 470 is connected to an input terminal 421 for receiving a second synchronous rectified signal SR2. The drain terminal D of the first FET 470 is connected to a second AC input node 125. Therefore, the first FET 470 selectively conducts a constant current I between the second AC input node 125 and the source terminal of the first FET based on the logic level condition of the second synchronous rectified signal SR2. HV When the second synchronous rectification signal SR2 is high, the first FET 470 is conductive, allowing the current source 422 to conduct a constant current I between the second AC input node 125 and the negative output node 132 of the PFC converter 101.HV When the second synchronous rectification signal SR2 is at a low level, the first FET 470 is in a non-conductive state, thereby preventing the constant current source 422 from conducting a constant current I between the second AC input node 125 and the negative output node 132 of the PFC converter 101. HV .

[0062] Current source 422 also includes operation in saturation mode to regulate constant current I. HV The second FET 472 defines drain, source, and gate terminals labeled D, S, and G, respectively. The gate terminal G of the second FET 472 is connected to the negative output node 132. The drain terminal D of the second FET 472 is connected to the source terminal of the first FET 470. A resistor 474 is connected between the source terminals S of the second FET 472. A constant current I... HV The value of the quantity can depend on the resistance value of resistor 474, and can remain relatively constant as long as there is sufficient voltage between the second AC input node 125 and the negative output node 132.

[0063] Figure 8 The flowchart illustrates a method 500 for operating a power factor correction (PFC) converter. According to some embodiments of this disclosure, various functions of method 500 can be performed by controller 150. As will be understood from this disclosure, the sequence of operations within this method is not limited to... Figure 8 The executive sequence is not applicable; execution may be performed in one or more different sequences as needed and in accordance with this disclosure.

[0064] To simplify the explanation, method 700 is... Figure 8 The methods described herein are a series of operations. However, these operations may be performed in various orders and / or simultaneously, and / or together with other operations not presented and described herein. Additionally, for ease of explanation, method 500 is... Figure 8 Depicting and combining Figure 1 The examples shown in the text have Figure 3 The PFC converter 101, which serves as the first slow branch switch 300 used as the slow branch low-side switch 112, is described. However, the operation of method 500 can be applied to PFC converters with... Figure 3 The first slow branch switch 300, which serves as the high-side switch 111 of the slow branch, or has Figure 5 Other totem-pole PFC converter designs (such as,) used as the second slow branch switch 400 for either or both of the slow branch high-side switch 111 and / or slow branch low-side switch 112. Figure 1 The PFC converter 101 is illustrated in the figure.

[0065] At block 502, an AC power source is coupled to a first AC input node and a second AC input node to apply an AC voltage between the first AC input node and the second AC input node. For example, and referring to... Figure 1 Box 502 may include an AC power source 102 that applies an AC line voltage V between the first AC input node 124 and the second AC input node 125. AC .

[0066] At box 504, current is conducted between the first AC input node and the fast branch switch node by an inductor. For example, and referring to... Figure 1 Block 504 may include an inductor 104 that conducts current between the first AC input node 124 of the PFC converter 101 and the fast branch switch node 123.

[0067] At block 506, a DC output voltage is generated between the positive and negative output nodes by the fast branch selectively conducting current between the fast branch switching node and each of the following: the positive output node and the negative output node. For example, and referring to... Figure 1 Block 506 may include controller 150 commanding the high-side fast tributary switch 121 of fast tributary 120 to selectively conduct current between fast tributary switch node 123 and positive output node 131 of PFC converter 101. Block 506 may also include controller 150 commanding the low-side fast tributary switch 122 of fast tributary 120 to selectively conduct current between fast tributary switch node 123 and negative output node 132 of PFC converter 101.

[0068] At box 508, the slow branch high-side switch selectively conducts current between the second AC input node and the positive output node. For example, and referring to... Figure 1 Block 508 may include controller 150 commanding slow branch high-side switch 111 of slow branch 110 to selectively conduct current between second AC input node 125 and positive output node 131 of PFC converter 101.

[0069] At block 510, the slow branch low-side switch selectively conducts current between the second AC input node and the negative output node. For example, and referring to... Figure 1 Block 510 may include controller 150 commanding slow branch low-side switch 112 to selectively conduct current between second AC input node 125 and negative output node 132 of PFC converter 101.

[0070] Boxes 508 and 510 can be adjusted according to the AC line voltage V. ACThe polarity is switched back and forth to perform synchronous rectification. In other words, the high-side switch 111 and the low-side switch 112 of the slow branch can each be driven to a conductive state at different times to rectify the AC power from the AC power source 102.

[0071] At block 512, the field-effect transistor in at least one of the slow branch low-side switch or the slow branch high-side switch is operated in saturation mode to gradually change the voltage on the second AC input node. For example, and referring to... Figure 3 Block 512 may include a first slow branch switch 300 operating a first rectifier FET 310 in saturation mode to gradually reduce the slow branch voltage V on the second AC input node 125 during a time period between time t2 and t3. SL ,like Figure 4 The graph is shown. In another example, and referring to... Figure 5 and Figure 7 Block 512 may include a second FET 472 operating the current source 422 in saturation mode to conduct a constant current between the second AC input node 125 and the negative output node 132, thereby gradually reducing the slow branch voltage V on the second AC input node 125 during the time period between time t2 and t3. SL ,like Figure 6 The curve is shown in the figure.

[0072] In some implementations, block 512 includes field-effect transistors in each of the slow branch low-side switch and the slow branch high-side switch that operate in saturation mode to gradually change the voltage on the second AC input node. For example, a totem-pole PFC converter may be configured with both a slow branch high-side switch 111 and a slow branch low-side switch 112 that include circuitry similar to or identical to that of the first slow branch switch 300 and / or the second slow branch switch 400.

[0073] In some embodiments, method 500 may further include: determining, by an amplifier, that the voltage at the second AC input node has reached a target voltage due to the field-effect transistor operating in saturation mode; and driving the field-effect transistor to a low-impedance state in response to determining that the voltage at the second AC input node has reached the target voltage. For example, and referring to Figure 3 The first slow branch switch 300, when the slow branch voltage V on the second AC input node 125... SL When the target voltage of zero volts is reached, the sensed voltage signal V is measured because the first rectifier FET 310 operates in saturation mode. S It also reaches zero. Then, amplifier 330 can sense the voltage signal V. S The signal is compared with a reference signal REF. When the sensed voltage signal V... SWhen the voltage reaches zero, amplifier 330 can apply a predetermined maximum voltage to the gate G of the first rectifier FET 310, which is sufficient to drive the first rectifier FET 310 to a low impedance state.

[0074] In some embodiments, method 500 may further include: generating a sensed voltage signal based on the voltage at the second AC input node by a voltage scaler coupled to the second AC input node, and determining that the voltage at the second AC input node reaches a target voltage further includes comparing the sensed voltage signal with a reference voltage by an amplifier. For example, and the reference... Figure 3 The first slow branch switch 300 and the first voltage scaler 312 can be based on the slow branch voltage V on the second AC input node 125. SL To generate a sensed voltage signal V at the first sensor terminal 318 S Furthermore, amplifier 330 can sense the voltage signal V S The voltage V on the slow branch at the second AC input node 125 is compared with the reference signal REF to determine the voltage V. SL The target voltage has been reached.

[0075] In some embodiments, method 500 may further include: generating a sensed voltage signal based on the voltage at the second AC input node by a voltage scaler coupled to the second AC input node; gradually changing a reference signal by a reference signal generator in response to a digital input signal; and generating a drive voltage at an output terminal by an amplifier based on the difference between the sensed voltage signal and the reference signal, wherein the output terminal is connected to the gate of a field-effect transistor, and wherein generating the drive voltage at the output terminal causes the field-effect transistor to operate in saturation mode to gradually change the voltage at the second AC input node. For example, and referring to... Figure 3 The first slow branch switch 300 and the first voltage scaler 312 can be based on the slow branch voltage V on the second AC input node 125. SL To generate a sensed voltage signal V at the first sensor terminal 318 S Additionally, the reference signal generator 322 may, in response to the assertion of a second synchronous rectified signal SR2, reduce the voltage at the reference output terminal 324 in a linear manner (e.g., by transitioning from a low-level condition to a high-level condition). Additionally, the amplifier 330 may, based on the sensed voltage signal V... S The difference between the reference signal REF and the reference signal is used to generate a drive voltage DRV at the output terminal 336 connected to the gate G of the first rectifier FET 310, and thus causes the first rectifier FET 310 to operate in saturation mode to gradually change the slow branch voltage V on the second AC input node 125 during the time period during which the reference signal REF on the reference output terminal 324 is changed by the reference signal generator 322.SL .

[0076] In some embodiments, method 500 may further include: responding to a digital input signal and conducting a constant current between a second AC input node and a corresponding positive or negative output node via a current source, wherein the current source may include a field-effect transistor operating in saturation mode to gradually change the voltage on the second AC input node. For example, and referring to... Figure 5 The second slow branch switch 400 and Figure 7 The current source 422 can operate in saturation mode. The second FET 472 of the current source 422 conducts a constant current between the second AC input node 125 and the negative output node 132, thereby gradually reducing the slow branch voltage V on the second AC input node 125 during the time period between time t2 and t3. SL ,like Figure 6 The graph is shown below.

[0077] In some embodiments, method 500 may further include: selectively conducting current between a second field-effect transistor and a corresponding one of a second AC input node and a positive output node or a negative output node. For example, and referring to... Figure 5 The second slow branch switch 400 and the second rectifier FET 410 can selectively conduct current between the second AC input node 125 and the negative output node 132 in the parallel path to the current source 422.

[0078] In some embodiments, method 500 may further include driving the second field-effect transistor to a low-impedance state by the comparator responding to a target voltage reached due to the field-effect transistor operating in saturation mode. For example, and referring to Figure 5 The second slow branch switch 400 and comparator 430 can determine the sensed voltage signal V on the second sensor terminal 418. S The voltage is lower than the target voltage because the second FET 472 of the current source 422 is operating in saturation mode. This is because the sensed voltage signal V... S V represents the slow branch voltage V on the second AC input node 125. SL Therefore, the sensed voltage signal V on the second sensor terminal 418 is determined. S The voltage being less than the target voltage can also be used to determine the slow branch voltage V on the second AC input node 125. SL The corresponding target voltage value is reached. Then, comparator 430 can determine the slow branch voltage V on the second AC input node 125 in response. SL The second rectifier FET 410 is driven to a low impedance state to reach the corresponding target voltage value.

[0079] In some implementations, method 500 may further include: generating a sensed voltage signal based on the voltage at the second AC input node by a voltage scaler coupled to the second AC input node; and monitoring the sensed voltage signal and the target voltage by a comparator. For example, and referring to Figure 5 The second slow branch switch 400 and the second voltage scaler 412 can be based on the slow branch voltage V on the second AC input node 125. SL To generate the sensed voltage signal V at the second sensor terminal 418 S Comparator 430 can monitor the sensed voltage signal V on the first input terminal 432. S Each of the target voltages on the second input terminal 434 is used to determine the sensed voltage signal V on the second sensor terminal 418. S Less than the target voltage.

[0080] In some embodiments, method 500 may further include: energizing an output terminal by a comparator in response to a sensed voltage signal being less than a target voltage, wherein the output terminal is coupled to a set input of a set-reset (SR) latch; and maintaining a second field-effect transistor in a low-impedance state by energizing the SR latch in response to the set input. For example, and referring to Figure 5 The set input 442 of the second slow branch switch 400 SR latch 440 is coupled to the output terminal 436 of the comparator 430. The latched output 446 of the SR latch 440 is coupled to the second rectifier FET 410 to maintain the second rectifier FET 410 in a low impedance state when the output terminal 436 of the comparator 430 is energized, and to continue until the second synchronous rectifier signal SR2 is deasserted.

[0081] The foregoing discussion is intended to illustrate the principles and various embodiments of the invention. Once the foregoing disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. The following claims are intended to encompass all such variations and modifications.

Claims

1. A power factor correction (PFC) converter, the power factor correction (PFC) converter comprising: A totem pole network having a first AC input node and a second AC input node, the first AC input node and the second AC input node being configured together to be coupled to an AC power source; An inductor, wherein the inductor is connected between the first AC input node and the fast branch switch node; A fast branch, the fast branch being configured to generate a DC output voltage between a positive output node and a negative output node by selectively conducting current between the fast branch switching node and each of the following: the positive output node and the negative output node; and The slow branch includes a slow branch high-side switch and a slow branch low-side switch, wherein the slow branch high-side switch is configured to selectively conduct current between the second AC input node and the positive output node, and wherein the slow branch low-side switch is configured to selectively conduct current between the second AC input node and the negative output node. At least one of the slow branch low-side switch or the slow branch high-side switch includes a field-effect transistor configured to operate in saturation mode to gradually change the voltage on the second AC input node.

2. The power factor correction (PFC) converter of claim 1, wherein the slow branch low-side switch comprises the field-effect transistor configured to operate in the saturation mode to gradually change the voltage on the second AC input node, and The slow branch high-side switch includes another field-effect transistor configured to operate in the saturation mode to gradually change the voltage on the second AC input node.

3. The power factor correction (PFC) converter of claim 1, wherein at least one of the slow branch low-side switch or the slow branch high-side switch further comprises an amplifier, wherein the amplifier is configured to drive the field-effect transistor to a low-impedance state in response to the voltage at the second AC input node reaching a target voltage due to the operation of the field-effect transistor in the saturation mode.

4. The power factor correction (PFC) converter of claim 3, wherein at least one of the slow branch low-side switch or the slow branch high-side switch further comprises a voltage scaler, the voltage scaler being coupled to the second AC input node and configured to generate a sensed voltage signal based on the voltage at the second AC input node, and The amplifier is configured to compare the sensed voltage signal with a reference voltage to determine if the voltage at the second AC input node reaches the target voltage.

5. The power factor correction (PFC) converter of claim 3, wherein at least one of the slow branch low-side switch or the slow branch high-side switch further comprises: A voltage scaler, which is coupled to the second AC input node and configured to generate a sensed voltage signal based on the voltage on the second AC input node; and A reference signal generator, configured to gradually change a reference signal in response to a digital input signal. The amplifier defines an output terminal connected to the gate of the field-effect transistor, a first input terminal connected to the reference signal generator for monitoring the reference signal, and a second input terminal connected to the voltage scaler for monitoring the sensed voltage signal. The amplifier is further configured to generate a drive voltage at the output terminal based on the difference between the sensed voltage signal and the reference signal, thereby causing the field-effect transistor to operate in the saturation mode to gradually change the voltage at the second AC input node.

6. The power factor correction (PFC) converter of claim 1, wherein at least one of the slow branch low-side switch or the slow branch high-side switch further comprises a current source configured to conduct a constant current between the second AC input node and a corresponding one of the positive output node or the negative output node in response to a digital input signal, and The current source includes the field-effect transistor configured to operate in the saturation mode.

7. The power factor correction (PFC) converter of claim 1, wherein at least one of the slow branch low-side switch or the slow branch high-side switch further comprises a second field-effect transistor configured to selectively conduct current between the second AC input node and a corresponding one of the positive output node or the negative output node.

8. The power factor correction (PFC) converter of claim 7, wherein at least one of the slow branch low-side switch or the slow branch high-side switch further comprises a comparator configured to drive the second field-effect transistor to a low-impedance state in response to the voltage at the second AC input node reaching a target voltage due to the operation of the field-effect transistor in the saturation mode.

9. The power factor correction (PFC) converter of claim 8, wherein at least one of the slow branch low-side switch or the slow branch high-side switch further comprises: A voltage scaler, which is coupled to the second AC input node and configured to generate a sensed voltage signal based on the voltage on the second AC input node; and The comparator is defined as a first input terminal connected to the voltage scaler for monitoring the sensed voltage signal and a second input terminal connected to a reference node defining the target voltage.

10. The power factor correction (PFC) converter of claim 9, wherein the comparator defines an output terminal, and wherein the comparator is configured to energize the output terminal in response to a sensed voltage signal at the first input terminal being less than a target voltage at the second input terminal, and The at least one of the slow branch low-side switch or the slow branch high-side switch further includes: A set-reset (SR) latch defines a set input coupled to the output terminal of the comparator and a latch output coupled to the second field-effect transistor for maintaining the second field-effect transistor in the low-impedance state.

11. A method for operating a power factor correction (PFC) converter, the method comprising: An AC power source is coupled to a first AC input node and a second AC input node to apply an AC voltage between the first AC input node and the second AC input node; The inductor conducts current between the first AC input node and the fast branch switch node; A DC output voltage is generated between the positive output node and the negative output node by a fast branch selectively conducting current between the fast branch switching node and each of the following: the positive output node and the negative output node; The high-side switch of the slow branch selectively conducts current between the second AC input node and the positive output node; The slow branch low-side switch selectively conducts current between the second AC input node and the negative output node; as well as In saturation mode, the field-effect transistor in at least one of the slow branch low-side switch or the slow branch high-side switch is operated to gradually change the voltage on the second AC input node.

12. The method of claim 11, wherein operating the field-effect transistor in at least one of the slow branch low-side switch or the slow branch high-side switch in saturation mode to gradually change the voltage on the second AC input node comprises: In the saturation mode, the field-effect transistors in each of the slow branch low-side switch and the slow branch high-side switch are operated to gradually change the voltage on the second AC input node.

13. The method according to claim 11, further comprising: The voltage at the second AC input node is determined by the amplifier to reach the target voltage due to the operation of the field-effect transistor in the saturation mode; as well as In response to determining that the voltage on the second AC input node has reached the target voltage, the field-effect transistor is driven to a low-impedance state.

14. The method according to claim 13, further comprising: A voltage scaler coupled to the second AC input node generates a sensed voltage signal based on the voltage at the second AC input node, and The determination that the voltage on the second AC input node reaches the target voltage further includes: the amplifier comparing the sensed voltage signal with a reference voltage.

15. The method according to claim 13, further comprising: A sensed voltage signal is generated by a voltage scaler coupled to the second AC input node based on the voltage on the second AC input node; The reference signal is gradually changed by the reference signal generator in response to the digital input signal; as well as An amplifier generates a drive voltage at an output terminal based on the difference between the sensed voltage signal and the reference signal, wherein the output terminal is connected to the gate of the field-effect transistor, and wherein generating the drive voltage at the output terminal causes the field-effect transistor to operate in the saturation mode to gradually change the voltage at the second AC input node.

16. The method according to claim 11, further comprising: In response to a digital input signal and through a current source, a constant current is conducted between the second AC input node and the corresponding one of the positive output node or the negative output node, and The current source includes the field-effect transistor that operates in the saturation mode to gradually change the voltage on the second AC input node.

17. The method according to claim 11, further comprising: The second field-effect transistor selectively conducts current between the second AC input node and the corresponding one of the positive output node or the negative output node.

18. The method according to claim 17, further comprising: The comparator responds to the voltage at the second AC input node reaching the target voltage due to the operation of the field-effect transistor in the saturation mode, thereby driving the second field-effect transistor to a low-impedance state.

19. The method according to claim 18, further comprising: A sensed voltage signal is generated by a voltage scaler coupled to the second AC input node based on the voltage on the second AC input node; as well as The comparator monitors the sensed voltage signal and the target voltage.

20. The method according to claim 19, further comprising: The comparator energizes an output terminal in response to the sensed voltage signal being less than the target voltage, wherein the output terminal is coupled to the set input of a set-reset (SR) latch; as well as The set-reset (SR) latch maintains the second field-effect transistor in the low-impedance state in response to the set input being energized.

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