Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention relates to a solar cell, a solar cell and a preparation method thereof, and a photovoltaic module. The solar cell includes: a semiconductor substrate; the first tunneling layer is located on the surface of one side of the semiconductor substrate; the carbon-doped polycrystalline silicon layer is located on the surface of the side, away from the semiconductor substrate, of the first tunneling layer; the second tunneling layer is located on the surface of the side, away from the first tunneling layer, of the carbon-doped polycrystalline silicon layer; the doped polycrystalline silicon layer is located on the surface of the side, away from the carbon-doped polycrystalline silicon layer, of the second tunneling layer, the first passivation layer is electrically connected with the doped polycrystalline silicon layer, and ohmic contact is achieved through the first electrode and the doped polycrystalline silicon layer; the second tunneling layer is in contact with the doped polycrystalline silicon layer on the outer layer and can block the metal slurry of the metal electrode; the carbon-doped polycrystalline silicon layer has an anti-corrosion effect on the metal slurry, can inhibit the corrosion of the slurry to the semiconductor substrate and the first tunneling layer, can improve the contact stability, and can improve the conversion efficiency of the solar cell.

Description

Technical Field

[0001] This application relates to the field of solar photovoltaic cell technology, and in particular to a solar cell, a method for preparing the same, and a photovoltaic module. Background Technology

[0002] In solar cells, those with tunneling oxide passivation contact structures have become one of the mainstream technologies in the industry. A typical tunneling oxide passivation contact structure includes a tunneling oxide layer and a doped silicon thin film layer. This tunneling oxide passivation contact structure can effectively reduce surface recombination and metal-to-metal contact recombination, thereby improving the cell's conversion efficiency.

[0003] In related technologies, the passivation effect of passivated contact structures in solar cells is relatively poor. Summary of the Invention

[0004] Therefore, it is necessary to provide a solar cell, its preparation method, and a photovoltaic module to address the above-mentioned problems.

[0005] In a first aspect, embodiments of this application provide a solar cell, comprising:

[0006] Semiconductor substrate;

[0007] The first tunneling layer is located on one side surface of the semiconductor substrate;

[0008] A carbon-doped polycrystalline silicon layer is located on the side of the first tunneling layer facing away from the semiconductor substrate;

[0009] The second tunneling layer is located on the side surface of the carbon-doped polycrystalline silicon layer that is away from the first tunneling layer.

[0010] A doped polycrystalline silicon layer is located on the side surface of the second tunneling layer opposite to the carbon-doped polycrystalline silicon layer; wherein the conductive dopant element of the carbon-doped polycrystalline silicon layer has the same conductivity type as the conductive dopant element of the carbon-doped polycrystalline silicon layer.

[0011] The first passivation layer is located on the surface of the doped polysilicon layer opposite to the second tunneling layer.

[0012] The first electrode is located on the side of the first passivation layer away from the doped polysilicon layer, and the first electrode is in electrical contact with the doped polysilicon layer.

[0013] In one exemplary embodiment, along the direction gradually away from the semiconductor substrate, in the thickness direction of the solar cell, the carbon concentration near the first tunneling layer in the carbon-doped polycrystalline silicon layer is lower than the carbon concentration of the first passivation layer.

[0014] In one exemplary embodiment, the carbon concentration in the carbon-doped polycrystalline silicon layer ranges from 1 × 10⁻⁶. 20atoms / cm 3 -5×10 21 atoms / cm 3 .

[0015] In one exemplary embodiment, the concentration of conductive dopant elements in the carbon-doped polysilicon layer is lower than the concentration of conductive dopant elements in the doped polysilicon layer.

[0016] In one exemplary embodiment, the thickness of the doped polycrystalline silicon layer ranges from 30 nm to 130 nm.

[0017] In one exemplary embodiment, the total thickness of the first tunneling layer, the carbon-doped polysilicon layer, the second tunneling layer, and the doped polysilicon layer ranges from 40 nm to 200 nm.

[0018] In one exemplary embodiment, the conductive dopant element is phosphorus or boron.

[0019] In one exemplary embodiment, the first electrode penetrates the first passivation layer and is disposed in contact with the doped polysilicon layer; wherein,

[0020] The depth to which the first electrode is pressed into the doped polysilicon layer is less than the thickness of the doped polysilicon layer.

[0021] In one exemplary embodiment, the solar cell further includes:

[0022] The emitter is located on the side surface of the semiconductor substrate opposite to the first tunneling layer;

[0023] The second passivation layer is located on the side of the emitter facing away from the semiconductor substrate;

[0024] The second electrode is in contact with the emitter.

[0025] Secondly, embodiments of this application provide a method for preparing a solar cell, the method comprising:

[0026] Provide semiconductor substrates;

[0027] A first tunneling layer is formed on one side surface of the semiconductor substrate;

[0028] A carbon-doped amorphous silicon layer is formed on the side of the first tunneling layer facing away from the semiconductor substrate;

[0029] A second tunneling layer is formed on the side of the carbon-doped amorphous silicon layer opposite to the first tunneling layer;

[0030] A doped amorphous silicon layer is formed on the side of the second tunneling layer opposite to the carbon-doped amorphous silicon layer; wherein the conductive doping element of the carbon-doped amorphous silicon layer has the same conductivity type as the conductive doping element of the doped amorphous silicon layer.

[0031] The obtained structure is subjected to annealing treatment; wherein, after annealing treatment, the carbon-doped amorphous silicon layer is converted into a carbon-doped polycrystalline silicon layer, and the doped amorphous silicon layer is converted into a doped polycrystalline silicon layer.

[0032] A first passivation layer is formed on the side of the doped polysilicon layer opposite to the second tunneling layer;

[0033] A first electrode is formed on the side of the first passivation layer opposite to the doped polysilicon layer; the first electrode is in electrical contact with the doped polysilicon layer.

[0034] In an exemplary embodiment, forming a carbon-doped amorphous silicon layer on the surface of the first tunneling layer opposite to the semiconductor substrate includes:

[0035] A first gas source is introduced to form a first sub-carbon-doped amorphous silicon layer on the side surface of the first tunneling layer opposite to the semiconductor substrate;

[0036] A second gas source is introduced to form a second sub-carbon-doped amorphous silicon layer on the surface of the first sub-carbon-doped amorphous silicon layer away from the first tunneling layer; wherein, the first gas source and the second gas source respectively include: a silicon source, a carbon source and a conductive doping source, the carbon source gas flow rate ratio in the second gas source is greater than the carbon source gas flow rate ratio in the first gas source, and the phosphorus source gas flow rate ratio in the second gas source is greater than the phosphorus source gas flow rate ratio in the first gas source.

[0037] In an exemplary embodiment, the silicon source is silane and the carbon source is methane; wherein, in the second gas source, the gas flow rate ratio of silane to methane is in the range of 1:3.

[0038] In one exemplary embodiment, the silicon source is silane, the carbon source is methane, and the conductive dopant source is hydrodiluted phosphine; wherein,

[0039] In the first gas source, the gas flow rate of silane ranges from 2000 to 6000 sccm, the gas flow rate of phosphine ranges from 50 to 300 sccm, the gas flow rate of hydrogen ranges from 5000 to 12000 sccm, and the gas flow rate of methane ranges from 50 to 500 sccm.

[0040] In the second gas source, the gas flow rate of silane ranges from 2000 to 6000 sccm, the gas flow rate of phosphine ranges from 300 to 900 sccm, the gas flow rate of hydrogen ranges from 5000 to 12000 sccm, and the gas flow rate of methane ranges from 2000 to 6000 sccm.

[0041] In an exemplary embodiment, forming a doped amorphous silicon layer on the surface of the second tunneling layer opposite to the carbon-doped amorphous silicon layer includes:

[0042] A third gas source is introduced to form a doped amorphous silicon layer on the surface of the second tunneling layer opposite to the carbon-doped polycrystalline silicon layer. The third gas source includes silane and a conductive dopant source.

[0043] The proportion of the gas flow rate of the conductive doped source in the third gas source is greater than the proportion of the gas flow rate of the conductive doped source in the second gas source.

[0044] In an exemplary embodiment, the flow rate of silane in the third gas source ranges from 2000 to 6000 sccm, the flow rate of phosphine ranges from 900 to 1500 sccm, and the flow rate of hydrogen ranges from 5000 to 12000 sccm.

[0045] In an exemplary embodiment, forming a carbon-doped amorphous silicon layer on the surface of the first tunneling layer opposite to the semiconductor substrate further includes:

[0046] An intrinsic amorphous silicon layer is formed on the side of the first tunneling layer away from the semiconductor substrate using silane and hydrogen; wherein, after annealing, the intrinsic amorphous silicon layer is converted into a partially doped polycrystalline silicon layer.

[0047] In an exemplary embodiment, before forming a carbon-doped amorphous silicon layer on the surface of the first tunneling layer facing away from the semiconductor substrate, the method further includes:

[0048] An emitter is formed on the side of the semiconductor substrate opposite to the first tunneling layer;

[0049] Before forming the first electrode on the side of the doped polysilicon layer opposite to the second tunneling layer, the method further includes:

[0050] A second passivation layer is formed on the surface of the emitter facing away from the semiconductor substrate;

[0051] The method further includes:

[0052] A second electrode is formed, and the second electrode is in contact with the emitter.

[0053] In one exemplary embodiment, the first electrode and the second electrode are formed in a manner including:

[0054] Silver paste is applied to the first passivation layer and the second passivation layer using printing technology to form a predetermined first electrode pattern and a second electrode pattern, respectively.

[0055] The resulting structure is subjected to laser sintering to form the first electrode and the second electrode; wherein the bias voltage of the laser sintering is less than the reference voltage.

[0056] Thirdly, embodiments of this application provide a photovoltaic module, including at least one battery string, wherein the battery string includes at least two solar cells prepared by the aforementioned method for manufacturing solar cells, or, as described above, solar cells.

[0057] In the aforementioned solar cell, its fabrication method, and photovoltaic module, the doped polycrystalline silicon layer serves as a contact layer, electrically connected to the first electrode of the solar cell to form an ohmic contact. Since the doped polycrystalline silicon layer is a carbon-free polycrystalline silicon layer, it does not reduce the activation concentration of active doping atoms (e.g., phosphorus) in the doped polycrystalline silicon layer, ensuring good contact between the doped polycrystalline silicon layer and the metal electrode. Furthermore, the second tunneling layer contacts the outer doped polycrystalline silicon layer, blocking the metal paste (e.g., silver paste) from penetrating the outer doped polycrystalline silicon layer during sintering and contacting the carbon-doped polycrystalline silicon layer located in the middle layer. Additionally, the carbon-doped polycrystalline silicon layer in the middle layer provides corrosion resistance to the metal paste, inhibiting the erosion of the semiconductor substrate and the first tunneling layer by corrosive components in the paste (e.g., glass phase, organic carrier residues, metal ions), while also preventing itself from being damaged by the metal paste. This improves passivation and contact stability, thereby increasing the conversion efficiency of the solar cell. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 A cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0060] Figure 2a A schematic diagram of the surface morphology of doped polycrystalline silicon;

[0061] Figure 2b This is a schematic diagram of the surface morphology of a carbon-doped polycrystalline silicon layer;

[0062] Figure 3 This is a schematic diagram of the cross-sectional structure of a solar cell provided in another embodiment of this application;

[0063] Figure 4 A schematic flowchart illustrating a method for fabricating a solar cell according to an embodiment of this application;

[0064] Figure 5 A schematic flowchart illustrating a method for fabricating a solar cell according to another embodiment of this application;

[0065] Figure 6 A schematic flowchart illustrating a method for fabricating a solar cell according to another embodiment of this application;

[0066] Figure 7 This is a schematic diagram of the ECV curves of an exemplary embodiment 1 and a comparative embodiment 1 of this application;

[0067] Figure 8 This is a schematic diagram of the SIMS curve (total carbon concentration) of an exemplary embodiment 1 and a comparative embodiment 1 of this application;

[0068] Figure 9 This is a schematic diagram of the SIMS curve (total hydrogen concentration) of an exemplary embodiment 1 and a comparative embodiment 1 of this application;

[0069] Figure 10 This is a schematic diagram of the SIMS curve (total phosphorus concentration) of an exemplary embodiment 1 and a comparative embodiment 1 of this application.

[0070] Figure label:

[0071] 110 - Semiconductor substrate; 120 - First tunneling layer; 130 - Carbon-doped polycrystalline silicon layer;

[0072] 140 - Second tunneling layer; 150 - Doped polysilicon layer; 170 - Emitter;

[0073] 181 - First passivation layer; 182 - First antireflection layer; 191 - Second passivation layer; 192 - Second antireflection layer;

[0074] 101 - First electrode; 102 - Second electrode. Detailed Implementation

[0075] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0076] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0077] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0078] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0079] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0080] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the application.

[0081] This application provides a solar cell. Exemplary types of solar cells include, but are not limited to, TOPCon cells, hybrid passivated back contact (HTBC) cells, tunnel oxide passivated back contact (TBC) cells, heterojunction back contact (HBC) cells, and heterojunction with intrinsic thin-layer (HJT) cells. The solar cells include, but are not limited to, bifacial poly structures and polyfinger structures. For example, the TOPCon cell provided in this application improves the cell conversion efficiency by more than 0.05%. This efficiency improvement mainly comes from the increase in open circuit voltage (Voc) and short circuit current (Isc). Compared to conventional TOPCon cells, the TOPCon cell has a Voc increase of more than 1mV and a short circuit current Isc increase of 2-30mA.

[0082] like Figure 1 As shown, in an exemplary embodiment, the solar cell includes a semiconductor substrate 110, and a first tunneling layer 120, a carbon-doped polycrystalline silicon layer 130, a second tunneling layer 140, a doped polycrystalline silicon layer 150, a first passivation layer 181, and a first electrode 101, which are sequentially located on one side surface of the semiconductor substrate 110. The doped polycrystalline silicon layer 150 serves as a contact layer for electrical connection between the solar cell and the first electrode 101.

[0083] Semiconductor substrate 110 includes, but is not limited to, doped semiconductor substrates made of materials such as silicon or germanium, or doped compound semiconductor substrates made of materials such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. In this embodiment, an N-type silicon substrate is used as an example for illustration.

[0084] In an optional embodiment, at least one side surface of the semiconductor substrate 110 is a pyramid light-trapping structure, which can increase light absorption and improve minority carrier lifetime.

[0085] The first tunneling layer 120 is located on one side surface of the semiconductor substrate 110. Exemplarily, the material of the first tunneling layer 120 includes, but is not limited to, SiO2, Al2O3, oxynitride, etc.

[0086] A carbon-doped polysilicon layer 130 is located on the side of the first tunneling layer 120 facing away from the semiconductor substrate 110. The carbon-doped polysilicon layer 130 can be understood as a polysilicon layer doped with an active dopant element and carbon, wherein the active dopant element can be understood as a conductive dopant element. For example, the conductivity type of the conductive dopant element in the carbon-doped polysilicon layer 130 can be N-type or P-type. For example, the conductive dopant element can be phosphorus (P) or boron (B). In this embodiment, for ease of explanation, the semiconductor substrate 110 is N-type and the conductive dopant element is P-type, such as phosphorus, for example. For instance, the carbon-doped polysilicon layer 130 is a phosphorus-doped carbon-doped polysilicon layer 130. The first tunneling layer 120 and the carbon-doped polysilicon layer 130 can form a passivation contact, achieving selective carrier transport through the electron tunneling effect (e.g., allowing electron tunneling and blocking holes), while effectively passivating the silicon surface, reducing surface recombination, and increasing the open-circuit voltage.

[0087] The second tunneling layer 140 is located on the surface of the carbon-doped polycrystalline silicon layer 130 facing away from the first tunneling layer 120. Exemplarily, the material of the second tunneling layer 140 includes, but is not limited to, SiO2, Al2O3, and oxides of nitrogen. In the embodiments of this application, the materials of the first tunneling layer 120 and the second tunneling layer 140 can be the same or different. For ease of explanation, this example uses SiO2 layers as both the first tunneling layer 120 and the second tunneling layer 140 as an example.

[0088] A doped polysilicon layer 150 is located on the surface of the second tunneling layer 140 opposite to the carbon-doped polysilicon layer 130. The doped polysilicon layer 150 is a carbon-free polysilicon layer, and the conductivity type of the conductive dopant element in the doped polysilicon layer 150 is the same as that in the carbon-doped polysilicon layer 130. For example, the conductive dopant element in the doped polysilicon layer 150 may be the same as that in the carbon-doped polysilicon layer 130; for instance, the doped polysilicon layer 150 may be a phosphorus-doped polysilicon layer. Optionally, the conductive dopant element in the doped polysilicon layer 150 may be different from that in the carbon-doped polysilicon layer 130. For example, the conductive dopant element in the doped polysilicon layer 150 and the conductive dopant element in the carbon-doped polysilicon layer 130 may have the same conductivity type, but different conductive dopant elements. These conductive dopant elements include, but are not limited to, phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). In the embodiments of this application, the specific elements of the conductive dopant elements of the doped polysilicon layer 150 and the conductive dopant elements of the carbon-doped polysilicon layer 130 are not limited.

[0089] The first passivation layer 181 is located on the surface of the doped polysilicon layer 150 opposite to the second tunneling layer 140. Exemplarily, the material of the first passivation layer 181 may include aluminum oxide. In optional embodiments, the material of the first passivation layer 181 includes aluminum oxide, and also includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. Exemplarily, the first passivation layer 181 may be a single-layer structure of aluminum oxide. In optional embodiments, the first passivation layer 181 may also be a multilayer structure, where each layer may be made of the same or different materials; this is not limited in this embodiment. In this embodiment, a passivation material may be deposited, and then the first passivation layer 14 may be formed by a process such as high-temperature (e.g., temperature > 250°C) annealing.

[0090] In an optional embodiment, the solar cell further includes a first antireflective layer 182 located on the surface of the first passivation layer 181 facing away from the doped polycrystalline silicon layer. The material of the first antireflective layer 182 includes silicon nitride. In an optional embodiment, the material of the first antireflective layer 182 includes silicon nitride, and may also include at least one of silicon oxynitride, silicon oxide, thin-film silicon, and magnesium fluoride. In an exemplary embodiment, the first antireflective layer 182 may have a single-layer structure or a multi-layer structure. For example, in a multi-layer structure of the first antireflective layer 182, the material of each layer may be silicon nitride, silicon oxynitride, silicon oxide, thin-film silicon, or magnesium fluoride, etc.

[0091] In this embodiment, by providing the first antireflection layer 182 and the first passivation layer 181, carrier recombination and surface reflectivity can be reduced, allowing more light to be transmitted into the semiconductor substrate 110, thereby further improving the photoelectric conversion efficiency of the solar cell.

[0092] The first electrode 101 is located on the side of the passivation layer opposite to the doped polycrystalline silicon layer 150. The first electrode 101 can be electrically connected to the doped polycrystalline silicon layer 150 through a transparent conductive material, or it can be connected to the doped polycrystalline silicon layer 150 through a stack penetrating the first passivation layer 181 or the first passivation layer 181 and the first antireflection layer 182. The doped polycrystalline silicon layer 150 can serve as the contact layer of a solar cell, forming an ohmic contact through the first electrode.

[0093] The solar cell provided in this application includes a semiconductor substrate, and a first tunneling layer, a carbon-doped polycrystalline silicon layer, a second tunneling layer, a doped polycrystalline silicon layer, a first passivation layer, and a first electrode, sequentially located on one side surface of the semiconductor substrate. The doped polycrystalline silicon layer is electrically connected to the first electrode to form an ohmic contact. Since the doped polycrystalline silicon layer is a carbon-free polycrystalline silicon layer, it does not reduce the activation concentration of active dopant atoms (e.g., phosphorus) in the doped polycrystalline silicon layer, ensuring good contact between the doped polycrystalline silicon layer and the metal electrode. Furthermore, the carbon-doped polycrystalline silicon layer is located on the side of the second tunneling layer closest to the semiconductor substrate. The second tunneling layer contacts the outer doped polycrystalline silicon layer, which can block the metal paste (such as silver paste) of the metal electrode, preventing the metal paste from penetrating the outer doped polycrystalline silicon layer during sintering and contacting the carbon-doped polycrystalline silicon layer located in the middle layer. In addition, the carbon-doped polycrystalline silicon layer located in the middle layer has an anti-corrosion effect on the metal paste. It can inhibit the erosion of the semiconductor substrate and the first tunneling layer by corrosive components in the paste (such as glass phase, organic carrier residue, metal ions), and at the same time, it can also prevent itself from being damaged by the metal paste. This can improve passivation and contact stability, thereby improving the conversion efficiency of the solar cell.

[0094] In an exemplary embodiment, in the thickness direction of the solar cell, the carbon concentration in the carbon-doped polycrystalline silicon layer 130 near the first tunneling layer 120 is lower than the carbon concentration in the first passivation layer 181. Specifically, the carbon concentration in the carbon-doped polycrystalline silicon layer 130 is lower closer to the first tunneling layer 120 and higher closer to the first passivation layer 181.

[0095] In an alternative embodiment, the carbon concentration in the carbon-doped polysilicon layer 150 increases in a direction gradually moving away from the semiconductor substrate 110.

[0096] In one exemplary embodiment, the carbon concentration in the carbon-doped polycrystalline silicon layer 150 ranges from 1 × 10⁻⁶. 20 atoms / cm 3 -5×10 21 atoms / cm 3 For example, the carbon concentration in the carbon-doped polycrystalline silicon layer 150 can be 1 × 10⁻⁶. 20 atoms / cm 3 2×10 20atoms / cm, 3×10 20 atoms / cm, 4×10 20 atoms / cm, 5×10 20 atoms / cm, 6×10 20 atoms / cm, 7×10 20 atoms / cm, 8×10 20 atoms / cm 3 9×10 20 atoms / cm, 1×10 21 atoms / cm, 2×10 21 atoms / cm, 3×10 21 atoms / cm, 4×10 21 atoms / cm or 5×10 21 atoms / cm 3 , or any value between any two of the above values.

[0097] In this embodiment, in the thickness direction of the solar cell, the carbon concentration near the first tunneling layer in the carbon-doped polycrystalline silicon layer is lower than that in the first passivation layer. The carbon-doped polycrystalline silicon layer near the first tunneling layer is a lightly doped structure, which helps to maintain the passivation effect of the first tunneling layer interface. The carbon-doped polycrystalline silicon layer near the second tunneling layer is a heavily phosphorus-doped and heavily carbon-doped layer. Its proximity to the doped polycrystalline silicon layer can effectively reduce the recombination rate and improve the selective transport capability of charge carriers. It can also block the metal paste (such as silver paste) of the metal electrode, preventing the metal paste from passing through the outer doped polycrystalline silicon layer during sintering and contacting the carbon-doped polycrystalline silicon layer located in the middle layer. In addition, the carbon-doped polycrystalline silicon layer located in the middle layer has an anti-corrosion effect on the metal paste. Furthermore, the carbon-doped polycrystalline silicon layers with different carbon concentration gradient distributions can control the distribution state of H in different regions of the carbon-doped polycrystalline silicon layer, thereby effectively controlling the concentration of H in the tunneling oxide layer (SiO2), and ultimately reducing the phenomenon of film bursting in the carbon-doped polycrystalline silicon layer.

[0098] In one exemplary embodiment, the concentration of conductive dopant elements in the carbon-doped polysilicon layer 150 is lower than the concentration of conductive dopant elements in the doped polysilicon layer 150. For example, the phosphorus concentration in the carbon-doped polysilicon layer 150 is lower than the phosphorus concentration in the doped polysilicon layer 150.

[0099] In this embodiment, the concentration of conductive dopant elements (e.g., phosphorus) in the outer polysilicon doped layer used to form ohmic contact with the metal electrode is higher than that in the carbon-doped polysilicon layer located in the middle layer, which helps to improve its ohmic contact with the metal electrode. In addition, in the high-temperature processes of device manufacturing (such as annealing and oxidation), the dopant atoms of high-concentration phosphorus-doped polysilicon are not easily desorbed, and the contact interface structure is stable. Furthermore, since the concentration of conductive dopant elements (e.g., phosphorus) in its polysilicon doped layer is higher, under the condition of a certain total concentration, the thickness of the polysilicon doped layer can be reduced to achieve the same ohmic contact effect, thereby reducing parasitic absorption and improving the short-circuit current of the solar cell, so as to improve the photoelectric conversion efficiency of the solar cell.

[0100] In one exemplary embodiment, the thickness of the doped polycrystalline silicon layer 150 ranges from 30 nm to 130 nm. For example, the thickness of the doped polycrystalline silicon layer 150 can be 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 10 nm, 110 nm, 120 nm, 130 nm, 140 nm, or 150 nm, or any value between any two of the above values. In this embodiment, thickness refers to the dimension in the thickness direction of the solar cell.

[0101] In an optional embodiment, the total thickness ranges from 30nm to 50nm. For example, the total thickness can be 30nm, 32nm, 34nm, 36nm, 38nm, 40nm, 42nm, 44nm, 46nm, 48nm, or 50nm, or any value between any two of the above values.

[0102] Figure 2a This is a schematic diagram of the surface morphology of the doped polycrystalline silicon layer. Figure 2b This is a schematic diagram of the surface morphology of a carbon-doped polysilicon layer. For example, it shows the surface morphology of the carbon-doped polysilicon layer after the back metal gate lines have been removed using an acid solution. The circled area in the diagram represents the exposed carbon-doped polysilicon surface layer. Figure 2a and Figure 2b As can be seen, the carbon-doped polysilicon layer has fewer corrosion pits than the doped polysilicon layer, which indicates that the carbon-doped polysilicon layer is more resistant to metal paste corrosion than the doped polysilicon layer, thus reducing the thickness requirement of the doped polysilicon layer for metal paste.

[0103] In this embodiment, by providing a second tunneling layer and a carbon-doped polycrystalline silicon layer in the middle layer, the metal paste (such as silver paste) of the metal electrode is blocked from corroding, preventing the metal paste from penetrating the outer doped polycrystalline silicon layer and contacting the carbon-doped polycrystalline silicon layer in the middle layer during sintering. Therefore, the thickness of the doped polycrystalline silicon layer in this embodiment can be reduced compared to the thickness of the doped polycrystalline silicon layer in solar cells without a carbon-doped polycrystalline silicon layer in related technologies (e.g., 70-80 nm). For example, its thickness ranges from 30 nm to 50 nm. Thus, in addition to achieving good ohmic contact with the first electrode, the doped polycrystalline silicon layer in this embodiment can also reduce parasitic absorption while meeting the depth requirements for metal paste corrosion of polycrystalline silicon and ensuring that the metal paste does not contact the carbon-doped polycrystalline silicon layer. This is beneficial for improving the short-circuit current of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell. In an exemplary embodiment, the total thickness of the first tunneling layer 120, the carbon-doped polysilicon layer 130, the second tunneling layer 140, and the doped polysilicon layer 150 ranges from 40 nm to 200 nm. For example, the total thickness of the first tunneling layer 120, the carbon-doped polysilicon layer 130, the second tunneling layer 140, and the doped polysilicon layer 150 can be 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, or any value between any two of the above values.

[0104] In an optional embodiment, the total thickness ranges from 80nm to 90nm. For example, the total thickness can be 80nm, 81nm, 82nm, 83nm, 84nm, 85nm, 86nm, 87nm, 88nm, 89nm, or 90nm, or any value between any two of the above values.

[0105] In this embodiment, the solar cell includes a semiconductor substrate and, sequentially located on one side of the semiconductor substrate, a first tunneling layer, a carbon-doped polycrystalline silicon layer, a second tunneling layer, a doped polycrystalline silicon layer, a first passivation layer, and a first electrode. By positioning each layer, the total thickness of the first tunneling layer, the carbon-doped polycrystalline silicon layer, the second tunneling layer, and the doped polycrystalline silicon layer can be controlled within the range of 80nm-90nm. Compared to related technologies that do not include a carbon-doped polycrystalline silicon layer, this reduces the thickness of the solar cell. Furthermore, it reduces parasitic absorption, which helps to increase the short-circuit current of the solar cell, thereby improving its photoelectric conversion efficiency.

[0106] In an exemplary embodiment, the first electrode 101 penetrates the first passivation layer 181 and is disposed in contact with the doped polysilicon layer 150. The depth to which the first electrode 101 is pressed into the doped polysilicon layer 150 is less than the thickness of the doped polysilicon layer 150. It should be understood that the first electrode 101 is in contact with the doped polysilicon layer 150, but not with the second tunneling layer 140 or the carbon-doped polysilicon layer 130. This avoids the possibility of poor contact between the first electrode and the doped polysilicon layer.

[0107] like Figure 3 As shown, in an exemplary embodiment, the solar cell further includes an emitter 170, a second passivation layer 191, and a second electrode 102. The emitter 170 is located on the side of the semiconductor substrate 110 facing away from the first tunneling layer 120. The emitter 170 includes, but is not limited to, a diffusion layer, a polycrystalline silicon layer, etc.

[0108] The second passivation layer 191 is located on the side surface of the emitter 170 facing away from the semiconductor substrate 110. The material of the second passivation layer 191 can refer to the material and structure of the first passivation layer 181 described above, and will not be repeated here.

[0109] In an optional embodiment, the solar cell further includes a second antireflection layer 192 located on the surface of the second passivation layer 191 facing away from the emitter 170. The material and structure of the second antireflection layer 192 can be referred to the first antireflection layer 182, and will not be described again here.

[0110] The second electrode 102 is in contact with the emitter 170. The second electrode 102 can be electrically connected to the emitter 170 through a transparent conductive material, or it can be in contact with the emitter 170 through a stack of the second passivation layer 191 or the second passivation layer 191 and the second antireflection layer 192, so as to achieve electrical connection with the doped emitter 170.

[0111] like Figure 4 As shown, this application provides a method for fabricating a solar cell. In an exemplary embodiment, the method for fabricating a solar cell includes steps 402-416.

[0112] Step 402, provide a semiconductor substrate.

[0113] Semiconductor substrate 110 includes, but is not limited to, doped semiconductor substrates made of materials such as silicon or germanium, or doped compound semiconductor substrates made of materials such as silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. In this embodiment, an N-type silicon substrate is used as an example for illustration. After providing an N-type silicon substrate, the surface dicing damage layer can be removed by alkaline polishing, and the first and second surfaces of the N-type silicon substrate, which are disposed opposite to each other, can be pre-cleaned to remove impurities on the surface of the N-type silicon substrate.

[0114] In an optional embodiment, at least one side may be texturized to form a surface pyramid light-trapping structure, increase light absorption, and improve minority carrier lifetime.

[0115] Step 404: A first tunneling layer is formed on one side surface of the semiconductor substrate.

[0116] In an exemplary embodiment, a first tunneling layer 120 may be formed on one side of a semiconductor substrate 110 using techniques such as plasma enhanced chemical vapor deposition (PECVD), thermal oxidation, or atomic layer deposition (ALD).

[0117] For ease of explanation, this embodiment uses the formation of a first tunneling layer 120 on one side of a semiconductor substrate 110 using PECVD technology as an example. The first tunneling layer 120 is an ultrathin silicon oxide layer, which can be deposited on one side of the semiconductor substrate 110 using a PECVD process. For example, the reactant gas is nitrous oxide (N2O) with a flow rate of 5000 sccm - 15000 sccm. By setting appropriate gas pressure, deposition temperature, deposition power (e.g., 10000W), and deposition time (e.g., 90-100s), an ultrathin silicon oxide layer is formed to achieve effective carrier tunneling transport and surface passivation. The flow rate of nitrous oxide (N2O) can be 5000 sccm, 6000 sccm, 7000 sccm, 8000 sccm, 9000 sccm, 10000 sccm, 11000 sccm, 12000 sccm, 13000 sccm, 14000 sccm or 15000 sccm; or a value between any two of the above values.

[0118] Step 406: A carbon-doped amorphous silicon layer is formed on the side of the first tunneling layer facing away from the semiconductor substrate.

[0119] For example, after the first tunneling layer 120 is formed, a carbon-doped amorphous silicon layer can be formed on the side of the first tunneling layer 120 away from the semiconductor substrate 110 using process technologies such as LPCVD, PECVD, PEALD, hot filament chemical vapor deposition (HWCVD).

[0120] For ease of explanation, in this embodiment, a carbon-doped amorphous silicon layer is formed on the side of the first tunneling layer 120 facing away from the semiconductor substrate 110 using PECVD technology. For example, the reaction gas is silane, phosphine (or borane), hydrogen, or methane. By setting appropriate gas pressure, deposition temperature, deposition power, and deposition time, the carbon-doped amorphous silicon layer is formed.

[0121] Step 408: A second tunneling layer is formed on the side of the carbon-doped amorphous silicon layer facing away from the first tunneling layer.

[0122] The preparation method of the second tunneling layer 140 can be the same as or different from that of the first tunneling layer 120. To improve preparation efficiency and reduce cost, in this embodiment, the first tunneling layer 120 and the second tunneling layer 140 are prepared using the same method. For example, the second tunneling layer 140 is also an ultrathin silicon oxide layer, which can be deposited on the surface of the carbon-doped amorphous silicon layer 150 away from the first tunneling layer 120 using a PECVD process. For example, the reactant gas is nitrous oxide (N2O) with a flow rate of 5000 sccm - 15000 sccm. By setting appropriate gas pressure, deposition temperature, deposition power (e.g., 10000 W), and deposition time (e.g., 90-100 s), an ultrathin silicon oxide layer is formed.

[0123] Step 410: A doped amorphous silicon layer is formed on the side of the second tunneling layer opposite to the carbon-doped amorphous silicon layer.

[0124] The conductive dopant element in the carbon-doped amorphous silicon layer has the same conductivity type as the conductive dopant element in the doped amorphous silicon layer. The conductive dopant element can be phosphorus or boron. In this embodiment, for ease of explanation, an example is given where both the carbon-doped amorphous silicon layer and the doped amorphous silicon layer have phosphorus as the conductive dopant element.

[0125] The preparation method of the doped amorphous silicon layer can be the same as or different from that of the carbon-doped polycrystalline silicon layer 130. To improve preparation efficiency and reduce cost, in this embodiment, the doped amorphous silicon layer and the carbon-doped polycrystalline silicon layer 130 are prepared using the same method. For example, a PECVD process can be used to deposit the second tunneling layer 140 on the side facing away from the carbon-doped amorphous silicon layer. The reaction gas for the doped amorphous silicon layer may include silane, phosphine (or borane), and hydrogen. By setting appropriate gas pressure, deposition temperature, deposition power, and deposition time, the doped amorphous silicon layer is formed.

[0126] Step 412: Anneal the obtained structure.

[0127] After forming the doped amorphous silicon layer, the structure can be annealed to form a structure like... Figure 1 The solar cell shown is an example of an annealing process. The annealing temperature range is 900-950°C, and the annealing time is 5-50 minutes. After annealing, the carbon-doped amorphous silicon layer is converted into a carbon-doped polycrystalline silicon layer 130, and the doped amorphous silicon layer is converted into a doped polycrystalline silicon layer 150.

[0128] Step 414: A first passivation layer is formed on the side of the doped polysilicon layer opposite to the second tunneling layer.

[0129] For example, a first passivation layer 181 may be formed on the side of the doped polysilicon layer away from the second tunneling layer using processes such as deposition. The material of the first passivation layer 181 includes, but is not limited to, at least one of alumina, silicon oxide, silicon nitride, and silicon oxynitride.

[0130] Optionally, the method for fabricating a solar cell may further include the step of forming a first antireflection layer on the side of the first passivation layer 181 opposite to the doped polycrystalline silicon layer. The material of the first antireflection layer 182 includes, but is not limited to, at least one of silicon nitride, silicon oxynitride, or silicon oxide.

[0131] Step 416: A first electrode is formed on the side of the first passivation layer opposite to the doped polysilicon layer.

[0132] The first electrode 101 is in electrical contact with the doped polycrystalline silicon layer.

[0133] The method for fabricating a solar cell provided in this application embodiment can be based on a provided semiconductor substrate, in which a first tunneling layer, a carbon-doped amorphous silicon layer, a second tunneling layer and a doped amorphous silicon layer are sequentially formed on one side surface of the semiconductor substrate, and then the structure is annealed, in which case the carbon-doped amorphous silicon layer can be converted into a carbon-doped polycrystalline silicon layer and the doped amorphous silicon layer can be converted into a doped polycrystalline silicon layer; further, a first passivation layer and a first electrode can be formed. The doped polycrystalline silicon layer serves as the contact layer for the solar cell, forming an ohmic contact with the first electrode. Since the doped polycrystalline silicon layer is a carbon-free polycrystalline silicon layer, it does not reduce the activation concentration of active doping atoms (e.g., phosphorus) in the doped polycrystalline silicon layer, ensuring good contact between the doped polycrystalline silicon layer and the metal electrode. Furthermore, the carbon-doped polycrystalline silicon layer is located on the side of the second tunneling layer closest to the semiconductor substrate. The second tunneling layer contacts the outer doped polycrystalline silicon layer and can block the metal paste (such as silver paste) of the metal electrode, preventing the metal paste from penetrating the outer doped polycrystalline silicon layer during sintering and contacting the carbon-doped polycrystalline silicon layer located in the middle layer. In addition, the carbon-doped polycrystalline silicon layer located in the middle layer has an anti-corrosion effect on the metal paste. It can inhibit the erosion of the semiconductor substrate and the first tunneling layer by corrosive components in the paste (such as glass phase, organic carrier residues, and metal ions), while also preventing itself from being damaged by the metal paste, thus improving contact stability.

[0134] In an exemplary embodiment, forming a carbon-doped amorphous silicon layer on the side surface of the first tunneling layer away from the semiconductor substrate includes the steps of: introducing a first gas source to form a first sub-carbon-doped amorphous silicon layer on the side surface of the first tunneling layer away from the semiconductor substrate, and introducing a second gas source to form a second sub-carbon-doped amorphous silicon layer on the side surface of the first sub-carbon-doped amorphous silicon layer away from the first tunneling layer.

[0135] In the embodiments of this application, the carbon-doped amorphous silicon layer may include a first sub-carbon-doped amorphous silicon layer and a second sub-carbon-doped amorphous silicon layer. It should be understood that both the first sub-carbon-doped amorphous silicon layer and the second sub-carbon-doped amorphous silicon layer can be prepared using the same fabrication process. For example, they can be deposited sequentially on the side of the first tunneling layer 120 facing away from the semiconductor substrate 110 using a PECVD process.

[0136] During the formation process, the first gas source forming the first carbon-doped amorphous silicon layer and the second gas source forming the first carbon-doped amorphous silicon layer have the same composition, but the doping ratios of the different types of gas sources are different. The first gas source and the second gas source respectively include: a silicon source, a carbon source, and a conductive dopant source. The silicon source is silane, and the carbon source is methane; the conductive dopant source can be hydrogen-diluted phosphine or hydrogen-diluted borane. In the embodiments of this application, for ease of explanation, phosphine is used as an example for illustrating the conductive dopant source.

[0137] The carbon source gas flow rate in the second gas source is greater than that in the first gas source. The phosphorus source gas flow rate in the second gas source is also greater than that in the first gas source. Therefore, the first sub-carbon-doped amorphous silicon layer formed can be a lightly phosphorus-doped and lightly carbon-doped amorphous silicon layer, and the second sub-carbon-doped amorphous silicon layer can be a heavily phosphorus-doped and heavily carbon-doped amorphous silicon layer. Thus, the formation of the carbon-doped amorphous silicon layer involves two steps: first, a lightly phosphorus-doped and lightly carbon-doped amorphous silicon layer (the first sub-carbon-doped amorphous silicon layer) is formed, and then a heavily phosphorus-doped and heavily carbon-doped amorphous silicon layer (the second sub-carbon-doped amorphous silicon layer) is formed.

[0138] In an exemplary embodiment, in the first gas source, the flow rate of silane ranges from 2000 to 6000 sccm, the flow rate of phosphine ranges from 50 to 300 sccm, the flow rate of hydrogen ranges from 5000 to 12000 sccm, and the flow rate of methane ranges from 50 to 500 sccm. For example, the flow rate of silane is 2000 sccm, 3000 sccm, 4000 sccm, 5000 sccm, or 6000 sccm; or a value between any two of the aforementioned values. The flow rate of phosphine is 50 sccm, 100 sccm, 150 sccm, 200 sccm, 250 sccm, or 300 sccm; or a value between any two of the aforementioned values. The hydrogen gas flow rate is 5000 sccm, 6000 sccm, 7000 sccm, 8000 sccm, 9000 sccm, 10000 sccm, 11000 sccm, or 12000 sccm; or a value between any two of the aforementioned values. The methane gas flow rate is 50 sccm, 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, 350 sccm, 400 sccm, 550 sccm, or 500 sccm; or a value between any two of the aforementioned values.

[0139] In the second gas source, the flow rate of silane ranges from 2000 to 6000 sccm, the flow rate of phosphine ranges from 300 to 900 sccm, the flow rate of hydrogen ranges from 5000 to 12000 sccm, and the flow rate of methane ranges from 2000 to 6000 sccm. For example, the flow rate of silane is 2000 sccm, 3000 sccm, 4000 sccm, 5000 sccm, or 6000 sccm; or a value between any two of the aforementioned values. The flow rate of phosphine is 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, 800 sccm, or 900 sccm; or a value between any two of the aforementioned values. The hydrogen gas flow rate is 5000 sccm, 6000 sccm, 7000 sccm, 8000 sccm, 9000 sccm, 10000 sccm, 11000 sccm, or 12000 sccm; or a value between any two of the aforementioned values. The methane gas flow rate is 2000 sccm, 3000 sccm, 4000 sccm, 5000 sccm, or 6000 sccm; or a value between any two of the aforementioned values.

[0140] For example, forming a carbon-doped amorphous silicon layer on the surface of the first tunneling layer 120 away from the semiconductor substrate 110 includes: using a PECVD process, introducing 2000 sccm of silane, 200 sccm of phosphine, 8000 sccm of hydrogen, and 100 sccm of methane to deposit a 20 nm lightly phosphorus-doped and lightly carbon-doped amorphous silicon layer on the surface of the first tunneling layer 120 away from the semiconductor substrate 110; introducing 2000 sccm of silane, 600 sccm of phosphine, 8000 sccm of hydrogen, and 2000 sccm of methane to deposit a heavily phosphorus-doped and heavily carbon-doped amorphous silicon layer on the surface of the lightly phosphorus-doped and lightly carbon-doped amorphous silicon layer away from the first tunneling layer 120. For example, the thickness of the formed lightly phosphorus-doped and lightly carbon-doped amorphous silicon layer is 15-25 nm, and the thickness of the formed heavily phosphorus-doped and heavily carbon-doped amorphous silicon layer is 8-16 nm.

[0141] In this embodiment, during the formation of the carbon-doped amorphous silicon layer, a lightly phosphorus-doped and lightly carbon-doped amorphous silicon layer is formed first, followed by a heavily phosphorus-doped and heavily carbon-doped amorphous silicon layer. The deposition parameters of each layer can be independently controlled, allowing for precise adjustment of the single-layer thickness of the first and second sub-carbon-doped amorphous silicon layers. The carbon content of the lightly carbon-doped and lightly phosphorus-doped amorphous silicon layer falls between that of the semiconductor substrate and the heavily carbon-doped and heavily phosphorus-doped amorphous silicon layer, reducing the mismatch in the interfacial thermal expansion coefficient. Furthermore, the distribution of hydrogen (H) in different regions of the carbon-doped polycrystalline silicon layer can be controlled, effectively controlling the concentration of H in the tunneling oxide layer (SiO2), ultimately reducing the occurrence of film bursting in the carbon-doped polycrystalline silicon layer. Furthermore, the first sub-carbon-doped polysilicon layer is a lightly doped structure, which helps maintain the passivation effect of the first tunneling layer interface. The second sub-carbon-doped polysilicon layer is a heavily phosphorus-doped and heavily carbon-doped layer. Its placement close to the doped polysilicon layer can effectively reduce the recombination rate and improve the selective transport capability of charge carriers. It can also block the metal paste (such as silver paste) of the metal electrode, preventing the metal paste from passing through the outer doped polysilicon layer and contacting the carbon-doped polysilicon layer located in the middle layer during sintering. In addition, the carbon-doped polysilicon layer located in the middle layer has an anti-corrosion effect on the metal paste.

[0142] In one exemplary embodiment, the flow rate ratio of silane to methane in the second gas source is in the range of 1:3. It should be understood that during the formation of the heavily phosphorus-doped and heavily carbon-doped amorphous silicon layer, the flow rate of silane introduced is less than the flow rate of methane introduced.

[0143] For example, if the gas flow rate of silane is 2000 sccm, the gas flow rate of methane is 2000 sccm-6000 sccm. If the gas flow rate of silane is 3000 sccm, the gas flow rate of methane is 3000 sccm-6000 sccm. If the gas flow rate of silane is 4000 sccm, the gas flow rate of methane is 4000 sccm-6000 sccm. If the gas flow rate of silane is 6000 sccm, the gas flow rate of methane is 6000 sccm.

[0144] In this embodiment, during the formation of the second carbon-doped amorphous silicon layer, i.e., the heavily phosphorus-doped and heavily carbon-doped amorphous silicon layer, the ratio of silane to methane gas flow rate is reasonably controlled. This avoids the situation where the methane flow rate is set too high, causing carbon to diffuse into the doped polycrystalline silicon layer during annealing, affecting the ohmic contact between the doped polycrystalline silicon layer and the metal electrode. It also avoids the insulation and carrier selectivity of the second tunneling layer being damaged due to the excessive methane flow rate. Furthermore, it avoids the situation where carbon elements diffuse into the semiconductor substrate during annealing due to the excessive methane flow rate, forming deep-level recombination centers and affecting the bulk lifetime of the semiconductor substrate. Furthermore, by setting a reasonable gas flow ratio of silane and methane, the resulting heavily phosphorus- and heavily carbon-doped amorphous silicon layer, after annealing, can block the metal paste (such as silver paste) of the metal electrode, preventing the metal paste from penetrating the outer doped polycrystalline silicon layer during sintering and contacting the carbon-doped polycrystalline silicon layer located in the middle layer. In addition, the carbon-doped polycrystalline silicon layer located in the middle layer has an anti-corrosion effect on the metal paste, which can inhibit the erosion of the semiconductor substrate and the first tunneling layer by corrosive components in the paste (such as glass phase, organic carrier residue, and metal ions), while also preventing itself from being damaged by the metal paste, thus improving contact stability.

[0145] In one exemplary embodiment, forming a doped amorphous silicon layer on the surface of the second tunneling layer opposite to the carbon-doped amorphous silicon layer includes: introducing a third gas source to form the doped amorphous silicon layer on the surface of the second tunneling layer opposite to the carbon-doped amorphous silicon layer, wherein the third gas source includes silane and a conductive dopant source. The proportion of the flow rate of the conductive dopant source in the third gas source is greater than the proportion of the flow rate of the conductive dopant source in the second gas source.

[0146] For example, phosphine is used as the conductive doping source. In the second gas source, the phosphine flow rate ranges from 300 to 900 sccm. In the third gas source, the phosphine flow rate ranges from 900 to 1500 sccm; for example, the phosphine flow rate in the third gas source is 900 sccm, 1000 sccm, 1100 sccm, 1200 sccm, 1300 sccm, 1400 sccm, or 1500 sccm; or any value between any two of the aforementioned values.

[0147] In this embodiment, during the process of forming a doped amorphous silicon layer (e.g., a phosphorus-doped amorphous silicon layer), the proportion of the conductive dopant source in the third gas source is greater than the proportion of the conductive dopant source in the second gas source. That is, the phosphorus concentration of the doped amorphous silicon layer is higher than the phosphorus concentration in the heavily phosphorus-doped and heavily carbon-doped amorphous silicon layer located in the middle layer. In the high-temperature process of device manufacturing (such as annealing), the dopant atoms of the high-concentration phosphorus-doped polycrystalline silicon are not easily desorbed, and the contact interface structure is stable. In addition, it also helps to improve its ohmic contact with the metal electrode.

[0148] In an exemplary embodiment, in the third gas source, the flow rate of silane ranges from 2000 to 6000 sccm, the flow rate of phosphine ranges from 900 to 1500 sccm, and the flow rate of hydrogen ranges from 5000 to 12000 sccm. For example, the flow rate of silane is 2000 sccm, 3000 sccm, 4000 sccm, 5000 sccm, or 6000 sccm; or a value between any two of the aforementioned values. The flow rate of phosphine is 900 sccm, 1000 sccm, 1100 sccm, 1200 sccm, 1300 sccm, or 1500 sccm; or a value between any two of the aforementioned values. The hydrogen flow rate is 5000 sccm, 6000 sccm, 7000 sccm, 8000 sccm, 9000 sccm, 10000 sccm, 11000 sccm or 12000 sccm; or a value between any two of the aforementioned values.

[0149] For example, forming a doped amorphous silicon layer on the surface of the second tunneling layer opposite to the carbon-doped amorphous silicon layer includes: using a PECVD process, introducing silane at 2000 sccm, phosphine at 960 sccm, and hydrogen at 8000 sccm to form a heavily phosphorus-doped amorphous silicon layer on the surface of the second tunneling layer opposite to the carbon-doped amorphous silicon layer. For example, the thickness of the formed heavily phosphorus-doped amorphous silicon layer is 30 nm-50 nm.

[0150] In this embodiment, the thickness of the formed doped amorphous silicon layer can be smaller than that of the doped amorphous silicon layer in solar cells without a carbon-doped polycrystalline silicon layer in related technologies (e.g., 70-80 nm), for example, its thickness ranges from 30 nm to 50 nm. Thus, after annealing, the doped amorphous silicon layer in this embodiment is converted into a doped polycrystalline silicon layer, which not only achieves good ohmic contact with the metal electrode but also reduces parasitic absorption, thereby improving the short-circuit current of the solar cell and enhancing its photoelectric conversion efficiency.

[0151] In one exemplary embodiment, based on any of the foregoing embodiments, forming a carbon-doped amorphous silicon layer on the side surface of the first tunneling layer away from the semiconductor substrate further includes the step of forming an intrinsic amorphous silicon layer on the side surface of the first tunneling layer away from the semiconductor substrate using silane and hydrogen.

[0152] For example, using a PECVD process, 2000-6000 sccm of silane and 5000-12000 sccm of hydrogen are introduced to form an intrinsic amorphous silicon layer on the surface of the first tunneling layer 120 facing away from the semiconductor substrate 110. The silane flow rate is 2000 sccm, 3000 sccm, 4000 sccm, 5000 sccm, or 6000 sccm; or a value between any two of the aforementioned values. The hydrogen flow rate is 5000 sccm, 6000 sccm, 7000 sccm, 8000 sccm, 9000 sccm, 10000 sccm, 11000 sccm, or 12000 sccm; or a value between any two of the aforementioned values.

[0153] For example, using the PECVD process, an intrinsic amorphous silicon layer of 3nm-10nm is prepared by introducing silane at 2000 sccm and hydrogen at 8000 sccm. The formed intrinsic amorphous silicon layer is then annealed in step 412, and the intrinsic amorphous silicon layer is converted into a partially carbon-doped polycrystalline silicon layer.

[0154] In one exemplary embodiment, the thickness of the intrinsic amorphous silicon layer ranges from 3 nm to 10 nm. For example, the thickness of the intrinsic amorphous silicon layer can be 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm, or any value between any two of the above values.

[0155] In this embodiment, by reasonably setting the thickness range of the intrinsic amorphous silicon layer to 3nm-10nm, the uniformity of the intrinsic amorphous silicon layer thickness can be ensured, and the situation where hydrogen overflow causes the film layer to break (e.g., film bursting) during the formation of carbon-doped polycrystalline silicon layer or doped polycrystalline silicon layer can be prevented.

[0156] In this embodiment, after forming the first tunneling layer, an intrinsic amorphous silicon layer, a carbon-doped amorphous silicon layer, a second tunneling layer, and a doped amorphous silicon layer are formed sequentially. The resulting structure is then annealed to achieve the conversion from amorphous silicon to polycrystalline silicon. Since the intrinsic polycrystalline silicon layer is located between the first tunneling layer and the carbon-doped polycrystalline silicon layer, it can protect the first tunneling layer. For example, it can prevent metal atoms in the metal paste from diffusing into the tunneling oxide layer, thus avoiding the accumulation of metal atoms in the first tunneling layer (e.g., the tunneling oxide layer SiO2) to form defects (such as metal deposits or ion traps), which would lead to a decrease in the breakdown electric field and an increase in leakage current in the first tunneling layer.

[0157] In one exemplary embodiment, a method for fabricating a solar cell is also provided. The types of solar cells include, but are not limited to, TOPCon cells, TBC cells, HBC cells, and HJT cells.

[0158] In the embodiments of this application, for ease of explanation, a TOPCon cell is used as an example to illustrate its preparation method.

[0159] like Figure 5 As shown, the method for preparing a solar cell includes steps 502-508.

[0160] Step 502, providing a semiconductor substrate;

[0161] Step 504: An emitter is formed on the side of the semiconductor substrate facing away from the first tunneling layer.

[0162] Please continue to refer to this. Figure 3 In an exemplary embodiment, the emitter 170 may be formed during the formation of the solar cell. For example, after the semiconductor substrate 110 is provided and before the first tunneling layer 120 is formed, the emitter 170 is formed on one side surface of the semiconductor substrate 110 of the first tunneling layer 120. The semiconductor substrate 110 includes a first surface and a second surface disposed opposite to each other. One of the first surface and the second surface is a light-receiving surface (or front surface), and the other of the first surface and the second surface is a back surface (or back surface).

[0163] For ease of explanation, we will use the first side as the front and the second side as the back as an example.

[0164] For example, when the semiconductor substrate 110 is an N-type silicon substrate, P-type diffusion can be performed on the first side of the semiconductor substrate 110 to form a P-type emitter 170. For example, the texturized semiconductor substrate 110 and a boron source are placed together in a diffusion furnace. When the diffusion furnace is heated to a predetermined temperature, boron atoms begin to evaporate from the boron source, pass through the silicon wafer surface into the silicon lattice, and are then absorbed by the silicon wafer surface to form P-type doping. In some embodiments, the boron source includes, but is not limited to, boric acid (H3BO3), trifluoroboric acid (BF3), or organic compounds of boron such as borohydrides. A dense tunneling oxide layer 120 is formed on the second side using the dense tunneling oxide layer 120 method described in any of the foregoing embodiments.

[0165] In optional embodiments, the emitter may also be a doped polycrystalline silicon layer. In the embodiments of this application, the specific material of the emitter is not specifically limited.

[0166] Step 506: A first tunneling layer is formed on one side surface of the semiconductor substrate.

[0167] Step 508: A carbon-doped amorphous silicon layer is formed on the side of the first tunneling layer facing away from the semiconductor substrate.

[0168] Step 510: A second tunneling layer is formed on the side of the carbon-doped amorphous silicon layer facing away from the first tunneling layer.

[0169] Step 512: A doped amorphous silicon layer is formed on the side of the second tunneling layer opposite to the carbon-doped amorphous silicon layer; wherein the conductive doping element of the carbon-doped amorphous silicon layer is the same as the conductive doping element of the doped amorphous silicon layer.

[0170] Step 514: Anneal the obtained structure; wherein, after annealing, the carbon-doped amorphous silicon layer is converted into a carbon-doped polycrystalline silicon layer, and the doped amorphous silicon layer is converted into a doped polycrystalline silicon layer.

[0171] Step 516: A first passivation layer is formed on the side of the doped polysilicon layer opposite to the second tunneling layer.

[0172] Step 518: A second passivation layer is formed on the side of the emitter facing away from the semiconductor substrate.

[0173] For example, a second passivation layer 191 may be formed on the side of the emitter facing away from the semiconductor substrate using a process such as deposition. The material of the second passivation layer 191 includes, but is not limited to, at least one of aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0174] Optionally, the method for fabricating a solar cell may further include the step of forming a second antireflection layer 192 on the side of the second passivation layer 191 opposite to the emitter. The material of the second antireflection layer 192 includes, but is not limited to, at least one of silicon nitride, silicon oxynitride, or silicon oxide.

[0175] In practical applications, the first passivation layer 181 and the second passivation layer 182 can be formed simultaneously, as can the first antireflection layer 191 and the second antireflection layer 192.

[0176] Step 520: Form a first electrode and a second electrode; the first electrode is in electrical contact with the doped polycrystalline silicon layer, and the second electrode is in contact with the emitter.

[0177] The first electrode 101 is located on the side of the first surface of the semiconductor substrate 110 and is electrically connected to the emitter 170; the second electrode 102 is located on the side of the second surface of the semiconductor substrate 110 and is electrically connected to the doped polysilicon layer 150.

[0178] The solar cell fabrication method provided in this application includes the solar cell fabrication method in any of the foregoing embodiments, and the various electrical performance parameters (e.g., open-circuit voltage, conversion efficiency, etc.) of the resulting solar cell are improved to varying degrees. For example, if the solar cell fabrication method is used to fabricate a TOPCon cell, the cell conversion efficiency of the TOPCon cell is improved by more than 0.05%. The improvement in efficiency mainly comes from the increase in open-circuit voltage (Voc) and short-circuit current Isc. Compared with conventional TOPCon cells, the TOPCon cell has an increase of more than 1mV in Voc and an increase of 2-30mA in short-circuit current Isc.

[0179] In one exemplary embodiment, forming a first electrode and a second electrode includes: applying silver paste to the passivation antireflection layer using a printing technique to form a predetermined first electrode pattern and a second electrode pattern; and performing laser sintering on the resulting structure to form the first electrode and the second electrode. The bias voltage of the laser sintering is less than a reference voltage.

[0180] The reference voltage for laser sintering is 18V. In this embodiment, the bias voltage for laser sintering the obtained structure can be set to 17V, which can prevent the metal electrode from contacting the carbon-doped polycrystalline silicon layer and thus improve the ohmic contact between the metal electrode and the outermost doped polycrystalline silicon layer of the solar cell.

[0181] Exemplary Implementation Example 1

[0182] like Figure 6 As shown, the method for fabricating a solar cell (e.g., a TOPCon cell) includes steps one through seven.

[0183] Step 1: Provide a semiconductor substrate.

[0184] For example, the semiconductor substrate 110 layer is cleaned and texturized to obtain an N-type silicon wafer substrate. The thickness of the semiconductor substrate 110 layer ranges from 80 micrometers to 180 micrometers, for example, 80µm, 90µm, 100µm, 110µm, 120µm, 130µm, 140µm, 150µm, 160µm, 170µm, or 180µm; or any value between any two of the above values.

[0185] Step 2: Perform boron diffusion treatment on the front side of the semiconductor substrate to form a front boron emitter.

[0186] Step 3: After polishing the back side of the substrate, PECVD technology is used to sequentially form a first tunneling oxide layer, an intrinsic amorphous silicon layer, a lightly phosphorus-doped and lightly carbon-doped amorphous silicon layer, a heavily phosphorus-doped and heavily carbon-doped amorphous silicon layer, a second tunneling oxide layer, and a heavily phosphorus-doped amorphous silicon layer.

[0187] For example, using PECVD technology, 8000 sccm of nitrous oxide is introduced to prepare a first tunneling oxide layer; then 2000 sccm of silane and 8000 sccm of hydrogen are introduced to prepare a 3 nm intrinsic amorphous silicon layer; 2000 sccm of silane, 200 sccm of phosphine, 8000 sccm of hydrogen, and 100 sccm of methane are introduced to prepare a 20 nm lightly phosphorus-doped and lightly carbon-doped amorphous silicon layer; 2000 sccm of silane, 600 sccm of phosphine, 8000 sccm of hydrogen, and 2000 sccm of methane are introduced to prepare a 12 nm heavily phosphorus-doped and heavily carbon-doped amorphous silicon layer; then 8000 sccm of nitrous oxide is introduced to prepare a second tunneling oxide layer; finally, 2000 sccm of silane, 960 sccm of phosphine, and 8000 sccm of hydrogen are introduced to prepare a 50 nm heavily phosphorus-doped amorphous silicon layer.

[0188] Step four: Anneal the obtained structure to convert the amorphous silicon layer into the corresponding polycrystalline silicon layer.

[0189] For example, the annealing temperature range is 920°C and the annealing time range is 30 minutes.

[0190] Step 5: Form a first passivation layer and a second passivation layer on opposite sides of the obtained structure, respectively.

[0191] For example, an antireflective material, such as aluminum oxide, is deposited on opposite sides of the resulting structure using a deposition process (e.g., atomic layer deposition, chemical vapor deposition, etc.) to form a first passivation layer 181 on the side containing the first surface of the semiconductor substrate 110 and a second passivation layer 191 on the side containing the second surface of the semiconductor substrate 110. Depositing an aluminum oxide film on both the front and back sides of the silicon wafer can reduce carrier recombination at the silicon wafer surface / interface, thereby achieving a passivation effect.

[0192] In an optional embodiment, before forming the antireflective layer, the structure formed in step 808 may be subjected to decoating and RCA cleaning to remove residual structures and impurities.

[0193] Step 6: Form a first antireflection layer and a second antireflection layer on opposite sides of the obtained structure, respectively.

[0194] For example, an antireflective material, such as silicon nitride (SiNx), is deposited on opposite sides of the resulting structure using a deposition process (e.g., plasma-enhanced chemical vapor deposition (PECVD)). This forms a first antireflective layer 182 on the first side of the semiconductor substrate 110 and a second antireflective layer 192 on the second side of the semiconductor substrate 110. Forming a second passivation layer 191 and a first antireflective layer 182 on the back side of the battery increases light absorption. Simultaneously, hydrogen atoms generated during the SiNx layer formation process passivate the silicon wafer. Forming the second passivation layer 191 and the first antireflective layer 182 on the back side of the battery serves essentially the same purpose as on the back side. Furthermore, the aluminum oxide layer deposited on the front side is very thin and easily damaged during subsequent battery assembly fabrication; the first antireflective layer 182 on the front side also protects the aluminum oxide.

[0195] Step 7: Form the first electrode and the second electrode on opposite sides of the obtained structure, respectively.

[0196] For example, a first electrode 101 (e.g., a front electrode) and a second electrode 102 (e.g., a back electrode) can be obtained by methods such as screen printing.

[0197] Step eight: After photoinjection, the electrode pattern is sintered using the LECO process. The bias voltage for LECO is set to 17V.

[0198] Comparative Example 1

[0199] The difference from exemplary embodiment 1 is as follows:

[0200] (1) In Comparative Example 1, no carbon-doped polycrystalline silicon layer was formed on 130.

[0201] (2) In step three, 2000 sccm of silane, 600 sccm of phosphine and 8000 sccm of hydrogen are introduced to prepare a 70 nm heavily phosphorus-doped amorphous silicon layer.

[0202] (3) In step eight, the bias voltage of LECO is set to 18V.

[0203] Comparative Example 2

[0204] The difference from the exemplary embodiment 1 is that the doped polysilicon layer 150 in contact with the metal electrode is a carbon-doped polysilicon layer 130.

[0205] Based on the aforementioned exemplary Example 1 and comparative Examples 1 and 2, the solar cells prepared were subjected to electrochemical capacitance-voltage (ECV) testing. Figure 7The above are schematic diagrams of ECV curves for exemplary embodiment 1 and comparative embodiment 1.

[0206] ECV is used to characterize the change in phosphorus activation concentration in the film structure. The ECV curve is the ECV curve of the silicon substrate measured from the outer surface of the doped polysilicon layer 150 (e.g., the surface of the doped polysilicon layer 150 away from the second tunneling layer 140).

[0207] from Figure 7 As can be seen, in Exemplary Embodiment 1, the surface phosphorus concentration of the solar cell can be consistent with that of the solar cell in Comparative Embodiment 1, for example, 5.3E20cm³. -3 The outer doped polycrystalline silicon layer 150 can be used to provide good contact. In exemplary embodiment 1, at a depth of approximately 45 nm in the solar cell, the phosphorus concentration decreases significantly due to the introduction of carbon; the phosphorus concentration in exemplary embodiment 1 is 2E20cm⁻¹. -3 Its sheet resistance is -66.9 Ω / sq; while the phosphorus concentration in Comparative Example 1 is 3.9E20cm. -3 Its sheet resistance is -65.7Ω / sq, and the sheet resistances of the two are close.

[0208] from Figure 7 As can be seen, in Exemplary Example 1, the phosphorus concentration decreases significantly at a depth of approximately 45 nm in the solar cell due to the introduction of carbon. The phosphorus concentration in Exemplary Example 1 is 2E20cm⁻¹. -3 Its sheet resistance is -66.9 Ω / sq; while in Comparative Example 2, the phosphorus concentration will decrease to 1.8E20cm⁻¹. -3 The sheet resistance increases to 72Ω / sq, and the ohmic contact deteriorates.

[0209] The total carbon concentration in solar cells prepared based on the aforementioned exemplary Example 1 and Comparative Example 1 was measured using secondary ion mass spectrometry (SIMS). Figure 8 This is a schematic diagram of the SIMS curves (total carbon concentration) for an exemplary embodiment 1 and a comparative embodiment 1. The SIMS curves are SIMS curves of the silicon substrate measured from the outer surface of the doped polysilicon layer 150 (e.g., the surface of the doped polysilicon layer 150 away from the second tunneling layer 140).

[0210] from Figure 8It can be seen that in Exemplary Embodiment 1, the trend of the total carbon concentration of the solar cell matches the film structure setting; the carbon concentration in the carbon-doped polycrystalline silicon layer 130 of the solar cell is two orders of magnitude higher than the carbon concentration of the solar cell in Comparative Embodiment 1; furthermore, the carbon concentration of the semiconductor substrate 110 in Exemplary Embodiment 1 is nearly one order of magnitude higher than the carbon concentration of the semiconductor substrate 110 in the solar cell in Comparative Embodiment 1. In the solar cell provided by this application embodiment, the carbon concentration gradually decreases from the outside to the inside after high-temperature annealing. According to the SIMS results, the position of the carbon-doped polycrystalline silicon layer can be determined by the positions of the two tunneling layers (first tunneling layer and second tunneling layer) in the figure, and the carbon concentration in the carbon-doped polycrystalline silicon layer is between 3 × 10⁻⁶. 20 atoms / cm 3 -1.2×10 21 atoms / cm 3 From the silicon substrate to a depth of 280 nm within the silicon substrate, the carbon concentration increases from 4 × 10⁻⁶. 20 atoms / cm 3 Reduced to 5×10 16 atoms / cm 3 Baseline level. In Comparative Example 1, the carbon concentration increased from 4 × 10⁻⁶ at a depth of 280 nm within the silicon substrate. 18 atoms / cm 3 Reduced to 5×10 16 atoms / cm 3 Baseline level. As can be seen, the semiconductor substrate 110 (e.g., silicon substrate) in this embodiment will also contain carbon (carbon has the functions of hydrogen capture, gettering, etc.), which is beneficial to improving the open circuit voltage Voc of the solar cell.

[0211] The total hydrogen concentration in the solar cells prepared based on the aforementioned exemplary Example 1 and Comparative Example 1 was measured by secondary ion mass spectrometry (SIMS). Figure 9 This is a schematic diagram of the SIMS curves (total hydrogen concentration) for Exemplary Example 1 and Comparative Example 1. From... Figure 9 As can be seen, in Exemplary Example 1, the hydrogen concentration decreases more slowly near the silicon substrate, and the hydrogen concentration remains higher than that of the solar cell in Comparative Example 1 up to a depth of 350 nm within the silicon substrate. In Exemplary Example 1, the hydrogen concentration decreases from 1.2 × 10⁻⁶ to a depth of 280 nm within the silicon substrate. 20 atoms / cm 3 Decreased to 3.7 × 10 17 atoms / cm 3 In comparison to Example 1, the depth from the silicon substrate to 280 nm within the silicon substrate was 2.3 × 10⁻⁶. 20 atoms / cm3 Decrease to 1×10 17 atoms / cm 3 Therefore, it can be seen that in the embodiments of this application, the hydrogen concentration decreases more slowly, and the hydrogen concentration is more than twice that of comparative embodiment 1 at a depth of 70-280 nm.

[0212] The total phosphorus concentration in solar cells prepared based on the aforementioned exemplary Example 1 and Comparative Example 1 was measured using secondary ion mass spectrometry (SIMS). Figure 10 This is a schematic diagram of the SIMS curves (total phosphorus concentration) for Exemplary Example 1 and Comparative Example 1. From... Figure 10 As can be seen, the slope of the phosphorus concentration in the solar cells in Exemplary Example 1 is approximately the same as that in Comparative Example 1, and their total phosphorus concentration is consistent.

[0213] The solar cells prepared based on the aforementioned exemplary embodiment 1 and comparative embodiment 1 were tested. The short-circuit current density Isc, open-circuit voltage Voc, fill factor FF, and photoelectric conversion efficiency PCE of the solar cells in each embodiment are shown in Table 1.

[0214] Table 1 is a comparison table of the performance of the solar cells of Exemplary Example 1 and Comparative Example 1 through various tests.

[0215]

[0216] Comparative Example 3

[0217] The difference from the exemplary embodiment 1 is that the carbon-doped polycrystalline silicon layer is located between the second tunneling layer and the doped polycrystalline silicon.

[0218] Table 2 compares the performance of the solar cells in Comparative Example 1 and Comparative Example 2 through various tests.

[0219]

[0220] As can be seen from Table 2, compared with the solar cell prepared in Example 3, the contact between the metal paste and the doped polycrystalline silicon layer is worse, resulting in a high Rs of the solar cell and a low fill factor FF. In order to improve the contact between the metal paste and the doped polycrystalline silicon layer, increasing the thickness of the doped polycrystalline silicon layer would result in a thicker film and severe parasitic absorption.

[0221] As can be seen from Tables 1 and 2, the solar cell prepared in Exemplary Example 1 has an open-circuit voltage Voc that is increased by 1.1-1.7 mV, a short-circuit current density Isc that is increased by 2-30 mA, and a conversion efficiency Eta that is increased by more than 0.06% compared with the solar cells prepared in Comparative Example 1 and Comparative Example 3.

[0222] This application provides a photovoltaic module, including the solar cell in any of the foregoing embodiments, or the solar cell prepared by the solar cell preparation method in any of the foregoing embodiments.

[0223] For example, the photovoltaic module includes multiple solar cells, which can be wired together in series via solder strips to collect the electrical energy generated by each individual solar cell for subsequent transmission. Of course, the solar cells can be arranged at intervals or stacked together in a shingled configuration.

[0224] Furthermore, the photovoltaic module also includes an encapsulation layer and a cover plate. The encapsulation layer covers the surface of the cell string, and the cover plate covers the surface of the encapsulation layer away from the cell string. Solar cells are electrically connected in a single unit or in multiple segments to form multiple cell strings, which are electrically connected in series and / or parallel. Specifically, in some embodiments, multiple cell strings can be electrically connected through conductive links. The encapsulation layer covers the surface of the solar cell. Exemplarily, the encapsulation layer can be an organic encapsulation film such as an ethylene-vinyl acetate copolymer film, a polyethylene octene co-elastomer film, or a polyethylene terephthalate film. The cover plate can be a light-transmitting cover plate such as a glass cover plate or a plastic cover plate.

[0225] It should be understood that, in the embodiments of this application, at least some of the steps in the accompanying drawings may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0226] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0227] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A solar cell, characterized in that, include: Semiconductor substrate; The first tunneling layer is located on one side surface of the semiconductor substrate; A carbon-doped polycrystalline silicon layer is located on the side of the first tunneling layer facing away from the semiconductor substrate; The second tunneling layer is located on the side surface of the carbon-doped polycrystalline silicon layer that is away from the first tunneling layer. A doped polycrystalline silicon layer is located on the side surface of the second tunneling layer opposite to the carbon-doped polycrystalline silicon layer; wherein the conductive dopant element of the carbon-doped polycrystalline silicon layer has the same conductivity type as the conductive dopant element of the doped polycrystalline silicon layer. The first passivation layer is located on the surface of the doped polysilicon layer that is away from the second tunneling layer. The first electrode is located on the side of the first passivation layer away from the doped polysilicon layer, and the first electrode is in electrical contact with the doped polysilicon layer.

2. The solar cell according to claim 1, characterized in that, In the thickness direction of the solar cell, in the carbon-doped polycrystalline silicon layer, the carbon concentration near the first tunneling layer is lower than the carbon concentration of the first passivation layer.

3. The solar cell according to claim 2, characterized in that, The carbon concentration in the carbon-doped polycrystalline silicon layer is in the range of 1×10⁻⁶. 20 atoms / cm 3 -5×10 21 atoms / cm 3 .

4. The solar cell according to claim 1, characterized in that, The concentration of conductive dopant elements in the carbon-doped polycrystalline silicon layer is lower than that in the doped polycrystalline silicon layer.

5. The solar cell according to claim 1, characterized in that, The thickness of the doped polycrystalline silicon layer ranges from 30 nm to 130 nm.

6. The solar cell according to claim 1, characterized in that, The total thickness of the first tunneling layer, the carbon-doped polycrystalline silicon layer, the second tunneling layer, and the doped polycrystalline silicon layer ranges from 40 nm to 200 nm.

7. The solar cell according to claim 1, characterized in that, The conductive doping element is phosphorus or boron.

8. The solar cell according to claim 1, characterized in that, The first electrode penetrates the first passivation layer and is disposed in contact with the doped polysilicon layer; wherein... The depth to which the first electrode is pressed into the doped polysilicon layer is less than the thickness of the doped polysilicon layer.

9. The solar cell according to claim 1, characterized in that, The solar cell also includes: The emitter is located on the side surface of the semiconductor substrate opposite to the first tunneling layer; The second passivation layer is located on the side of the emitter facing away from the semiconductor substrate; The second electrode is in contact with the emitter.

10. A method for preparing a solar cell, characterized in that, The method includes: Provide semiconductor substrates; A first tunneling layer is formed on one side surface of the semiconductor substrate; A carbon-doped amorphous silicon layer is formed on the side of the first tunneling layer facing away from the semiconductor substrate; A second tunneling layer is formed on the side of the carbon-doped amorphous silicon layer opposite to the first tunneling layer; A doped amorphous silicon layer is formed on the side of the second tunneling layer opposite to the carbon-doped amorphous silicon layer; wherein the conductive doping element of the carbon-doped amorphous silicon layer has the same conductivity type as the conductive doping element of the doped amorphous silicon layer. The obtained structure is subjected to annealing treatment; wherein, after annealing treatment, the carbon-doped amorphous silicon layer is converted into a carbon-doped polycrystalline silicon layer, and the doped amorphous silicon layer is converted into a doped polycrystalline silicon layer. A first passivation layer is formed on the side of the doped polysilicon layer opposite to the second tunneling layer; A first electrode is formed on the side of the first passivation layer opposite to the doped polysilicon layer; the first electrode is in electrical contact with the doped polysilicon layer.

11. The method for preparing a solar cell according to claim 10, characterized in that, The formation of a carbon-doped amorphous silicon layer on the side of the first tunneling layer facing away from the semiconductor substrate includes: A first gas source is introduced to form a first sub-carbon-doped amorphous silicon layer on the side surface of the first tunneling layer opposite to the semiconductor substrate; A second gas source is introduced to form a second sub-carbon-doped amorphous silicon layer on the surface of the first sub-carbon-doped amorphous silicon layer away from the first tunneling layer; wherein, the first gas source and the second gas source respectively include: a silicon source, a carbon source and a conductive doping source, the carbon source gas flow rate ratio in the second gas source is greater than the carbon source gas flow rate ratio in the first gas source, and the phosphorus source gas flow rate ratio in the second gas source is greater than the phosphorus source gas flow rate ratio in the first gas source.

12. The method for preparing a solar cell according to claim 11, characterized in that, The silicon source is silane, and the carbon source is methane; wherein, in the second gas source, the gas flow rate ratio of silane to methane is in the range of 1:

3.

13. The method for preparing a solar cell according to claim 11, characterized in that, The silicon source is silane, the carbon source is methane, and the conductive doping source is hydrogen-diluted phosphine; wherein... In the first gas source, the gas flow rate of silane ranges from 2000 to 6000 sccm, the gas flow rate of phosphine ranges from 50 to 300 sccm, the gas flow rate of hydrogen ranges from 5000 to 12000 sccm, and the gas flow rate of methane ranges from 50 to 500 sccm. In the second gas source, the gas flow rate of silane ranges from 2000 to 6000 sccm, the gas flow rate of phosphine ranges from 300 to 900 sccm, the gas flow rate of hydrogen ranges from 5000 to 12000 sccm, and the gas flow rate of methane ranges from 2000 to 6000 sccm.

14. The method for preparing a solar cell according to claim 11, characterized in that, The formation of a doped amorphous silicon layer on the side of the second tunneling layer opposite to the carbon-doped amorphous silicon layer includes: A third gas source is introduced to form a doped amorphous silicon layer on the surface of the second tunneling layer opposite to the carbon-doped polycrystalline silicon layer. The third gas source includes silane and a conductive dopant source. The proportion of the gas flow rate of the conductive doped source in the third gas source is greater than the proportion of the gas flow rate of the conductive doped source in the second gas source.

15. The method for preparing a solar cell according to claim 14, characterized in that, In the third gas source, the gas flow rate of silane ranges from 2000 to 6000 sccm, the gas flow rate of phosphine ranges from 900 to 1500 sccm, and the gas flow rate of hydrogen ranges from 5000 to 12000 sccm.

16. The method for preparing a solar cell according to claim 12, characterized in that, The method of forming a carbon-doped amorphous silicon layer on the surface of the first tunneling layer opposite to the semiconductor substrate further includes: An intrinsic amorphous silicon layer is formed on the side of the first tunneling layer away from the semiconductor substrate using silane and hydrogen; wherein, after annealing, the intrinsic amorphous silicon layer is converted into a partially doped polycrystalline silicon layer.

17. The method for preparing a solar cell according to claim 11, characterized in that, Before forming a carbon-doped amorphous silicon layer on the side of the first tunneling layer facing away from the semiconductor substrate, the method further includes: An emitter is formed on the side of the semiconductor substrate opposite to the first tunneling layer; Before forming the first electrode on the side of the doped polysilicon layer opposite to the second tunneling layer, the method further includes: A second passivation layer is formed on the surface of the emitter that is away from the semiconductor substrate; The method further includes: A second electrode is formed, and the second electrode is in contact with the emitter.

18. The method for fabricating a solar cell according to claim 17, wherein the first electrode and the second electrode are formed in a manner comprising: Silver paste is applied to the first passivation layer and the second passivation layer using printing technology to form a predetermined first electrode pattern and a second electrode pattern, respectively. The resulting structure is subjected to laser sintering to form the first electrode and the second electrode; wherein the bias voltage of the laser sintering is less than the reference voltage.

19. A photovoltaic module, characterized in that, It includes at least one battery string, the battery string comprising at least two solar cells as described in any one of claims 1-9, or solar cells prepared by the method of manufacturing a solar cell as described in any one of claims 10-18.

Images