Integrated circuit testing method, apparatus, device, and storage medium

Abstract

This application relates to an integrated circuit testing method, apparatus, device, and storage medium. The method includes: after mounting the integrated circuit under test (ICT) onto a test socket and initiating the testing process, triggering the application of continuous dynamic stress required for the current testing scenario to the IC; acquiring a multi-dimensional dynamic response signal generated by the IC in response to the dynamic stress; constructing dynamic behavioral fingerprint data characterizing the performance features of the IC based on the multi-dimensional dynamic response signal; analyzing the dynamic behavioral fingerprint data of the IC, making adaptive decisions for the IC, and executing the corresponding testing process. This application's solution at least addresses the problem of inflexibility in existing chip testing technologies using static testing modes.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technology, and in particular to an integrated circuit testing method, apparatus, equipment and storage medium. Background Technology

[0002] With the development of smart home appliances, the demands on chips are becoming increasingly stringent. As a core component of electronic devices, the performance stability and functional integrity of chips directly determine the quality of the final product; therefore, the testing process before chips leave the factory is crucial.

[0003] Traditional chip testing methods generally employ static testing schemes with fixed test modes and predefined criteria. The test process and verification standards of such schemes are all pre-set before testing, and cannot be flexibly adjusted according to the actual working state of the chip. To address the shortcomings of traditional testing methods, some optimization technologies have emerged in related fields. For example, Chinese invention patent CN120066875A discloses a chip testing method that uses an interpreter to parse scripts. This method completes the testing process by running a compiled program on a server, primarily addressing the compatibility issue between different programming languages, enabling the test program to be compatible with scripts written in multiple programming languages. However, this technology essentially still executes a fixed testing process; the test decision logic remains within a pre-defined framework and cannot respond to the dynamic operating characteristics of the chip. Another approach, such as Chinese invention patent CN119575148A, employs a frequency testing and graded verification method. This involves running test programs on the chip at initial and maximum frequencies, and then classifying the chip based on the duration of the runtime. However, this method only focuses on the runtime index of the chip at a specific frequency and does not delve into the multi-dimensional characteristics of the chip during its dynamic operation. In summary, existing chip testing technologies, whether based on fixed-process testing with script parsing or frequency-level index verification, have failed to overcome the inherent limitations of static testing. Summary of the Invention This application provides an integrated circuit testing method, apparatus, device, and storage medium to at least solve the problem of inflexible chip testing methods in existing chip testing technologies that use static testing modes.

[0004] In a first aspect, this application provides an integrated circuit testing method, the method being applied to an adaptive test platform, the method comprising: After the integrated circuit under test is installed in the test socket and the test process begins, continuous dynamic stress required for the current test scenario is triggered on the integrated circuit. The multidimensional dynamic response signal generated by the integrated circuit in response to the dynamic stress is acquired. Based on the multidimensional dynamic response signal, dynamic behavioral fingerprint data characterizing the performance features of the integrated circuit is constructed; The dynamic behavioral fingerprint data of the integrated circuit is analyzed, adaptive decisions are made for the integrated circuit, and the corresponding test processing flow is executed.

[0005] In an optional embodiment of this application, applying the dynamic stress required for the current test scenario to the integrated circuit after it is mounted onto the test socket and the test process begins includes: After the integrated circuit is installed in the test socket and the test process begins, a sweep frequency power supply stress and an execution operation stress are simultaneously applied to the integrated circuit. The frequency sweep power supply stress is achieved by superimposing a sinusoidal ripple on the core power supply voltage of the integrated circuit, wherein the frequency of the sinusoidal ripple is a linear frequency sweep from 1MHz to 50MHz. The computational stress is achieved by triggering the integrated circuit to execute a pre-set task with a periodically changing computational load.

[0006] In an optional embodiment of this application, the acquisition of the multidimensional dynamic response signal generated by the integrated circuit in response to the dynamic stress includes: During the continuous application of the dynamic stress, multidimensional dynamic response signals generated by the stress are synchronously acquired through preset hardware sensors: The multidimensional dynamic response signal includes: dynamic current signal and dynamic heat distribution signal.

[0007] In an optional embodiment of this application, the step of constructing dynamic behavioral fingerprint data characterizing the performance features of the integrated circuit based on the multidimensional dynamic response signal includes: Feature extraction is performed on the dynamic current signal and dynamic thermal signal of the integrated circuit to obtain frequency domain features, time-domain-thermal domain features and trajectory features; The obtained frequency domain features, time-domain-thermal domain features, and trajectory features are combined in sequence to obtain a quantized four-dimensional feature vector, which serves as the dynamic behavior fingerprint data.

[0008] In an optional embodiment of this application, the step of analyzing the dynamic behavioral fingerprint data of the integrated circuit, making adaptive decisions for the integrated circuit, and executing the test processing flow under the corresponding decisions includes: The dynamic behavior fingerprint data of the integrated circuit is compared with a preset threshold in the policy library; The quality level of the integrated circuit is determined based on the comparison results. If the integrated circuit is classified as a high-quality integrated circuit, then the integrated circuit undergoes a reduced testing process and enters a rapid confirmation process. If the quality level of the integrated circuit is a questionable integrated circuit, then a deep testing and screening process for the integrated circuit is triggered; If the quality grade of the integrated circuit is a failed integrated circuit, the integrated circuit is determined to be unqualified, the test process is terminated, and the integrated circuit is marked.

[0009] In an optional embodiment of this application, the dynamic stress further includes: accelerated aging stress, which is achieved by applying periodic high-current impacts to the integrated circuit in a high-temperature environment above a specified temperature.

[0010] In an optional embodiment of this application, the step of analyzing the dynamic behavioral fingerprint data of the integrated circuit, making adaptive decisions for the integrated circuit, and executing the test processing flow under the corresponding decisions further includes: The reliability prediction model in the preset strategy library is invoked, and the dynamic behavioral fingerprint data characterizing the performance degradation rate of the integrated circuit is used as input. Based on the reliability prediction model, the expected lifetime level of the integrated circuit is predicted. Based on the lifespan level, the integrated circuit is marked and classified and / or the corresponding processing flow is triggered.

[0011] Secondly, embodiments of this application provide an integrated circuit testing apparatus, which is applied to an adaptive testing platform, and the apparatus includes: The triggering module is used to apply dynamic stress required for the current test scenario to the integrated circuit after it is installed in the test socket and the test process begins. The acquisition module is used to acquire the multidimensional dynamic response signal generated by the integrated circuit in response to the dynamic stress; A construction module is used to construct dynamic behavioral fingerprint data characterizing the performance features of the integrated circuit based on the multidimensional dynamic response signal; The adaptive decision module is used to analyze the dynamic behavioral fingerprint data of the integrated circuit, make adaptive decisions for the integrated circuit, and execute the test processing flow under the corresponding decision.

[0012] In an optional embodiment of this application, the triggering module is specifically used for: After the integrated circuit under test is installed in the test socket and the test process begins, a sweep frequency power supply stress and a computational stress are synchronously applied to the integrated circuit. The frequency sweep power supply stress is achieved by superimposing a sinusoidal ripple on the core power supply voltage of the integrated circuit, wherein the frequency of the sinusoidal ripple is a linear frequency sweep from 1MHz to 50MHz. The computational stress is achieved by controlling the integrated circuit to perform a pre-set computational load that changes periodically.

[0013] In an optional embodiment of this application, the acquisition module is specifically used for: During the continuous application of the dynamic stress, a multidimensional dynamic response signal generated by the stress is synchronously acquired by a preset hardware sensor. The multidimensional dynamic response signal includes: dynamic current signal and dynamic heat distribution signal.

[0014] In an optional embodiment of this application, the construction module specifically includes: The acquisition unit is used to extract features from the acquired dynamic current signal and dynamic thermal signal of the integrated circuit to obtain frequency domain features, time-domain-thermal domain features and trajectory features; The quantization unit is used to combine the obtained frequency domain features, time-domain-thermal domain features and trajectory features in sequence to obtain a quantized four-dimensional feature vector, which serves as the dynamic behavior fingerprint data.

[0015] In an optional embodiment of this application, the adaptive decision-making module specifically includes: A comparison unit is used to compare the dynamic behavior fingerprint data of the integrated circuit with a preset threshold in the policy library; A determining unit is used to determine the quality level of the integrated circuit corresponding to the integrated circuit based on the comparison results; The verification unit is used to perform a reduced testing process on the integrated circuit and enter a fast verification process if the quality level of the integrated circuit is a high-quality integrated circuit. A deep testing unit is used to trigger a deep testing and screening process for the integrated circuit if the quality level of the integrated circuit is a questionable integrated circuit. The termination unit is used to determine that the integrated circuit is unqualified if the quality level of the integrated circuit is a failed integrated circuit, trigger the termination test process, and mark the integrated circuit.

[0016] In an optional embodiment of this application, the dynamic stress further includes: accelerated aging stress, which is achieved by applying periodic high-current impacts to the integrated circuit in a high-temperature environment above a specified temperature.

[0017] In an optional embodiment of this application, the adaptive module further includes: The calling unit is used to call the reliability prediction model in the preset strategy library, take the dynamic behavior fingerprint data characterizing the performance degradation rate of the integrated circuit as input, and predict the expected lifetime level of the integrated circuit based on the reliability prediction model. The marking unit is used to mark and classify the integrated circuit according to its lifetime level and / or trigger the corresponding processing flow.

[0018] Thirdly, this application provides a communication fault location device for home appliances, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, communication interface, and memory communicate with each other through the communication bus. Memory, used to store computer programs; When a processor executes a program stored in memory, it implements the steps of the method as described in any embodiment of the first aspect.

[0019] Fourthly, this application also provides a computer-readable storage medium, characterized in that it stores a computer program thereon, which, when executed by a processor, implements the steps of the method described in any embodiment of the first aspect.

[0020] Compared with the prior art, the technical solution provided in this application has the following advantages: The integrated circuit testing method provided in this application involves an adaptive testing platform that, after the integrated circuit under test is installed in the test socket and the testing process begins, triggers the application of dynamic stress required for the current test scenario to the integrated circuit. Different test indicators require different test scenarios, and the applied dynamic stress may also differ. The platform collects multi-dimensional dynamic response signals generated by the integrated circuit in response to dynamic stress; based on these multi-dimensional dynamic response signals, it constructs dynamic behavioral fingerprint data characterizing the performance features of the integrated circuit under test; the platform analyzes the dynamic behavioral fingerprint data of the integrated circuit and makes adaptive decisions, executing the corresponding test processing flow based on the adaptive decision results. In this application embodiment, stress corresponding to different integrated circuit test scenarios is applied, and then the test strategy is adaptively selected for the integrated circuit based on its different stress responses, solving the problem of inflexible chip testing methods in existing chip testing technologies that use static testing modes. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0024] Figure 1 A flowchart illustrating a testing method for an integrated circuit provided in an embodiment of this application; Figure 2 A flowchart illustrating a method for constructing dynamic behavioral fingerprint data according to an embodiment of this application; Figure 3 This is a flowchart illustrating adaptive decision-making for an integrated circuit, provided as a specific embodiment of this application. Figure 4 A flowchart illustrating adaptive decision-making for integrated circuit quality is provided for a specific embodiment of this application; Figure 5 A schematic diagram of the apparatus for an integrated circuit testing method provided in this application embodiment; Figure 6 This is a schematic diagram of the structure of an integrated circuit testing device provided in an embodiment of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0027] Traditional chip testing methods primarily employ static testing schemes with fixed patterns and predefined criteria, resulting in incomplete test coverage, low efficiency, and a lack of deep capture and adaptive decision-making capabilities for the dynamic characteristics of integrated circuits. Consequently, the comprehensiveness, accuracy, and flexibility of testing still need improvement. Therefore, there is an urgent need for a testing technology capable of dynamically responding to the chip's operating state and deeply mining its dynamic characteristics to address the shortcomings of existing technologies. Based on this, this application provides an integrated circuit testing method, apparatus, device, and storage medium. The following detailed embodiments illustrate the solution provided in this application.

[0028] Figure 1 A flowchart illustrating an integrated circuit testing method provided in this application embodiment; see reference. Figure 1 As shown, this method is applied to an adaptive testing platform, and includes the following steps S10-S40: S10. After the integrated circuit under test is installed in the test socket and the test process begins, the adaptive test platform triggers the application of continuous dynamic stress required by the current test scenario to the integrated circuit.

[0029] In this embodiment, the adaptive platform can support different integrated circuit testing scenarios and configure different dynamic stresses for the test targets under different testing scenarios, so as to meet the integrated circuit testing work of different test targets under various scenarios.

[0030] In this step, dynamic composite stress is used as the excitation source. Compared with the traditional static testing method, it can capture richer information on the stress behavior of integrated circuits during the testing process.

[0031] In one embodiment of this application, step S10 above, after the integrated circuit under test is installed on the test socket and the test process begins, applies the dynamic stress required for the current test scenario to the integrated circuit, specifically including the following step A10: Step A10: After the integrated circuit under test is installed in the test socket and the test process begins, a sweep frequency power supply stress and a computational stress are synchronously applied to the integrated circuit.

[0032] In this embodiment, the aforementioned frequency sweep power supply stress is achieved by superimposing a sinusoidal ripple with an amplitude of 5%·VDD on the core power supply voltage VDD of the integrated circuit. The frequency of the sinusoidal ripple is a linear frequency sweep from 1MHz to 50MHz.

[0033] The aforementioned computational stress is achieved by controlling the integrated circuit to perform a pre-set task with periodically varying computational load. For example, this stress is achieved by controlling the integrated circuit to perform a specially designed task with periodically varying computational load, thereby causing corresponding dynamic fluctuations in its internal power consumption.

[0034] S20. Acquire the multidimensional dynamic response signal generated by the integrated circuit in response to the dynamic stress.

[0035] The platform applies composite dynamic stress to enable integrated circuits to generate multidimensional dynamic response signals.

[0036] In one embodiment of this application, taking the platform simultaneously applying the aforementioned power supply stress and computational stress as an example, step S20, which involves acquiring the multi-dimensional dynamic response signal generated by the integrated circuit in response to the dynamic stress, specifically includes the following step B10: Step B10: During the continuous application of the dynamic stress, the multidimensional dynamic response signal generated by the stress is synchronously acquired through a preset hardware sensor.

[0037] The aforementioned multidimensional dynamic response signals include: dynamic current signals and dynamic heat distribution signals.

[0038] In a specific embodiment of this application, the adaptive testing platform synchronously acquires two types of dynamic response signals through hardware sensors during the entire process of continuous stress application, such as 10 milliseconds. One is a dynamic current signal, which records the subtle current fluctuation waveform on the power supply pin through a current probe; the other is a dynamic thermal signal, which can be recorded by a thermal imager at a speed of 1000 frames per second to capture the dynamic changes in the surface temperature field of the integrated circuit.

[0039] S30. Based on the multidimensional dynamic response signal, construct dynamic behavioral fingerprint data characterizing the performance features of the integrated circuit.

[0040] In one embodiment of this application, the high-dimensional waveform data collected is used to generate a low-dimensional feature vector with clear physical meaning through a feature extraction algorithm. This feature vector is called dynamic behavioral fingerprint data, which is a summary of the behavior of the integrated circuit under stress.

[0041] Figure 2 A flowchart illustrating a method for constructing dynamic behavioral fingerprint data according to an embodiment of this application; see reference. Figure 2 In the specific embodiment shown, step S30 above, based on the multi-dimensional dynamic response signal, constructs dynamic behavioral fingerprint data characterizing the performance features of the integrated circuit, specifically including the following steps S301-S302: S301. Extract features from the acquired dynamic current signal and dynamic thermal signal of the integrated circuit to obtain frequency domain features, time-domain-thermal domain features and trajectory features.

[0042] In one specific embodiment, after acquiring dynamic current signals and thermal imaging sequences (dynamic thermal distribution signals) during the integrated circuit testing process, the system control unit performs feature extraction on the raw data within milliseconds, specifically extracting the following three types of features to constitute a unique behavioral fingerprint of the integrated circuit: (1) Frequency domain characteristics: The above dynamic current signal is analyzed, and the noise harmonic amplitude at two key frequency points of 20MHz and 40MHz is extracted and denoted as I_noise_20M and I_noise_40M respectively. (2) Time-domain-thermal domain characteristics: Locate the "hot spot" region of the integrated circuit from the thermal image sequence, calculate the temperature rise curve of the "hot spot" region, and obtain the integral area of ​​the temperature rise curve in the first 5 milliseconds, denoted as Thermal_Area. (3) Trajectory characteristics: Using the "instantaneous current value" of the integrated circuit as the X-axis and the "instantaneous hot spot temperature" as the Y-axis, draw the state trajectory diagram of the integrated circuit in this test, and calculate the area of ​​the graphic enclosed by the state trajectory diagram, denoted as Trajectory_Area.

[0043] S302. The obtained frequency domain features, time-domain-thermal domain features and trajectory features are combined in sequence to obtain a quantized four-dimensional feature vector, which is used as the dynamic behavior fingerprint data.

[0044] In this embodiment, after obtaining the frequency domain features, time-domain-thermal domain features, and trajectory feature data, the above data I_noise_20M, I_noise_40M, Thermal_Area, and Trajectory_Area are combined in sequence to form a quantized four-dimensional feature vector. This four-dimensional feature vector is the behavioral fingerprint of the integrated circuit, and its expression is: Fingerprint=[I_noise_20M, I_noise_40M, Thermal_Area, Trajectory_Area], abbreviated as vector F.

[0045] S40. Analyze the dynamic behavior fingerprint data of the integrated circuit, make adaptive decisions for the integrated circuit, and execute the test processing flow under the corresponding decision.

[0046] After obtaining the four-dimensional feature fingerprint vector F, the test processing flow of the integrated circuit is adaptively decided based on the fingerprint vector F and the adaptive strategy library.

[0047] Figure 3 This application provides a schematic flowchart illustrating adaptive decision-making for integrated circuits according to an embodiment of the present application; see reference. Figure 3As shown, in step S40 above, the dynamic behavioral fingerprint data of the integrated circuit is analyzed, adaptive decisions are made for the integrated circuit, and the test processing flow under the corresponding decision is executed, specifically including the following steps S401-S405: S401. Compare the dynamic behavior fingerprint data of the integrated circuit with a preset threshold in the policy library.

[0048] S402. Determine the quality level of the integrated circuit corresponding to the integrated circuit based on the comparison results.

[0049] For example, the quality level of the integrated circuit can be divided into: high-quality integrated circuit, doubtful integrated circuit, and failed integrated circuit, and different decisions can be made for different integrated circuit categories.

[0050] S403. If the integrated circuit is of high quality, then the integrated circuit undergoes a reduced testing process and enters a rapid confirmation process.

[0051] S404. If the quality level of the integrated circuit is a questionable integrated circuit, then a deep testing and screening process is triggered for the integrated circuit.

[0052] S405. If the quality grade of the integrated circuit is a failed integrated circuit, the integrated circuit is determined to be unqualified, the test termination process is triggered, and the integrated circuit is marked.

[0053] For example, you can refer to Figure 4 The specific embodiment of the adaptive decision-making scenario for chip quality shown compares the fingerprint vector F calculated in real time with multiple preset thresholds in the policy library, and automatically executes one of the following three strategies: Decision A (the goal is to quickly release high-quality chips): If all feature values ​​in vector F are within the set threshold range for high-quality chips, the system determines that the chip is a high-quality chip. At this time, the system will skip multiple subsequent routine tests for this chip and directly enter a simplified fast confirmation process, which reduces the total testing time of the chip by about 50%.

[0054] Decision B (the purpose is to deeply screen suspicious chips): If some feature values ​​in vector F (e.g., I_noise_40M) are within the threshold range of suspicious chips but do not reach the failure threshold, the system determines that the chip has potential risks. At this time, the system will automatically trigger an additional, more intense high-load stress test to deeply screen the chip by extending the test time and increasing the test intensity.

[0055] Decision C (the goal is to quickly eliminate failed chips): If any feature value in vector F is within the failure threshold range, the system will immediately determine that the chip is unqualified; at this time, the system will terminate the entire testing process and mark the chip as defective, thereby effectively saving all subsequent testing resources.

[0056] In this embodiment, a dynamic testing system is established to apply dynamic stress that varies according to specific rules in real time during testing, targeting different testing scenarios and objectives. Simultaneously, multi-dimensional response signals from the chip are acquired, thereby capturing subtle characteristics of the chip in its actual operating state. Then, deep features not readily apparent from these dynamic signals are extracted to construct a unique behavioral fingerprint for each chip—a kind of dynamic identity card. Based on this, the system further compares the behavioral fingerprint with a preset intelligent strategy library, generating and executing an optimal testing plan in real time and dynamically.

[0057] The technical solution of this application can more effectively screen out chips with potential defects, while significantly shortening the inspection time of high-quality chips. The testing is more comprehensive and flexible, and can be widely applied to various integrated circuit testing scenarios.

[0058] In another embodiment of this application, in the testing scenario of automotive-grade chips, such as the testing scenario of MCU / SoC chips for engine controllers and braking systems, the testing objective in this scenario is not only to determine whether the chip test passes or fails, but also to predict the long-term reliability of the chip and to perform fine classification in order to determine the different safety levels of applications to which it is applicable.

[0059] Furthermore, in the aforementioned test scenario, the dynamic stresses set by the system also include: accelerated aging stress, which is achieved by applying periodic high-current surges to the integrated circuit at a high-temperature environment above a specified temperature. Specifically, periodic high-current surges can be applied to the integrated circuit at a high-temperature environment above 125°C to simulate and accelerate its aging process.

[0060] In this embodiment, during the response signal acquisition process, in addition to the dynamic current signal, the transmission delay data of the critical path of the integrated circuit is also acquired. Specifically, this can be done online through the ring oscillator integrated inside the integrated circuit or a dedicated timing measurement unit.

[0061] The integrated circuit dynamic behavior fingerprint data in this embodiment aims to characterize the performance degradation rate of the integrated circuit. A final fingerprint vector is constructed by extracting degradation trajectory features over multiple test cycles. For example: Feature 1: the rate of change of the dynamic current peak after each stress cycle; Feature 2: the increase in critical path delay after each stress cycle. This fingerprint vector is a feature set that can quantify the performance degradation trend of the integrated circuit.

[0062] Therefore, in this embodiment, step S40 above, which involves analyzing the dynamic behavioral fingerprint data of the integrated circuit, making adaptive decisions for the integrated circuit, and executing the test processing flow under the corresponding decisions, further includes the following steps C10-C20: Step C10: Call the reliability prediction model in the preset strategy library, take the dynamic behavioral fingerprint data characterizing the performance degradation rate of the integrated circuit as input, and predict the expected lifetime level of the integrated circuit based on the reliability prediction model.

[0063] In this embodiment, the strategy library can be a reliability prediction model, such as a machine learning model trained with a large amount of historical data. By inputting real-time fingerprint data into the prediction model, the expected lifespan of the integrated circuit can be predicted.

[0064] Step C20: According to the lifespan level, the integrated circuit is marked and classified and / or the corresponding processing flow is triggered.

[0065] For example, integrated circuits can be classified into Class A, Class B, or Class C based on their expected lifespan. Class A represents the highest reliability integrated circuits used in core security applications, Class B represents high reliability integrated circuits used in general control applications, and Class C represents commercial-grade integrated circuits that can be downgraded or phased out.

[0066] Based on the final classification results, the testing system writes different identifiers for the aforementioned integrated circuits and distributes them to different application areas.

[0067] The solution presented in this embodiment elevates testing from quality inspection to quality prediction and empowerment. It addresses not only testing efficiency but also the ultimate reliability of the product. The introduction of online aging monitoring and data model-based predictive grading significantly distinguishes it from traditional single-condition testing in both methodology and objectives, and sets it apart from existing testing solutions that focus solely on the "current state" rather than "future trends."

[0068] Figure 5 This is a schematic diagram of the structure of an integrated circuit testing device provided in an embodiment of this application; see reference. Figure 5 As shown in this embodiment, an integrated circuit testing apparatus is provided. This apparatus is applied to an adaptive test platform and includes: Trigger module 501 is used to trigger the application of continuous dynamic stress required by the current test scenario to the integrated circuit after the integrated circuit is installed into the test socket and the test process begins. The acquisition module 502 is used to acquire the multidimensional dynamic response signal generated by the integrated circuit in response to the dynamic stress; Construction module 503 is used to construct dynamic behavioral fingerprint data characterizing the performance features of the integrated circuit based on the multidimensional dynamic response signal; The adaptive decision module 504 is used to analyze the dynamic behavioral fingerprint data of the integrated circuit, make adaptive decisions for the integrated circuit, and execute the test processing flow under the corresponding decision.

[0069] In an optional embodiment of this application, the triggering module 501 is specifically used for: After the integrated circuit is installed in the test socket and the test process begins, a sweep frequency power supply stress and a computational stress are synchronously applied to the integrated circuit. The frequency sweep power supply stress is achieved by superimposing a sinusoidal ripple on the core power supply voltage of the integrated circuit, wherein the frequency of the sinusoidal ripple is a linear frequency sweep from 1MHz to 50MHz. The computational stress is achieved by controlling the integrated circuit to perform a pre-set computational load that changes periodically.

[0070] In an optional embodiment of this application, the aforementioned acquisition module 502 is specifically used for: During the continuous application of the dynamic stress, a multidimensional dynamic response signal generated by the stress is synchronously acquired by a preset hardware sensor. The multidimensional dynamic response signal includes: dynamic current signal and dynamic heat distribution signal.

[0071] In an optional embodiment of this application, the above-mentioned construction module 503 specifically includes: The acquisition unit is used to extract features from the acquired dynamic current signal and dynamic thermal signal of the integrated circuit to obtain frequency domain features, time-domain-thermal domain features and trajectory features; The quantization unit is used to combine the obtained frequency domain features, time-domain-thermal domain features and trajectory features in sequence to obtain a quantized four-dimensional feature vector, which serves as the dynamic behavior fingerprint data.

[0072] In an optional embodiment of this application, the adaptive decision module 504 specifically includes: A comparison unit is used to compare the dynamic behavior fingerprint data of the integrated circuit with a preset threshold in the policy library; A determining unit is used to determine the quality level of the integrated circuit corresponding to the integrated circuit based on the comparison results; The verification unit is used to perform a reduced testing process on the integrated circuit and enter a fast verification process if the quality level of the integrated circuit is a high-quality integrated circuit. A deep testing unit is used to trigger a deep testing and screening process for the integrated circuit if the quality level of the integrated circuit is a questionable integrated circuit. The termination unit is used to determine that the integrated circuit is unqualified if the quality level of the integrated circuit is a failed integrated circuit, trigger the termination test process, and mark the integrated circuit.

[0073] In an optional embodiment of this application, the dynamic stress further includes: accelerated aging stress, which is achieved by applying periodic high-current surges to the integrated circuit in a high-temperature environment above a specified temperature.

[0074] In an optional embodiment of this application, the adaptive decision module 504 further includes: The calling unit is used to call the reliability prediction model in the preset strategy library, take the dynamic behavior fingerprint data characterizing the performance degradation rate of the integrated circuit as input, and predict the expected lifetime level of the integrated circuit based on the reliability prediction model. The marking unit is used to mark and classify the integrated circuit according to its lifetime level and / or trigger the corresponding processing flow.

[0075] The specific workflow of the integrated circuit testing device provided in this embodiment is described in the above method embodiment, and will not be repeated here.

[0076] like Figure 6 As shown in the figure, this application provides an integrated circuit testing device, including a processor 111, a communication interface 112, a memory 113, and a communication bus 114, wherein the processor 111, the communication interface 112, and the memory 113 communicate with each other through the communication bus 114. Memory 113 is used to store computer programs; In one embodiment of this application, when the processor 111 executes the program stored in the memory 113, it implements the integrated circuit testing method provided in any of the foregoing method embodiments, including: after the integrated circuit is installed in the test socket and the test process starts, triggering the application of continuous dynamic stress required by the current test scenario to the integrated circuit; The multidimensional dynamic response signal generated by the integrated circuit in response to the dynamic stress is acquired. Based on the multidimensional dynamic response signal, dynamic behavioral fingerprint data characterizing the performance features of the integrated circuit is constructed; The dynamic behavioral fingerprint data of the integrated circuit is analyzed, adaptive decisions are made for the integrated circuit, and the corresponding test processing flow is executed.

[0077] In an optional embodiment of this application, when the processor 111 executes the program stored in the memory 113, it implements the integrated circuit testing method provided in any of the foregoing method embodiments, including the following steps: After the integrated circuit is installed in the test socket and the test process begins, a sweep frequency power supply stress and a computational stress are synchronously applied to the integrated circuit. The frequency sweep power supply stress is achieved by superimposing a sinusoidal ripple on the core power supply voltage of the integrated circuit, wherein the frequency of the sinusoidal ripple is a linear frequency sweep from 1MHz to 50MHz. The computational stress is achieved by controlling the integrated circuit to perform a pre-set computational load that changes periodically.

[0078] In an optional embodiment of this application, when the processor 111 executes the program stored in the memory 113, it implements the integrated circuit testing method provided in any of the foregoing method embodiments, including the following steps: During the continuous application of the dynamic stress, a multidimensional dynamic response signal generated by the stress is synchronously acquired by a preset hardware sensor. The multidimensional dynamic response signal includes: dynamic current signal and dynamic heat distribution signal.

[0079] In an optional embodiment of this application, when the processor 111 executes the program stored in the memory 113, it performs the following steps: Feature extraction is performed on the dynamic current signal and dynamic thermal signal of the integrated circuit to obtain frequency domain features, time-domain-thermal domain features and trajectory features; The obtained frequency domain features, time-domain-thermal domain features, and trajectory features are combined in sequence to obtain a quantized four-dimensional feature vector, which serves as the dynamic behavior fingerprint data.

[0080] In an optional embodiment of this application, when the processor 111 executes the program stored in the memory 113, it implements the integrated circuit testing method provided in any of the foregoing method embodiments, including the following steps: The dynamic behavior fingerprint data of the integrated circuit is compared with a preset threshold in the policy library; The quality level of the integrated circuit is determined based on the comparison results. If the integrated circuit is classified as a high-quality integrated circuit, then the integrated circuit undergoes a reduced testing process and enters a rapid confirmation process. If the quality level of the integrated circuit is a questionable integrated circuit, then a deep testing and screening process for the integrated circuit is triggered; If the quality grade of the integrated circuit is a failed integrated circuit, the integrated circuit is determined to be unqualified, the test process is terminated, and the integrated circuit is marked.

[0081] In an optional embodiment of this application, the dynamic stress further includes: accelerated aging stress, which is achieved by applying periodic high-current surges to the integrated circuit in a high-temperature environment above a specified temperature.

[0082] In an optional embodiment of this application, when the processor 111 executes the program stored in the memory 113, it implements the integrated circuit testing method provided in any of the foregoing method embodiments, including the following steps: The reliability prediction model in the preset strategy library is invoked, and the dynamic behavioral fingerprint data characterizing the performance degradation rate of the integrated circuit is used as input. Based on the reliability prediction model, the expected lifetime level of the integrated circuit is predicted. Based on the lifespan level, the integrated circuit is marked and classified and / or the corresponding processing flow is triggered.

[0083] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the integrated circuit testing method provided in any of the foregoing method embodiments: After the integrated circuit is installed in the test socket and the test process begins, continuous dynamic stress required for the current test scenario is triggered on the integrated circuit. The multidimensional dynamic response signal generated by the integrated circuit in response to the dynamic stress is acquired. Based on the multidimensional dynamic response signal, dynamic behavioral fingerprint data characterizing the performance features of the integrated circuit is constructed; The dynamic behavioral fingerprint data of the integrated circuit is analyzed, adaptive decisions are made for the integrated circuit, and the corresponding test processing flow is executed.

[0084] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0085] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0086] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0087] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for testing integrated circuits, characterized in that, The method is applied to an adaptive testing platform, and the method includes: After the integrated circuit under test is installed in the test socket and the test process begins, continuous dynamic stress required for the current test scenario is triggered on the integrated circuit. The multidimensional dynamic response signal generated by the integrated circuit in response to the dynamic stress is acquired. Based on the multidimensional dynamic response signal, dynamic behavioral fingerprint data characterizing the performance features of the integrated circuit is constructed; The dynamic behavioral fingerprint data of the integrated circuit is analyzed, adaptive decisions are made for the integrated circuit, and the corresponding test processing flow is executed.

2. The method according to claim 1, characterized in that, The step of applying dynamic stress required for the current test scenario to the integrated circuit after it is mounted onto the test socket and the test process begins includes: After the integrated circuit is installed in the test socket and the test process begins, a sweep frequency power supply stress and a computational stress are synchronously applied to the integrated circuit. The frequency sweep power supply stress is achieved by superimposing a sinusoidal ripple on the core power supply voltage of the integrated circuit, wherein the frequency of the sinusoidal ripple is a linear frequency sweep from 1MHz to 50MHz. The computational stress is achieved by controlling the integrated circuit to perform a pre-set computational load that changes periodically.

3. The method according to claim 1 or 2, characterized in that, The acquisition of the multidimensional dynamic response signal generated by the integrated circuit in response to the dynamic stress includes: During the continuous application of the dynamic stress, a multidimensional dynamic response signal generated by the stress is synchronously acquired by a preset hardware sensor. The multidimensional dynamic response signal includes: dynamic current signal and dynamic heat distribution signal.

4. The method according to claim 3, characterized in that, The construction of dynamic behavioral fingerprint data characterizing the performance features of the integrated circuit based on the multidimensional dynamic response signal includes: Feature extraction is performed on the dynamic current signal and dynamic thermal signal of the integrated circuit to obtain frequency domain features, time-domain-thermal domain features and trajectory features; The obtained frequency domain features, time-domain-thermal domain features, and trajectory features are combined in sequence to obtain a quantized four-dimensional feature vector, which serves as the dynamic behavior fingerprint data.

5. The method according to claim 1 or 2, characterized in that, The analysis of the dynamic behavioral fingerprint data of the integrated circuit, the adaptive decision-making for the integrated circuit, and the execution of the corresponding test processing flow include: The dynamic behavior fingerprint data of the integrated circuit is compared with a preset threshold in the policy library; The quality level of the integrated circuit is determined based on the comparison results. If the integrated circuit is classified as a high-quality integrated circuit, then the integrated circuit undergoes a reduced testing process and enters a rapid confirmation process. If the quality level of the integrated circuit is a questionable integrated circuit, then a deep testing and screening process for the integrated circuit is triggered; If the quality grade of the integrated circuit is a failed integrated circuit, the integrated circuit is determined to be unqualified, the test process is terminated, and the integrated circuit is marked.

6. The method according to claim 1 or 2, characterized in that, The dynamic stress also includes accelerated aging stress, which is achieved by applying periodic high-current surges to the integrated circuit in a high-temperature environment above a specified temperature.

7. The method according to claim 6, characterized in that, The step of analyzing the dynamic behavioral fingerprint data of the integrated circuit, making adaptive decisions for the integrated circuit, and executing the corresponding test processing flow under the decisions further includes: The reliability prediction model in the preset strategy library is invoked, and the dynamic behavioral fingerprint data characterizing the performance degradation rate of the integrated circuit is used as input. Based on the reliability prediction model, the expected lifetime level of the integrated circuit is predicted. Based on the lifespan level, the integrated circuit is marked and classified and / or the corresponding processing flow is triggered.

8. An integrated circuit testing device, characterized in that, The device is used in an adaptive testing platform, and the device includes: The triggering module is used to trigger the application of continuous dynamic stress required by the current test scenario to the integrated circuit after it is installed in the test socket and the test process begins. The acquisition module is used to acquire the multidimensional dynamic response signal generated by the integrated circuit in response to the dynamic stress; A construction module is used to construct dynamic behavioral fingerprint data characterizing the performance features of the integrated circuit based on the multidimensional dynamic response signal; The adaptive decision module is used to analyze the dynamic behavioral fingerprint data of the integrated circuit, make adaptive decisions for the integrated circuit, and execute the test processing flow under the corresponding decision.

9. A communication fault location device for home appliances, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus. The processor, communication interface, and memory communicate with each other through the communication bus. Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the steps of the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the steps of the method as described in any one of claims 1-7.

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