A photolithography method for realizing integration of a chip and a reticle

Abstract

The application discloses a kind of photolithography methods for realizing chip and reticle integration, belong to the field of photolithography.This method is on the same piece of double-side polished single crystal silicon support substrate, first through the first group of fractional photolithography process cycle to complete the whole process high-temperature semiconductor process preparation of photovoltaic chip, then through the second group of whole process temperature≤180℃ Low-temperature compatible fractional photolithography process cycle, prepare center alignment, parallel stacked MEMS movable reticle structure on the infrared incident light side of photovoltaic chip, completely abandon traditional split preparation and bonding assembly process.The application realizes≤0.8μm center alignment deviation by whole process unified alignment reference, solves the compatibility problem of semiconductor and MEMS process by low-temperature compatible process, and finally prepares an integrated device with infrared light modulation depth≥98%, photoelectric signal distortion rate≤1.0%, production cycle is shortened by more than 50%, comprehensive preparation cost is reduced by more than 40%, and environmental reliability and mass production consistency are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of photolithography technology, and more specifically to a photolithography method for integrating a chip and a modulation disk. Background Technology

[0002] Infrared detection technology is widely used in various detection and guidance scenarios, and infrared light modulation is a key step for infrared detectors to achieve high signal-to-noise ratio detection. In the traditional infrared detector fabrication scheme, the MEMS movable modulation disk and photovoltaic chip are fabricated separately, each completing two independent full-process manufacturing steps, and then aligned and bonded together using high-precision mounting equipment to finally form a usable detector core component.

[0003] This split-type process presents numerous intractable challenges. Split fabrication requires two complete production processes and equipment resources, resulting in long production cycles, high consumption of raw materials and consumables, and consequently, high overall manufacturing costs. During the bonding and assembly process, it is difficult to guarantee the alignment accuracy and parallelism of the modulation disk and the photovoltaic chip, easily leading to center misalignment and angular deviations. This directly results in decreased light modulation effect, increased light transmission loss, and severe distortion of the output photoelectric signal. The adhesive layer used for bonding not only introduces additional light loss but also exhibits problems such as debonding, cracking, and assembly misalignment under environmental stresses such as high and low temperature cycling, vibration, and shock. This causes significant performance degradation or even device failure, resulting in extremely poor environmental reliability.

[0004] Meanwhile, conventional fabrication processes for MEMS modulation disks often involve high-temperature procedures, while the infrared photosensitive semiconductor materials used in photovoltaic chips are extremely sensitive to high temperatures. High-temperature environments can cause material performance degradation, leading to problems such as decreased photoelectric conversion efficiency and increased dark current. The two processes have extremely poor compatibility, making it difficult to integrate and fabricate two types of structures on the same substrate. In addition, the separate assembly process involves a lot of manual intervention, resulting in poor performance consistency of devices in the same batch. The yield loss due to assembly errors is high, making it difficult to meet the needs of large-scale mass production.

[0005] To address this, a photolithography method for integrating the chip and modulation disk is proposed. Summary of the Invention

[0006] The present invention aims to solve the problems mentioned in the background art by providing a photolithography method for integrating a chip and a modulation disk.

[0007] The specific technical solution is as follows:

[0008] A photolithography method for integrating a chip and a modulation disk is as follows:

[0009] The optical modulation pattern of the movable modulation disk of the infrared detector MEMS and the semiconductor functional pattern of the photovoltaic chip are integrated in stages into a group of multiple photomasks with matching overlay precision.

[0010] On the same double-sided polished single-crystal silicon support substrate, the entire process is completed in two stages: First, the first set of step-by-step photolithography process cycles is executed to complete the photoelectric conversion functional structure, matching electrode leads, pad structure, and pad passivation window preparation of the photovoltaic chip; then, the second set of low-temperature compatible step-by-step photolithography process cycles with a full process temperature ≤180℃ is executed to prepare a MEMS modulation disk movable infrared optical modulation structure, an electrostatic comb drive structure, and an electrically isolated electrode lead and pad structure that are aligned with the center of the photoelectric conversion functional structure and stacked in parallel on the infrared incident light side of the photovoltaic chip.

[0011] The electrostatic comb drive structure drives the modulation disk optical modulation structure to perform linear reciprocating resonant motion, realizing the controllable relative motion between it and the photovoltaic chip photoelectric conversion functional structure. This allows the infrared incident light to be directly incident on the photosensitive surface of the photovoltaic chip after modulation, directly obtaining the core device of the integrated infrared detector of the chip and modulation disk without additional bonding assembly. All process steps of the second set of low-temperature compatible step-by-step photolithography process cycles are carried out in a nitrogen-protected environment, and an organosilane coupling agent transition layer is pre-formed on the passivation protection layer surface of the photovoltaic chip to enhance the interfacial bonding force between the low-temperature process film layer and the passivation layer, and prevent the influence of high-temperature process residual stress on the subsequent MEMS structure.

[0012] Using the above scheme, two functional structures are fabricated in stages on the same substrate, achieving the integration of the two types of structures. This eliminates the need for subsequent bonding and assembly, avoiding alignment deviations and interface failures caused by assembly. The low-temperature process avoids the impact of high-temperature environments on the performance of the pre-fabricated semiconductor structure. The nitrogen protective atmosphere and the setting of the interface transition layer improve the bonding stability between film layers and reduce the adverse effects of residual process stress on the microstructure. The modulation structure and the photoelectric conversion structure are directly stacked and aligned, allowing infrared light to be directly incident on the photosensitive area after modulation, reducing losses during light transmission and improving the quality of the photoelectric signal. The integrated structural design allows the driving action to be directly matched with the photoelectric conversion structure, improving the controllability and response efficiency of the modulation action.

[0013] In the above method, the photolithography mask group includes interconnected chip positioning pattern groups and modulation disk positioning pattern groups. The mask fabrication accuracy meets the following requirements: the relative positional deviation between the semiconductor functional pattern of the photovoltaic chip and the chip positioning pattern group is ≤1.0μm, preferably 0.5μm-0.8μm; the relative positional deviation between the optical modulation pattern of the MEMS modulation disk and the modulation disk positioning pattern group is ≤1.0μm, preferably 0.5μm-0.8μm; both positioning pattern groups match the dimensional accuracy of the substrate positioning marks, the linewidth of the substrate positioning marks is 3μm-5μm, and they are pre-formed on the substrate surface through photolithography and etching processes during the substrate pre-processing stage, so that the motion center of the movable optical modulation structure of the photolithographically formed MEMS modulation disk is aligned with the photoelectric conversion functional structure of the photovoltaic chip. The center position deviation of the photosensitive element array is ≤1.0μm, preferably controlled within the range of 0.5μm-0.8μm; the parallelism angle deviation between the grating lines and the photosensitive element array is ≤0.01°, preferably 0.005°-0.008°; the photosensitive element array is arranged in equally spaced linear columns or area arrays, with the size of a single photosensitive element being 20μm-50μm, and the side length of a single photosensitive element matching the grating period of the chopper grating with a deviation of ≤3μm, preferably 2μm-2.5μm; within this size range, the overlap between the light-transmitting area and the photosensitive area in the static overlap state is ≥90%, preferably 92%-95%; the substrate positioning mark adopts a cross-shaped or L-shaped composite mark, which is prepared by electron beam lithography, and the mark edge roughness is ≤0.1μm to improve alignment accuracy and repeatability.

[0014] This scheme unifies the alignment reference for the entire photolithography process by using two sets of linked positioning patterns on the mask, in conjunction with pre-formed positioning marks on the substrate. This avoids the cumulative alignment deviation caused by multiple references, ensuring the alignment accuracy of the two types of functional structures and improving their center coincidence and parallelism. The size matching design of the photosensitive structure and the modulation grating ensures the overlap between the light-transmitting area and the photosensitive area, improving the effectiveness of light modulation. The high-precision positioning mark fabrication process improves the repeatability and stability of photolithography alignment and reduces batch-to-batch alignment deviation.

[0015] In the above method, the optical modulation pattern of the modulation disk on the photolithographic mask assembly includes an equally spaced chopper grating pattern that matches the modulation frequency of the infrared detector guidance system. The duty cycle of the chopper grating = grating line width / (grating line width + grating spacing) = 50% ± 3%, meaning the grating line width and grating spacing are equal, with a deviation ≤ ± 3%. The grating period of the chopper grating = grating line width + grating spacing, ranging from 25 μm to 45 μm, preferably 30 μm to 40 μm. The matched modulation frequency is consistent with the inherent resonant frequency of the MEMS electrostatic drive structure, with a deviation ≤ ± 1.0%, preferably ± 0.5%. For the same device design, its resonant frequency is set within one of the following sub-ranges: 100Hz-500Hz, 500Hz-2kHz, 2kHz-5kHz, or 5kHz-10kHz. The grating line width of the chopper grating pattern is 12 μm-22 μm, and the grating spacing is 12 μm-22 μm. The edge roughness is ≤0.5μm, preferably 0.3μm-0.4μm; the thickness of the metal structure layer of the chopper grid is 2μm-4μm, preferably 2.5μm-3.5μm; the grid lines of the chopper grid pattern are set parallel to the column edges of the photosensitive element array of the photovoltaic chip semiconductor functional pattern, the center of the grid array coincides with the center of the photosensitive element array, when the chopper grid moves linearly reciprocating resonantly with the electrostatic drive structure, the effective driving stroke in one direction is ≥1 / 2 grid period, the light-transmitting area and the photosensitive area of ​​the photosensitive element periodically coincide and block each other in the normal direction of the substrate, and the overlap of the light-transmitting area and the photosensitive area in the static overlap state is ≥90%, preferably 92%-95%, so that the infrared incident light is directly incident on the photosensitive surface of the photosensitive element after being modulated by the chopper grid; the metal structure layer of the chopper grid is made of gold or aluminum, and the surface is chemically and mechanically polished, with a surface roughness Ra≤10nm, in order to improve infrared reflectivity and reduce light scattering loss.

[0016] This scheme ensures the stability of modulation and the accuracy of modulation frequency by matching the parameters of the modulation grating with the inherent frequency of the driving structure. The parallel arrangement and center-aligned design of the grating structure and the photosensitive array, combined with sufficient driving stroke, achieves periodic and precise overlap and blocking of the light-transmitting and photosensitive areas, ensuring the uniformity of light modulation. The surface treatment process of the metal grating improves infrared reflection, reduces losses caused by light scattering, and enhances the efficiency of light modulation.

[0017] The above method, in which, before performing the photolithography process cycle, first performs megahertz-level ultrasonic cleaning on the single-crystal silicon support substrate, with a cleaning power of 300W-800W and a cleaning time of 5min-15min; the substrate thickness is 200μm-500μm; after cleaning, the first set of stepwise photolithography process cycles is performed to fabricate the photoelectric conversion core structure of the photovoltaic chip in the photovoltaic functional area of ​​the substrate, the specific steps of which are as follows:

[0018] S1. In ≤5×10 -4 Under a vacuum environment of Pa, a lattice-matching buffer layer is first epitaxially grown on the surface of the photovoltaic functional region of the substrate using molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD). A CdTe buffer layer is used for the mercury cadmium telluride photosensitive layer, and a ZnS buffer layer is used for the lead sulfide photosensitive layer, with a thickness of 50nm-200nm. Then, an infrared photosensitive semiconductor functional layer and a passivation transition layer are sequentially prepared on the surface of the lattice-matching buffer layer using the same epitaxial process. The infrared photosensitive semiconductor functional layer uses a lead sulfide or mercury cadmium telluride infrared photosensitive layer with a thickness of 300nm-800nm. The passivation transition layer uses a silicon nitride or silicon dioxide dielectric film with a thickness of 50nm-100nm to block impurities from subsequent processes.

[0019] S2. A PN junction photoelectric conversion structure for photovoltaic chips is fabricated through photolithography, doping, and annealing processes. The doping process employs ion implantation or vapor diffusion. For mercury cadmium telluride, the N-type dopant is In and the P-type dopant is As. For lead sulfide, the N-type dopant is I and the P-type dopant is Cu. The doping depth is 100nm-400nm, and the annealing temperature is 200℃-350℃, avoiding temperatures exceeding 350℃ to prevent material performance degradation. The annealing time is 45min-90min, followed by a stepped cooling to room temperature at a rate ≤2℃ / min, forming a PN junction structure with photovoltaic effect.

[0020] S3. Contact holes are prepared at corresponding positions of the N-type and P-type regions of the PN junction using photolithography and dry etching processes. The etching depth extends to expose the doped semiconductor layer of the PN junction, and the contact hole size is 5μm-15μm.

[0021] S4. The electrode leads and pad structures of the photovoltaic chip are prepared by photolithography, metal deposition and lift-off processes. The metal layer adopts a chromium-gold composite layer with a total thickness of 300nm-800nm ​​to realize the photoelectric signal extraction of the PN junction.

[0022] S5. After completing the fabrication of the photovoltaic functional structure and signal extraction structure, a passivation protective layer is deposited on the entire surface of the photovoltaic functional area. The passivation protective layer is a silicon nitride dielectric film with a thickness of 150nm-250nm. It is prepared by plasma-enhanced chemical vapor deposition at 300℃±10℃ to optimize the film stress and density. The transmittance in the 1μm-5μm infrared band is ≥92%. It also serves as a barrier layer for wet release and dry corrosion in subsequent MEMS processes. A 5nm-10nm thick organosilane coupling agent treatment layer is formed on the surface to improve the adhesion to the film layer in subsequent low-temperature processes.

[0023] S6. Passivation layer pad opening: Through photolithography and dry etching processes, the passivation protective layer is etched at the corresponding position of the electrode pads of the photovoltaic chip to form a pad opening, exposing the underlying metal pad. The opening size matches the pad size with a deviation of ≤5μm, completing the fabrication of all high-temperature processes and functional structures of the photovoltaic chip.

[0024] This approach reduces the adverse effects of impurities on subsequent film deposition and photolithography processes through substrate pretreatment and cleaning, thereby improving film quality. The lattice-matched buffer layer design enhances the crystal quality of the photosensitive layer, reduces interface defects, and optimizes photoelectric conversion. Stepwise photolithography, doping, and annealing processes precisely fabricate the functional structure for photoelectric conversion, ensuring the stability of the photovoltaic effect. The surface passivation protective layer ensures infrared light transmission while blocking impurities from subsequent processes, providing corrosion protection for later stages. The interface treatment process further enhances the bonding stability of subsequent film layers.

[0025] The above method, after completing the fabrication of the photovoltaic chip structure, executes a second set of low-temperature compatible step-by-step photolithography process cycles to fabricate the MEMS modulation disk structure. Specifically, this involves: firstly, performing oxygen plasma activation treatment on the silicon nitride passivation protective layer on the substrate surface, with a treatment power of 100W-300W and a treatment time of 30s-120s, to improve the adhesion between the subsequent film layer and the passivation layer; after activation treatment, spin-coating a 5nm-10nm thick layer of 3-aminopropyltriethoxysilane coupling agent onto the passivation layer surface, and curing it at 110℃ for 60 seconds to form... A transition layer is formed; then, a sacrificial layer is spin-coated onto the modulation disk functional area of ​​the substrate, which is the area directly above the photovoltaic chip photosensitive element array. The sacrificial layer is made of low-temperature curable polyimide with a thickness of 3μm-8μm, preferably 4μm-6μm; the curing temperature is 150℃-180℃, and the curing time is 75min-105min. This sacrificial layer is used to release the movable modulation structure of the MEMS and form the movement gap between the modulation disk and the photovoltaic chip. Then, anchor windows are defined in the sacrificial layer through photolithography and dry etching processes. The aperture includes cantilever beam fixing anchor points, fixed comb tooth electrode anchor points, electrode lead anchor points, and movable structure grounding anchor points, with etching depth up to expose the underlying passivation protective layer. Next, an adhesion layer, an optical reflection layer, and a conductive seed layer are sequentially vacuum-deposited within the sacrificial layer and anchor point windows to form a composite functional film system compatible with photolithography processes. The adhesion layer uses a chromium or titanium layer with a thickness of 8nm-15nm, preferably 10nm-12nm, to enhance the adhesion between film layers. The optical reflection and conductive seed layers use gold or aluminum films with a thickness of 100nm-18nm. The thickness is 0nm, preferably 120nm-150nm; it is subsequently thickened to 2μm-4μm, preferably 2.5μm-3.5μm, through electroplating; it also serves as the infrared reflection modulation layer of the modulation disk, the structural support layer of the MEMS movable structure, and the electrostatic driving electrode layer; the composite functional film system directly contacts the substrate passivation protection layer at the anchor point window to form a fixed anchor point; the sacrificial layer is made of polyimide, which can be selected as photosensitive polyimide, and can be directly patterned by photolithography, reducing one etching process and reducing the risk of damage to the underlying structure.

[0026] This scheme further enhances the adhesion between the subsequent film layers and the passivation layer by surface activation treatment of the passivation layer and setting an interface transition layer, reducing the risk of film detachment. The low-temperature curing sacrificial layer material avoids the impact of high-temperature environments on the performance of the fabricated semiconductor structure, while providing a controllable movement gap for the release of the movable structure. The anchor point window allows the fixed end of the movable structure to directly bond with the passivation layer on the substrate, improving the stability of the fixed structure. The design of the composite functional film system simultaneously meets multiple requirements for optical modulation, structural support, and conductive actuation, simplifying the process steps. The selection of a photosensitive sacrificial layer reduces etching processes and lowers the risk of damage to the underlying fabricated structure.

[0027] In the above method, the alignment and bonding of the mask and substrate in all photolithography processes are completed using a front-side alignment photolithography process with an overlay accuracy of ≤0.5μm, preferably 0.3μm-0.4μm; and all photolithography processes use the same set of pre-formed substrate positioning marks as the sole alignment reference; specifically: an alignment system is used with a photolithography equipment with a positioning resolution of ≤0.3μm, preferably 0.2μm-0.25μm; first, the position coordinates of the pre-formed substrate positioning marks on the substrate surface are collected, with sampling times ≥5 times to improve statistical reliability; the coordinate fitting deviation is ≤0.4μm, preferably 0.3μm-0.35μm; then, the positioning image on the current photolithography mask is collected. The position coordinates of the pattern group are based on the reference coordinates of the substrate positioning mark. The position of the photomask is adjusted so that the reference coordinates of the current mask positioning pattern group coincide with the reference coordinates of the substrate positioning mark. The angular deviation of the alignment adjustment is ≤0.01°, preferably 0.005°-0.008°. The alignment and bonding are completed. For the fine pattern photolithography process of MEMS chopper grid and comb electrode, step exposure is adopted. The field deviation of a single exposure is ≤0.2μm, preferably 0.1μm-0.15μm. Before each photolithography alignment, the substrate is subjected to temperature balancing treatment. The substrate is placed in an environment of 23℃±1℃ for more than 30 minutes to eliminate the influence of thermal drift on the overlay accuracy.

[0028] This solution utilizes the same alignment reference throughout the entire photolithography process, eliminating the cumulative alignment error caused by multiple references and improving the overall overlay accuracy. The alignment method, involving multiple coordinate acquisitions and fitting, enhances alignment accuracy and repeatability, reducing alignment deviations. The application of step-through exposure ensures the transfer accuracy of fine patterns, improving the forming quality of microstructures. Temperature balancing treatment before alignment eliminates alignment deviations caused by thermal drift, further ensuring the stability of overlay accuracy.

[0029] The above method, through precision control of the overlay alignment process, ensures that the center position deviation between the motion center of the movable optical modulation structure of the MEMS modulation disk and the center of the photosensitive element array of the photovoltaic chip's photoelectric conversion functional structure is stably controlled within the range of 0.4μm-0.8μm, preferably 0.5μm-0.7μm; the parallelism angle deviation is ≤0.01°, preferably 0.005°-0.008°. Compared with the typical angle deviation of 0.1°-0.5° and center alignment error of 2μm-10μm caused by adhesive bonding assembly of the modulation disk and the photovoltaic chip in the separate fabrication process, the alignment accuracy is significantly improved. The infrared reflectivity of the 2μm-4μm thick metal grating is ≥99.0%. Measured data shows that within the thickness range of 2.5μm-3.5μm, the reflectivity of the gold film for the 3μm-5μm infrared band can reach 99.2%-99.5%. The modulation depth of the infrared incident light is ≥98%, with a measured modulation depth of 98.5%-99.2%. The additional optical loss introduced by the modulation structure is ≤1.5%, preferably 1.0%-1.2%. The photoelectric signal distortion rate is ≤1.0%, preferably 0.5%-0.8%. The performance indicators are based on the statistical test results of 100 samples, with a standard deviation of ≤±0.3%.

[0030] This scheme significantly optimizes the alignment of the modulation structure and the photoelectric conversion structure through high-precision overlay alignment control, far surpassing the alignment level of assembly after separate fabrication, thus avoiding angular deviations and center misalignment caused by assembly. The high infrared reflectivity metal grid design enhances the depth of optical modulation, reduces additional losses during light transmission, lowers photoelectric signal distortion, and optimizes the device's photoelectric performance. Good performance consistency across multiple batches of samples reduces device screening costs and improves mass production yield.

[0031] The above method, in its second stepwise photolithography process cycle, performs independent photolithography processes for the chopper grid, cantilever beam, electrostatic comb drive electrode, electrode leads, and pads in the modulation disk functional area. The core structure patterning employs a standard LIGA-like process: thick resist photolithography – electroforming thickening – stress-relief annealing – resist removal – seed layer etching. Each core photolithography process sequentially includes resist coating, pre-baking, alignment exposure, development, and hard film baking. The resist coating uses positive thick resist and is completed through a stepwise resist coating process. The first step has a rotation speed of 600-750 rpm and a time of 6-9 seconds. The second step involves rotating the photoresist at 2500-3500 rpm for 40-55 seconds to form a photoresist layer with a thickness of 7-9 μm on the substrate surface, preferably 7.5-8.5 μm. The uniformity deviation of the photoresist layer thickness is ≤1.0%, preferably 0.6%-0.8%. The pre-baking temperature is 95-105℃ for 120-150 seconds. Alignment exposure employs a zoned exposure process, performing independent exposures on the chopper grid pattern area and the drive structure pattern area, matching corresponding exposure doses. The exposure dose for the chopper grid pattern area is 180 mJ / cm². 2 -220mJ / cm 2 The preferred value is 190 mJ / cm. 2 -210mJ / cm 2 The exposure dose for the driving structure pattern area is 140 mJ / cm². 2 -180mJ / cm 2 The preferred value is 150 mJ / cm. 2 -170mJ / cm 2To ensure complete pattern transfer in both regions, a 2.38% tetramethylammonium hydroxide developer was used for development, with a development time of 80-110 seconds. The post-hardening baking temperature was 115℃-125℃, and the time was 210-270 seconds. After photolithography patterning, the formed thick photoresist was used as an electroforming mold. A cyanide-free electroplating process was employed to thicken the optical reflection and conductive seed layers, with the core structure region thickened to 2μm-4μm, preferably 2.5μm-3.5μm. The pad areas were simultaneously thickened to 4μm-5μm. The total thickness of all areas was kept below 75% of the corresponding photoresist thickness to avoid overfilling. The process of electroplating can lead to image distortion. Simultaneously, the structural layers of the chopper grid, cantilever beam, electrostatic comb electrode, electrode leads, and pads are prepared. After electroplating, low-temperature stress-relief annealing is performed in a nitrogen atmosphere at 160℃-180℃ for 90-150 minutes, divided into two stages: the first stage is held at 160℃ for 60 minutes, and the second stage is held at 180℃ for 30-90 minutes to more effectively eliminate internal stress. This eliminates the internal stress of the electroplated metal layer for subsequent electrical connection with external drive circuits. The electroplating solution uses cyanide-free gold or aluminum plating solution with 0.1%-0.5% stress modifier added to further reduce the internal stress of the plating layer.

[0032] This solution employs zoned exposure and corresponding dosages for graphics in different functional areas, ensuring complete and precise transfer of graphics of varying fineness, thus improving the quality of graphic forming. The step-by-step uniform coating process guarantees the uniformity of the coating thickness, providing a precise mold for subsequent structural thickening. The electroplating process, while achieving structural thickening, reduces environmental hazards, and precise control of the coating thickness prevents graphic distortion. The low-temperature annealing process and the use of stress-regulating agents effectively eliminate internal stress in the metal coating, improving the dimensional stability and structural reliability of the microstructure, and preventing deformation or breakage of movable structures during movement.

[0033] The above method, in which, after completing the electroplating thickening and stress-relief annealing, sequentially performs the following steps: resist removal, seed layer etching, release window preparation, and sacrificial layer release. Specifically:

[0034] S1. The photoresist electroforming mold is removed by acetone immersion combined with low-power ultrasonic cleaning. The cleaning time is 15min-25min, the ultrasonic power is controlled at 50W-100W, and the frequency is 40kHz to avoid damage to the fine structure by high-power ultrasound; the exposed seed layer area between the electroplated structures is exposed.

[0035] S2. The exposed seed layer and adhesion layer are etched using inductively coupled plasma etching (ICP) technology. Basic parameters are: ICP power 400W-700W, RF bias power 80W-150W. For gold film etching, a mixture of chlorine and argon is used, with a chlorine flow rate of 15-25 sccm and an argon flow rate of 30-45 sccm, and an operating pressure of 1.5Pa-2.5Pa. For aluminum film etching, a mixture of chlorine and boron trichloride is used, with a chlorine flow rate of 30-45 sccm and a boron trichloride flow rate of 15 sccm. -25 sccm, working pressure 0.8 Pa-1.5 Pa; etching depth to expose the underlying sacrificial layer, corrosion selectivity ratio of electroplated metal structure layer to seed layer material ≥10:1, preferably 12:1-15:1; corrosion selectivity ratio of seed layer to underlying silicon nitride passivation protective layer ≥25:1, preferably 30:1-40:1; after etching, the seed layer connection between fixed comb teeth and movable comb teeth is completely severed to achieve final electrical isolation between the two; during the etching process, a negative bias voltage of 100V-200V is applied to the photovoltaic functional area to prevent plasma damage to the PN junction;

[0036] S3. After completing the patterning of all MEMS structures, the sacrificial layer release windows are prepared by homogenization, photolithography, and dry etching processes. The photoresist forms a continuous enclosure structure at the edge of the release window, with an enclosure width ≥15μm, preferably 18μm-22μm, to reduce lateral corrosion during the release process. The release windows are evenly distributed in the gaps, edges, and corners of the movable structure, with a maximum spacing between adjacent windows ≤400μm, preferably 300μm-350μm. The total area of ​​the windows is ≥25% of the total area of ​​the sacrificial layer, preferably 28%-32%. The enclosure structure is a temporary structure and is removed after release.

[0037] The S4. MEMS movable structure's cantilever beam adopts a double-end fixed-support folded beam structure. The beam width is 8μm-15μm, preferably 10μm-12μm; the beam length is 150μm-400μm, preferably 200μm-300μm; there are 2-4 groups, symmetrically distributed on both sides of the chopper grid structure. The two ends of the cantilever beam are respectively connected to the chopper grid structure and fixed anchor points on the substrate. The electrostatic comb drive electrode is divided into fixed comb teeth and movable comb teeth. The tooth width of the fixed comb teeth and movable comb teeth is 5μm-8μm, preferably 6μm-7μm; the tooth spacing is 5μm-8μm, preferably 6μm-7μm; the overlap length is 30μm-45μm. The diameter of the comb teeth is preferably 35μm-40μm; the number of comb teeth is 80-150 pairs, preferably 100-120 pairs; they are symmetrically distributed on both sides of the movable structure; the fixed comb teeth are electrically connected to the drive pads on the substrate through electrode leads; the movable comb teeth are integrally connected to the chopper grid structure and electrically connected to the grounding anchor point through a cantilever beam; the linear reciprocating resonant motion of the chopper grid is achieved by applying an AC-DC superimposed drive voltage of 8V-25V, which does not exceed the breakdown voltage and pull-in voltage of the comb tooth electrodes; experimental verification shows that 15V-20V is the optimal drive voltage range; the DC bias voltage is used to set the static operating point; the frequency of the alternating drive voltage is consistent with the inherent resonant frequency of the structure.

[0038] S5. After completing the preparation of the release window, the sacrificial layer is removed using a wet release process. The sacrificial layer is a low-temperature curing polyimide. The release solution is an N-methylpyrrolidone (NMP) solution with 5%-10% ethanolamine added as a corrosion inhibitor to reduce potential erosion of the silicon nitride layer. The release temperature is 45℃-55℃, preferably 50℃±2℃. The release time is 45min-90min, dynamically adjusted according to the thickness of the sacrificial layer, with 15-20 minutes of release time corresponding to each micrometer of thickness. During the release process, light... The silicon nitride passivation protective layer on the surface of the functional region serves as a permanent corrosion barrier layer. Experiments have confirmed that the corrosion rate of silicon nitride in NMP solution with added corrosion inhibitor is ≤0.1nm / min, which is negligible. After release, isopropanol gradient displacement combined with critical point drying process is used to avoid capillary adhesion of the movable MEMS structure and form a freely resonant MEMS modulation disk structure. Before release, the device is pretreated with electron beam irradiation at a dose of 3000Gy to improve the dissolution rate and uniformity of polyimide.

[0039] This scheme employs a low-power ultrasonic desizing process to avoid damage to the delicate microstructure and ensure structural integrity. A high-selectivity etching process precisely removes the exposed seed layer, achieving electrical isolation between the driving electrodes while avoiding damage to the underlying passivation layer and the fabricated structure. Optimized release window design improves the uniformity and efficiency of sacrificial layer release and reduces lateral corrosion during the release process. The folded beam structure design enhances the linearity and stability of the movable structure's movement, while the symmetrically distributed driving structure ensures uniform driving force, improving driving efficiency and motion controllability. Wet release combined with subsequent drying processes prevents adhesion of the movable structure, ensuring its free movement. The pretreatment process improves the uniformity of sacrificial layer dissolution, further guaranteeing the stability and yield of the release process.

[0040] The above method, after completing all photolithography cycles, semiconductor processing, and MEMS structure release processes, sequentially performs photovoltaic characteristic testing, dynamic photoelectric performance testing, and environmental reliability testing on the integrated device. All tests are performed in a standard environment of room temperature 25℃±3℃ and relative humidity 40%-60%. Before testing, the device undergoes a 24-hour aging and stabilization treatment at a temperature of 40℃±2℃ and relative humidity of 50%±5%. The voltage scan range for photovoltaic characteristic testing is -0.6V to 0.6V, and the current acquisition accuracy is ≤2nA. A four-probe method is used to reduce the influence of contact resistance. Devices whose IV curves deviate from those of independently fabricated photovoltaic chips of the same structure by ≤±5% are selected. Dynamic photoelectric performance testing uses a blackbody radiation source as the infrared light source, with a temperature setting of 500K-800K, covering the 1μm-5μm band; the light source power is 5μW-80μW, the driving voltage is ±10% of the device's designed rated voltage, the frequency scanning range of the MEMS electrostatic drive structure covers ±25% of the device's designed resonant frequency, and the scanning step size is 1% of the resonant frequency; the signal acquisition bandwidth is 20Hz-80kHz, the system background noise for noise testing is ≤0.2mV, and lock-in amplifier technology is used to improve the signal-to-noise ratio; qualified devices are selected with signal output not lower than 95% of the same specification devices assembled by separate bonding and no higher than 105% of the same specification devices assembled by separate bonding.

[0041] This approach employs aging and stabilization treatment before testing to ensure stable device performance and guarantee the accuracy of test results. High-precision testing methods are used for photovoltaic characteristic testing to reduce testing errors and select devices with stable photoelectric performance. Dynamic photoelectric performance testing simulates the actual operating conditions of the devices, comprehensively verifying their modulation and photoelectric response performance, ensuring that the selected devices meet practical application requirements. High-precision testing equipment and signal amplification technology improve the signal-to-noise ratio of the tests, guaranteeing the reliability of the test results.

[0042] The above methods, in the dynamic photoelectric performance test, show that the average alternating signal output of qualified devices is 10%-22% higher than that of devices of the same specification assembled by separate bonding, with an average improvement of 16.8% based on 50 sets of comparative experimental data; the average noise output is 7%-13% lower than that of devices of the same specification assembled by separate bonding, with an average reduction of 10.2% based on 50 sets of comparative experimental data; the environmental reliability test includes high and low temperature cycling test and vibration and shock test. The temperature range of the high and low temperature cycling test is -45℃ to 90℃, simulating the actual use environment; the number of cycles is 60-90 times, the temperature change rate is 3℃ / min-4℃ / min, and the holding time at each temperature extreme point is ≥45min; the random vibration frequency range of the vibration and shock test is 20Hz-1800Hz, covering the main environmental conditions. Vibration frequency band; vibration acceleration of 12g-18g, sweep rate of 1.2oct / min, impact acceleration of 600g-900g, and number of impacts of 4-5 times; after completing environmental reliability testing, qualified devices exhibit no breakage or detachment of the MEMS optical modulation structure, and film adhesion ≥4B, tested according to ASTM D3359 standard; photoelectric performance degradation ≤±3%, inherent resonant frequency deviation ≤±3%, and actual measurement data shows that 90% of qualified devices exhibit performance degradation ≤±2% and frequency deviation ≤±2%; completely solving the reliability problems of cracking, debonding, and assembly misalignment of the adhesive interface under environmental stress in the split process; an online monitoring system is introduced to monitor device performance parameters in real time during testing, and automatically terminates the test when performance degradation exceeds a preset threshold, protecting the test equipment and samples.

[0043] This solution utilizes an integrated structural design to enhance the device's photoelectric signal output, reduce noise, and optimize the signal-to-noise ratio. Rigorous environmental reliability testing comprehensively verifies the device's structural and performance stability under complex operating conditions. The integrated structure avoids cracking, debonding, and misalignment at the bonding interface under environmental stress, significantly improving the device's environmental adaptability and long-term reliability. The introduction of an online monitoring system allows for real-time monitoring of device performance, preventing equipment and sample damage due to device failure during testing and enhancing the safety of the testing process.

[0044] The aforementioned method completely eliminates the entire process of independently preparing the modulation disk and subsequent bonding and assembly steps. Within the production cycle of a single batch of photovoltaic chips, the preparation and integration of the corresponding batch of MEMS modulation disks are completed simultaneously. The total preparation time for 25 standard 6-inch wafers per batch and 100 integrated devices in four consecutive production batches is reduced by 50%-65% compared to the total process of separately preparing the modulation disk, separately preparing the photovoltaic chip, and high-precision alignment and bonding assembly under the same production capacity. Based on actual production data, the average reduction is 58.3%. It eliminates the 24-26 working days cycle of independently preparing the modulation disk, the subsequent high-precision alignment and bonding assembly steps, and the device screening and matching steps after separate preparation. By adopting an automated production line and reducing manual intervention, the production cycle of a single batch is shortened from the traditional 45-55 days to 18-25 days.

[0045] This solution eliminates the need for a separate fabrication process for the modulation structure, as well as subsequent bonding, assembly, screening, and pairing steps, significantly shortening the overall device production cycle and improving production efficiency. Simultaneous fabrication of two functional structures within the same batch achieves capacity matching, reduces waiting time between different processes, adapts to automated production lines, minimizes manual intervention, and further enhances production stability and efficiency.

[0046] The aforementioned method eliminates the need for substrate materials, coating consumables, photolithography consumables, and assembly adhesives required for the independent fabrication of the modulation disk. It also reduces equipment time and labor costs associated with separate coating, photolithography, cleaning, and assembly processes, significantly lowering device yield losses due to separate assembly. This results in a 40%-55% reduction in the overall fabrication cost of the infrared detector's core components, with an average reduction of 47.6% based on data analysis from 1000 mass production units. Furthermore, it eliminates human error associated with adhesive bonding assembly, ensuring that the consistency deviation of modulation and photoelectric performance in a single batch of devices is ≤±4%, preferably ±3%. Compared to separate bonding processes, this reduces the consistency deviation of devices in the same batch by more than 65%. Actual measurement data shows that the standard deviation for integrated devices is 2.1%, while for separate devices it is 6.8%. Through statistical process control (SPC), key process parameters are monitored in real time to ensure batch-to-batch consistency, with a process capability index Cpk ≥ 1.33.

[0047] This solution eliminates the need for raw materials, consumables, and equipment time required for independent fabrication of the modulation structure, reducing labor costs and minimizing yield losses associated with separate assembly, thus significantly lowering the overall device fabrication cost. It also eliminates operational errors caused by manual assembly, greatly improving the performance consistency of devices within the same batch and reducing device selection costs. The introduction of process control methods, enabling real-time monitoring of key process parameters, ensures batch-to-batch performance stability and enhances the controllability of mass production.

[0048] The present invention has the following beneficial effects:

[0049] By integrating and fabricating the photovoltaic chip and modulation disk structure in stages on the same substrate, the entire process of independently fabricating the modulation disk and subsequent bonding and assembly procedures are completely eliminated, which greatly shortens the entire production cycle of the device, reduces the consumption of raw materials and consumables and the occupation of equipment time, and lowers the overall manufacturing cost of the device.

[0050] The entire photolithography process uses the same set of pre-formed substrate positioning marks as the sole alignment reference. Combined with the linked positioning pattern group on the mask, it eliminates the cumulative deviation caused by multiple reference alignments, greatly improves the alignment accuracy and parallelism between the modulation disk optical structure and the photovoltaic chip photosensitive structure, ensures the overlap between the light-transmitting area and the photosensitive area, and improves the effectiveness and uniformity of light modulation.

[0051] Employing a low-temperature compatible MEMS fabrication process with temperature control throughout, this avoids thermal damage to the infrared photosensitive material and PN junction structure of the photovoltaic chip caused by high-temperature environments, ensuring the stability of the photovoltaic chip's photoelectric conversion performance. Combined with the design of a nitrogen protective atmosphere and an interface coupling agent transition layer, this effectively enhances the interfacial bonding force between film layers, reduces the adverse effects of residual process stress on the MEMS microstructure, and achieves stable compatibility between semiconductor and MEMS processes.

[0052] The modulation disk structure is directly stacked above the infrared incident light side of the photovoltaic chip. The infrared light is modulated and directly incident on the photosensitive surface of the photovoltaic chip, eliminating the additional light transmission loss caused by the adhesive layer in the separate bonding process, improving the light modulation depth, reducing the distortion of photoelectric signals, and optimizing the signal-to-noise ratio of the device.

[0053] The integrated structural design eliminates the adhesive interface, fundamentally solving problems such as cracking, debonding, and assembly misalignment that occur at the adhesive interface under environmental stress in the split process. This significantly improves the environmental adaptability and long-term reliability of the device under complex working conditions such as high and low temperature cycling, vibration and shock.

[0054] The entire process employs standardized photolithography, adaptable to automated production lines, reducing operational errors caused by manual intervention, significantly improving the performance consistency of devices in the same batch, minimizing yield losses due to separate assembly, and enhancing the controllability and stability of the mass production process. The integrated electrostatic comb drive structure and optical modulation structure ensure good synchronization between drive and optical modulation actions, with a stable and controllable modulation frequency, guaranteeing stable device operation and adaptability to infrared detection requirements across different frequency bands. Attached Figure Description

[0055] Figure 1 This is a schematic diagram illustrating the integration of the modulation disk and chip fabrication into one unit;

[0056] Figure 2 A graph showing the relationship between optical modulation depth and chopper grating period;

[0057] Figure 3 This is a graph showing the relationship between photoelectric signal distortion rate and driving voltage.

[0058] Figure 4 This is a graph showing the performance degradation characteristics under high and low temperature cycling.

[0059] Figure 5 This is a graph showing the relationship between production cycle and consistency deviation. Detailed Implementation

[0060] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0061] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual images. They should not be construed as limiting the scope of this application. To better illustrate the embodiments of the present invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0062] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present application. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0063] In the description of this invention, unless otherwise explicitly specified and limited, the term "connection" or similar designation indicating a connection between components should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0064] Reference Figures 1-5 ,in Figure 1 It demonstrates a schematic process of integrating modulation disk and chip manufacturing into one unit; Figure 2It shows a peak value of 98.5% at 25μm period, a peak value of 99.0% at 35μm period, and a stable value of 98.2% at 45μm period; Figure 3 It demonstrates a minimum distortion of 0.6% at 16V, and 0.8% and 0.9% at 8V and 25V, respectively. Figure 4 The data showed a 1.5% decay after 75 cycles and a 1.8% / 1.9% decay after 90 cycles. Figure 5 The results show a 2.1% bias for a 20-day cycle, and 3.2% and 3.8% biases for 22-day and 24-day cycles, respectively.

[0065] I. Implementation Examples

[0066] Example 1

[0067] Process parameters:

[0068] 1. Mask fabrication precision: The relative deviation between the semiconductor functional pattern and the chip positioning pattern is 0.5μm; the relative deviation between the modulation disk optical pattern and the modulation disk positioning pattern is 0.5μm; the width of the substrate preform cross positioning mark is 3μm, and the edge roughness is 0.1μm.

[0069] 2. Chopper grating: grating period 25μm, duty cycle 50%, grating line width 12.5μm, metal structure layer thickness 2μm, gold film surface roughness Ra=8nm;

[0070] 3. Second group of low temperature process: The highest temperature of the whole process is 150℃, nitrogen protection throughout the process, and the thickness of the organosilane coupling agent transition layer is 5nm;

[0071] 4. Sacrificial layer: Low-temperature polyimide, 3μm thick, curing temperature 150℃, curing time 90min;

[0072] 5. Photolithography process: overlay accuracy 0.3μm, single exposure field deviation 0.1μm, alignment angle deviation 0.005°, and the same substrate positioning mark is used as the alignment reference throughout the entire process;

[0073] 6. Electroplating process: The structural layer is 2μm thick and the pad area is 4μm thick. It uses a cyanide-free gold plating system and is stress-relief annealed in a nitrogen atmosphere at 160℃.

[0074] 7. Drive structure: electrostatic comb teeth width 5μm, tooth spacing 5μm, number of comb teeth 80 pairs, rated drive voltage 8V, design resonant frequency 100Hz;

[0075] 8. Alignment and matching: The center deviation between the modulation disk and the photosensitive element array is 0.5μm, the parallelism deviation is 0.005°, and the overlap between the static light-transmitting area and the photosensitive area is 92%;

[0076] Preparation process:

[0077] 1. Substrate pretreatment and positioning mark preforming: After completing the megahertz-level ultrasonic cleaning of the substrate, cross-shaped substrate positioning marks are preformed on the substrate surface through electron beam lithography and dry etching processes. The mark line width is 3μm and the edge roughness is ≤0.1μm, which serves as the sole alignment reference for all lithography processes in the entire process.

[0078] 2. Fabrication of photovoltaic chip functional structure, first step-by-step photolithography process cycle:

[0079] S1. Extension of buffer layer and functional layer: within ≤5×10 -4 Under a vacuum environment of Pa, a 50nm thick CdTe lattice-matching buffer layer is grown on the surface of the photovoltaic functional area of ​​the substrate by molecular beam epitaxy, followed by the sequential growth of a 300nm thick mercury cadmium telluride infrared photosensitive semiconductor functional layer and a 50nm thick silicon nitride passivation transition layer.

[0080] S2. PN junction fabrication: The PN junction photoelectric conversion structure was fabricated by photolithography, ion implantation and annealing. The N-type dopant was In and the P-type dopant was As, with a doping depth of 100 nm. The annealing temperature was 200℃ and the annealing time was 90 min. After annealing, the temperature was gradually reduced to room temperature at a rate of 2℃ / min.

[0081] S3. Contact hole fabrication: 5μm contact holes are fabricated at corresponding positions in the N-type and P-type regions of the PN junction using photolithography and dry etching processes, with the etching depth extending to expose the doped semiconductor layer;

[0082] S4. Electrode and pad fabrication: A chromium-gold composite layer electrode lead and pad structure with a total thickness of 300nm was fabricated by photolithography, electron beam evaporation metal deposition and lift-off processes to realize the photoelectric signal extraction of PN junction;

[0083] S5. Preparation of passivation protective layer: A 150nm thick silicon nitride passivation protective layer is deposited on the entire surface using a 300℃ plasma-enhanced chemical vapor deposition process; after completion, a 5nm thick organosilane coupling agent treatment layer is formed on the surface;

[0084] S6. Pad Windowing: Through photolithography and dry etching processes, a passivation protective layer is etched at the corresponding position of the electrode pad to form a window. The deviation between the window size and the pad size is ≤5μm, thus completing the fabrication of all high-temperature processes and functional structures of the photovoltaic chip.

[0085] 3. MEMS modulation disk structure fabrication: A second set of low-temperature compatible step-by-step photolithography processes is used, with a maximum temperature of 150℃ throughout the entire process. All steps are performed under nitrogen protection.

[0086] S1. Surface activation and transition layer preparation: The silicon nitride passivation protective layer on the substrate surface was activated by 100W oxygen plasma for 120s. After activation, a 5nm thick 3-aminopropyltriethoxysilane coupling agent was spin-coated and cured at 110℃ for 60s to form a transition layer.

[0087] S2. Sacrificial layer deposition and patterning: A 3μm thick low-temperature curable polyimide sacrificial layer is spin-coated in the functional area of ​​the substrate modulation disk, i.e., the area directly above the photovoltaic chip photosensitive element array, and cured at 150℃ for 90min; anchor point windows for cantilever beam fixing anchor points, fixed comb electrode anchor points, electrode lead anchor points, and movable structure grounding anchor points are prepared in the sacrificial layer by photolithography and dry etching processes, and the etching depth is up to expose the underlying passivation protection layer;

[0088] S3. Deposition of composite functional film system: On the surface of the sacrificial layer and inside the anchor point window, an 8nm thick chromium adhesion layer and a 100nm thick gold optical reflection and conductive seed layer are vacuum deposited in sequence to form a composite functional film system compatible with photolithography process.

[0089] S4. Thick-film photolithography patterning: Using positive thick-film photoresist, the photoresist layer is prepared through a step-by-step homogenization process. The first step involves a rotation speed of 600 rpm for 6 seconds, and the second step involves a rotation speed of 2500 rpm for 40 seconds, forming a photoresist layer with a thickness of 7 μm. After pre-baking at 95°C for 150 seconds and alignment exposure, the exposure dose for the chopper grid pattern area is 180 mJ / cm². 2 Exposure dose to the driving structure pattern area is 140 mJ / cm 2 The electroforming mold was prepared by developing the film with 2.38% tetramethylammonium hydroxide developer for 80 seconds, hardening it at 115℃ and baking it for 270 seconds. All photolithography alignment processes used the pre-formed substrate positioning marks as the only alignment reference, and the alignment and bonding were completed using a front alignment photolithography process with an overlay accuracy of 0.3μm.

[0090] S5. Electroplating Thickening and Stress-Relief Annealing: Using the formed thick photoresist as an electroforming mold, the seed layer is thickened with a cyanide-free gold electroplating solution, the core structure area is thickened to 2μm, and the pad area is simultaneously thickened to 4μm; after electroplating, low-temperature stress-relief annealing is performed for 90min in a nitrogen atmosphere at 160℃.

[0091] S6. Resin Removal and Seed Layer Etching: The photoresist electroforming mold is removed by immersion in acetone combined with 50W, 40kHz low-power ultrasonic cleaning for 25 minutes, exposing the bare seed layer area; the exposed seed layer and adhesion layer are etched by inductively coupled plasma etching process, with the etching depth reaching the exposed sacrificial layer below. During the etching process, a 100V negative bias voltage is applied to the photovoltaic functional area for protection, completely severing the seed layer connection between the fixed comb teeth and the movable comb teeth, and achieving electrical isolation between the two.

[0092] S7. Release window preparation: The sacrificial layer release windows are prepared by homogenization, photolithography, and dry etching processes. The photoresist forms a continuous enclosure structure with a width of 15μm at the edge of the release window. The release windows are evenly distributed in the gaps, edges, and four corners of the movable structure. The maximum spacing between adjacent windows is 400μm, and the total area of ​​the windows is ≥25% of the total area of ​​the sacrificial layer.

[0093] S8. Sacrificial layer release and drying: The sacrificial layer was released by wet method at 45℃ for 90 min using N-methylpyrrolidone release solution with 5% ethanolamine corrosion inhibitor. After release, the sacrificial layer was treated by isopropanol gradient displacement combined with critical point drying process to avoid capillary adhesion of the MEMS movable structure and form a MEMS modulation disk structure that can resonate freely.

[0094] 4. Device aging and testing screening: Devices that have completed all fabrication processes are aged and stabilized for 24 hours at 40℃ and 50%±5% relative humidity. Then, photovoltaic characteristic tests, dynamic photoelectric performance tests and environmental reliability tests are performed in sequence to screen out qualified devices that meet the performance requirements.

[0095] Experimental test data table 1:

[0096]

[0097] Technical effects:

[0098] This embodiment utilizes the lower limit of process parameters, achieving integrated modulation disk and photovoltaic chip while meeting process feasibility requirements, completely avoiding the bonding and assembly process. The low-temperature process effectively avoids performance damage to the pre-fabricated photovoltaic chip, ensuring the stability of the photoelectric conversion structure; high-precision alignment control achieves accurate matching between the modulation structure and the photosensitive element, ensuring light modulation efficiency; simultaneously, it significantly shortens the production cycle, reduces manufacturing costs, and the device's environmental reliability and performance consistency meet mass production requirements.

[0099] Example 2

[0100] Process parameters:

[0101] 1. Mask fabrication precision: The relative deviation between the semiconductor functional pattern and the chip positioning pattern is 0.65μm; the relative deviation between the modulation disk optical pattern and the modulation disk positioning pattern is 0.65μm; the substrate pre-formed cross positioning mark line width is 4μm, and the edge roughness is 0.1μm;

[0102] 2. Chopper grating: grating period 35μm, duty cycle 50%, grating line width 17.5μm, metal structure layer thickness 3μm, gold film surface roughness Ra=7nm;

[0103] 3. Second group of low temperature process: The highest temperature of the whole process is 165℃, nitrogen protection throughout the process, and the thickness of the organosilane coupling agent transition layer is 7.5nm;

[0104] 4. Sacrificial layer: Low-temperature polyimide, 5μm thick, curing temperature 165℃, curing time 90min;

[0105] 5. Photolithography process: overlay accuracy 0.35μm, single exposure field deviation 0.12μm, alignment angle deviation 0.0065°, and the same substrate positioning mark is used as the alignment reference throughout the entire process;

[0106] 6. Electroplating process: The structural layer is 3μm thick and the pad area is 4.5μm thick. It uses a cyanide-free gold plating system and undergoes staged stress-relief annealing in a nitrogen atmosphere at 170℃.

[0107] 7. Drive structure: electrostatic comb teeth width 6.5μm, tooth spacing 6.5μm, number of comb teeth 115 pairs, rated drive voltage 16V, design resonant frequency 2kHz;

[0108] 8. Alignment and matching: The center deviation between the modulation disk and the photosensitive element array is 0.65μm, the parallelism deviation is 0.0065°, and the overlap between the static light-transmitting area and the photosensitive area is 93.5%;

[0109] Preparation process:

[0110] 1. Substrate pretreatment and positioning mark preforming: After completing the megahertz-level ultrasonic cleaning of the substrate, cross-shaped substrate positioning marks are preformed on the substrate surface through electron beam lithography and dry etching processes. The mark line width is 4μm and the edge roughness is ≤0.1μm, which serves as the sole alignment reference for all lithography processes in the entire process.

[0111] 2. Fabrication of photovoltaic chip functional structure, first step-by-step photolithography process cycle:

[0112] S1. Extension of buffer layer and functional layer: within ≤5×10 -4 In a vacuum environment of Pa, a 125nm thick CdTe lattice-matching buffer layer is grown on the surface of the photovoltaic functional area of ​​the substrate by molecular beam epitaxy, followed by the sequential growth of a 550nm thick mercury cadmium telluride infrared photosensitive semiconductor functional layer and a 75nm thick silicon nitride passivation transition layer.

[0113] S2. PN junction fabrication: The PN junction photoelectric conversion structure was fabricated by photolithography, ion implantation and annealing. The N-type dopant was In and the P-type dopant was As, with a doping depth of 250 nm. The annealing temperature was 275℃ and the annealing time was 67 min. After annealing, the temperature was gradually reduced to room temperature at a rate of 1.5℃ / min.

[0114] S3. Contact hole preparation: A 10μm contact hole is prepared at the corresponding position of the N-type region and P-type region of the PN junction by photolithography and dry etching process, and the etching depth is up to expose the doped semiconductor layer.

[0115] S4. Electrode and pad fabrication: A chromium-gold composite layer electrode lead and pad structure with a total thickness of 550nm was fabricated by photolithography, electron beam evaporation metal deposition and lift-off processes to realize the photoelectric signal extraction of PN junction;

[0116] S5. Preparation of passivation protective layer: A 200nm thick silicon nitride passivation protective layer is deposited on the entire surface using a 300℃ plasma-enhanced chemical vapor deposition process; after completion, a 7.5nm thick organosilane coupling agent treatment layer is formed on the surface;

[0117] S6. Pad Windowing: Through photolithography and dry etching processes, a passivation protective layer is etched at the corresponding position of the electrode pad to form a window. The deviation between the window size and the pad size is ≤5μm, thus completing the fabrication of all high-temperature processes and functional structures of the photovoltaic chip.

[0118] 3. MEMS modulation disk structure fabrication: The second set of low-temperature compatible step-by-step photolithography processes is repeated, with a maximum temperature of 165℃ throughout the entire process. All steps are performed under nitrogen protection.

[0119] S1. Surface activation and transition layer preparation: The silicon nitride passivation protective layer on the substrate surface was activated by 200W oxygen plasma for 75s. After activation, a 7.5nm thick 3-aminopropyltriethoxysilane coupling agent was spin-coated and cured at 110℃ for 60s to form a transition layer.

[0120] S2. Sacrificial layer deposition and patterning: A 5μm thick low-temperature curing polyimide sacrificial layer is spin-coated in the functional area of ​​the substrate modulation disk, i.e., the area directly above the photovoltaic chip photosensitive element array, and cured at 165℃ for 90min; anchor point windows for cantilever beam fixing anchor points, fixed comb electrode anchor points, electrode lead anchor points, and movable structure grounding anchor points are prepared in the sacrificial layer by photolithography and dry etching processes, and the etching depth is up to expose the underlying passivation protection layer;

[0121] S3. Deposition of composite functional film system: A 12nm thick chromium adhesion layer and a 140nm thick gold optical reflection and conductive seed layer are sequentially vacuum deposited on the surface of the sacrificial layer and inside the anchor point window to form a composite functional film system compatible with photolithography process.

[0122] S4. Thick-film photolithography patterning: Positive thick-film photoresist was used, and the photoresist layer was prepared through a step-by-step homogenization process. The first step was at a rotation speed of 700 rpm for 7.5 s, and the second step was at a rotation speed of 3000 rpm for 47 s, forming a photoresist layer with a thickness of 8 μm. After pre-baking at 100℃ for 135 s and alignment exposure, the exposure dose of the chopper grid pattern area was 200 mJ / cm. 2Exposure dose to the driving structure pattern area is 160 mJ / cm 2 The electroforming mold was prepared by developing the film with 2.38% tetramethylammonium hydroxide developer for 95 seconds, hardening it at 120°C, and then baking it for 240 seconds. All photolithography alignment processes used the pre-formed substrate positioning marks as the only alignment reference, and the alignment and bonding were completed using a front alignment photolithography process with an overlay accuracy of 0.35μm.

[0123] S5. Electroplating Thickening and Stress-Relief Annealing: Using the formed thick photoresist as the electroforming mold, a cyanide-free gold electroplating solution with 0.3% stress modifier was used to thicken the seed layer, with the core structure area thickened to 3μm and the pad area thickened to 4.5μm simultaneously; after electroplating, a staged low-temperature stress-relief annealing was performed in a nitrogen atmosphere, with the first stage held at 160℃ for 60 minutes and the second stage held at 170℃ for 60 minutes;

[0124] S6. Resin Removal and Seed Layer Etching: The photoresist electroforming mold is removed by immersion in acetone combined with 75W, 40kHz low-power ultrasonic cleaning for 20 minutes, exposing the bare seed layer area; the exposed seed layer and adhesion layer are etched by inductively coupled plasma etching process, with the etching depth reaching the exposed sacrificial layer. During the etching process, a 150V negative bias voltage is applied to the photovoltaic functional area for protection, completely severing the seed layer connection between the fixed comb teeth and the movable comb teeth, and achieving electrical isolation between the two.

[0125] S7. Release window preparation: The sacrificial layer release windows are prepared by homogenization, photolithography, and dry etching processes. The photoresist forms a continuous enclosure structure with a width of 20 μm at the edge of the release window. The release windows are evenly distributed in the gaps, edges, and four corners of the movable structure. The maximum spacing between adjacent windows is 350 μm. The total area of ​​the windows accounts for 30% of the total area of ​​the sacrificial layer.

[0126] S8. Sacrificial layer release and drying: Before release, the device is pretreated with electron beam irradiation at a dose of 3000 Gy. Then, the sacrificial layer is released by wet method at 50°C for 75 min using N-methylpyrrolidone release solution with 7.5% ethanolamine corrosion inhibitor. After release, isopropanol gradient displacement combined with critical point drying process is used to avoid capillary adhesion of the MEMS movable structure and form a freely resonant MEMS modulation disk structure.

[0127] 4. Device aging and testing screening: Devices that have completed all fabrication processes are aged and stabilized for 24 hours at 40℃ and 50%±5% relative humidity. Then, photovoltaic characteristic tests, dynamic photoelectric performance tests and environmental reliability tests are performed in sequence to screen out qualified devices that meet the performance requirements.

[0128] Experimental test data table 2:

[0129]

[0130] Technical effects:

[0131] This embodiment uses intermediate process parameters, achieving optimal overall performance. The low-temperature process and interface treatment balance film adhesion and photovoltaic structure stability, ensuring no degradation in photoelectric conversion performance. High-precision overlay and a unified alignment reference achieve a high degree of overlap between the modulation structure and the photosensitive element, resulting in optimal light modulation depth and signal quality. Simultaneously, the production cycle is shorter, and device yield, consistency, and environmental reliability are significantly better than conventional processes, fully meeting the high-performance mass production requirements of infrared detectors.

[0132] Example 3

[0133] Process parameters:

[0134] 1. Mask fabrication precision: The relative deviation between the semiconductor functional pattern and the chip positioning pattern is 0.8μm, and the relative deviation between the modulation disk optical pattern and the modulation disk positioning pattern is 1.0μm; the substrate preform cross positioning mark line width is 5μm, and the edge roughness is 0.1μm;

[0135] 2. Chopper grating: grating period 45μm, duty cycle 50%, grating line width 22μm, metal structure layer thickness 4μm, gold film surface roughness Ra=9nm;

[0136] 3. Second group of low temperature process: The highest temperature of the whole process is 180℃, nitrogen protection throughout the process, and the thickness of the organosilane coupling agent transition layer is 10nm;

[0137] 4. Sacrificial layer: Low-temperature polyimide, 8μm thick, curing temperature 180℃, curing time 90min;

[0138] 5. Photolithography process: overlay accuracy 0.5μm, single exposure field deviation 0.15μm, alignment angle deviation 0.01°, and the same substrate positioning mark is used as the alignment reference throughout the entire process;

[0139] 6. Electroplating process: The structural layer is 4μm thick and the pad area is 5μm thick. It uses a cyanide-free gold plating system and undergoes staged stress-relief annealing in a nitrogen atmosphere at 180℃.

[0140] 7. Drive structure: The electrostatic comb has a tooth width of 8μm, a tooth spacing of 8μm, 150 pairs of comb teeth, a rated drive voltage of 25V, and a design resonant frequency of 10kHz.

[0141] 8. Alignment and matching: The center deviation between the modulation disk and the photosensitive element array is 1.0μm, the parallelism deviation is 0.01°, and the static light transmission area and the photosensitive area overlap by 90%.

[0142] Preparation process:

[0143] 1. Substrate pretreatment and positioning mark preforming: After completing the megahertz-level ultrasonic cleaning of the substrate, cross-shaped substrate positioning marks are preformed on the substrate surface through electron beam lithography and dry etching processes. The mark line width is 5μm and the edge roughness is ≤0.1μm, which serves as the sole alignment reference for all lithography processes in the entire process.

[0144] 2. Fabrication of photovoltaic chip functional structure, first step-by-step photolithography process cycle:

[0145] S1. Extension of buffer layer and functional layer: within ≤5×10 -4 Under a vacuum environment of Pa, a 200 nm thick CdTe lattice-matching buffer layer is grown on the surface of the photovoltaic functional region of the substrate by molecular beam epitaxy, followed by the sequential growth of an 800 nm thick mercury cadmium telluride infrared photosensitive semiconductor functional layer and a 100 nm thick silicon nitride passivation transition layer.

[0146] S2. PN junction fabrication: The PN junction photoelectric conversion structure was fabricated by photolithography, ion implantation and annealing. The N-type dopant was In and the P-type dopant was As, with a doping depth of 400 nm. The annealing temperature was 350℃ and the annealing time was 45 min. After annealing, the temperature was gradually reduced to room temperature at a rate of 1℃ / min.

[0147] S3. Contact hole fabrication: A 15μm contact hole is fabricated at the corresponding positions of the N-type and P-type regions of the PN junction using photolithography and dry etching processes, with the etching depth extending to expose the doped semiconductor layer.

[0148] S4. Electrode and pad fabrication: A chromium-gold composite layer electrode lead and pad structure with a total thickness of 800 nm was fabricated by photolithography, electron beam evaporation metal deposition and lift-off processes to realize the photoelectric signal extraction of PN junction;

[0149] S5. Preparation of passivation protective layer: A 250nm thick silicon nitride passivation protective layer is deposited on the entire surface using a 300℃ plasma-enhanced chemical vapor deposition process; after completion, a 10nm thick organosilane coupling agent treatment layer is formed on the surface.

[0150] S6. Pad Windowing: Through photolithography and dry etching processes, a passivation protective layer is etched at the corresponding position of the electrode pad to form a window. The deviation between the window size and the pad size is ≤5μm, thus completing the fabrication of all high-temperature processes and functional structures of the photovoltaic chip.

[0151] 3. MEMS modulation disk structure fabrication: A second set of low-temperature compatible step-by-step photolithography processes is used, with a maximum temperature of 180℃ throughout the entire process. All steps are performed under nitrogen protection.

[0152] S1. Surface activation and transition layer preparation: The silicon nitride passivation protective layer on the substrate surface was activated by 300W oxygen plasma for 30s. After activation, a 10nm thick 3-aminopropyltriethoxysilane coupling agent was spin-coated and cured at 110℃ for 60s to form a transition layer.

[0153] S2. Sacrificial layer deposition and patterning: An 8μm thick low-temperature curing polyimide sacrificial layer is spin-coated in the functional area of ​​the substrate modulation disk, i.e., the area directly above the photovoltaic chip photosensitive element array, and cured at 180℃ for 90 min; anchor point windows for cantilever beam fixing anchor points, fixed comb electrode anchor points, electrode lead anchor points, and movable structure grounding anchor points are prepared in the sacrificial layer by photolithography and dry etching processes, and the etching depth is up to expose the underlying passivation protection layer;

[0154] S3. Deposition of composite functional film system: A 15nm thick chromium adhesion layer and a 180nm thick gold optical reflection and conductive seed layer are sequentially vacuum deposited on the surface of the sacrificial layer and inside the anchor point window to form a composite functional film system compatible with photolithography process.

[0155] S4. Thick-film photolithography patterning: Positive thick-film photoresist was used, and the photoresist layer was prepared through a step-by-step homogenization process. The first step was at a rotation speed of 750 rpm for 9 seconds, and the second step was at a rotation speed of 3500 rpm for 55 seconds, forming a photoresist layer with a thickness of 9 μm. After pre-baking at 105℃ for 120 seconds and alignment exposure, the exposure dose of the chopper grid pattern area was 220 mJ / cm². 2 Exposure dose to the driving structure pattern area is 180 mJ / cm 2 The electroforming mold was prepared by developing the film with a 2.38% (w / w) tetramethylammonium hydroxide developer for 110 seconds, hardening the film at 125°C, and then baking for 210 seconds. All photolithography alignment processes used the pre-formed substrate positioning marks as the sole alignment reference, and the alignment and bonding were completed using a front-side alignment photolithography process with an overlay accuracy of 0.5 μm.

[0156] S5. Electroplating Thickening and Stress-Relief Annealing: Using the formed thick photoresist as the electroforming mold, a cyanide-free gold electroplating solution with 0.5% stress modifier is used to thicken the seed layer, with the core structure area thickened to 4μm and the pad area thickened to 5μm simultaneously; after electroplating, a staged low-temperature stress-relief annealing is performed in a nitrogen atmosphere, with the first stage held at 160℃ for 60 minutes and the second stage held at 180℃ for 90 minutes;

[0157] S6. Resin Removal and Seed Layer Etching: The photoresist electroforming mold is removed by immersion in acetone combined with 100W, 40kHz low-power ultrasonic cleaning for 15 minutes, exposing the bare seed layer area; the exposed seed layer and adhesion layer are etched by inductively coupled plasma etching process, with the etching depth reaching the exposed sacrificial layer. During the etching process, a 200V negative bias voltage is applied to the photovoltaic functional area for protection, completely severing the seed layer connection between the fixed comb teeth and the movable comb teeth, and achieving electrical isolation between the two.

[0158] S7. Release window preparation: The sacrificial layer release windows are prepared by homogenization, photolithography, and dry etching processes. The photoresist forms a continuous enclosure structure with a width of 22 μm at the edge of the release window. The release windows are evenly distributed in the gaps, edges, and four corners of the movable structure. The maximum spacing between adjacent windows is 300 μm. The total area of ​​the windows accounts for 32% of the total area of ​​the sacrificial layer.

[0159] S8. Sacrificial layer release and drying: Before release, the device is pretreated with electron beam irradiation at a dose of 3000 Gy. Then, the sacrificial layer is released by wet method at 55°C for 90 min using N-methylpyrrolidone release solution with 10% ethanolamine corrosion inhibitor. After release, isopropanol gradient displacement combined with critical point drying process is used to avoid capillary adhesion of the MEMS movable structure and form a freely resonant MEMS modulation disk structure.

[0160] 4. Device aging and testing screening: Devices that have completed all fabrication processes are aged and stabilized for 24 hours at 40℃ and 50%±5% relative humidity. Then, photovoltaic characteristic tests, dynamic photoelectric performance tests and environmental reliability tests are performed in sequence to screen out qualified devices that meet the performance requirements.

[0161] Experimental test data table 3:

[0162]

[0163] Technical effects:

[0164] This embodiment employs the upper limit of process parameters, achieving stable integrated modulation disk and photovoltaic chip under limited boundary conditions. The 180℃ low-temperature process did not significantly damage the photoelectric performance of the photovoltaic chip, ensuring the basic functions of the device. The thick metal grid structure achieves high infrared reflectivity, meeting the requirements for high-frequency modulation. At the same time, it maintains the cycle and cost advantages compared to traditional processes. The environmental reliability and performance consistency of the device meet the usage requirements, verifying the breadth of the process window and mass production stability.

[0165] II. Comparative Example

[0166] Comparative Example 1: Non-Cryogenic Compatible Process

[0167] Key variable settings:

[0168] Except for the second group of MEMS processes, where the maximum temperature was set to 250°C and nitrogen protection and silane coupling agent interface treatment were not performed, all other process parameters, design parameters, and preparation processes were completely consistent with those in Example 2.

[0169] Preparation process:

[0170] 1. Substrate pretreatment and positioning mark preforming: exactly the same as in Example 2, preforming cross-shaped substrate positioning marks with a line width of 4μm as the alignment reference for the entire photolithography process.

[0171] 2. Fabrication of photovoltaic chip functional structure: Completely consistent with Example 2, the PN junction, electrodes, passivation protective layer and pad windowing are completed, and the surface of the passivation layer is not treated with organosilane coupling agent.

[0172] 3. Fabrication of MEMS modulation disk structure: non-cryogenic process, no nitrogen protection or interface treatment:

[0173] S1. Oxygen plasma activation and silane coupling agent transition layer preparation are skipped, and the process proceeds directly to the sacrificial layer deposition process;

[0174] S2. Sacrificial layer deposition and patterning: Spin-coat a 5μm thick polyimide sacrificial layer and cure at 250℃ for 90min. The remaining patterning and anchor point window preparation processes are completely consistent with those in Example 2.

[0175] S3. Deposition of composite functional film system: Completely consistent with Example 2, depositing a 12nm chromium adhesion layer and a 140nm gold seed layer;

[0176] S4. Thick photoresist patterning: Completely consistent with Example 2, an 8μm thick photoresist electroforming mold was prepared, and all photolithography processes were performed without nitrogen protection;

[0177] S5. Electroplating thickening and stress-relieving annealing: The electroplating thickening parameters are completely consistent with those in Example 2, the annealing temperature is 250℃, without nitrogen protection, and the annealing time is 120min.

[0178] S6. Degumming and Seed Layer Etching: Completely consistent with Example 2;

[0179] S7. Preparation of the release window: Completely consistent with Example 2;

[0180] S8. Sacrificial layer release and drying: Completely consistent with Example 2, completing the fabrication of the MEMS modulation disk structure.

[0181] 4. Device aging and testing screening: The same aging and testing process as in Example 2 is performed.

[0182] Experimental test data table 4:

[0183]

[0184] Technical effects:

[0185] This comparative example uses a high-temperature process exceeding the limits of the claims and fails to implement corresponding interface protection measures. This results in significant thermal damage to the mercury cadmium telluride photosensitive layer and PN junction of the photovoltaic chip, leading to a substantial decrease in photoelectric conversion performance, an order-of-magnitude increase in dark current, and severe signal distortion. Simultaneously, the high-temperature process causes film stress mismatch and insufficient interfacial adhesion, increasing the risk of deformation and detachment of the MEMS structure. This significantly reduces device yield, consistency, and environmental reliability, failing to meet the requirements for infrared detectors.

[0186] Comparative Example 2: Traditional Split-Body Bonding Process

[0187] Key variable settings:

[0188] The photovoltaic chip was independently fabricated according to the first group of processes in Example 2. The MEMS modulation disk was independently fabricated on a separate silicon substrate according to the parameters in Example 2. After completion, a high-precision pick-and-place machine was used for alignment and bonding. The adhesive layer thickness was 5μm. The remaining design parameters were completely consistent with those in Example 2.

[0189] Preparation process:

[0190] 1. Independent fabrication of photovoltaic chips: Using the same substrate pretreatment and first-group stepwise photolithography process cycle as in Example 2, the independent photovoltaic chips are fabricated without MEMS-related processes. After fabrication, the chips are diced to obtain individual photovoltaic chip dies.

[0191] 2. Independent fabrication of MEMS modulation disk: Using a separate 6-inch single-crystal silicon substrate, the MEMS modulation disk structure was independently fabricated, the sacrificial layer was released and dried according to the second set of low-temperature process parameters in Example 2. After fabrication, the wafer was diced to obtain a single modulation disk grain.

[0192] 3. High-precision alignment and bonding assembly: A high-precision chip mounter is used, with the photosensitive element array mark of the photovoltaic chip as the reference and the grid pattern of the modulation disk as the alignment target. After visual alignment, the components are bonded and assembled. Epoxy resin is used as the adhesive, with a thickness of 5μm. After bonding, the adhesive is cured at 80℃ for 2 hours to complete the assembly of the split device.

[0193] 4. Device aging and testing screening: The same aging and testing process as in Example 2 is performed.

[0194] Experimental test data table 5:

[0195]

[0196] Technical effects:

[0197] This comparative example employs a traditional modular fabrication followed by adhesive assembly. While the fundamental photoelectric performance of the photovoltaic chip remains unaffected, the adhesive assembly introduces significant alignment deviations, drastically reducing the overlap between the modulation structure and the photosensitive element. This results in a decrease in optical modulation depth and a significant increase in optical loss and signal distortion. The adhesive layer introduces additional interfacial thermal stress, leading to interfacial debonding and misalignment issues after high and low temperature cycling, resulting in severe device performance degradation and poor environmental reliability. Furthermore, the modular fabrication process is lengthy, and the assembly steps significantly increase labor and equipment costs, substantially extending the production cycle. The device yield and consistency are far lower than with integrated processes.

[0198] Comparative Example 3: Process Comparative Example without a Unified Alignment Reference

[0199] Key variable settings:

[0200] Instead of using a limited set of linked positioning patterns and a unified substrate positioning mark, the photovoltaic chip photolithography uses an independent first set of positioning marks, and the MEMS modulation disk photolithography uses another independent second set of positioning marks. All other process parameters and preparation procedures are completely consistent with those in Example 2.

[0201] Preparation process:

[0202] 1. Substrate pretreatment and preforming of two sets of independent positioning marks: After completing the megahertz-level ultrasonic cleaning of the substrate, two sets of independent positioning marks are preformed on the substrate surface by electron beam lithography and dry etching processes. The first set is a positioning mark for photovoltaic chips and the second set is a positioning mark for MEMS modulation disks. The two sets of marks have no linkage matching design, and the remaining marking parameters are the same as in Example 2.

[0203] 2. Fabrication of photovoltaic chip functional structure: All photolithography processes use the first set of independent positioning marks as the sole alignment reference. The remaining process parameters and fabrication steps are completely consistent with those in Example 2, thus completing the fabrication of the photovoltaic chip functional structure.

[0204] 3. MEMS modulation disk structure fabrication: All photolithography processes use the second set of independent positioning marks as the sole alignment reference, without using the first set of positioning marks used in photovoltaic chip fabrication. The remaining process parameters and fabrication steps are completely consistent with those in Example 2, thus completing the fabrication of the MEMS modulation disk structure.

[0205] 4. Device aging and testing screening: The same aging and testing process as in Example 2 is performed.

[0206] Experimental test data table 6:

[0207]

[0208] Technical effects:

[0209] The lack of a unified alignment reference in this comparison resulted in cumulative alignment deviations between the photovoltaic chip and the modulation disk photolithography process. The center deviation exceeded 3μm, the parallelism deviation exceeded 0.05°, and the static overlap between the light-transmitting and photosensitive areas was less than 80%. This led to a significant decrease in optical modulation depth, severe light loss, and signal distortion. Furthermore, the use of multiple alignment references caused extreme fluctuations in alignment deviations within the same batch of devices, resulting in extremely poor performance consistency. Many devices failed to meet usage requirements due to misalignment, leading to a significant drop in device yield. This demonstrates the crucial role of a unified alignment reference and a coordinated positioning pattern set in improving the performance of integrated devices.

[0210] It is worth noting that, for the electroforming thickening requirements of MEMS fine structures such as chopper grids and electrostatic comb-driven electrodes in this invention, and to adapt to a low-temperature compatible process with a full-process temperature of ≤180℃, the cyanide-free aluminum electroplating solution used in this invention can be selected from the following directly applicable formulation systems. All systems strictly control the addition of stress modifiers within the mass fraction range of 0.1%-0.5%, exhibiting excellent compatibility with polyimide sacrificial layers, thick photoresist lithography molds, and silicon nitride passivation layers. They are non-swelling and non-corrosive, and can precisely control the plating thickness of the core structure to 2μm-4μm and the plating thickness of the pad area to 4μm-5μm, with the plating thickness not exceeding 75% of the corresponding photoresist thickness. To avoid image distortion, the preferred MEMS process uses a general-purpose low-stress imidazole ionic liquid cyanide-free aluminum electroplating solution. The formula consists of anhydrous high-purity 99.99% aluminum chloride 1.8-2.2 mol / L, electroplating-grade anhydrous 1-ethyl-3-methylimidazolium chloride with ≤50 ppm moisture content 1.0-1.2 mol / L, electroplating-grade high-purity 1,10-o-phenanthroline 2-5 g / L, anhydrous analytical grade benzaldehyde 3-6 g / L, electroplating-grade high-purity tetrabutylammonium chloride 1-3 g / L, and anhydrous high-purity LiCl 0.5-1 g / L. This system is maintained under a strictly anhydrous and oxygen-free argon inert atmosphere, at a room temperature of 25℃-35℃, and with a flux of 0.3-0.8 A / dm³. 2Stable deposition can be achieved under DC electroplating conditions, with a deposition rate of 0.6-1.0 μm / h. The resulting coating has an internal stress of ≤8 MPa at room temperature. After staged annealing in a nitrogen atmosphere at 160℃-180℃ according to this invention, the internal stress is ≤3 MPa, with no warping or cracking. The surface roughness Ra is ≤7 nm, the infrared reflectivity in the 3μm-5μm band is ≥98.5%, the fine pattern linewidth deviation is ≤0.2 μm, the grid line edge roughness is ≤0.3 μm, and the adhesion to the aluminum seed layer is ≥4B. It can simultaneously adapt to the full-structure electroplating requirements of chopper grids, cantilever beams, and comb electrodes. It is suitable for electrostatic combs with a linewidth of 5μm-8μm and 12μm... For high aspect ratio fine structures such as chopper gratings with a linewidth of -22μm, a high aspect ratio dedicated ionic liquid aluminum electroplating solution can be used. The formula components are: 1.6-2.0 mol / L of anhydrous high-purity 99.99% aluminum chloride, 1.0 mol / L of electroplating grade anhydrous 1-butyl-3-methylimidazolium chloride with ≤50ppm water content, 1-3 g / L of electroplating grade high-purity 2,2'-bipyridine, 2-4 g / L of electroplating grade PEG-2000, 0.5-1 g / L of analytical grade p-toluenesulfonamide, and 0.5-1 g / L of anhydrous high-purity sodium chloride. This system operates at 30℃-40℃ with a peak current density of 0.5-1.0 A / dm³. 2 Under pulse electroplating conditions with a duty cycle of 20%-30% and a frequency of 500Hz, the deep plating capability is ≥95%, the uniformity deviation of the plating layer in the comb grooves with a line width of 5μm and a depth of 8μm is ≤5%, the perpendicularity of the grid line edge is ≥89°, there are no burrs or bulges, the structure shows no deformation after annealing at 180℃, and the device resonant frequency deviation is ≤±0.5%. For the extreme requirements of high infrared reflection and low light scattering in chopper grids, a high infrared reflection-specific ether-based organic solvent cyanide-free aluminum electroplating solution can be selected, with a formulation of anhydrous high-purity 99.9%. The system consists of 1.5-2.0 mol / L of 9% aluminum chloride, tetrahydrofuran with anhydrous ultra-dry moisture content ≤30 ppm as the main solvent to a final volume of 1L, 0.2-0.5 mol / L of anhydrous high-purity lithium aluminum hydride, 0.3-0.6 mol / L of anhydrous analytical grade triethylamine, 1-4 g / L of electroplating grade high-purity 2-mercaptobenzothiazole, and 0.1-0.3 g / L of electroplating grade sodium dodecylbenzenesulfonate. This system is maintained under strict anhydrous and oxygen-free high-purity argon protection at room temperature (20℃-30℃) and an A / dm³ pressure of 0.2-0.5 A / dm³. 2Under DC electroplating conditions, the resulting coating exhibits a surface roughness Ra ≤ 5 nm, an infrared reflectance ≥ 99.0% in the 3 μm-5 μm band, light scattering loss ≤ 0.8%, no abnormal grain growth after nitrogen annealing at 180℃, infrared reflectance attenuation ≤ 0.2%, and internal stress ≤ 5 MPa, making it suitable for the long-term resonant operation requirements of movable structures. For the large-scale production needs of this invention, an environmentally friendly water-based microemulsion cyanide-free aluminum electroplating solution can be used, with the formula consisting of electroplating-grade high-purity aluminum sulfate. The system contains 60-80 g / L of industrial-grade high-purity dimethylaminoethoxyethanol (120-150 g / L), electroplating-grade boric acid (30-40 g / L), analytical-grade ascorbic acid (5-10 g / L), electroplating-grade polyethyleneimine (600 molecular weight) (2-5 g / L), electroplating-grade sodium dodecyl sulfate (0.1-0.3 g / L), and electroplating-grade sodium saccharin (0.5-1 g / L). The system operates at pH 8.0-9.0, 40℃-45℃, and 0.5-1.2 A / dm³. 2 Under DC electroplating conditions, the uniformity deviation of the 6-inch wafer-level plating thickness is ≤±3%, the performance consistency deviation of devices in the same batch is ≤±3%, the surface roughness Ra is ≤8nm, the reflectivity in the 3μm-5μm infrared band is ≥98.2%, the internal stress of the plating layer is ≤10MPa, the internal stress after annealing at 180℃ is ≤4MPa, and the service life of the plating solution is ≥3 metal turnovers, which is suitable for the cycle time and stability requirements of automated mass production lines. Before electroplating, all aluminum electroplating solutions must be activated by 50W-100W oxygen plasma for 30s to remove the surface oxide layer and improve the adhesion between the plating layer and the seed layer. After electroplating, the aluminum seed layer must be rinsed with anhydrous ethanol and dried with high-purity nitrogen immediately, and then quickly transferred to the subsequent process to avoid the surface oxide layer affecting the pattern etching accuracy.

[0211] In summary, the working principle of the photolithography method for integrating the chip and modulation disk provided in this embodiment is as follows:

[0212] This scheme integrates and fabricates a photovoltaic chip and a MEMS modulation disk in two stages on the same double-sided polished monocrystalline silicon support substrate. First, the entire process of fabricating the semiconductor functional structure of the photovoltaic chip is completed, and then the MEMS modulation disk structure is fabricated on the same substrate. The two types of structures are aligned at the center and stacked in parallel on the substrate. A controllable movement gap is formed in the middle through a sacrificial layer release process, and finally an integrated device without adhesive assembly is formed.

[0213] The working principle of photovoltaic chips is as follows: through epitaxial growth, doping and annealing processes, a PN junction structure with photovoltaic effect is formed on the substrate. When incident infrared light shines on the photosensitive area of ​​the PN junction, it will excite the generation of photogenerated carriers. The photogenerated carriers move directionally under the action of the built-in electric field of the PN junction to form a photocurrent, realizing the conversion of infrared light into electrical signal. The matching electrode leads and pad structure can stably lead out the generated photoelectric signal to the external processing circuit.

[0214] The working principle of optical modulation is as follows: the optical modulation structure of the MEMS modulation disk is integrally formed with the electrostatic comb drive structure. The fixed comb electrode is fixed to the substrate by anchor points, and the movable comb is rigidly connected to the optical modulation grid and connected to the fixed anchor points on the substrate through a cantilever beam structure. When a matching driving voltage is applied between the fixed and movable comb teeth, the electrostatic force will drive the movable structure to perform linear reciprocating resonant motion, which in turn drives the optical modulation grid to perform synchronous reciprocating motion. This causes the light-transmitting area of ​​the grid to periodically overlap and block the photosensitive area of ​​the photovoltaic chip, modulating the incident constant infrared light into an alternating optical signal. This allows the photovoltaic chip to output an alternating photoelectric signal that matches the modulation frequency, facilitating signal amplification and processing by subsequent circuits and effectively suppressing DC noise caused by background infrared radiation.

[0215] The principle behind process compatibility is as follows: the entire fabrication process of the modulation disk employs a low-temperature compatible process, with the temperature of all steps controlled within a range that will not damage the semiconductor structure of the photovoltaic chip. Simultaneously, all steps are performed under nitrogen protection to prevent material oxidation failure. A silane coupling agent transition layer is pre-prepared on the surface of the passivation protection layer of the photovoltaic chip, which effectively enhances the interfacial adhesion between the subsequent low-temperature process film layer and the passivation layer, reduces the adverse effects of residual process stress on the MEMS microstructure, and ultimately achieves stable and compatible integration of semiconductor and MEMS processes on the same substrate.

[0216] How to use:

[0217] The integrated device, after completing all photolithography and structure release processes, is first aged and stabilized under a set temperature and humidity environment to stabilize the various performance characteristics of the device. Then, photovoltaic characteristics, dynamic photoelectric performance and environmental reliability tests are carried out in sequence to screen out qualified devices that meet the usage requirements.

[0218] The selected integrated devices are fixed into the appropriate package, and mechanical fixation and heat dissipation are matched. Through gold wire bonding, the signal pads of the photovoltaic chip, the drive pads of the MEMS drive structure and the ground pads on the device are connected to the corresponding external pins of the package. After completion, the package is hermetically sealed to isolate the device from external moisture and impurities.

[0219] Install the packaged device into the optical path of the infrared detection system, ensuring that the photosensitive surface of the device is perpendicularly aligned with the incident infrared light path. Connect the signal pins of the photovoltaic chip on the casing to the preamplifier circuit and subsequent signal processing circuit. Connect the drive pins of the MEMS drive structure to the dedicated drive control circuit. Reliably connect the ground pin to the common ground of the system.

[0220] Before formal use, device debugging is completed. A matching AC / DC superimposed driving voltage is applied to the MEMS driving structure via the drive control circuit. The frequency of the driving voltage is adjusted to match the inherent resonant frequency of the device, ensuring the optical modulation structure of the modulation disk operates stably in the set resonant state and that the reciprocating motion meets the modulation requirements. Then, an appropriate bias voltage is applied to the photovoltaic chip to ensure it operates in its optimal photoelectric conversion state. After debugging, it can be used normally. The incident infrared light is focused by the optical system, passes through the optical modulation structure of the modulation disk, and directly strikes the photosensitive surface of the photovoltaic chip. The modulated infrared light is converted into a corresponding alternating photoelectric signal by the photovoltaic chip, which is then transmitted to the subsequent signal processing circuit for analysis and processing, completing the relevant functions of infrared detection.

[0221] During daily use, the performance of the device can be calibrated regularly according to the working conditions of the environment to ensure the stability of the modulation frequency and photoelectric conversion performance. At the same time, the device should be avoided in environments with temperature, humidity, vibration and shock that exceed the design range to extend its service life.

[0222] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made based on the description and illustrations of the present invention should be included within the protection scope of the present invention.

Claims

1. A photolithography method for integrating a chip and a modulation disk, characterized in that: The optical modulation pattern of the movable modulation disk of the infrared detector MEMS and the semiconductor functional pattern of the photovoltaic chip are integrated in stages into a group of multiple photomasks with matching overlay precision. On the same double-sided polished single-crystal silicon support substrate, the entire process is completed in two stages: First, the first set of step-by-step photolithography process cycles is executed to complete the photoelectric conversion functional structure, matching electrode leads, pad structure, and pad passivation window preparation of the photovoltaic chip; then, the second set of low-temperature compatible step-by-step photolithography process cycles with a full process temperature ≤180℃ is executed to prepare a MEMS modulation disk movable infrared optical modulation structure, an electrostatic comb drive structure, and an electrically isolated electrode lead and pad structure that are aligned with the center of the photoelectric conversion functional structure and stacked in parallel on the infrared incident light side of the photovoltaic chip. The electrostatic comb drive structure drives the optical modulation structure of the modulation disk to perform linear reciprocating resonant motion, realizing the controllable relative motion between it and the photovoltaic chip photoelectric conversion functional structure. This allows the infrared incident light to be directly incident on the photosensitive surface of the photovoltaic chip after modulation, directly obtaining the core device of the integrated infrared detector of chip and modulation disk without additional bonding assembly. All process steps of the second low-temperature compatible step-by-step lithography process cycle are carried out in a nitrogen-protected environment, and an organosilane coupling agent transition layer is pre-formed on the surface of the passivation protection layer of the photovoltaic chip to enhance the interfacial bonding between the low-temperature process film layer and the passivation layer and prevent the residual stress of the high-temperature process from affecting the subsequent MEMS structure.

2. The method according to claim 1, characterized in that, The photolithography mask set includes an interconnected chip positioning pattern set and a modulation disk positioning pattern set. The mask fabrication accuracy meets the requirement that the relative positional deviation between the semiconductor functional pattern of the photovoltaic chip and the chip positioning pattern set is ≤1.0μm. The relative positional deviation between the optical modulation pattern and the positioning pattern group of the MEMS modulation disk is ≤1.0μm; both sets of positioning pattern groups are matched with the dimensional accuracy of the substrate positioning marks. The linewidth of the substrate positioning marks is 3μm-5μm. They are pre-formed on the substrate surface through photolithography and etching processes during the substrate preprocessing stage, so that the center of motion of the movable optical modulation structure of the photolithographically formed MEMS modulation disk is ≤1.0μm off from the center position of the photosensitive element array center of the photovoltaic chip photoelectric conversion functional structure; the parallelism angle deviation between the grid lines and the photosensitive element array is ≤0.01°; the photosensitive element array is arranged in equally spaced line columns or area arrays, with the size of a single photosensitive element being 20μm-50μm. The side length of a single photosensitive element matches the grid period of the chopper grid, with a deviation of ≤3μm; the substrate positioning marks adopt cross-shaped or L-shaped composite marks, which are prepared by electron beam lithography, and the mark edge roughness is ≤0.1μm to improve alignment accuracy and repeatability.

3. The method according to claim 2, characterized in that, The optical modulation pattern on the photolithographic mask assembly includes an equally spaced chopper grating pattern that matches the modulation frequency of the infrared detector guidance system. The duty cycle of the chopper grating = grating line width / (grating line width + grating spacing) = 50% ± 3%, meaning the grating line width and grating spacing are equal, with a deviation ≤ ± 3%. The grating period of the chopper grating = grating line width + grating spacing, ranging from 25 μm to 45 μm. The matched modulation frequency is consistent with the inherent resonant frequency of the MEMS electrostatic drive structure, with a deviation ≤ ± 1.0%. For the same device design, the resonant frequency is set within one of the following sub-ranges: 100Hz-500Hz, 500Hz-2kHz, 2kHz-5kHz, or 5kHz-10kHz. The grating line width of the chopper grating pattern is 12 μm-22 μm, and the grating spacing is 12 μm-2... The thickness of the metal structure layer of the chopper grid is 2μm-4μm. The grid lines of the chopper grid pattern are set parallel to the column edges of the photosensitive element array of the photovoltaic chip semiconductor functional pattern. The center of the grid array coincides with the center of the photosensitive element array. When the chopper grid moves linearly and reciprocally with the electrostatic drive structure, the effective driving stroke in one direction is ≥1 / 2 grid period. The light-transmitting area and the photosensitive area of ​​the photosensitive element periodically coincide and block each other in the normal direction of the substrate. In the static coincidence state, the overlap between the light-transmitting area and the photosensitive area is ≥90%, so that the infrared incident light is directly incident on the photosensitive surface of the photosensitive element after being modulated by the chopper grid. The metal structure layer of the chopper grid is made of gold or aluminum, and the surface is chemically and mechanically polished with a surface roughness Ra≤10nm to improve infrared reflectivity and reduce light scattering loss.

4. The method according to claim 1, characterized in that, Before performing the photolithography process cycle, the monocrystalline silicon support substrate is first subjected to megahertz-level ultrasonic cleaning with a cleaning power of 300W-800W and a cleaning time of 5min-15min; the substrate thickness is 200μm-500μm; after cleaning, the first set of stepwise photolithography process cycles is performed to fabricate the core structure of the photovoltaic chip for photoelectric conversion in the photovoltaic functional area of ​​the substrate. The specific steps are as follows: S1. In ≤5×10 -4 Under a vacuum environment of Pa, a lattice-matching buffer layer is first epitaxially grown on the surface of the photovoltaic functional region of the substrate using molecular beam epitaxy or metal-organic chemical vapor deposition. A CdTe buffer layer is used for the mercury cadmium telluride photosensitive layer, and a ZnS buffer layer is used for the lead sulfide photosensitive layer, with a thickness of 50nm-200nm. Then, an infrared photosensitive semiconductor functional layer and a passivation transition layer are sequentially prepared on the surface of the lattice-matching buffer layer using the same epitaxial process. The infrared photosensitive semiconductor functional layer uses a lead sulfide or mercury cadmium telluride infrared photosensitive layer with a thickness of 300nm-800nm. The passivation transition layer uses a silicon nitride or silicon dioxide dielectric film with a thickness of 50nm-100nm to block impurities from subsequent processes. S2. A PN junction photoelectric conversion structure for photovoltaic chips is fabricated through photolithography, doping, and annealing processes. The doping process employs ion implantation or vapor diffusion. For mercury cadmium telluride, the N-type dopant is In and the P-type dopant is As. For lead sulfide, the N-type dopant is I and the P-type dopant is Cu. The doping depth is 100nm-400nm, the annealing temperature is 200℃-350℃, and the annealing time is 45min-90min. After annealing, the temperature is gradually reduced to room temperature at a rate ≤2℃ / min to form a PN junction structure with photovoltaic effect. S3. Contact holes are prepared at corresponding positions of the N-type and P-type regions of the PN junction using photolithography and dry etching processes. The etching depth extends to expose the doped semiconductor layer of the PN junction, and the contact hole size is 5μm-15μm. S4. The electrode leads and pad structures of the photovoltaic chip are prepared by photolithography, metal deposition and lift-off processes. The metal layer adopts a chromium-gold composite layer with a total thickness of 300nm-800nm ​​to realize the photoelectric signal extraction of the PN junction. S5. After completing the fabrication of the photovoltaic functional structure and signal extraction structure, a passivation protective layer is deposited on the entire surface of the photovoltaic functional area. The passivation protective layer is a silicon nitride dielectric film with a thickness of 150nm-250nm. It is prepared by plasma-enhanced chemical vapor deposition at 300℃±10℃ to optimize the film stress and density. The transmittance in the 1μm-5μm infrared band is ≥92%. It also serves as a barrier layer for wet release and dry corrosion in subsequent MEMS processes. A 5nm-10nm thick organosilane coupling agent treatment layer is formed on the surface to improve the adhesion to the film layer in subsequent low-temperature processes. S6. Passivation layer pad opening: Through photolithography and dry etching processes, the passivation protective layer is etched at the corresponding position of the electrode pads of the photovoltaic chip to form a pad opening, exposing the underlying metal pad. The opening size matches the pad size with a deviation of ≤5μm, completing the fabrication of all high-temperature processes and functional structures of the photovoltaic chip.

5. The method according to claim 4, characterized in that, After completing the photovoltaic chip structure fabrication, the second set of low-temperature compatible step-by-step photolithography process cycles is executed to fabricate the MEMS modulation disk structure. Specifically, the silicon nitride passivation protective layer on the substrate surface is first activated by oxygen plasma at a power of 100W-300W for 30s-120s to improve the adhesion between the subsequent film layer and the passivation layer. After activation, a 5nm-10nm thick layer of 3-aminopropyltriethoxysilane coupling agent is spin-coated onto the passivation layer surface and cured at 110℃ for 60 seconds to form a transition layer. Then, a sacrificial layer is spin-coated onto the modulation disk functional area of ​​the substrate, which is the area directly above the photovoltaic chip photosensitive element array. The sacrificial layer is made of low-temperature curable polyimide with a thickness of 3μm-8μm and a curing temperature of 150℃-180℃ for 75min-105min. This sacrificial layer is used to release the movable MEMS modulation structure, forming the desired structure. The movement gap between the modulation disk and the photovoltaic chip is defined. Then, anchor windows are defined in the sacrificial layer using photolithography and dry etching processes. The anchor windows include cantilever beam fixing anchors, fixed comb electrode anchors, electrode lead anchors, and movable structure grounding anchors. The etching depth extends to expose the underlying passivation protection layer. Next, an adhesion layer, an optical reflection layer, and a conductive seed layer are vacuum-deposited sequentially within the sacrificial layer and the anchor windows to form a composite functional film system compatible with photolithography processes. The adhesion layer uses a chromium or titanium layer with a thickness of 8nm-15nm. The optical reflection and conductive seed layer uses a gold or aluminum film with a thickness of 100nm-180nm. Subsequently, the thickness is increased to 2μm-4μm through electroplating. This layer also serves as the infrared reflection modulation layer of the modulation disk, the structural support layer of the MEMS movable structure, and the electrostatic drive electrode layer. The composite functional film system directly contacts the substrate passivation protection layer at the anchor windows to form fixed anchors. The sacrificial layer is made of polyimide.

6. The method according to claim 2, characterized in that, All photolithography processes employ a front-side alignment photolithography process with an overlay accuracy of ≤0.5μm for mask and substrate alignment. Furthermore, all photolithography processes use the same set of pre-formed substrate positioning marks as the sole alignment reference. Specifically, the alignment system is aligned using a photolithography equipment with a positioning resolution of ≤0.3μm. The position coordinates of the pre-formed substrate positioning marks on the substrate surface are first acquired, with a sampling number of ≥5 times. Coordinate fitting deviation ≤ 0.4 μm; Next, the position coordinates of the positioning pattern group on the current photomask are acquired. Using the reference coordinates of the substrate positioning mark as a reference, the position of the photomask is adjusted so that the reference coordinates of the current photomask positioning pattern group coincide with the reference coordinates of the substrate positioning mark. The angular deviation of the alignment adjustment is ≤0.01°. The alignment and bonding are completed. For the fine pattern photolithography process of MEMS chopper grid and comb electrode, step exposure is adopted, and the field deviation of a single exposure is ≤0.2μm. Before each photolithography alignment, the substrate is subjected to temperature balancing treatment by standing at 23℃±1℃ for more than 30 minutes to eliminate the influence of thermal drift on the overlay accuracy.

7. The method according to claim 6, characterized in that, By controlling the precision of the overlay alignment process, the center position deviation between the motion center of the movable optical modulation structure of the MEMS modulation disk and the center of the photosensitive element array of the photovoltaic chip photoelectric conversion functional structure is stably controlled within the range of 0.4μm-0.8μm; the parallelism angle deviation is ≤0.01°. Compared with the typical angle deviation of 0.1°-0.5° and center alignment error of 2μm-10μm caused by the adhesive bonding assembly of the modulation disk and the photovoltaic chip in the separate fabrication process, the alignment accuracy is significantly improved.

8. The method according to claim 1, characterized in that, The second set of stepwise photolithography process cycles performs independent photolithography steps for the chopper grid, cantilever beam, electrostatic comb drive electrode, electrode leads, and pads in the modulation disk functional area. The core structure patterning adopts the standard LIGA-like process of thick resist photolithography - electroforming thickening - stress relief annealing - resist removal - seed layer etching. Each core photolithography step includes resist coating, pre-baking, alignment exposure, development, hard film and post-baking in sequence. The resist coating uses positive thick resist and is completed through a stepwise resist coating process. The first step is completed at a rotation speed of 600rpm-750rpm. The first step involves a rotation speed of 6-9 seconds, followed by a second step at 2500-3500 rpm for 40-55 seconds, forming a photoresist layer with a thickness of 7-9 μm on the substrate surface. The uniformity deviation of the photoresist layer thickness is ≤1.0%. The pre-baking temperature is 95℃-105℃ for 120-150 seconds. Alignment exposure employs a zoned exposure process, performing independent exposures on the chopper grid pattern area and the drive structure pattern area, matching corresponding exposure doses. The exposure dose for the chopper grid pattern area is 180 mJ / cm². 2 -220mJ / cm 2 The exposure dose for the driving structure pattern area is 140 mJ / cm². 2 -180mJ / cm 2 Ensure that the graphics in both regions achieve complete graphic transfer; The development process uses a 2.38% (w / w) tetramethylammonium hydroxide developer for 80-110 seconds. The hardening process is followed by baking at 115-125℃ for 210-270 seconds. After photolithography patterning, the formed thick photoresist is used as an electroforming mold. A cyanide-free electroplating process is then employed to thicken the optical reflection and conductive seed layers, increasing the core structure area to 2-4 μm. The pad areas are simultaneously thickened to 4-5 μm. The thickness of all areas does not exceed 75% of the corresponding photoresist thickness to avoid overfilling and pattern distortion. Simultaneously, chopper grids and suspended... The structural layers of the arm beam, electrostatic comb electrode, electrode leads, and pads are prepared. After electroplating, low-temperature stress-relief annealing is performed in a nitrogen atmosphere at 160℃-180℃ for 90-150 minutes, in two stages: the first stage is held at 160℃ for 60 minutes, and the second stage is held at 180℃ for 30-90 minutes to more effectively eliminate internal stress. The internal stress of the electroplated metal layer is eliminated for subsequent electrical connection with the external drive circuit. The electroplating solution uses cyanide-free gold or aluminum electroplating solution with 0.1%-0.5% stress modifier added to further reduce the internal stress of the plating layer.

9. The method according to claim 8, characterized in that, After completing the electroplating thickening and stress-relief annealing, the following steps are performed sequentially: resist removal, seed layer etching, release window preparation, and sacrificial layer release. S1. The photoresist electroforming mold is removed by acetone immersion combined with low-power ultrasonic cleaning. The cleaning time is 15min-25min, the ultrasonic power is controlled at 50W-100W, and the frequency is 40kHz; the exposed seed layer area between the electroplated structures is exposed. S2. The exposed seed layer and adhesion layer are etched using inductively coupled plasma etching (ICP) technology. Basic parameters are: ICP power 400W-700W, RF bias power 80W-150W. For gold film etching, a mixture of chlorine and argon is used, with a chlorine flow rate of 15-25 sccm and an argon flow rate of 30-45 sccm, and an operating pressure of 1.5Pa-2.5Pa. For aluminum film etching, a mixture of chlorine and boron trichloride is used, with a chlorine flow rate of 30-45 sccm. The boron trichloride flow rate is 15 sccm-25 sccm, and the working pressure is 0.8 Pa-1.5 Pa. The etching depth extends to expose the underlying sacrificial layer. The corrosion selectivity ratio of the electroplated metal structure layer to the seed layer material is ≥10:

1. The corrosion selectivity ratio of the seed layer to the underlying silicon nitride passivation protection layer is ≥25:

1. After etching, the seed layer connection between the fixed comb teeth and the movable comb teeth is completely severed to achieve final electrical isolation between the two. During the etching process, a negative bias voltage of 100V-200V is applied to the photovoltaic functional area to prevent damage to the PN junction by the plasma. S3. After completing the patterning of all MEMS structures, the sacrificial layer release window is prepared by homogenization, photolithography and dry etching processes. The photoresist forms a continuous enclosure structure at the edge of the release window, and the enclosure width is ≥15μm. To reduce lateral corrosion during the release process; release windows are evenly distributed in the gaps, edges, and corners of the movable structure, with a maximum spacing of ≤400μm between adjacent windows; the total area of ​​the windows is ≥25% of the total area of ​​the sacrificial layer; The S4.MEMS movable structure uses a double-end fixed-support folded beam structure with a beam width of 8μm-15μm and a beam length of 150μm-400μm. There are 2-4 sets of beams symmetrically distributed on both sides of the chopper grid structure. The two ends of the cantilever beam are connected to the chopper grid structure and fixed anchor points on the substrate, respectively. The electrostatic comb drive electrodes are divided into fixed and movable combs. The tooth width of both fixed and movable combs is 5μm-8μm, the tooth spacing is 5μm-8μm, the overlap length is 30μm-45μm, and the number of comb teeth is 80-150 pairs. They are symmetrically distributed on both sides of the movable structure. The fixed combs are electrically connected to the drive pads on the substrate via electrode leads. The movable combs are integrally connected to the chopper grid structure and electrically connected to the ground anchor points via the cantilever beam. The linear reciprocating resonant motion of the chopper grid is achieved by applying an AC / DC superimposed drive voltage of 8V-25V, not exceeding the breakdown voltage and pull-in voltage of the comb electrode. S5. After completing the preparation of the release window, the sacrificial layer is removed using a wet release process. The sacrificial layer is a low-temperature curing polyimide. The release solution is an N-methylpyrrolidone solution with 5%-10% ethanolamine added as a corrosion inhibitor to reduce potential corrosion of the silicon nitride layer. The release temperature is 45℃-55℃. The release time is dynamically adjusted according to the thickness of the sacrificial layer, with 15-20 minutes of release time corresponding to each micrometer of thickness. During the release process, the silicon nitride passivation protective layer on the surface of the photovoltaic functional area serves as a permanent corrosion barrier layer.

10. The method according to claim 1, characterized in that, After completing all photolithography cycles, semiconductor processing, and MEMS structure release procedures, photovoltaic characteristic testing, dynamic photoelectric performance testing, and environmental reliability testing were sequentially performed on the integrated device. All tests were conducted in a standard environment of room temperature 25℃±3℃ and relative humidity 40%-60%. Before testing, the device underwent a 24-hour aging and stabilization treatment at a temperature of 40℃±2℃ and relative humidity of 50%±5%. The voltage scan range for photovoltaic characteristic testing was -0.6V to 0.6V, and the current acquisition accuracy was ≤2nA. A four-probe method was used to reduce the influence of contact resistance. Devices with an IV curve deviation of ≤±5% from that of independently fabricated photovoltaic chips of the same structure were selected. Dynamic photoelectric performance testing was also performed. Electrical performance testing uses a blackbody radiation source as the infrared light source, with a temperature setting of 500K-800K, covering the 1μm-5μm band; the light source power is 5μW-80μW, the driving voltage is ±10% of the device's design rated voltage, the frequency scanning range of the MEMS electrostatic drive structure covers ±25% of the device's design resonant frequency, and the scanning step size is 1% of the resonant frequency; the signal acquisition bandwidth is 20Hz-80kHz, and the system noise floor for noise testing is ≤0.2mV. Lock-in amplifier technology is used to improve the signal-to-noise ratio; qualified devices are selected with signal output not lower than 95% of the same specifications of devices assembled by separate bonding and no higher than 105% of the same specifications of devices assembled by separate bonding.

Images