Communication methods of memory controller and memory controller

Abstract

This disclosure provides a communication method for a memory controller and a memory controller. The method includes: obtaining the relative positional relationship of a ring connection between a corresponding processor and multiple circuit modules through a processor; setting a transmission bitmap in the transmission data packet by the processor according to the relative positional relationship and at least one target circuit module of the transmission data packet; when the current circuit module among the multiple circuit modules receives the transmission data packet, the current circuit module parses the transmission bitmap to determine whether the at least one target circuit module includes the current circuit module; if the at least one target circuit module includes the current circuit module, the current circuit module obtains the corresponding target data from the transmission data of the transmission data packet and transmits the transmission data packet to the next circuit module; if the at least one target circuit module does not include the current circuit module, the current circuit module bypasses the transmission data packet and transmits it to the next circuit module.

Description

Technical Field

[0001] This disclosure relates to the field of memory controller technology, and in particular to a communication method and a memory controller for improving the transmission link architecture of various circuit modules within a memory controller. Background Technology

[0002] The storage controller chip is used to control and manage storage devices, and is responsible for managing data transmission between the storage units in the storage device and the host. A storage controller chip typically includes functional modules such as a processor, interface controller, RAM controller, and SRAM cache to achieve data transmission and storage management.

[0003] In existing technologies, a star topology is typically used when the processor inside a storage controller chip communicates with other functional modules. In a star topology, the processor establishes independent data connections with each functional module, with each connection used for data exchange between the processor and its corresponding module. However, this star connection method has several technical problems. First, as the number of functional modules increases, the number of data connections the processor needs to maintain also increases, leading to increased wiring complexity and difficulty in routing within the chip. Second, multiple independent data connections occupy a significant amount of chip wiring space, resulting in an increased chip area. Furthermore, the increased chip area leads to higher overall power consumption, affecting the energy efficiency of the storage device. Summary of the Invention

[0004] In view of this, this disclosure provides a communication method and a memory controller for a memory controller. By changing the connection method between the processor and multiple circuit modules from a star topology to a ring connection, and employing a bitmap addressing mechanism to identify the target circuit module for transmitting data packets, the processor and multiple circuit modules can communicate through a single data path. Each circuit module determines whether it is a target based on the transmission bitmap. If it is a target, it acquires the corresponding data; otherwise, it bypasses and forwards the data packet. Through the above technical solution, this disclosure can reduce the number of data connections, reduce wiring complexity, shrink chip area, and reduce power consumption, thereby solving the aforementioned technical problems existing in the current star topology architecture.

[0005] According to one or more embodiments of this disclosure, a communication method for a memory controller is provided, applicable to a memory controller configured with a processor and multiple circuit modules. The method includes: obtaining, via the processor, the relative positional relationship of a ring connection between the corresponding processor and the multiple circuit modules; setting a transmission bitmap in the transmission data packet via the processor, based on the relative positional relationship and at least one target circuit module of the transmission data packet; when the current circuit module among the multiple circuit modules receives the transmission data packet, the current circuit module parses the transmission bitmap to determine whether the at least one target circuit module includes the current circuit module; if the at least one target circuit module includes the current circuit module, the current circuit module obtains the corresponding target data from the transmission data of the transmission data packet and transmits the transmission data packet to the next circuit module; if the at least one target circuit module does not include the current circuit module, the current circuit module bypasses the transmission data packet transmission to the next circuit module.

[0006] According to one or more embodiments of this disclosure, a memory controller is provided, including: a processor; and a plurality of circuit modules, which are connected in a ring to the processor via a single data path. The processor is configured to acquire the relative positional relationship between the corresponding processor and the plurality of circuit modules in the ring connection, and to set a transmission bitmap in the transmission data packet based on the relative positional relationship and at least one target circuit module of the transmission data packet. Each of the plurality of circuit modules is configured with a bitmap parsing circuit. When the current circuit module receives the transmission data packet, the current circuit module parses the transmission bitmap to determine whether the at least one target circuit module includes the current circuit module. If the at least one target circuit module includes the current circuit module, the current circuit module obtains target data from the transmission data of the transmission data packet and transmits the transmission data packet to the next circuit module. If the at least one target circuit module does not include the current circuit module, the current circuit module bypasses the transmission data packet and transmits it to the next circuit module.

[0007] Based on the above, the communication method and memory controller of the memory controller provided in this disclosure, by establishing a ring connection between the processor and multiple circuit modules, replaces the complex wiring of multiple independent data lines in the traditional star topology with a single data path, which significantly reduces the wiring complexity and winding difficulty inside the chip, thereby reducing the chip area and power consumption.

[0008] Meanwhile, this disclosure introduces a transmission bitmap-based addressing mechanism, allowing the processor to specify one or more target circuit modules by setting identifier bits in the bitmap. It supports multiple transmission modes such as unicast and multicast, improving the flexibility and efficiency of data transmission. Furthermore, this disclosure simplifies control logic and ensures efficient data packet flow in ring connections by parsing and directing the transmission bitmap (processing or bypassing) through each circuit module. Attached Figure Description

[0009] Figure 1A This is a schematic diagram of a traditional star topology.

[0010] Figure 1B This is a schematic diagram of a ring topology architecture shown according to an embodiment of the present disclosure;

[0011] Figure 2 This is a block diagram illustrating a host system and storage device according to an embodiment of the present disclosure;

[0012] Figure 3 A flowchart illustrating a communication method of a memory controller according to an embodiment of the present disclosure;

[0013] Figure 4 This is a schematic diagram illustrating the structure of a data packet according to an embodiment of the present disclosure;

[0014] Figure 5 This is a schematic diagram illustrating an example of a transmission bitmap and an update process according to an embodiment of the present disclosure;

[0015] Figure 6 A flowchart illustrating the circuit module processing transmitted data packets according to embodiments of this disclosure;

[0016] Figure 7A This is a flowchart illustrating path cost calculation according to embodiments of the present disclosure;

[0017] Figure 7B This is a schematic diagram illustrating the determination of the transmission direction according to an embodiment of the present disclosure;

[0018] Figure 8 This is a flowchart illustrating fault tolerance and direction switching according to embodiments of the present disclosure;

[0019] Figure 9 This is a schematic diagram illustrating the transmission of local data packets for each circuit module according to embodiments of the present disclosure;

[0020] Figure 10 This is a schematic diagram illustrating priority arbitration according to an embodiment of the present disclosure. Detailed Implementation

[0021] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0022] Figure 1A This is a schematic diagram of a traditional star topology. Figure 1B This is a schematic diagram of a ring topology architecture according to an embodiment of the present disclosure. Please refer to... Figure 1A In traditional memory controller architectures, the processor is connected to multiple circuit modules using a star topology. Specifically, the processor establishes independent data connections (also called communication links) with circuit modules A, B, C, and so on up to N. Each data connection is used for bidirectional data exchange between the processor and its corresponding circuit module. In this star topology, if the memory controller has N circuit modules, the processor needs to maintain N independent data connections. As the number of circuit modules increases, the number of data connections also increases, leading to increased wiring complexity within the chip. Furthermore, multiple independent data connections require corresponding wiring space during chip layout. When the number of circuit modules is large, the increased wiring space leads to a larger chip area, thus affecting the overall power consumption of the chip. In particular, the processor needs to connect to N circuit modules through N communication links to maintain the integrity of the data transmission architecture.

[0023] Please refer to Figure 1B In one embodiment, this disclosure provides a ring topology to replace the conventional star topology described above. In the ring topology, the processor and multiple circuit modules establish a ring connection through a single data path. Specifically, the processor is connected to both the beginning and end of the ring connection, and multiple circuit modules are sequentially connected in series within the ring connection. Figure 1B Taking the configuration shown as an example, the processor's output is connected to circuit module A, circuit module A is connected to circuit module B, circuit module B is connected to circuit module C, and so on up to circuit module N. Circuit module N is then connected back to the processor's input, thus forming a complete ring connection. In this ring topology, regardless of the number of circuit modules configured in the memory controller, the processor only needs to connect to the beginning and end of the ring connection, reducing the number of data connections from N in a star topology to a fixed number. That is, compared to the traditional star topology, the processor itself only needs to connect to two circuit modules through two communication links, significantly reducing wiring complexity.

[0024] In another embodiment, the ring connection can be configured as a unidirectional ring topology. In a unidirectional ring topology, data packets sequentially pass through multiple circuit modules along a fixed transmission direction. Figure 1B Taking the configuration shown as an example, if a unidirectional ring topology is used and the transmission direction is clockwise, the data packet sent from the processor will sequentially pass through circuit module A, circuit module B, circuit module C, and finally circuit module N, before returning to the processor. In a unidirectional ring topology, the processor is connected to both the beginning and end of the ring, with the beginning serving as the processor's output and the end as its input. This unidirectional configuration can further simplify hardware design, allowing for a significant reduction in chip area.

[0025] In another embodiment, the ring connection can be configured as a bidirectional ring topology. Please refer to... Figure 1B In a bidirectional ring topology, solid arrows represent clockwise data transmission paths, and dashed arrows represent counter-clockwise data transmission paths. The processor can selectively send data packets in either a clockwise or counter-clockwise direction. Specifically, if the processor chooses to send data packets clockwise, the data packets sequentially pass through circuit modules A, B, C, and N. If the processor chooses to send data packets counter-clockwise, the data packets sequentially pass through circuit modules N, C, B, and A. Compared to a unidirectional ring topology, a bidirectional ring topology provides greater flexibility in path selection, allowing the processor to choose the direction with the smaller transmission step size based on the location of the target circuit module, thereby reducing the number of circuit modules the data packets need to pass through to reach the target circuit module. Furthermore, a bidirectional ring topology can bypass the faulty node by switching to the opposite direction when a link in one direction fails, thus providing fault tolerance.

[0026] In another embodiment, the processor can pre-configure a default transmission direction. The default transmission direction can be configured as clockwise or counterclockwise. When the processor needs to send a data packet, if there is no specific path selection requirement, the processor can directly send the data packet along the default transmission direction. In one embodiment, the processor can dynamically adjust the default transmission direction according to the access frequency of each circuit module, so that the circuit modules with more access frequency are located in positions with smaller transmission steps relative to the processor in the default transmission direction, thereby statistically shortening the average transmission path length.

[0027] By using the aforementioned ring topology architecture, this disclosure replaces the multiple independent data connections in a traditional star topology with a single data path, thereby reducing the number of data connections and wiring complexity, and consequently reducing chip area and power consumption. Furthermore, the ring topology architecture supports both unidirectional and bidirectional configurations, allowing for trade-offs between chip area and transmission flexibility based on actual application requirements.

[0028] Figure 2 This is a block diagram illustrating a host system and storage device according to embodiments of the present disclosure. Please refer to... Figure 2The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also called a second processor), host memory 120 (also called host RAM), and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also called electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be disposed on the motherboard of the host system 10.

[0029] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214.

[0030] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0031] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0032] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0033] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0034] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0035] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the memory module 220 according to the instructions of the host system 10, and to execute the communication method of the memory controller provided in this disclosure.

[0036] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program codes, and these control instructions / program codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data.

[0037] In this disclosure, multiple circuit modules within the memory controller 210 are connected to the processor 211 in a ring via a single data path, replacing the multiple independent data connections between the processor 211 and each circuit module in a traditional star topology. Specifically, the multiple circuit modules include a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214, which are sequentially connected in series with the processor 211 to form a ring connection. In one embodiment, the ring connection can be configured as a unidirectional ring topology or a bidirectional ring topology.

[0038] In a bidirectional ring topology configuration, processor 211 is connected to data management circuit 212 in a clockwise direction. Data management circuit 212 is connected to memory interface control circuit 213, memory interface control circuit 213 is connected to buffer memory 214, and buffer memory 214 is then connected back to processor 211, thus forming a clockwise ring data transmission path. In a counter-clockwise direction, processor 211 is connected to buffer memory 214, buffer memory 214 is connected to memory interface control circuit 213, memory interface control circuit 213 is connected to data management circuit 212, and data management circuit 212 is then connected back to processor 211, thus forming a counter-clockwise ring data transmission path. Through this bidirectional ring topology configuration, processor 211 can select either a clockwise or counter-clockwise direction to send data packets based on the location of the target circuit module, thereby shortening the number of circuit modules the data packets need to pass through to reach the target circuit module.

[0039] In a unidirectional ring topology configuration, data packets are transmitted sequentially through multiple circuit modules along a fixed transmission direction. For example, if a clockwise direction is used as the fixed transmission direction, the data packet, after being sent from processor 211, sequentially passes through data management circuit 212, memory interface control circuit 213, and buffer memory 214, and finally returns to processor 211. In a unidirectional ring topology, processor 211 is connected to both the beginning and end of the unidirectional ring topology, with the beginning serving as the output of processor 211 and the end serving as the input of processor 211.

[0040] Furthermore, processor 211 is configured to execute the communication method of the memory controller provided in this disclosure. Specifically, processor 211 is used to obtain the relative positional relationship of the ring connection between processor 211 and multiple circuit modules, and to set the transmission bitmap in the transmission data packet according to the relative positional relationship and at least one target circuit module of the transmission data packet. In a bidirectional ring topology configuration, processor 211 is also used to determine whether to use a clockwise or counterclockwise direction as the transmission direction to send the transmission data packet based on the clockwise and counterclockwise transmission step size of each circuit module relative to processor 211. Processor 211 can also start timeout monitoring after sending the transmission data packet. If no response signal is received from at least one target circuit module within a preset time threshold, processor 211 can determine that there is a link failure in the transmission direction and set the transmission direction to the opposite direction to resend the transmission data packet to achieve fault tolerance.

[0041] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and this disclosure is not limited thereto.

[0042] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0043] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to perform data transmission. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data into the memory module 220 via the memory interface control circuit 213. Alternatively, it performs a read operation according to a read instruction from the host system 10, reads data from one or more physical units of the memory module 220 via the memory interface control circuit 213, and writes the read data into the host system 10 via the connection interface circuit 230. In this disclosure, the data management circuit 212, as one of multiple circuit modules, is configured with a bitmap parsing circuit for parsing a transmission bitmap when receiving a transmission data packet to determine whether at least one target circuit module includes the data management circuit 212. If at least one target circuit module includes a data management circuit 212, the data management circuit 212 obtains the corresponding target data from the transmission data of the transmission data packet and transmits the transmission data packet to the next circuit module. If at least one target circuit module does not include a data management circuit 212, the data management circuit 212 bypasses the transmission of the transmission data packet to the next circuit module.

[0044] It should be noted that in this disclosure, each of the multiple circuit modules is configured with a bitmap parsing circuit. The bitmap parsing circuit parses the transmission bitmap when receiving a transmission data packet to determine whether at least one target circuit module includes itself. Specifically, the bitmap parsing circuit reads the identifier bit corresponding to the circuit module in the transmission bitmap and performs corresponding operations based on the state of the identifier bit. If the identifier bit is valid, the bitmap parsing circuit determines that the circuit module is the target circuit module for the transmission data packet and controls the circuit module to obtain the corresponding target data from the transmission data of the transmission data packet. If the identifier bit is invalid, the bitmap parsing circuit determines that the circuit module is not the target circuit module for the transmission data packet and controls the circuit module to bypass the transmission data packet and pass it to the next circuit module.

[0045] In another embodiment, the processor 211 may also be configured with a bitmap parsing circuit (or execute a corresponding program module). When a source circuit module among multiple circuit modules generates local data and needs to transmit it to the processor 211, the source circuit module generates a local data packet, which includes a local transmission bitmap, in which the identifier bit corresponding to the processor 211 is set to an active state. When the processor 211 receives the local data packet, the bitmap parsing circuit in the processor 211 parses the local transmission bitmap to determine whether the processor 211 is the target of the local data packet, and accordingly retrieves the corresponding data from the local data packet. By configuring a bitmap parsing circuit in the processor 211, the processor 211 and multiple circuit modules can use a unified bitmap addressing mechanism for bidirectional data transmission.

[0046] In another embodiment, the data management circuit 212 may also be integrated into the processor 211. The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform write (also known as programming), read, or erase operations on the memory module 220. In this disclosure, the memory interface control circuit 213, as one of a plurality of circuit modules, is also configured with a bitmap parsing circuit (not shown) for parsing the transmission bitmap when receiving transmission data packets to determine whether at least one target circuit module includes the memory interface control circuit 213, and performing corresponding data acquisition or bypass transmission operations based on the determination result.

[0047] Furthermore, data to be written to memory module 220 is converted into a format acceptable to memory module 220 via memory interface control circuit 213. Specifically, if processor 211 needs to access memory module 220, processor 211 transmits a corresponding instruction sequence to memory interface control circuit 213 to instruct memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0048] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages) configured for the memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also called the logical-to-physical mapping table) to find the physical unit mapped to a logical unit (e.g., find the physical page mapped to a logical page; find the physical address mapped to a logical address), and the memory controller 210 can use the physical-to-logical address mapping table (also called the physical-to-logical mapping table) to find the logical unit mapped to a physical unit (e.g., find the logical page mapped to a physical page; find the logical address mapped to a physical address).

[0049] Buffer memory 214 is electrically connected to processor 211 and is used to temporarily store data and instructions from host system 10, data from memory module 220, and various system data for managing storage device 20. In this disclosure, buffer memory 214, as one of multiple circuit modules, is also configured with bitmap parsing circuitry to parse the transmission bitmap when receiving transmission data packets, in order to determine whether at least one target circuit module includes buffer memory 214, and to perform corresponding data acquisition or bypass transmission operations based on the determination result.

[0050] Furthermore, in one embodiment, the buffer memory 214 is also used to store the module location index table and load status information required by this disclosure. Specifically, the module location index table records the clockwise and counterclockwise transmission step sizes of each circuit module relative to the processor 211. The processor 211 can query the module location index table to determine the transmission direction. The load status information records the local load indicators of each circuit module, including buffer utilization or the number of pending data packets. The processor 211 can select the direction with the smaller cumulative load value as the transmission direction based on the load status information. In addition, the buffer memory 214 can also be used to store access count statistics, and the processor 211 can dynamically adjust the default transmission direction based on the access count.

[0051] The memory module 220 is electrically connected to the memory controller 210 (specifically, electrically connected to the memory interface control circuit 213) and is used to store user data sent by the host system 10. In this disclosure, the memory module 220 serves as a storage medium managed by the memory controller 210. The processor 211 in the memory controller 210 communicates with multiple circuit modules through a ring connection to realize data writing, reading, and erasing operations on the memory module 220.

[0052] In one embodiment, the memory cell structure of the memory module 220 can be understood as a multi-layered physical organization architecture. Specifically, the memory module 220 includes multiple chips, each chip has multiple planes, and each plane contains multiple physical blocks, each physical block consisting of multiple physical pages. It should be noted that this disclosure is not limited to the specific size of each physical page and logical page.

[0053] It is worth mentioning that, in one embodiment, each circuit module is internally configured with a buffer for temporarily storing transmitted data packets to support various data processing and flow control mechanisms in the ring connection. The buffer can be implemented as static random access memory (SRAM) or a register array, and its capacity can be configured according to the processing capability of the circuit module and the expected data flow.

[0054] The buffer performs multiple functions in the communication process of a ring connection. In data reception, when a circuit module receives a data packet from the ring connection, the data packet is first written into the buffer. The circuit module then reads the data packet from the buffer to perform operations such as bitmap parsing, data acquisition, and forwarding. In priority arbitration, when a circuit module faces multiple data packets to be forwarded simultaneously, lower-priority packets are temporarily stored in the buffer to wait. After higher-priority packets have been forwarded, the circuit module retrieves the lower-priority packets from the buffer and performs the forwarding operation.

[0055] The buffer capacity configuration affects the number of data packets that the circuit module can temporarily store and the overall system traffic carrying capacity. With a larger buffer capacity, the circuit module can temporarily store more data packets to be processed, and the ring connection can withstand higher instantaneous data traffic. With a smaller buffer capacity, the circuit module's hardware resource consumption is lower, but the backpressure mechanism may be triggered earlier under high traffic conditions. Those skilled in the art can select an appropriate buffer capacity configuration based on the application scenario and performance requirements of the memory controller 210.

[0056] In one embodiment, the buffer can be implemented using static random access memory (SRAM). SRAM stores data in a six- or eight-transistor cell structure, maintaining data content without periodic refresh, making it suitable for medium to large capacity buffer configurations. In another embodiment, the buffer can be implemented using a register array, which consists of multiple flip-flops. This array offers faster access speeds than SRAM and is suitable for small-capacity buffer configurations with high latency requirements. In yet another embodiment, the buffer can be configured as a first-in, first-out (FIFO) queue, allowing data to be read out sequentially in the order it was written, naturally supporting the sequential processing requirements of data packets. In yet another embodiment, the buffer can be implemented using a dual-port memory, providing two independent access ports, allowing the circuit module to simultaneously perform data reception and forwarding operations. Those skilled in the art can choose an appropriate implementation method based on the buffer's capacity requirements, access speed requirements, and hardware area limitations. This disclosure does not limit the specific hardware implementation of the buffer.

[0057] Figure 3 This is a flowchart illustrating a communication method for a memory controller according to an embodiment of this disclosure. Please refer to... Figure 3 The communication method for the memory controller provided in this disclosure is applicable to a memory controller 210 configured with a processor 211 and multiple circuit modules, wherein the multiple circuit modules and the processor 211 are connected in a ring via a single data path. The communication method for the memory controller includes steps S310 to S350.

[0058] First, in step S310, the relative positional relationship between the processor 211 and the multiple circuit modules in the ring connection is obtained through the processor 211. Specifically, the relative positional relationship describes the topological position of each circuit module relative to the processor 211 in the ring connection. In one embodiment, the relative positional relationship may include the arrangement order of each circuit module in the ring connection. In another embodiment, if the ring connection is a bidirectional ring topology, the relative positional relationship may further include the clockwise and counterclockwise transmission step sizes of each circuit module relative to the processor 211. The processor 211 may obtain the relative positional relationship during the initialization of the memory controller 210 and store the relative positional relationship in an internal register or buffer memory 214 for subsequent querying.

[0059] In step S320, the processor 211 sets a transmission bitmap in the data packet based on the relative positional relationship and at least one target circuit module of the data packet. Specifically, when the processor 211 needs to transmit data to one or more circuit modules among multiple circuit modules, the processor 211 first determines at least one target circuit module of the data packet, and then generates a transmission bitmap based on the relative positional relationship. The transmission bitmap is used to identify the target circuit module of the data packet, and each circuit module in the multiple circuit modules corresponds to an identifier bit in the transmission bitmap. The processor 211 sets the identifier bit corresponding to at least one target circuit module to a valid state (e.g., logic "1"), and sets the identifier bit corresponding to a non-target circuit module to an invalid state (e.g., logic "0"). Through the transmission bitmap, the processor 211 can flexibly implement various transmission modes such as unicast (single target), multicast (multiple targets), and broadcast (all targets).

[0060] In step S330, when the current circuit module among multiple circuit modules receives a data packet, the current circuit module parses the transmission bitmap to determine whether at least one target circuit module includes the current circuit module. Specifically, the current circuit module is configured with a bitmap parsing circuit, which reads the current identifier bit corresponding to the current circuit module in the transmission bitmap and determines whether the current circuit module is a target circuit module for the data packet based on the state of the current identifier bit. If the current identifier bit is valid, it is determined that at least one target circuit module includes the current circuit module. If the current identifier bit is invalid, it is determined that at least one target circuit module does not include the current circuit module.

[0061] In step S340, if at least one target circuit module includes the current circuit module, the current circuit module obtains the corresponding target data from the transmission data of the transmission data packet and transmits the transmission data packet to the next circuit module. Specifically, the transmission data packet typically includes a header and a data payload. The header includes a transmission bitmap, and the data payload includes the transmission data. The current circuit module identifies and extracts the target data corresponding to itself from the transmission data according to the transmission bitmap. After obtaining the target data, the current circuit module transmits the transmission data packet to the next circuit module in the ring connection, so that the transmission data packet continues to be passed in the ring connection to other possible target circuit modules.

[0062] In step S350, if at least one target circuit module does not include the current circuit module, the data packet is bypassed and transmitted to the next circuit module through the current circuit module. Specifically, the current circuit module does not perform data acquisition operations on the data packet, but directly forwards the data packet to the next circuit module in the ring connection. Through the bypass transmission mechanism, non-target circuit modules can quickly forward data packets, thereby reducing the processing delay of data packets at non-target circuit modules.

[0063] Through steps S310 to S350, the processor 211 can specify the target circuit module for transmitting data packets by setting a transmission bitmap. Each circuit module can autonomously determine and execute corresponding data acquisition or bypass transmission operations based on the transmission bitmap. The transmission data packets pass sequentially through each circuit module in the ring connection. The target circuit module acquires the corresponding target data from the transmission data packets, while non-target circuit modules bypass the transmission data packets, thereby realizing directional data transmission between the processor 211 and multiple circuit modules based on a single data path.

[0064] Figure 4 This is a schematic diagram illustrating the structure of a data packet transmitted according to an embodiment of this disclosure. Please refer to... Figure 4 In one embodiment, the Transmit Data Packet (TDP) is used to transmit data and control information in a ring connection between the processor 211 and multiple circuit modules. The TDP includes two main parts: a header (HD) and a payload (DPL). The header (HD) carries transmission control-related information, while the payload (DPL) carries the transmission data to be transmitted to the target circuit module.

[0065] In one embodiment, the packet header HD further includes a priority field PRT and a transmission bitmap TBM. The priority field PRT is used to indicate the transmission priority level of the transmitted data packet TDP. When the circuit module has multiple data packets to be transmitted simultaneously, the circuit module can parse the priority field PRT of each data packet and perform arbitration operation according to the priority level.

[0066] In one embodiment, a transmission bitmap (TBM) is used to identify the target circuit module of a transmission data packet (TDP). Before sending the transmission data packet TDP, the processor 211 sets the contents of the transmission bitmap (TBM) according to the relative positional relationships and at least one target circuit module. Figure 4 As shown, the expanded Transmission Bitmap (TBM) includes multiple flag bits (MB(1) to MB(N)), which are mapped to multiple circuit modules respectively. The bit width N of the Transmission Bitmap (TBM) corresponds to the number of multiple circuit modules.

[0067] Each flag bit has a valid state (e.g., "1") and an invalid state (e.g., "0"). When the processor 211 needs to transmit data to a specific target circuit module, the processor 211 sets the flag bit in the transmission bitmap TBM corresponding to the target circuit module to a valid state. After receiving the transmission data packet TDP, each circuit module reads the flag bit in the transmission bitmap TBM corresponding to itself through the bitmap parsing circuit, and determines whether it is the target circuit module of the transmission data packet TDP based on the state of the flag bit.

[0068] To mark the specific location of the target data, in other embodiments, the header HD further includes a data offset field (not shown). The data offset field is used to indicate the starting position of the current target data in the data payload DPL, and its initial value is set by the processor 211 (typically 0).

[0069] In one embodiment, the data payload DPL is used to carry the transmission data that the processor 211 intends to transmit to the target circuit module. Depending on the transmission mode, this disclosure provides a flexible data acquisition mechanism:

[0070] (1) In unicast or broadcast (same data) scenarios, the data payload DPL contains a single data segment, and all target circuit modules read the same data from the start position of the data payload DPL.

[0071] (2) In multicast (different data) scenarios, the data payload (DPL) contains multiple data segments arranged in sequence, each corresponding to a different target circuit module. In this case, the target circuit module uses the data offset field in the packet header (HD) to locate its own target data. Specifically, when the current circuit module determines itself as the target, it reads the target data from the data payload (DPL) based on the current data offset field. Subsequently, the current circuit module adds the length of the read data to the value of the data offset field to update the data offset field and updates the identifier bit in the transmission bitmap (TBM) corresponding to itself to an invalid state. Through this "read-update offset-clear bitmap" mechanism, when the next target circuit module receives the transmission data packet (TDP), it can accurately locate its corresponding data segment based on the updated data offset field, thereby enabling the distribution of multiple independent data sets carried by a single data packet.

[0072] It's worth noting that once the current circuit module confirms itself as the target and acquires data, it further executes a feedback and bitmap maintenance mechanism. Specifically, the current circuit module generates a response signal and sends it back to the processor to confirm the data reception status. Simultaneously, to avoid redundant processing and dynamically indicate the transmission progress, the current circuit module updates its own flag in the transmission bitmap to an invalid state. Subsequently, the current circuit module checks the updated transmission bitmap. If it finds that all flags in the transmission bitmap have become invalid, it means the data packet has been successfully delivered to all predetermined target circuit modules. In this case, the current circuit module will directly discard the data packet and stop passing it down, thus preventing invalid data from wasting bandwidth in the ring connection. Conversely, if there are still flags in the transmission bitmap that are in a valid state, it indicates that there are still downstream targets to be received, and the current circuit module will continue to forward the data packet to the next circuit module.

[0073] The following utilizes Figure 5 , Figure 6This section will explain in detail the management mechanism of the transmission bitmap disclosed herein.

[0074] Figure 5 This is a schematic diagram illustrating an example of a transmission bitmap and an update process according to embodiments of this disclosure. Please refer to... Figure 5 In one embodiment, it is assumed that the memory controller 210 is configured with three circuit modules (i.e., N=3), namely circuit module A ( Figure 5 If we refer to them as module A, circuit module B, and circuit module C, then the transmission bitmap includes three flag bits, which correspond to circuit module A, circuit module B, and circuit module C in order from least significant bit to most significant bit. It should be noted that the order of the three flag bits from least significant bit to most significant bit corresponds to the respective circuit module based on the transmission direction. For example, Figure 5 In the example, the transmission direction is from circuit module A to circuit module B, and then to circuit module C.

[0075] In one embodiment, in a unicast scenario, processor 211 only needs to transmit data to a single target circuit module. As shown in the transmission bitmap TBM1, if processor 211 wants to transmit data to circuit module B, processor 211 sets the transmission bitmap to the binary value "010", where the flag bit corresponding to circuit module B is set to the valid state "1", and the flag bits corresponding to circuit modules A and C are set to the invalid state "0". When the transmission data packet is transmitted in the ring connection, circuit modules A and C parse the transmission bitmap and determine that they are not the target circuit modules, so they bypass the transmission data packet; circuit module B parses the transmission bitmap and determines that it is the target circuit module, so it obtains the corresponding target data from the transmission data packet.

[0076] In one embodiment, in a multicast scenario, processor 211 needs to transmit data to multiple, but not all, circuit modules. As shown in the transmission bitmap TBM2, if processor 211 wants to transmit data to circuit module A and circuit module C simultaneously, processor 211 sets the transmission bitmap to the binary value "101", where the flag bits corresponding to circuit modules A and C are set to the valid state "1", and the flag bit corresponding to circuit module B is set to the invalid state "0". Through the multicast mechanism, processor 211 can transmit data to multiple target circuit modules simultaneously using a single transmission data packet, without having to send an independent transmission data packet for each target circuit module.

[0077] In one embodiment, in a broadcast scenario, processor 211 needs to transmit data to all circuit modules. As shown in the transmission bitmap TBM3, processor 211 sets the transmission bitmap to the binary value "111", and all three flag bits are set to the valid state "1". When the transmission data packet is transmitted in the ring connection, circuit module A, circuit module B, and circuit module C all determine themselves as the target circuit module and obtain the corresponding target data from the transmission data packet.

[0078] Please refer to Figure 5 In region B50 of the transmission bitmap, during multicast or broadcast scenarios, the transmission bitmap is dynamically updated as data packets pass through each target circuit module. Taking a broadcast scenario as an example, the bitmap update process is explained as follows: initially, the value of the transmission bitmap TBM30 is "111", indicating that circuit modules A, B, and C are all target circuit modules.

[0079] As shown by arrow A51, when the data packet passes through circuit module A, the position identifier of circuit module A is "001" (the first bit is "1"). After parsing the transmission bitmap TBM30, circuit module A determines that it is the target circuit module (because the first bit of the transmission bitmap TBM30 is "1"). Therefore, it obtains the target data from the transmitted data, generates a response signal and sends it to processor 211, and updates the identifier bit corresponding to circuit module A to an invalid state "0". The updated value of the transmission bitmap TBM31 becomes "110". After detecting the transmission bitmap TBM31, circuit module A finds that there is still an identifier bit in a valid state, so it transmits the data packet to the next circuit module, namely, circuit module B.

[0080] As shown by arrow A52, when the data packet passes through circuit module B, the position identifier of circuit module B is "010" (the second bit is "1"). After parsing the transmission bitmap TBM31, circuit module B determines that it is the target circuit module (because the second bit of transmission bitmap TBM31 is "1"). Therefore, it obtains the target data from the transmitted data, generates a response signal and sends it to processor 211, and updates the identifier bit corresponding to circuit module B to an invalid state "0". The updated value of transmission bitmap TBM32 becomes "100". After detecting transmission bitmap TBM32, circuit module B finds that there is still an identifier bit in a valid state, so it transmits the data packet to the next circuit module, namely, circuit module C.

[0081] As shown by arrow A53, when the data packet passes through circuit module C, the position identifier of circuit module C is "100" (the third bit is "1"). After parsing the transmission bitmap TBM32, circuit module C determines itself to be the target circuit module (because the third bit of transmission bitmap TBM32 is "1"). Therefore, it obtains the target data from the transmitted data, generates a response signal and sends it to processor 211, and updates the identifier bit corresponding to circuit module C to an invalid state "0". The updated value of transmission bitmap TBM33 becomes "000". After detecting the updated transmission bitmap TBM33, circuit module C finds that multiple identifier bits are in an invalid state, indicating that all target circuit modules of the transmitted data packet have completed the data acquisition operation. Then, as shown by arrow A54, circuit module C cancels the step of transmitting the data packet to the next circuit module. The transmission of the data packet is terminated at circuit module C and discarded.

[0082] Through the bitmap update and transmission termination mechanism described above, the transmission data packet stops being transmitted in the ring connection after it has been delivered to all target circuit modules. Each target circuit module confirms the data reception status to the processor 211 through a response signal, and the processor 211 can then grasp the transmission progress and completion status of the transmission data packet.

[0083] Figure 6 A flowchart illustrating the circuit module processing transmitted data packets according to embodiments of this disclosure is provided. Please refer to... Figure 6 In one embodiment, when the current circuit module among multiple circuit modules receives a data packet in a ring connection, the current circuit module... Figure 6 The process shown is for processing transmitted data packets.

[0084] In step S610, the current circuit module receives the transmission data packet. Specifically, the transmission data packet is passed from the previous circuit module or processor 211 to the current circuit module along the ring connection. The current circuit module receives the transmission data packet through the input port connected to the ring connection and temporarily stores the transmission data packet in the receive buffer inside the current circuit module for subsequent processing.

[0085] In step S620, the current circuit module determines whether the target includes the current circuit module. Specifically, the bitmap parsing circuit in the current circuit module reads the transmission bitmap in the header of the transmission data packet and extracts the current identifier bit corresponding to the current circuit module from the transmission bitmap. The bitmap parsing circuit determines whether at least one target circuit module includes the current circuit module based on the state of the current identifier bit. If the current identifier bit is in a valid state, the bitmap parsing circuit determines that the target circuit module includes the current circuit module, and the process proceeds to step S630. If the current identifier bit is in an invalid state, the bitmap parsing circuit determines that the target circuit module does not include the current circuit module, and the process directly proceeds to step S660.

[0086] In step S630, the current circuit module obtains the corresponding target data from the transmitted data packet and updates the current identifier bit in the transmission bitmap corresponding to the current circuit module to an invalid state. Specifically, the current circuit module identifies and extracts the target data corresponding to the current circuit module from the data payload of the transmitted data packet according to the transmission bitmap (and the data offset field mentioned in the foregoing embodiments, if applicable). After the target data is extracted, it is stored in the data register inside the current circuit module for subsequent functional operations. At the same time, the current circuit module updates the current identifier bit in the transmission bitmap from a valid state to an invalid state to indicate that the current circuit module has completed the data acquisition operation.

[0087] In step S670, the current circuit module generates a response signal and sends it to the processor 211. The response signal is used to notify the processor 211 that the current circuit module has successfully received the transmitted data packet and acquired the target data. In one embodiment, the response signal may include the identification information and reception status information of the current circuit module, and the processor 211 can confirm the completion status of data transmission based on the response signal. Step S670 may be executed in parallel with step S630 or after step S630, and this disclosure does not limit this.

[0088] In step S640, the current circuit module checks whether all the flag bits in the updated transmission bitmap are invalid. Specifically, the current circuit module performs a logical check (e.g., a logical OR operation) on all the flag bits in the transmission bitmap. If the operation result indicates that all flag bits are invalid, it means that all target circuit modules of the transmitted data packet have completed the data acquisition operation, and the process proceeds to step S650. If the detection result shows that there are still flag bits in a valid state, the process proceeds to step S660.

[0089] In step S650, the current circuit module completes the current ring transmission task and discards the transmitted data packet. Since all the flag bits in the transmission bitmap are invalid, the transmitted data packet does not need to continue being transmitted in the ring connection. The current circuit module cancels the step of transmitting the transmitted data packet to the next circuit module and removes the transmitted data packet from the receive buffer. Through the transmission termination mechanism, the transmitted data packet stops being transmitted after being delivered to all target circuit modules, avoiding invalid looping of the transmitted data packet in the ring connection.

[0090] In step S660, the current circuit module forwards the transmission data packet to the next circuit module. Since there are still valid flag bits in the transmission bitmap, it indicates that other target circuit modules have not yet completed data acquisition operations for the transmission data packet. The current circuit module sends the updated transmission data packet to the next circuit module through the output port connected to the ring connection, so that the transmission data packet continues to be passed to other target circuit modules in the ring connection.

[0091] It is worth noting that if the determination result of step S620 is that the target circuit module does not include the current circuit module, the current circuit module directly executes step S660, bypassing the transmission data packet to the next circuit module. During the bypass transmission process, the current circuit module does not perform data acquisition operations on the transmission data packet, nor does it perform update operations on the transmission bitmap; the content of the transmission data packet remains unchanged. Through the bypass transmission mechanism, non-target circuit modules can quickly forward transmission data packets, thereby reducing the dwell time of transmission data packets at non-target circuit modules.

[0092] It should be noted that the specific hardware implementation of bypass transmission can employ a low-latency pass-through mechanism. Specifically, the current circuit module is configured with a bypass control circuit. When the header of the transmission data packet arrives at the input port, the bitmap parsing circuit immediately decodes and compares it. Once it determines that it is not the target node, the bypass control circuit activates the pass-through path, directly guiding the data stream from the input port to the output port. In this mode, subsequent data payloads do not need to wait for complete reception or be stored in an internal deep buffer, but instead flow through the current circuit module in a "receive and send simultaneously" manner. This design significantly reduces the transmission latency at each hop, ensuring efficient flow of transmission data packets in long-distance ring links.

[0093] In one embodiment, the ring connection is configured as a unidirectional ring topology to achieve the simplest hardware architecture. In this configuration, the processor is connected to both the beginning and end of the unidirectional ring topology, designating the beginning as an output and the end as an input. Data packets are restricted to flow sequentially through each circuit module in a fixed transmission direction (e.g., clockwise only). This unidirectional transmission mechanism applies not only to downlink transmissions from the processor to the circuit modules but also to uplink responses from the circuit modules to the processor.

[0094] Specifically, when a source circuit module among multiple circuit modules needs to send a response data packet to the processor (e.g., returning read data or status confirmation), the source circuit module sends the response data packet following the fixed transmission direction described above. The response data packet is not transmitted in reverse; instead, it continues downstream along the fixed direction, sequentially passing through other circuit modules located between the source circuit module and the processor input, and finally returning to the processor. This design ensures that all data flows require only unidirectional drive at the physical layer, thereby simplifying the design of the interface circuitry and reducing the need for wiring resources.

[0095] In another embodiment, the ring connection can be configured as a bidirectional ring topology. In a bidirectional ring topology, the processor 211 is connected to both the beginning and end of the bidirectional ring topology, allowing the processor 211 to selectively send data packets in a clockwise or counterclockwise direction. In the bidirectional ring topology configuration, the step of the processor 211 obtaining the relative positional relationship specifically includes obtaining the clockwise and counterclockwise transmission step sizes of each of the plurality of circuit modules relative to the processor 211. The clockwise transmission step size represents the number of circuit modules that must be traversed from the processor 211 to reach the circuit module in a clockwise direction, and the counterclockwise transmission step size represents the number of circuit modules that must be traversed from the processor 211 to reach the circuit module in a counterclockwise direction. Figure 1B Taking the configuration shown as an example, if the memory controller 210 is configured with four circuit modules in sequence as circuit module A, circuit module B, circuit module C, and circuit module N, then the clockwise transmission step size of circuit module A relative to processor 211 is 1, and the counterclockwise transmission step size is 3. The clockwise transmission step size of circuit module B relative to processor 211 is 2, and the counterclockwise transmission step size is 2. Processor 211 stores the clockwise and counterclockwise transmission step sizes of each circuit module in a module location index table in buffer memory 214 for subsequent lookup when selecting the transmission direction.

[0096] In another embodiment, before sending the data packet, the processor 211 determines whether to use a clockwise or counterclockwise direction as the transmission direction based on the clockwise and counterclockwise transmission step sizes of each circuit module relative to the processor 211. Specifically, after the processor 211 identifies at least one target circuit module for the data packet, it queries the module location index table for the clockwise and counterclockwise transmission step sizes of each target circuit module, and evaluates the path length for sending the data packet along the clockwise and counterclockwise directions accordingly, selecting the direction with the shorter path length as the transmission direction. After determining the transmission direction, the processor 211 sets at least one target identifier bit in the transmission bitmap corresponding to at least one target circuit module based on the transmission direction. In a unicast scenario, the processor 211 sets the target identifier bit corresponding to a single target circuit module to a valid state. In a multicast scenario, the processor 211 sets multiple target identifier bits corresponding to multiple target circuit modules to a valid state. By using a transmission direction selection mechanism, the processor 211 can select the direction with a smaller transmission step size to send transmission data packets, thereby reducing the number of circuit modules that the transmission data packets need to pass through to reach the target circuit module.

[0097] Figure 7A This is a flowchart illustrating path cost calculation according to embodiments of the present disclosure. Figure 7B This is a schematic diagram illustrating the determination of the transmission direction according to an embodiment of the present disclosure.

[0098] Please refer to Figure 7A In one embodiment, when the ring connection is configured as a bidirectional ring topology, the processor 211 performs a transmission direction selection process before sending transmission data packets to determine whether to use a clockwise or counterclockwise direction as the transmission direction.

[0099] In step S710, processor 211 determines the target circuit module for transmitting the data packet. Based on the nature and destination of the data to be transmitted, processor 211 selects at least one target circuit module from multiple circuit modules. In a unicast scenario, processor 211 selects a single target circuit module; in a multicast scenario, processor 211 selects multiple target circuit modules.

[0100] In step S720, processor 211 obtains the clockwise and counterclockwise transmission step sizes of each target circuit module. Specifically, processor 211 can query a pre-stored module location index table (e.g., stored in buffer memory 214) to obtain the topological distance of each target circuit module relative to processor 211. The clockwise transmission step size represents the number of circuit modules that must be traversed from processor 211 in a clockwise direction to reach the target circuit module, while the counterclockwise transmission step size represents the number required in a counterclockwise direction.

[0101] In step S730, processor 211 calculates the clockwise path cost and the counterclockwise path cost. Especially in multicast scenarios, data packets need to be delivered sequentially to multiple target circuit modules. Therefore, the total path length required for the data packets to reach all target circuit modules is actually determined by the "farthest" target circuit module. Based on this, processor 211 selects the maximum value among the clockwise transmission step sizes of at least one target circuit module as the clockwise path cost, and selects the maximum value among the counterclockwise transmission step sizes of at least one target circuit module as the counterclockwise path cost.

[0102] In step S740, the processor 211 selects the direction corresponding to the smaller path cost (clockwise or counterclockwise) as the transmission direction. If the clockwise path cost is less than the counterclockwise path cost, the processor 211 determines the transmission direction to be clockwise; otherwise, it determines it to be counterclockwise. If the two are equal, the processor 211 can select according to the default settings. After determining the transmission direction, the processor 211 sets at least one target identifier bit in the transmission bitmap corresponding to at least one target circuit module based on the direction, and starts the transmission process.

[0103] To illustrate the algorithm more intuitively, please refer to [link / reference]. Figure 7B Assume that the memory controller 210 is configured with four circuit modules, namely circuit module A (CM1), circuit module B (CM2), circuit module C (CM3) and circuit module D (CM4) in sequence, and the processor 211 needs to perform multicast transmission to circuit module B and circuit module D (i.e., the multicast target is B and D).

[0104] like Figure 7B As shown in the upper part and region B71, if transmitted clockwise, the step size of circuit module B is 2, and the step size of circuit module D is 4. Processor 211 calculates the clockwise path cost as max(2, 4) = 4 steps. This means that the data packet must go through 4 hops to cover all targets.

[0105] like Figure 7B As shown in the lower half and region B72, if transmitted counterclockwise, the step size of circuit module D is 1, and the step size of circuit module B is 3. Processor 211 calculates the counterclockwise path cost as max(1, 3) = 3 steps. This means that the data packet only needs 3 hops to cover all targets.

[0106] In summary, since the cost of the counter-clockwise path (3 steps) is less than the cost of the clockwise path (4 steps), the processor 211 ultimately chooses the counter-clockwise direction as the transmission direction. This decision mechanism ensures that the transmitted data packets can cover all multicast targets with the shortest total path, thereby significantly reducing communication latency and bus occupancy.

[0107] In another embodiment, the processor 211 can dynamically adjust the default transmission direction based on the access frequency of each circuit module. Specifically, the processor 211 counts the number of times each of the multiple circuit modules is accessed within a preset period, which can be configured as a fixed time length or a fixed number of data packets. The processor 211 dynamically adjusts the default transmission direction based on the number of accesses, placing the circuit modules with more accesses at positions with smaller transmission steps relative to the processor 211 in the default transmission direction. For example, if circuit module A is accessed 50 times, circuit module B is accessed 30 times, circuit module C is accessed 10 times, and circuit module N is accessed 10 times in the preset period, the processor 211 determines that circuit module A has the most accesses. If the clockwise transmission step size of circuit module A relative to the processor 211 is 1 and the counterclockwise transmission step size is 3, then the clockwise direction places circuit module A at a position with a smaller transmission step size, and the processor 211 adjusts the default transmission direction to the clockwise direction. When the processor 211 needs to send data packets and there is no specific path selection requirement, the processor 211 sends the data packets along the default transmission direction. Through a dynamic adjustment mechanism, the processor 211 can optimize the default transmission direction according to the actual access mode, thereby statistically shortening the average transmission path length.

[0108] It is worth mentioning that, in another embodiment, when the ring connection is configured as a bidirectional ring topology, the processor 211 can further optimize the selection of the transmission direction based on a "load balancing" strategy. Since the processing capabilities or instantaneous workloads of each circuit module differ, optimal transmission latency may not be achieved solely based on physical distance (step size). Therefore, this disclosure introduces a dynamic path selection mechanism based on load status.

[0109] Specifically, multiple circuit modules continuously monitor their local load metrics. These metrics quantify the current workload of the modules, including buffer utilization (i.e., the ratio of used space to total capacity) or the number of pending data packets. Each circuit module generates load status information containing its own identifier and current load metric values, and sends it back to the processor 211 via a ring connection. Upon receiving this information, the processor 211 updates its maintained load status records, thereby gaining a real-time understanding of the load distribution across all nodes in the network.

[0110] When a data packet needs to be sent, the processor 211 not only considers the location of the target circuit module, but also calculates the "cumulative load value" in both clockwise and counterclockwise directions. The cumulative load value refers to the sum of the local load indices of all circuit modules that the data packet must pass through along the way before reaching the target.

[0111] Processor 211 compares the cumulative load values ​​in two directions and selects the direction with the smaller value as the transmission direction. For example, suppose memory controller 210 is configured with four circuit modules, and processor 211 needs to send data to circuit module C. If the data packet passes through circuit module A (load 30%) and circuit module B (load 50%) in a clockwise direction, the cumulative load value in the clockwise direction is 80%. If the data packet passes through circuit module D (load 20%) in a counterclockwise direction, the cumulative load value in the counterclockwise direction is 20%. In this case, processor 211 will choose the counterclockwise direction to avoid congested nodes A and B. This mechanism effectively reduces the queuing time of data packets at intermediate nodes and improves the overall communication efficiency.

[0112] In another embodiment, when a source circuit module among multiple circuit modules needs to send a reply data packet to the processor 211, the source circuit module can autonomously select the reply transmission direction. Specifically, during the initialization phase, the source circuit module obtains local location information from the processor 211, including the clockwise and counterclockwise transmission step sizes of the source circuit module relative to the processor 211. When the source circuit module generates a reply data packet and needs to send it to the processor 211, the source circuit module compares its own clockwise and counterclockwise transmission step sizes relative to the processor 211 and selects the direction with the smaller transmission step size as the reply transmission direction. For example, if the clockwise transmission step size of the source circuit module relative to the processor 211 is 3 and the counterclockwise transmission step size is 1, the source circuit module selects the counterclockwise direction as the reply transmission direction and sends the reply data packet to the processor 211 in the counterclockwise direction. Through the reply path selection mechanism, the source circuit module can select the direction with the smaller transmission step size to send the reply data packet, thereby shortening the number of circuit modules that the reply data packet needs to pass through to reach the processor 211 and reducing the transmission time of the reply data packet in the ring connection.

[0113] Figure 8 This is a flowchart illustrating fault tolerance and direction switching according to embodiments of this disclosure. Please refer to... Figure 8 In one embodiment, when the ring connection is configured as a bidirectional ring topology, the processor 211 utilizes the redundancy of the bidirectional paths to achieve fault tolerance. When one path cannot transmit data normally due to a circuit module failure or connection interruption, the processor 211 can automatically switch to the other path to maintain communication.

[0114] Specifically, in steps S810 and S820, processor 211 sends a transmission data packet along the currently determined transmission direction (clockwise or counterclockwise) and then initiates timeout monitoring. Timeout monitoring aims to wait for and acknowledge a response signal from at least one target circuit module. For example, processor 211 may maintain an internal timeout timer that starts when the transmission data packet is sent and triggers a timeout event when a preset time threshold is reached. The preset time threshold can be configured based on the size of the loop connection and the expected transmission delay (e.g., configured as twice the loop transmission period) to avoid misjudgment.

[0115] In step S830, the processor 211 continuously monitors whether a response signal is received within a preset time threshold. In a multicast scenario, the processor 211 can be configured, according to a strategy, to wait for responses from all target circuit modules or only for responses from key target circuit modules.

[0116] If a response signal is successfully received within the preset time threshold, the process proceeds to step S840. At this point, the processor 211 ends timeout monitoring, resets the timeout timer, and determines that the communication was successful, after which subsequent data transmission tasks can continue to be executed.

[0117] Conversely, if the timeout timer reaches the preset time threshold and no response signal is received, the process proceeds to step S850. At this time, the processor 211 determines that there is a link failure in the current transmission direction. The lack of a response signal may mean that a node on the transmission path has failed or the line is broken.

[0118] Following step S860, processor 211 triggers a direction switching mechanism to set the transmission direction to the opposite direction. Specifically, if the original direction was clockwise, it switches to counterclockwise; and vice versa. After the switch is completed, the process returns to step S810 (e.g., ...). Figure 8 (As indicated by the "Retransmit" arrow on the left), the processor 211 retransmits the transmission data packet along the new transmission direction. Through this mechanism, the memory controller 210 can automatically bypass faulty nodes or breakpoints, significantly improving the reliability and availability of the system.

[0119] Figure 9 This is a schematic diagram illustrating the transmission of local data packets for each circuit module according to embodiments of this disclosure. Please refer to... Figure 9 In one embodiment, in addition to the processor 211 acting as the initiator to send data, each circuit module in the ring connection also has the ability to actively communicate. This mechanism allows the circuit modules to actively generate and send local data packets when generating local data (such as status updates, interrupt requests, or direct memory access data), without passively waiting for polling instructions from the processor 211.

[0120] like Figure 9As shown in "Scenario 1" on the left, when a source circuit module (SCM) among multiple circuit modules needs to transmit data or a response to the processor 211, the source circuit module (SCM) generates a local data packet (LDP). The local data packet (LDP) contains a local transport bitmap and local data. It is worth noting that the structure of the local transport bitmap is similar to the aforementioned transport bitmap, but its identifier bits are mapped not only to other circuit modules but also to the processor 211. In this scenario, the source circuit module (SCM) sets the identifier bit in the local transport bitmap corresponding to the processor 211 to a valid state (e.g., "1"). Subsequently, as shown by arrow A91, the source circuit module (SCM) sends the local data packet (LDP) to the next node in the ring connection. The local data packet (LDP) is transmitted sequentially along the ring, with non-target circuit modules along the way selecting bypass transmission after parsing the bitmap, until the data packet reaches the processor 211. After receiving the packet, the processor 211 can obtain the local data uploaded by the source circuit module (SCM).

[0121] In another embodiment, this disclosure also supports direct communication between circuit modules (Peer-to-Peer, P2P). For example... Figure 9 As shown in "Scenario 2" on the right, when local data generated by the source circuit module SCM needs to be transmitted to another target circuit module TCM (instead of processor 211), the source circuit module SCM also generates a local data packet LDP, but at this time, the flag bit corresponding to the target circuit module TCM in the local transmission bitmap is set to the valid state. As shown by arrow A92, the local data packet LDP is transmitted in the ring connection until it is intercepted and processed by the target circuit module TCM.

[0122] like Figure 9 As described in section B91 below, the source circuit module (SCM) can directly exchange data with the target circuit module (TCM) through the aforementioned mechanism. Crucially, the local data packet (LDP) does not need to be uploaded to the processor 211 before being forwarded; instead, it flows directly on the hardware path. This design not only significantly shortens the data transmission path and reduces transmission latency but also effectively alleviates the data forwarding burden on the processor 211, freeing up its computing resources. Furthermore, based on the flexibility of the bitmap, the source circuit module (SCM) can even simultaneously set the flag bits corresponding to both the processor 211 and the target circuit module (TCM) to active status, thereby achieving "one-to-many" local multicast transmission.

[0123] Figure 10 This is a schematic diagram illustrating priority arbitration according to an embodiment of this disclosure. Please refer to... Figure 10Since all data packets in a ring connection share a single data path, transmission congestion may occur when multiple data packets converge at the same node simultaneously. To address this, this disclosure introduces a priority arbitration mechanism that uses a priority field in the data packets to indicate the urgency of the data (e.g., control commands are set to high priority, and batch data is set to low priority).

[0124] like Figure 10 As shown, the current circuit module B101 (which can be a processor or any circuit module) may face multiple transmission requests simultaneously. For example, as shown by arrow A101, transmission data packet TDP1 enters the current circuit module B101 with its priority field indicating "high priority"; at the same time, as shown by arrow A102, transmission data packet TDP2 also enters the module, but its priority is "low priority".

[0125] In this scenario, the current circuit module B101 performs the parsing and arbitration operations shown in area S101. Specifically, the module parses the priority field of each data packet and determines the forwarding order based on the priority. The arbitration result shows that TDP1 has a higher priority than TDP2. Therefore, as shown by arrow A104, the current circuit module B101 prioritizes forwarding the data packet TDP1 to the next node in the ring connection. Conversely, as shown by arrow A103, the lower-priority data packet TDP2 is temporarily moved into the buffer B111 configured inside the module to wait. TDP2 will only be retrieved and continue to be transmitted when the high-priority data transmission is completed or the bus is idle.

[0126] Through this mechanism, the system can ensure that critical tasks (such as interrupt response and real-time control) are not blocked by non-real-time transmission of large amounts of data, thereby guaranteeing the system's real-time response capability under limited bandwidth resources.

[0127] It should be noted that, in another embodiment, the value of the priority field can be set by the processor 211 when generating the transmission data packet according to the type and urgency of the data to be transmitted. The priority field can be configured with multiple bits to support the differentiation of multiple priority levels. For example, the priority field can be configured with 2 bits, corresponding to four priority levels: binary value "11" represents the highest priority, binary value "10" represents high priority, binary value "01" represents medium priority, and binary value "00" represents low priority. The processor 211 can pre-configure a priority mapping table according to the data type, and the priority mapping table defines the priority level corresponding to each data type.

[0128] Taking a typical application scenario of the memory controller 210 as an example, interrupt response instructions and error handling instructions are configured with the highest priority because they involve system stability; read instructions are configured with high priority because they directly affect the waiting time of the host system 10; write instructions are configured with medium priority because they can be temporarily stored using a buffer mechanism; and status query instructions and log recording data are configured with low priority because their timeliness requirements are lower. When the processor 211 generates a transmission data packet, the processor 211 queries the priority mapping table according to the type of transmission data and writes the corresponding priority level into the priority field of the transmission data packet. In another embodiment, the processor 211 can also dynamically adjust the configuration in the priority mapping table according to the current system load or specific application requirements to adapt to different operating scenarios.

[0129] It is worth mentioning that, in another embodiment, to further optimize chip layout and communication efficiency, the ring connection can adopt a "grouped serial" architecture. Specifically, multiple circuit modules are divided into several circuit module groups based on the similarity of their functional properties or the closeness of their data interaction. The processor is no longer simply connected sequentially to individual circuit modules, but rather these circuit module groups are connected in series through a large ring structure. Within each circuit module group, member modules still maintain serial connections. This architecture allows modules with close physical locations or high logical functional coupling to be grouped together, thereby shortening the physical trace distance between high-frequency interaction modules.

[0130] For example, a memory controller can be divided into a "front-end interface group" and a "back-end storage group." The front-end interface group includes host interface controllers (such as PCIe or SATA interfaces), data cache controllers, and encryption engines. These modules are mainly responsible for high-speed data interaction and security processing with the host system, and they need to frequently exchange cached data and key information. The back-end storage group includes multiple flash channel controllers and corresponding error correction code (ECC) engines. These modules focus on NAND flash read / write control and error correction, and there is a very high frequency of raw data flow between them.

[0131] In this architecture, the processor first connects to the front-end interface group via a ring connection. The data flow sequentially passes through the host interface, cache controller, and encryption engine, then enters the back-end storage group, passing through each flash channel controller and ECC engine, and finally returns to the processor. When the flash channel controller in the back-end storage group needs to use the ECC engine for data verification, the aforementioned direct inter-module communication mechanism allows data packets to complete the interaction only by transmitting a short distance within the back-end storage group, without needing to detour to the front-end interface group or the processor. This grouping design not only optimizes the chip's physical routing but also effectively isolates data traffic from different functional domains, improving the overall system's parallel processing efficiency.

[0132] In another embodiment, the ring connection can be configured with a backpressure mechanism to prevent data loss. In a ring communication architecture, if a circuit module is unable to receive data in a timely manner due to insufficient processing power or a full buffer, continuous data transmission from upstream nodes may lead to data loss or overwriting. The backpressure mechanism allows the data flow in the ring connection to be adaptively adjusted according to the receiving capabilities of each circuit module.

[0133] Specifically, each of the multiple circuit modules continuously monitors the utilization rate of its local receive buffer. When the buffer utilization rate reaches a preset backpressure threshold, the circuit module generates a backpressure signal and transmits it to the previous circuit module in the reverse direction of the loop connection. The circuit module receiving the backpressure signal suspends forwarding data packets downstream and temporarily stores the data packets to be forwarded in its local buffer. When the buffer utilization rate of the downstream circuit module drops below the release threshold, the circuit module generates a backpressure release signal to notify the upstream circuit module to resume forwarding operations. The backpressure threshold and release threshold can be configured according to the buffer capacity and system response requirements; for example, the backpressure threshold can be configured to 80% of the buffer capacity, and the release threshold can be configured to 50% of the buffer capacity.

[0134] Taking a real-world application scenario of the memory controller 210 as an example, when the memory interface control circuit 213 is performing a large number of flash memory write operations, its processing capacity is occupied, and the receive buffer gradually accumulates. When the buffer utilization rate reaches the backpressure threshold, the memory interface control circuit 213 sends a backpressure signal to the upstream data management circuit 212, and the data management circuit 212 suspends forwarding new data packets to the memory interface control circuit 213. After the flash memory write operation is completed and the buffer utilization rate decreases, the memory interface control circuit 213 sends a backpressure release signal, and the data management circuit 212 resumes normal forwarding. Through the backpressure mechanism, the ring connection can avoid data loss caused by buffer overflow.

[0135] In another embodiment, the transmitted data packet can be configured with a sequence number field to support the detection and filtering of duplicate data packets. In a fault-tolerant scenario, the processor 211 switches the transmission direction and retransmits the transmitted data packet after detecting a timeout. If the original transmitted data packet has already been received and processed by some target circuit modules, the retransmission operation may cause the same data to be processed repeatedly, resulting in data consistency issues. The sequence number mechanism enables the target circuit modules to identify and discard duplicate transmitted data packets.

[0136] Specifically, a sequence number field is added to the header of the transmitted data packet, and the processor 211 assigns an incrementing sequence number to each transmitted data packet. Each of the multiple circuit modules maintains a processed sequence number record, recording the maximum sequence number of the transmitted data packet that has successfully acquired the target data. When a circuit module receives a transmitted data packet and determines that it is the target circuit module, the circuit module compares the sequence number of the transmitted data packet with the maximum processed sequence number. If the sequence number of the transmitted data packet is less than or equal to the maximum processed sequence number, the circuit module determines that the transmitted data packet is a duplicate data packet and discards it, no longer acquiring the target data repeatedly; if the sequence number of the transmitted data packet is greater than the maximum processed sequence number, the circuit module acquires the target data normally and updates the maximum processed sequence number.

[0137] Furthermore, processor 211 can perform selective retransmission optimization. When processor 211 retransmits a data packet due to a timeout, it determines which target circuit modules have successfully received data based on the received response signals. Processor 211 removes the successfully received data segments from the retransmitted data packet and updates the transmission bitmap to include only the flag bits corresponding to the target circuit modules that have not yet been successfully received. For example, if the original data packet targets circuit modules A, B, and C, and processor 211 has received the response signal from circuit module A but not from circuit modules B and C, then the retransmitted data packet only contains the data segments sent to circuit modules B and C, and only the flag bits corresponding to circuit modules B and C are set to the valid state in the transmission bitmap.

[0138] In another embodiment, processor 211 can combine multiple data packets to be sent into a single batch transmission data packet to reduce transmission overhead. Each time processor 211 sends a transmission data packet, it needs to set a transmission bitmap and transmit it via a ring connection. When processor 211 needs to continuously send data to multiple target circuit modules in the same direction, sending them one by one would incur multiple bitmap setups and transmission overheads. The batch transmission mechanism can combine multiple data packets into a single transmission data packet, thereby reducing the number of transmissions.

[0139] Specifically, the processor 211 maintains a transmission queue and periodically checks the data to be transmitted in the queue. When multiple data items are to be transmitted in the transmission queue and the target circuit modules of these data items are located in the same transmission direction, the processor 211 merges these data items into a batch transmission data packet. The batch transmission data packet includes a batch transmission bitmap and multiple data segments. The identifier bits corresponding to each target circuit module in the batch transmission bitmap are all set to a valid state. Each data segment contains the target circuit module identifier and the corresponding transmission data. After parsing the batch transmission bitmap and determining that it is a target circuit module, each circuit module extracts the data segment corresponding to itself from the batch transmission data packet according to the target circuit module identifier in the data segment.

[0140] Taking a real-world application scenario of the memory controller 210 as an example, suppose the processor 211 has three data entries to be sent in its transmission queue, which are to be sent to circuit modules A, B, and C respectively, with all three circuit modules located in a clockwise direction. If sent one by one, the processor 211 would need to send three independent data packets, performing three bitmap settings and three transmission operations. Using a batch transmission mechanism, the processor 211 merges the three data entries into a single batch transmission data packet, sets the batch transmission bitmap to "111", and the data payload contains three data segments. The batch transmission data packet is transmitted clockwise, and circuit modules A, B, and C sequentially extract their respective data segments from the batch transmission data packet.

[0141] In another embodiment, the circuit module can be configured with a delayed acquisition mechanism to avoid delays in forwarding data packets during busy states. When a circuit module is busy, if it is the target circuit module for transmitting data packets, the conventional process requires acquiring the target data before performing the forwarding operation. This processing order may delay the delivery of data packets to subsequent target circuit modules. The delayed acquisition mechanism allows busy circuit modules to prioritize forwarding operations and acquire the target data only after the local busy state is resolved.

[0142] Specifically, each of the multiple circuit modules maintains a local busy status flag, which indicates whether the circuit module is currently executing an uninterruptible processing task. When a circuit module receives a transmission data packet, and the transmission bitmap indicates that it is the target circuit module, but its local busy status flag is true, the circuit module temporarily stores the transmission data packet in its local buffer and first performs a forwarding step to transmit the transmission data packet to the next circuit module in the ring connection. After the local busy status is cleared, the circuit module then reads the temporarily stored transmission data packet from its local buffer, obtains the corresponding target data, and performs subsequent processing.

[0143] Taking a practical application scenario of the memory controller 210 as an example, assume that the processor 211 performs multicast transmission to the data management circuit 212 and the memory interface control circuit 213, and the transmission data packets pass through the data management circuit 212 and the memory interface control circuit 213 in sequence. When the transmission data packet arrives at the data management circuit 212, the data management circuit 212 is busy performing a mapping table update operation. The data management circuit 212 temporarily stores the transmission data packet in its local buffer and immediately forwards the transmission data packet to the memory interface control circuit 213. The memory interface control circuit 213 can receive the transmission data packet and obtain the target data in a timely manner, unaffected by the busy state of the data management circuit 212. After the data management circuit 212 completes the mapping table update operation, it then obtains the target data from the local buffer.

[0144] In another embodiment, a priority aging mechanism can be configured for transmitted data packets to avoid starvation of low-priority data packets. In a priority arbitration mechanism, when high-priority data packets continuously enter the ring connection, low-priority data packets may be unable to get forwarded for an extended period due to being constantly preempted by high-priority packets, resulting in starvation. The priority aging mechanism allows low-priority data packets to automatically have their priority increased after passing through a certain number of circuit modules in the ring connection.

[0145] Specifically, a dwell count field is added to the header of the transmitted data packet. This dwell count field records the number of circuit modules the transmitted data packet traverses within the ring connection. When a transmitted data packet is forwarded by a circuit module to the next circuit module, the preceding circuit module increments the value of the dwell count field by one. Each of the multiple circuit modules checks the value of the dwell count field before forwarding the transmitted data packet. When the value of the dwell count field exceeds a preset aging threshold, the circuit module updates the priority field of the transmitted data packet to a higher priority level. The preset aging threshold can be configured according to the size of the ring connection and system response requirements; for example, it can be configured to be twice the total number of circuit modules.

[0146] Taking a real-world application scenario of the memory controller 210 as an example, assuming the memory controller 210 is configured with four circuit modules and a preset aging threshold of 8, the processor 211 sends a low-priority status query data packet with an initial dwell count field value of 0. As the status query data packet is transmitted in the ring connection, it is repeatedly buffered due to the continuous influx of high-priority read instruction data packets. After the status query data packet has passed through 8 circuit modules (potentially involving multiple loops), the dwell count field value reaches the preset aging threshold of 8, and the circuit modules elevate the priority of the status query data packet from low to high priority. The elevated status query data packet can then compete with other high-priority data packets for forwarding opportunities, thereby gaining forwarding access and being delivered to the target circuit module.

[0147] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the various steps of the communication method of the memory controller described above. The computer-readable storage medium can be a non-transitory computer-readable storage medium, such as a read-only memory, random access memory, optical disc read-only memory, magnetic tape, flash memory, hard disk, or solid-state drive. The computer program includes computer-readable instructions that, when executed by the processor 211, cause the memory controller 210 to perform the communication method of the memory controller described in the above embodiments.

[0148] The preset conditions, numerical configurations, and specific parameters described in the above embodiments are merely illustrative examples. Those skilled in the art can adjust them according to actual application needs, and this disclosure does not impose any restrictions on them.

[0149] Regarding the configuration of the transmission bitmap, the above embodiment uses the example of a valid state corresponding to a binary value "1" and an invalid state corresponding to a binary value "0". However, the definitions of valid and invalid states can be interchanged according to hardware design requirements. In another embodiment, a valid state can be defined as a binary value "0" and an invalid state can be defined as a binary value "1". The bitmap parsing circuit of each circuit module executes the corresponding judgment logic according to the interchanged definitions. Furthermore, the mapping relationship between each identifier bit in the transmission bitmap and each circuit module can also be adjusted according to the system configuration, and is not limited to the sequential arrangement from low to high bits described in the above embodiment.

[0150] Regarding the configuration of the priority field, the above embodiment uses a 2-bit priority field corresponding to four priority levels as an example. However, the number of bits in the priority field and the number of priority levels can be adjusted according to the complexity of the application scenario. In application scenarios with low priority differentiation requirements, the priority field can be configured with 1 bit to distinguish between high and low priority levels; in application scenarios with high priority differentiation requirements, the priority field can be configured with 3 bits or more bits to support eight or more priority levels. The mapping relationship between each data type and priority level can also be configured according to the system operating characteristics, and is not limited to the specific mapping method described in the above embodiment.

[0151] Regarding the configuration of timeout monitoring, the preset time threshold in the above embodiments can be configured according to the scale of the ring connection, the length of the transmitted data packet, and the system clock frequency. In a configuration with a small number of circuit modules, the preset time threshold can be configured to a shorter time length; in a configuration with a large number of circuit modules, the preset time threshold can be configured to a longer time length to accommodate the time required for the transmitted data packet to pass through more circuit modules. The preset time threshold can also be configured in a dynamic adjustment mode, whereby the processor 211 dynamically calculates an appropriate timeout threshold based on the location of the target circuit module and the current system load.

[0152] Regarding the calculation of load status, the above embodiments use buffer utilization and the number of pending data packets as examples of local load indicators. However, the definition of local load indicators can be expanded according to the system monitoring capabilities. In another embodiment, local load indicators may include other quantifiable load parameters such as the processing latency of a circuit module, the forwarding queue depth, or the number of data packets processed per unit time. The calculation method of cumulative load value can also be adjusted according to application requirements. For example, a weighted summation method can be used to assign different weights to the load of different circuit modules, or a maximum value method can be used to take the circuit module with the highest load on the path as the representative of the cumulative load value.

[0153] Regarding the configuration of the dynamic adjustment mechanism, the preset period in the above embodiments can be configured as a fixed time length or a fixed number of transmitted data packets. The length of the preset period can be adjusted according to the frequency of changes in the system access mode. In application scenarios where the access mode changes rapidly, the preset period can be configured as a shorter time length so that the default transmission direction can quickly adapt to changes; in application scenarios where the access mode is relatively stable, the preset period can be configured as a longer time length to avoid the overhead caused by frequent adjustments.

[0154] Regarding the topology configuration of ring connections, the above embodiments illustrate unidirectional and bidirectional ring topologies as examples. However, the specific configuration of the ring connection can be selected based on chip area limitations and communication requirements. In application scenarios with strict chip area limitations and low fault tolerance requirements, a unidirectional ring topology can be used to reduce the number of connections; in application scenarios with high requirements for transmission resilience and fault tolerance, a bidirectional ring topology can be used to provide path selection and direction switching capabilities. The clockwise and counterclockwise directions described in the above embodiments are defined as relative concepts. Those skilled in the art can define any direction as clockwise or counterclockwise based on the actual hardware layout.

[0155] In summary, the communication method and memory controller provided in this disclosure effectively solve the wiring congestion and power consumption problems caused by the increase in the number of circuit modules by reconstructing the underlying interconnect architecture and communication protocol.

[0156] At the connectivity architecture level, this disclosure replaces the traditional star topology with a ring topology. Compared to the star topology, which requires establishing N independent paths for N modules, the processor only needs to maintain the connection interfaces at the beginning and end of the ring topology. This topology change directly reduces the total number of data connections within the chip, reduces the difficulty of routing and the consumption of wiring resources, thereby significantly reducing the chip area and overall power consumption in physical implementation.

[0157] At the communication mechanism level, this disclosure utilizes a transmission bitmap to achieve flexible and efficient addressing. The processor only needs to set the bitmap to support unicast, multicast, and broadcast modes, without needing to send independent instructions to each target. The circuit module autonomously completes parsing, data interception, and bitmap updating based on the bitmap, and automatically terminates transmission after confirming that all targets have received the data. This "autonomous flow and automatic termination" mechanism greatly reduces the processor's control burden and avoids invalid data idling in the loop.

[0158] At the transmission strategy level, this disclosure provides intelligent path selection and fault tolerance capabilities by combining a bidirectional ring topology. The system can dynamically select the optimal transmission direction based on physical distance (path cost) or real-time congestion level (load status) to minimize transmission latency. Simultaneously, once a link failure is detected, the system can automatically switch to the opposite direction, ensuring communication reliability even in the event of partial node failure.

[0159] Furthermore, this disclosure introduces a priority arbitration mechanism and a direct inter-module communication mechanism. The former ensures that critical data such as control commands are not blocked, guaranteeing the system's real-time response capability; the latter allows circuit modules to proactively initiate transmissions and directly exchange data with other modules without processor relay, further freeing up processor computing resources and improving data exchange efficiency.

[0160] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A communication method for a memory controller, applicable to a memory controller configured with a processor and multiple circuit modules, characterized in that, include: The relative positional relationship between the processor and the plurality of circuit modules in the ring connection is obtained through the processor. The processor sets the transmission bitmap in the transmission data packet according to the relative positional relationship and at least one target circuit module of the transmission data packet; When the current circuit module among the plurality of circuit modules receives the transmission data packet, the current circuit module parses the transmission bitmap to determine whether the at least one target circuit module includes the current circuit module; If the at least one target circuit module includes the current circuit module, the corresponding target data is obtained from the transmission data of the transmission data packet through the current circuit module, and the transmission data packet is transmitted to the next circuit module. If the at least one target circuit module does not include the current circuit module, the data packet is transmitted to the next circuit module via a bypass through the current circuit module.

2. The communication method for the memory controller according to claim 1, characterized in that, The transmission bitmap includes multiple identifier bits respectively mapped to the plurality of circuit modules, wherein if the at least one target circuit module includes the current circuit module, the method further includes: The current circuit module generates a response signal and sends it to the processor. The current identifier bit corresponding to the current circuit module in the transmission bitmap is updated to an invalid state through the current circuit module. The current circuit module detects whether all of the multiple flag bits in the updated transmission bitmap are in an invalid state. If all the flag bits in the updated transmission bitmap are in the invalid state, then the step of transmitting the transmission data packet to the next circuit module is cancelled; and If the updated transmission bitmap still contains a valid flag bit, then the step of transmitting the transmission data packet to the next circuit module is performed.

3. The communication method for the memory controller according to claim 2, characterized in that, The ring connection is a unidirectional ring topology. The processor is connected to the beginning and end of the unidirectional ring topology, wherein the beginning serves as the output of the processor and the end serves as the input of the processor. The data packets are transmitted sequentially through the multiple circuit modules along a fixed transmission direction.

4. The communication method for the memory controller according to claim 3, characterized in that, When the source circuit module among the plurality of circuit modules needs to send a reply data packet to the processor, the reply data packet is transmitted to the processor by sequentially passing through other circuit modules located between the source circuit module and the input terminal of the processor along the fixed transmission direction.

5. The communication method for the memory controller according to claim 2, characterized in that, The ring connection is a bidirectional ring topology, and the processor is connected to the first and last ends of the bidirectional ring topology. The step of obtaining the relative positional relationship of the ring connection between the processor and the plurality of circuit modules includes: Obtain the clockwise and counterclockwise transmission step size of each of the plurality of circuit modules relative to the processor.

6. The communication method for the memory controller according to claim 5, characterized in that, The method further includes: The processor determines, based on the clockwise and counterclockwise transmission step sizes of each of the plurality of circuit modules relative to the processor, whether to use a clockwise or counterclockwise direction as the transmission direction to send the data packet; and The processor sets at least one target identifier bit in the transmission bitmap, corresponding to at least one target circuit module, based on the transmission direction.

7. The communication method for a memory controller according to claim 6, characterized in that, The step of determining whether to use the clockwise direction or the counterclockwise direction as the transmission direction to send the data packet based on the clockwise transmission step size and the counterclockwise transmission step size of each of the plurality of circuit modules relative to the processor includes: The maximum value among the clockwise transmission step sizes of the at least one target circuit module is selected as the clockwise path cost; The maximum value among the counterclockwise transmission step sizes of the at least one target circuit module is selected as the counterclockwise path cost; Based on the clockwise path cost and the counterclockwise path cost, the transmission direction is determined to be either the clockwise direction or the counterclockwise direction.

8. The communication method for a memory controller according to claim 6, characterized in that, The method further includes: After the processor sends the transmission data packet along the transmission direction, it initiates timeout monitoring; and If no response signal is received from the at least one target circuit module within a preset time threshold, the processor determines that there is a link failure in the transmission direction, sets the transmission direction to the opposite direction, and retransmits the transmission data packet.

9. The communication method for a memory controller according to claim 6, characterized in that, The method further includes: The processor counts the number of times each of the multiple circuit modules is accessed within a preset period; and The processor dynamically adjusts the default transmission direction based on the number of accesses, so that the circuit module with a higher number of accesses is located in a position with a smaller transmission step size relative to the processor in the default transmission direction.

10. The communication method of the memory controller according to claim 5, characterized in that, The method further includes: When a source circuit module among the plurality of circuit modules needs to send a reply data packet to the processor, the source circuit module, based on the clockwise and counterclockwise transmission step sizes relative to the processor, selects the direction with the smaller transmission step size as the reply transmission direction; and The response data packet is sent to the processor via the source circuit module along the response transmission direction.

11. The communication method of the memory controller according to claim 1, characterized in that, The transmitted data packet also includes a priority field, and the method further includes: When the current circuit module has multiple data packets to be transmitted, the priority field of each data packet is parsed; and Arbitration is performed according to the priority level indicated by the priority field, prioritizing the forwarding of data packets with higher priority levels, and temporarily storing data packets with lower priority levels in a buffer configured in the current circuit module.

12. The communication method for a memory controller according to claim 1, characterized in that, The method further includes: When a source circuit module among the plurality of circuit modules generates local data and needs to transmit it to the processor, a local data packet is generated through the source circuit module. This local data packet includes a local transmission bitmap and the local data, wherein the identifier bit in the local transmission bitmap corresponding to the processor is set to an active state. The local data packet is sent from the source circuit module to the next circuit module in the ring connection for transmission to the processor via the ring connection.

13. The communication method for a memory controller according to claim 12, characterized in that, When the local data generated by the source circuit module needs to be transmitted to a target circuit module among the plurality of circuit modules, the method further includes: The source circuit module sets the flag bit corresponding to the target circuit module in the local transmission bitmap to a valid state; and The local data packet is sent from the source circuit module to the next circuit module in the ring connection, so as to be transmitted to the target circuit module via the ring connection.

14. The communication method for a memory controller according to claim 12, characterized in that, The ring connection is a bidirectional ring topology, and the method further includes: The local location information of each of the plurality of circuit modules is pre-configured, wherein the local location information includes the clockwise transmission step size and the counterclockwise transmission step size of the circuit module relative to the processor and other circuit modules; and When the source circuit module sends the local data packet, it selects the direction with the smaller transmission step size as the local transmission direction based on the local location information.

15. The communication method for a memory controller according to claim 5, characterized in that, The method further includes: Through each of the plurality of circuit modules, local load indicators are monitored and load status information is generated, wherein the local load indicators include buffer utilization or the number of pending data packets. The processor receives and records the load status information of each circuit module. The processor calculates the cumulative load value of each circuit module in the clockwise direction and the cumulative load value of each circuit module in the counterclockwise direction based on the load status information; and The processor selects the direction with the smaller cumulative load value as the transmission direction to send the data packet.

16. A memory controller, characterized in that, include: processor; as well as Multiple circuit modules are connected to the processor in a ring via a single data path; The processor is used to obtain the relative positional relationship between the processor and the plurality of circuit modules in the ring connection, and to set the transmission bitmap in the transmission data packet according to the relative positional relationship and at least one target circuit module of the transmission data packet; Each of the plurality of circuit modules is configured with a bitmap parsing circuit, wherein when the current circuit module among the plurality of circuit modules receives the transmission data packet, the current circuit module parses the transmission bitmap to determine whether the at least one target circuit module includes the current circuit module; If the at least one target circuit module includes the current circuit module, the current circuit module obtains the target data from the transmission data of the transmission data packet and transmits the transmission data packet to the next circuit module; If the at least one target circuit module does not include the current circuit module, the current circuit module bypasses the transmission data packet to the next circuit module, wherein the memory controller is used to perform the communication method of the memory controller according to any one of claims 1 to 15.

Images