A chip simulation system and optimization method
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING TSINGMICRO INTELLIGENT TECH CO LTD
- Filing Date
- 2025-12-31
- Publication Date
- 2026-05-26
Smart Images
Figure CN122086597A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic system-level modeling and simulation technology, and in particular to a chip simulation system and optimization method. Background Technology
[0002] As the scale and complexity of System on Chip (SoC) continue to increase, adopting the Electronic System Level (ESL) approach to conduct system-level modeling and verification early in the design process has become an important means to reduce chip design complexity and shorten development cycles.
[0003] The SystemC simulator, a commonly used ES modeling and verification tool, is based on a simulation kernel with a Discrete-Event (DE) mechanism. It simulates the parallel behavior of complex on-chip systems by cooperating and scheduling multiple SystemC threads.
[0004] However, the traditional SystemC scheduling mechanism allows only a single SystemC thread to run at any given time, thus forcing the entire simulation process to proceed serially. When faced with computationally intensive architectures such as heterogeneous multi-core processors and Neural Processing Units (NPUs), this scheduling mode struggles to fully utilize the host machine's multi-core hardware resources, resulting in a significant decrease in simulation efficiency. This fails to meet the high-throughput, high-precision, and high-efficiency simulation requirements of large-scale on-chip systems during functional verification and performance analysis.
[0005] This section is intended to provide background or context for the embodiments of the invention set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention
[0006] This invention provides a chip simulation system to achieve multi-threaded parallel scheduling and efficient execution across multi-core CPUs for target transactions, thereby breaking through the performance bottleneck of single-threaded serial scheduling in traditional SystemC simulation and improving the simulation speed and resource utilization of complex on-chip systems in the system-level verification stage.
[0007] This chip simulation system runs on the host machine and includes: a transmitter, a target, and an interconnect port;
[0008] The sending end invokes multiple first System C threads to send multiple target transactions to the target end through the interconnect port;
[0009] The target end invokes multiple second System C threads to receive the corresponding target transactions; the second System C threads forward the target transactions to the corresponding parallel threads respectively, and call the recovery function to wake up the parallel threads; each of the parallel threads executes the corresponding target transactions in parallel on multiple CPU cores of the host machine;
[0010] The transmitting end and the target end adjust their performance indicators according to the feedback signal at a preset interval frequency in order to shorten the simulation time.
[0011] In some embodiments, the second System C thread is further configured to call a startup function to create a corresponding parallel thread; and call a stop function for the corresponding parallel thread to recycle the parallel thread.
[0012] In some embodiments, the second System C thread is bound to each of the parallel threads via a handle.
[0013] In some embodiments, after the parallel thread completes the target transaction, the second System C thread is further used to call a suspension function to control the parallel thread to enter a waiting state.
[0014] This invention also provides an optimization method for a chip simulation system, which enables multi-threaded parallel scheduling of target transactions and efficient execution across multi-core CPUs, thereby breaking through the performance bottleneck of single-threaded serial scheduling in traditional SystemC simulation and improving the simulation speed and resource utilization of complex on-chip systems in the system-level verification stage.
[0015] The optimization method for this chip simulation system, applied to the aforementioned chip simulation system, includes:
[0016] Create multiple System C threads, and call each System C thread to forward the received target transaction to the corresponding parallel thread;
[0017] The corresponding parallel thread is awakened by calling the recovery function of each System C thread. Each parallel thread changes from a waiting state to a ready state. The host operating system allocates each parallel thread in the ready state to each CPU core of the host machine for parallel execution.
[0018] The performance indicators are adjusted according to the preset interval frequency to shorten the simulation time.
[0019] In some embodiments, adjusting the performance indicators according to a preset interval frequency includes:
[0020] Performance metrics are acquired at preset intervals; wherein, the performance metrics include: average throughput, number of sub-parallel threads, average latency, and data block size.
[0021] The number of sub-parallel threads is dynamically adjusted based on the average throughput of the current period and the average throughput of the previous period.
[0022] The data block size is dynamically adjusted based on the average latency of the current period and the average latency of the previous period.
[0023] In some embodiments, dynamically adjusting the number of sub-parallel threads based on the average throughput of the current period and the average throughput of the previous period includes: increasing the number of sub-parallel threads when the average throughput of the current period is higher than a first preset threshold ratio of the average throughput of the previous period; decreasing the number of sub-parallel threads when the average throughput of the current period is lower than a second preset threshold ratio of the average throughput of the previous period; and linearly increasing the number of sub-parallel threads by a first preset step size when the average throughput of the current period is between the first threshold ratio and the second threshold ratio.
[0024] The method of dynamically adjusting the data block size based on the average latency of the current period and the average latency of the previous period includes: increasing the data block size when the average latency of the current period is lower than a third preset threshold ratio of the average latency of the previous period; decreasing the data block size when the average latency of the current period is higher than a fourth preset threshold ratio of the average latency of the previous period; and linearly increasing the data block size according to a second preset step size when the average latency of the current period is between the third threshold ratio and the fourth threshold ratio.
[0025] In some embodiments, if the product of the number of sub-parallel threads and the data block size is greater than a preset secure content window size, the data block size is re-determined based on the secure content window size and the number of sub-parallel threads.
[0026] In some embodiments, the method further includes:
[0027] Obtain the data transmission delay and data processing delay of the parallel threads;
[0028] If the difference between the data processing delay and the data transmission delay is greater than a first preset value, the number of sub-parallel threads is increased;
[0029] If the difference between the data transmission delay and the data processing delay is greater than a second preset value, the data block size is increased.
[0030] This invention also provides a computer program product, which includes a computer program that, when executed by a processor, implements the optimization method of the chip simulation system described above.
[0031] The chip simulation system and optimization method provided in this invention employ a hierarchical structure of sender and target ends within the chip simulation system running on the host machine. Transaction interaction is achieved through interconnect ports. Upon receiving a target transaction, the SystemC thread on the target end can distribute it to multiple parallel threads and schedule each parallel thread to execute in parallel across multiple CPU cores on the host machine. This overcomes the limitation of traditional SystemC discrete event scheduling, which can only execute a single thread at a time. By processing target transactions in parallel within a multi-core processing environment, the execution latency of target transactions can be significantly shortened, improving the parallel processing capability and hardware resource utilization of the virtual on-chip system during simulation. This allows for more efficient completion of system-level functional verification and performance analysis of the on-chip system, thereby enhancing the simulation performance of the chip simulation system. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:
[0033] Figure 1 This is a schematic diagram of the chip simulation system in an embodiment of the present invention;
[0034] Figure 2 This is a schematic diagram of the simulation results of the chip simulation system in an embodiment of the present invention;
[0035] Figure 3 This is a flowchart illustrating an optimization method for a chip simulation system according to an embodiment of the present invention;
[0036] Figure 4 This is a flowchart illustrating the optimization method of the chip simulation system in another embodiment of the present invention;
[0037] Figure 5 This is a flowchart illustrating the optimization method of the chip simulation system in another embodiment of the present invention;
[0038] Figure 6 This is a flowchart illustrating the optimization method of the chip simulation system in another embodiment of the present invention;
[0039] Figure 7 This is a flowchart illustrating the optimization method of a chip simulation system in another embodiment of the present invention. Detailed Implementation
[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with relevant laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant means, and the acquisition, storage, use, and processing of user information have been authorized and agreed upon by the customer.
[0041] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.
[0042] To address the issue of low simulation efficiency in heterogeneous multi-core system-on-chip (SoC) systems due to the inability of existing SystemC simulators to schedule threads serially and fully utilize the multi-core computing resources of the host machine, this invention provides a chip simulation system and its optimization method capable of implementing parallel transaction processing on a multi-core CPU. This chip simulation system creates and binds multiple parallel threads (PTs) within the SystemC thread on the target side. Upon receiving a target transaction, it synchronously wakes up these parallel threads, allocating them to multiple CPU cores on the host machine for parallel execution, thus overcoming the limitations of the SystemC single-thread scheduling mechanism. Simultaneously, by incorporating a dynamic adjustment mechanism for performance indicators such as throughput, latency, number of parallel threads, and data block size, the number of parallel threads and data block size can be adaptively optimized, thereby achieving efficient simulation of complex SoCs and improving simulation performance during the system-level verification phase.
[0043] like Figure 1 As shown, the chip emulation system is started in the host machine. The chip emulation system runs as a process on the host machine. The chip emulation system includes: an initiator, a target, and a connect bus.
[0044] The sending end invokes multiple first System C threads to send multiple target transactions to the target end through the interconnect port.
[0045] The target end invokes multiple second System C threads to receive the corresponding target transaction. Each second System C thread forwards the target transaction to its corresponding parallel thread and calls a recovery function to synchronously wake up the parallel thread. Each parallel thread executes the corresponding target transaction in parallel across multiple CPU cores of the host machine.
[0046] The transmitting and receiving ends adjust their performance indicators according to the preset interval frequency based on the feedback signal in order to shorten the simulation time.
[0047] According to the above embodiments, by adopting a hierarchical structure of sender and target in the chip simulation system running on the host machine, and realizing transaction interaction through interconnection ports, the SystemC thread on the target end can distribute the target transaction to multiple parallel threads after receiving it, and schedule each parallel thread to be executed in parallel on multiple CPU cores of the host machine. This breaks through the limitation of traditional SystemC discrete event scheduling, which can only execute a single thread at a time. By processing the target transaction in parallel in a multi-core processing environment, the execution latency of the target transaction can be significantly shortened, improving the parallel processing capability and hardware resource utilization of the virtual on-chip system during simulation. This allows the system-level functional verification and performance analysis of the on-chip system to be completed more efficiently, thereby improving the simulation performance of the chip simulation system.
[0048] In this embodiment of the invention, after the chip emulation system starts, it sequentially creates multiple functional modules (Intellectual Property, IP) of a virtual on-chip system in the host machine. These functional modules include a transmitting end functional module and a target end functional module. The transmitting end functional module can be an ARM processor (Advanced RISC-Machine Processor), a RISC-V processor, a DMA controller (Direct Memory Access Controller), or a neural processing unit, etc. The target end functional module can be a computing unit, a memory controller, a memory, and an accelerator, etc.
[0049] After creating the functional modules for both the sending and target ends, the chip simulation system configures the corresponding TLM (Transaction-Level Modeling Interface) for each module. The system then establishes a connection between the sending and target TLM interfaces via interconnect ports, enabling the sending module to send target transactions to the target module.
[0050] When creating the sending and target functional modules in the chip simulation system, each functional module registers its corresponding SystemC thread (SystemC-THREAD) with the SystemC kernel in its constructor.
[0051] The SystemC thread of the sending module initiates multiple requests and encapsulates each request into a corresponding target transaction. The sending SystemC thread then sends each target transaction to the target SystemC thread via the interconnect port.
[0052] In some embodiments, the second System C thread is also used to call a startup function to create a corresponding parallel thread. The second System C thread is the System C thread of the target functional module.
[0053] In this embodiment of the invention, each SystemC thread of the target functional module is used to call the launch function to create parallel threads. The SystemC thread of the target functional module can create one parallel thread or multiple parallel threads. After the parallel threads are created, each parallel thread is in a waiting state. These parallel threads are standard operating system threads, and their operation depends entirely on the operating system's thread scheduling mechanism, and is not constrained by the SystemC emulator's internal scheduling mechanism.
[0054] According to the above embodiments, by creating parallel threads from the SystemC threads of the target functional module and enabling each parallel thread to run independently in the host operating system, the limitations of single-threaded execution and non-preemptive scheduling in traditional SystemC simulators are overcome. This allows computationally intensive target transactions to fully utilize the multi-core computing resources of the host machine to achieve parallel processing, thereby significantly improving the running efficiency of on-chip system simulation and system-level verification capabilities.
[0055] In some embodiments, the second System C thread is bound to a parallel thread one by one via a handle.
[0056] In this embodiment of the invention, after a parallel thread is created in the SystemC thread of the target functional module, each SystemC thread of the target functional module stores the pointer of the corresponding parallel thread as a handle, so that each parallel thread establishes a unique binding relationship with the corresponding SystemC thread. This binding relationship can be one SystemC thread corresponding to one parallel thread, or one SystemC thread corresponding to multiple parallel threads; the invention is not limited to this.
[0057] According to the above embodiments, by storing pointers to parallel threads in the SystemC thread of the target functional module and establishing one-to-one or one-to-many binding relationships, each SystemC thread can precisely manage its corresponding parallel thread, thereby achieving deterministic distribution and scheduling control of target transactions to parallel threads. This method improves the flexibility and scalability of thread management.
[0058] In some embodiments, each SystemC thread of the target functional module receives the target transaction sent by each SystemC thread of the sending functional module. After receiving the target transaction, each SystemC thread of the target functional module allocates the target transaction to the parallel thread bound to it and calls the Resume function to wake up the parallel thread, so that the parallel thread switches from the waiting state to the ready state.
[0059] After each parallel thread is awakened, it is scheduled by the host machine's operating system to run in parallel on multiple CPU cores of the host machine, so that each parallel thread can process its corresponding target task in parallel.
[0060] Each parallel thread is used to execute the computational tasks or data transfer operations contained in the target transaction. After a parallel thread completes the processing of the target transaction, it updates the status field and the corresponding result data of the target transaction to indicate that the target transaction has been completed.
[0061] For example, suppose the target functional module has three SystemC threads ( , and ) respectively received the target transaction , and ,Right now Receive target transaction , Receive target transaction , Receive target transaction .
[0062] , and The recovery function is called to wake up the corresponding parallel thread. , and .
[0063] In parallel threads , and Once awakened, the target task is scheduled by the host machine's operating system to be executed in parallel on different CPU cores of the host machine.
[0064] Assumption The execution time is , The execution time is , The execution time is The total simulation execution time is .
[0065] like Figure 2 As shown, the multiple CPU cores of the host machine are scheduled by the host operating system during operation, and each CPU core can execute different parallel threads in parallel. Therefore, when functional modules execute simulation tasks, the total simulation execution time no longer increases linearly with the number of functional modules, but is determined by the parallel thread with the longest execution time, thereby significantly reducing the overall simulation time and improving the efficiency of parallel simulation.
[0066] For example, the execution time of the parallel thread corresponding to functional module IP0 is... The execution time of the parallel thread corresponding to functional module IP1 is The execution time of the parallel thread corresponding to functional module IP2 is ... Functional module IP N-1 The corresponding execution time of the parallel thread is Functional module IP N The corresponding execution time of the parallel thread is Assume that the execution time of each parallel thread satisfies The total simulation time for the entire simulation cycle depends on the parallel thread with the longest execution time, i.e., the total simulation time is... .
[0067] According to the above embodiments, multiple SystemC threads in the simulation system are used to receive and distribute target transactions, while multiple parallel threads bound to them run independently under the multi-threaded scheduling mechanism of the host operating system. By utilizing the multi-core processing power of the host machine, the parallel threads can execute in parallel across multiple CPU cores, thereby overcoming the serialization limitations imposed by the global time-order execution and non-preemptive scheduling model in traditional SystemC simulations. This achieves parallel processing of simulation tasks that originally needed to be executed sequentially on a single-threaded timeline, significantly improving the execution efficiency and scalability of the simulation system.
[0068] In some embodiments, after the parallel thread completes the target transaction, the second System C thread is also used to call a suspension function to control the parallel thread to enter a waiting state.
[0069] In this embodiment of the invention, when each parallel thread completes the execution of the corresponding target transaction and no new target transaction is detected, each SystemC thread of the target-side functional module calls the Suspend function to make the corresponding parallel thread enter a waiting state.
[0070] According to the above embodiments, the above method can maintain the binding relationship between SystemC threads and parallel threads while pausing the parallel threads during idle periods, thereby avoiding unnecessary CPU resource occupation and improving the operating efficiency and resource utilization of the simulation system.
[0071] In some embodiments, the second System C thread is also used to call the stop function of the corresponding parallel thread through a handle in order to reclaim the parallel thread.
[0072] In this embodiment of the invention, after the chip simulation system finishes simulation, the target functional module calls the corresponding stop function in its destructor through the pre-stored parallel thread handle to terminate the parallel threads that are in the running state or in the waiting state. This allows the CPU resources occupied by the parallel threads to be reclaimed in a timely manner, thereby avoiding the generation of zombie threads and ensuring that subsequent simulation tasks can start normally.
[0073] According to the above embodiments, the SystemC thread has control over the parallel thread and can manage the execution state of the parallel thread through the start function, suspend function, resume function and stop function. This ensures that the creation and execution process of the parallel thread is within the controllable range of the chip simulation system, thereby improving the security and predictability of the chip simulation system in terms of task scheduling and resource management.
[0074] This application provides an optimization method for a chip emulation system, applied to the aforementioned chip emulation system. This optimization method is based on the same inventive concept as the chip emulation system in one embodiment of this application, and the principle of solving the problem is similar. Therefore, the implementation of the optimization method is the same as that of the chip emulation system in one embodiment of this application, and repeated details will not be described again. The terms "unit" or "module" used below can refer to a combination of software and / or hardware that implements a predetermined function. Although the system described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.
[0075] The optimization method of this chip simulation system is implemented by the aforementioned chip simulation system itself. For example... Figure 3 As shown, the optimization method for the chip simulation system includes steps 301 to 303.
[0076] Step 301: Create multiple System C threads and call each System C thread to forward the received target transaction to the corresponding parallel thread.
[0077] Step 302: Each System C thread calls the recovery function to wake up the corresponding parallel thread. Each parallel thread changes from the waiting state to the ready state, so that the host operating system can allocate each parallel thread in the ready state to each CPU core of the host machine for parallel execution.
[0078] Step 303: Adjust the performance indicators according to the preset interval frequency to shorten the simulation time.
[0079] According to the above embodiments, through the above optimization method, the target task is distributed to parallel threads by multiple SystemC threads, and after the parallel threads are awakened, they are scheduled by the host operating system to different CPU computing cores for parallel processing. This breaks through the serial execution limitation of traditional SystemC simulation, enabling computationally intensive tasks to make full use of multi-core hardware resources, and significantly improving the execution efficiency and overall parallel processing capability of the chip simulation system.
[0080] In this embodiment of the invention, after the chip emulation system is started, it sequentially creates multiple functional modules of a virtual on-chip system in the host machine. These functional modules include a transmitting end functional module and a target end functional module. The optimization method of the chip emulation system described above is applied to the transmitting end functional module and / or the target end functional module.
[0081] The functional modules of the sending end and the functional modules of the target end register their corresponding SystemC threads with the SystemC kernel in their constructors.
[0082] Each SystemC thread in the sending module initiates multiple requests and encapsulates each request into a corresponding target transaction. Each SystemC thread in the sending module then sends each target transaction to its corresponding SystemC thread in the target module via the interconnect port.
[0083] Each SystemC thread in the target-side functional module calls the startup function to create a parallel thread. After the parallel thread is created, each parallel thread enters a waiting state. Each SystemC thread in the target-side functional module receives the target transaction sent by each SystemC thread in the sending-side functional module. Upon receiving the target transaction, each SystemC thread in the target-side functional module assigns the target transaction to its bound parallel thread and calls the recovery function to wake up the parallel thread, causing the parallel thread to switch from the waiting state to the ready state.
[0084] After being awakened, each parallel thread is scheduled by the host operating system to run in parallel across multiple CPU cores on the host machine, allowing each thread to process its corresponding target transaction in parallel. Each parallel thread executes the computational tasks or data transfer operations contained in the target transaction.
[0085] The functional modules of the sending end and / or the functional modules of the target end acquire the performance indicators of the current statistical period at a preset interval frequency, and adjust the number of parallel threads and the data block size of the next statistical period according to the performance indicators of the current period, so as to shorten the total simulation time.
[0086] In some embodiments, such as Figure 4 As shown, step 303 includes steps 401 to 403.
[0087] Step 401: Periodically acquire performance metrics at preset intervals. These performance metrics include: average throughput, number of sub-parallel threads, average latency, and data block size.
[0088] Step 402: Based on the average throughput of the current cycle and the average throughput of the previous cycle, dynamically adjust the number of sub-parallel threads in the next cycle.
[0089] Step 403: Based on the average delay of the current period and the average delay of the previous period, dynamically adjust the data block size for the next period. The preset interval frequency is M, but this invention is not limited to this.
[0090] According to the above embodiments, by periodically acquiring performance indicators such as throughput, latency, number of sub-parallel threads, and data block size, and dynamically adjusting the number of sub-parallel threads and data block size for the next statistical period based on the performance indicators of the current and previous statistical periods, the chip simulation system can achieve adaptive optimization under different load conditions. This ensures that the parallel execution strategy and data processing granularity are always optimally configured, thereby effectively improving the simulation efficiency, host resource utilization, and overall execution performance of the chip simulation system.
[0091] In this embodiment of the invention, the parallel thread (PT) is used to receive the target transaction forwarded by the SystemC thread of the corresponding target functional module, and to split the target transaction into multiple sub-tasks to be executed. The parallel thread assigns each sub-task to a different sub-parallel thread (SUB-PT), and each sub-parallel thread executes the data operation or data transmission operation corresponding to the sub-task.
[0092] Block size represents the amount of data processed by each sub-thread while executing its subtask. Latency represents the processing time required for a sub-thread to complete the subtask corresponding to one block.
[0093] Based on the data block size and latency, the throughput can be calculated using the following formula (1).
[0094]
[0095] Wherein, Block Size is the task granularity of each sub-parallel thread, and latency is the processing time required for a sub-parallel thread to complete the sub-task corresponding to a data block.
[0096] For example, after M data transfer operations at intervals, the chip simulation system obtains the number of sub-parallel threads and the data block size corresponding to the M data transfer operations. When each sub-parallel thread begins processing a subtask, its start timestamp t_start is recorded. After each subtask is completed, its end timestamp t_end is recorded. The difference between the end timestamp t_end and the start timestamp t_start is taken as the delay for that sub-parallel thread to process the data block. After completing M data transfer operations, the delays of all sub-parallel threads are summed and divided by M to obtain the average delay.
[0097] After each sub-parallel thread completes its corresponding subtask, its throughput can be calculated based on formula (1). After completing M data transmission operations, the throughput of each operation is summed and divided by M to obtain the average throughput.
[0098] In some embodiments, such as Figure 5 As shown, step 402 includes steps 501 to 503.
[0099] Step 501: When the average throughput of the current period is higher than the first preset threshold ratio of the average throughput of the previous period, increase the number of sub-parallel threads.
[0100] Step 502: When the average throughput of the current period is lower than the second preset threshold ratio of the average throughput of the previous period, reduce the number of sub-parallel threads.
[0101] Step 503: When the average throughput of the current period is between the first threshold ratio and the second threshold ratio, the number of sub-parallel threads is increased linearly according to the first preset step size. Wherein, the first preset threshold ratio is 10%, the second preset threshold ratio is 3%, and the first preset step size is 1; however, this invention is not limited to these limits.
[0102] In this embodiment of the invention, when the average throughput of the current statistical period increases by more than 10% compared with the average throughput of the previous statistical period, after the end of the statistical period, the number of sub-parallel threads is adjusted to twice the original number of sub-parallel threads in a doubling manner, and the updated number of sub-parallel threads is used as the number of sub-parallel threads for the next statistical period.
[0103] When the average throughput of the current statistical period decreases by more than 3% compared to the average throughput of the previous statistical period, after the end of the statistical period, the number of sub-parallel threads will be halved to half of the original number of sub-parallel threads, and the updated number of sub-parallel threads will be used as the number of sub-parallel threads for the next statistical period.
[0104] When the average throughput of the current statistical period does not change significantly from the average throughput of the previous statistical period, after the end of the statistical period, the number of sub-parallel threads is increased by 1 linearly, and the updated number of sub-parallel threads is used as the number of sub-parallel threads for the next statistical period. The above adjustment method can be appropriately modified by those skilled in the art according to actual application needs, and this invention is not limited thereto.
[0105] The range of the number of sub-parallel threads (SUB_PT_count) is: The number of CPU cores can be obtained by calling the API.
[0106] According to the above embodiments, by dynamically adjusting the number of sub-parallel threads based on the changing trend of the average throughput between the current statistical period and the previous statistical period, the chip simulation system can adaptively increase or decrease the parallelism when the load changes, thereby achieving better resource utilization efficiency and task execution performance in a multi-core environment. This strategy avoids the performance bottleneck caused by a fixed parallelism, ensuring that the chip simulation system maintains high throughput and simulation efficiency at different work stages.
[0107] In some embodiments, such as Figure 6 As shown, step 403 includes steps 601 to 603.
[0108] Step 601: When the average latency of the current period is lower than the third preset threshold ratio of the average latency of the previous period, increase the data block size.
[0109] Step 602: When the average latency of the current period is higher than the fourth preset threshold ratio of the average latency of the previous period, reduce the data block size.
[0110] Step 603: When the average delay of the current period is between the third threshold ratio and the fourth threshold ratio, the data block size is increased linearly according to the second preset step size. Wherein, the third preset threshold ratio is 5%, the fourth preset threshold ratio is 5%, and the second preset step size is 1; however, this invention is not limited thereto.
[0111] In this embodiment of the invention, when the average delay of the current statistical period increases by more than 5% compared to the average delay of the previous statistical period, after the end of the statistical period, the data block size is adjusted to twice the original data block size in a doubling manner, and the updated data block size is used as the data block size for the next statistical period.
[0112] When the average latency of the current statistical period decreases by more than 5% compared to the average latency of the previous statistical period, after the end of the statistical period, the data block size is halved to half of the original data block size, and the updated data block size is used as the data block size for the next statistical period.
[0113] When the average latency of the current statistical period does not change significantly from the average latency of the previous statistical period, the data block size is increased by 1 linearly after the end of the current statistical period, and the updated data block size is used as the data block size for the next statistical period. The above adjustment method can be appropriately modified by those skilled in the art according to actual application needs, and this invention is not limited thereto. The data block size range is... .
[0114] According to the above embodiments, by dynamically adjusting the data block size based on the trend of average latency changes, the chip simulation system can increase task granularity to improve throughput efficiency when latency improves, decrease task granularity to reduce single-processing overhead when latency deteriorates, and perform fine-grained adjustments when latency changes are small, thereby keeping the data processing scale consistently within an optimal range. This adjustment mechanism can significantly improve the execution efficiency of sub-parallel threads and the simulation performance of the chip simulation system.
[0115] In some embodiments, if the product of the number of sub-parallel threads and the data block size is greater than the preset security content window size, the data block size is re-determined based on the security content window size and the number of sub-parallel threads.
[0116] In this embodiment of the invention, to avoid storage bandwidth saturation caused by excessively large number of sub-parallel threads and data block size, the size of the security content window is set to half the memory capacity of the last-level cache. This invention is not limited to this.
[0117] If the product of the number of child parallel threads and the data block size is greater than the safe content window size, then the data block size is adjusted to the ratio of the safe content window size to the number of child parallel threads.
[0118] When the product of the number of sub-parallel threads and the data block size in the current statistical period exceeds the size of the safe content window, the data block size will be adjusted to the ratio of the safe content window size to the number of sub-parallel threads after the end of the statistical period.
[0119] According to the above embodiments, the adjustment mechanism ensures that the data processing scale remains within the range allowed by the host machine's caching capacity, thereby avoiding memory access overload caused by excessive parallelism.
[0120] In some embodiments, such as Figure 7 As shown, the optimization methods for chip simulation systems also include:
[0121] Step 701: Obtain the data transmission delay and data processing delay of the parallel thread.
[0122] Step 702: If the difference between the data processing delay and the data transmission delay is greater than the first preset value, increase the number of sub-parallel threads.
[0123] Step 703: If the difference between the data transmission delay and the data processing delay is greater than the second preset value, increase the data block size.
[0124] In this embodiment of the invention, when the target transaction is a data operation, a SystemC thread of the sending end functional module sends the target transaction to the target end functional module through the interconnect port. After receiving the target transaction, a SystemC thread of the target end functional module splits the target transaction into three sub-tasks and assigns them to the corresponding parallel threads.
[0125] The first parallel thread transmits input data from the sending functional module to the target functional module. The second parallel thread performs data operations (such as vector addition) based on the input data to generate a calculation result. The third parallel thread transmits the generated calculation result from the target functional module to the sending functional module.
[0126] After assigning the aforementioned subtasks to the respective parallel threads, the SystemC thread of the target functional module calls the recovery function to wake up the first, second, and third parallel threads. Once awakened, each parallel thread is scheduled by the host operating system to execute in parallel across multiple CPU cores on the host machine.
[0127] After M data operation intervals, the chip simulation system obtains the data transmission delay T_h2d of the first parallel thread, the data operation delay T_compute of the second parallel thread, and the data transmission delay T_d2h of the third parallel thread.
[0128] When the data computation delay T_compute of the second parallel thread is much greater than the data transmission delay T_h2d of the first parallel thread or the data transmission delay T_d2h of the third parallel thread, the chip simulation system increases the number of sub-parallel threads after the end of the statistical period and uses the updated number of sub-parallel threads as the number of sub-parallel threads for the next statistical period.
[0129] When the data transmission delay T_h2d of the first parallel thread or the data transmission delay T_d2h of the third parallel thread is much greater than the data computation delay T_compute of the second parallel thread, the chip simulation system increases the data block size after the end of the statistical cycle and uses the adjusted data block size as the data block size for the next statistical cycle.
[0130] According to the above embodiments, by dynamically adjusting the number of sub-parallel threads through the above algorithm, the execution time of parallel threads is shortened, thereby effectively reducing the overall simulation time of the chip simulation system and improving simulation efficiency.
[0131] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0132] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0133] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0134] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0135] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0136] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A chip emulation system, running on a host machine, characterized in that, include: Sending end, target end, and interconnection port; The sending end invokes multiple first System C threads to send multiple target transactions to the target end through the interconnect port; The target end invokes multiple second System C threads to receive the corresponding target transactions; the second System C threads forward the target transactions to the corresponding parallel threads respectively, and call the recovery function to wake up the parallel threads; each of the parallel threads executes the corresponding target transactions in parallel on multiple CPU cores of the host machine; The transmitting end and the target end adjust their performance indicators according to the feedback signal at a preset interval frequency in order to shorten the simulation time.
2. The system according to claim 1, characterized in that, The second System C thread is also used to call the start function to create the corresponding parallel thread; and to call the stop function of the corresponding parallel thread to reclaim the parallel thread.
3. The system according to claim 1, characterized in that, The second System C thread is bound to each of the parallel threads through a handle.
4. The system according to claim 1, characterized in that, After the parallel thread completes the target transaction, the second System C thread is also used to call a suspension function to control the parallel thread to enter a waiting state.
5. An optimization method for a chip simulation system, applied to the chip simulation system described in claims 1 to 4, characterized in that, include: Create multiple System C threads, and call each System C thread to forward the received target transaction to the corresponding parallel thread; The corresponding parallel thread is awakened by calling the recovery function of each System C thread. Each parallel thread changes from a waiting state to a ready state. The host operating system allocates each parallel thread in the ready state to each CPU core of the host machine for parallel execution. The performance indicators are adjusted according to the preset interval frequency to shorten the simulation time.
6. The method according to claim 5, characterized in that, The adjustment of performance indicators according to the preset interval frequency includes: Performance metrics are acquired at preset intervals; wherein, the performance metrics include: average throughput, number of sub-parallel threads, average latency, and data block size. The number of sub-parallel threads is dynamically adjusted based on the average throughput of the current period and the average throughput of the previous period. The data block size is dynamically adjusted based on the average latency of the current period and the average latency of the previous period.
7. The method according to claim 6, characterized in that, The method of dynamically adjusting the number of sub-parallel threads based on the average throughput of the current period and the average throughput of the previous period includes: increasing the number of sub-parallel threads when the average throughput of the current period is higher than a first preset threshold ratio of the average throughput of the previous period; decreasing the number of sub-parallel threads when the average throughput of the current period is lower than a second preset threshold ratio of the average throughput of the previous period; and linearly increasing the number of sub-parallel threads by a first preset step size when the average throughput of the current period is between the first threshold ratio and the second threshold ratio. The method of dynamically adjusting the data block size based on the average latency of the current period and the average latency of the previous period includes: increasing the data block size when the average latency of the current period is lower than a third preset threshold ratio of the average latency of the previous period; decreasing the data block size when the average latency of the current period is higher than a fourth preset threshold ratio of the average latency of the previous period; and linearly increasing the data block size according to a second preset step size when the average latency of the current period is between the third threshold ratio and the fourth threshold ratio.
8. The method according to claim 6, characterized in that, If the product of the number of sub-parallel threads and the data block size is greater than the preset security content window size, the data block size is re-determined based on the security content window size and the number of sub-parallel threads.
9. The method according to claim 6, characterized in that, Also includes: Obtain the data transmission delay and data processing delay of the parallel threads; If the difference between the data processing delay and the data transmission delay is greater than a first preset value, the number of sub-parallel threads is increased; If the difference between the data transmission delay and the data processing delay is greater than a second preset value, the data block size is increased.
10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method of any one of claims 5 to 9.