Monolithic 3D integrated chip

Abstract

This application provides a monolithic 3D integrated chip, relating to the field of semiconductor technology, primarily addressing the problem that current resistive random access memory (RRAM)-based logic architectures remain relatively fixed and lack flexible reconfigurability. The monolithic 3D integrated chip includes a logic layer, a memory computing layer, and a reconfigurable layer stacked sequentially, with interconnections between these layers. The logic layer transmits computation signals and data to the memory computing layer and configuration data and signals to the reconfigurable layer. The memory computing layer, under the control of the computation signals, performs matrix multiplication or addition on the computation data and outputs the computation results. The reconfigurable layer, under the control of the configuration signals, performs reconfigurable processing on the computation results according to the configuration data. This application endows the chip with flexible programmability and reconfigurability.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more particularly to a monolithic three-dimensional integrated chip. Background Technology

[0002] Existing implementations of M3D (Monolithic 3D Integration) primarily focus on two directions. One is logic-level layering, where high-performance complementary metal-oxide-semiconductor (CMOS) circuits are implemented at the bottom layer, and low-power or dedicated logic units are stacked on top to improve area utilization and functional scalability. The other is logic-memory layering, such as integrating the processor core at the bottom layer and stacking static random access memory (SRAM) or resistive random access memory (RRAM) cells on top, accelerating data access through close-range interconnects and reducing the bottleneck caused by memory walls. Among these existing solutions, RRAM cells are increasingly being introduced into 3D architectures due to their non-volatility, high density, and ability to support neuromorphic computing, to achieve accelerated in-memory computing. However, existing RRAM-based logic architectures remain relatively fixed and lack flexible reconfigurability. Summary of the Invention

[0003] This application proposes a monolithic three-dimensional integrated chip, which aims to improve the problem that the existing logic architecture based on resistive random access memory is still relatively fixed and lacks flexible reconfigurability.

[0004] To achieve the above objectives, embodiments of this application provide a monolithic 3D integrated chip, which includes a logic layer, a memory computing layer, and a reconfigurable layer stacked sequentially, with interconnections between the logic layer, the memory computing layer, and the reconfigurable layer; the logic layer is used to transmit computing signals and computing data to the memory computing layer, and to transmit configuration data and configuration signals to the reconfigurable layer; the memory computing layer is used to perform matrix multiplication or addition calculations on the computing data under the control of the computing signals, and output the calculation results; the reconfigurable layer is used to perform reconfigurable processing on the calculation results according to the configuration data under the control of the configuration signals.

[0005] The monolithic 3D integrated chip of the above embodiments of this application introduces a reconfigurable layer and establishes inter-layer interconnections with the logic layer and the in-memory computing layer. Due to the nanometer-level interlayer spacing, it has excellent bandwidth and energy efficiency. The computation results of the in-memory computing layer can be directly reconfigured in the reconfigurable layer, eliminating the need for data to travel to and from an external processor, thus reducing data movement, lowering latency and energy consumption, and improving throughput. Simultaneously, the reconfigurable processing of the reconfigurable layer can be completed online in a closed loop, allowing deviations caused by device non-ideals to be offset in real time. Its inference accuracy remains stable under long-term operation and under temperature drift and aging conditions, enabling a task-level trade-off between accuracy and energy efficiency. Through the structure of this monolithic 3D integrated chip, the chip can be given flexible programmability and reconfigurability without sacrificing the high energy efficiency characteristics of the in-memory computing layer, thereby solving the problem that existing architectures cannot quickly adapt to different application scenarios. Furthermore, this reconfigurable layer can also serve as a carrier for redundant scheduling and secure computation, improving the reliability and adaptability of the system.

[0006] In some embodiments, the reconfigurable layer performs a lookup or linear calculation based on the calculation result to obtain a first result; the logic layer compares the first result with a reference value to obtain an error; and the reconfigurable layer 30 performs parameter compensation for the lookup or linear calculation based on the error.

[0007] In some embodiments, the logic layer further includes a configuration control circuit, a reference data register, and an error calculation unit; the reconfigurable layer further includes a calibration control unit, a lookup table module, and a linear compensation module; the configuration control circuit is used to send a calculation signal to the in-memory computing layer, which performs calculations based on the calculation data to obtain a calculation result; the lookup table module performs mapping based on the calculation result to obtain a mapped value, or the linear compensation module performs linear calculations based on the calculation result to obtain a calculated value; the calibration control unit controls the lookup table module to compare the mapped value with a reference value in the reference data memory to obtain a first comparison error, or the calibration control unit controls the linear compensation module to compare the calculated value with a reference value in the linear compensation module to obtain a second comparison error; the calibration control unit controls the lookup table module to update parameters based on the first comparison error, or controls the linear compensation module to update parameters based on the second comparison error.

[0008] In some embodiments, the logic layer is further configured to construct operator paths for the computation results; the reconstruction layer is further configured to perform operator computations on the computation results based on the operator paths.

[0009] In some embodiments, the logic layer further includes a configuration control circuit, an operator scheduling unit, and a configuration parameter register; the reconfigurable layer further includes multiple operator modules; the operator scheduling unit is used to select operator paths in the reconfigurable layer, and the configuration control circuit sends control signals to the operator modules in the reconfigurable layer based on the operator paths; the configuration parameter register is used to store operator parameters; the operator modules are used to perform reconfigurable operator calculations on the calculation results of the in-memory computation layer based on the operator parameters in the configuration parameter register, and the reconfigurable operator calculations include table lookup activation, normalization / scaling, and pooling / downsampling.

[0010] In some embodiments, the logic layer is further configured to transmit programming signals and first data to the in-memory computing layer; the reconfigurable layer is further configured to monitor the data writing process and generate a redundancy check code based on the first data; the logic layer is further configured to send a check control signal to the reconfigurable layer to control the reconfigurable layer to perform redundancy check according to the redundancy check code and generate a redundancy check result; the logic layer is further configured to generate a repair trigger signal according to the redundancy check result to control the in-memory computing layer to rewrite the first data.

[0011] In some embodiments, the logic layer further includes an error detection feedback unit and a verification instruction register; the in-memory computing layer further includes a programming circuit and a resistive random access memory (RRAM) array; the reconfiguration layer further includes a redundancy generation module and a redundancy verification module; the programming circuit is used to write first data according to the instructions of the configuration control circuit; and to apply a programming signal to the RRAM array, which outputs read data based on the first data under the control of the programming signal; the verification instruction register is used to issue verification instructions to the redundancy generation module and the redundancy verification module; the redundancy generation module generates a redundancy code based on the first data under the control of the verification instructions; the redundancy verification module determines whether the read data is correct based on the redundancy code under the control of the verification instructions; and feeds back the determination result to the error detection feedback unit; the error feedback unit controls the programming circuit and the RRAM array to rewrite the first data according to the determination result.

[0012] In some embodiments, the logic layer is further configured to transmit programming signals and first data to the in-memory computing layer; the reconfigurable layer is further configured to monitor the process of writing the first data to the in-memory computing layer and generate a redundancy check code based on the first data; the logic layer is further configured to send a check control signal to the reconfigurable layer to control the reconfigurable layer to perform redundancy check according to the redundancy check code and generate a redundancy check result; the logic layer is further configured to generate a repair trigger signal according to the redundancy check result to control the in-memory computing layer to perform bypass repair.

[0013] In some embodiments, the logic layer further includes an error detection feedback unit and a verification instruction register; the in-memory computing layer further includes a programming circuit, a resistive random access memory (RRAM) array, and a bypass switch circuit; the reconfiguration layer further includes a redundancy generation module, a redundancy verification module, and an error flag fault-tolerant mapping module; the programming circuit is used to write first data according to the instructions of the configuration control circuit; and to apply a programming signal to the RRAM array, which outputs read data based on the first data under the control of the programming signal; the verification instruction register is used to issue verification instructions to the redundancy generation module and the redundancy verification module; the redundancy generation module generates a redundancy code based on the first data under the control of the verification instructions; the redundancy verification module determines whether the read data is correct based on the redundancy code under the control of the verification instructions; and feeds back the determination result to the error detection feedback unit; the error feedback unit triggers the bypass switch circuit to operate according to the determination result. The error flag fault-tolerant mapping module is used to transmit the input data of the programming circuit to the bypass switch circuit as the input data of the bypass switch circuit, and transmit the output data of the bypass switch circuit to the programming circuit as the output data of the programming circuit.

[0014] In some embodiments, the reconfigurable layer performs reconfigurable processing on computational data, including reconfigurable data paths, online calibration and linearization, sparse / pruning support, precision / quantization reconstruction, nonlinear activation, normalization / scaling, pooling / downsampling, attention post-processing, convolutional equivalent rearrangement, integer / bit order computation, encryption / decryption / hashing, error correction, fault-tolerant remapping, wavelet, filtering, and multiplication and addition operations. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0016] Figure 1 A schematic diagram of a monolithic three-dimensional integrated chip provided in an embodiment of this application; Figure 2 An internal structure diagram of a reconfigurable layer provided in an embodiment of this application; Figure 3 This is a schematic diagram illustrating parameter compensation for a monolithic 3D integrated chip, as provided in an embodiment of this application. Figure 4 This application provides a partial structure for parameter compensation of a monolithic 3D integrated chip. Figure 5 This is a schematic diagram illustrating the operation of a monolithic three-dimensional integrated chip for operator computation, provided in an embodiment of this application. Figure 6 This application provides a partial structure for a monolithic three-dimensional integrated chip used in operator operations. Figure 7 This is a schematic diagram illustrating the repair process of a monolithic 3D integrated chip provided in an embodiment of this application. Figure 8 This application provides a partial structure for repairing a monolithic three-dimensional integrated chip. Figure 9 A schematic diagram illustrating the repair work performed on another monolithic 3D integrated chip provided in an embodiment of this application; Figure 10 This is a partial structure used in the repair work of another monolithic three-dimensional integrated chip provided in the embodiments of this application. Detailed Implementation

[0017] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0018] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0019] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0020] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part. It can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0021] In addition, the use of "based on" implies openness and inclusivity, because processes, steps, calculations or other actions "based on" one or more conditions or values ​​can in practice be based on additional conditions or values ​​beyond those conditions.

[0022] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0023] In some embodiments, such as Figure 1 As shown, the monolithic 3D integrated chip 1 includes a logic layer 10, a memory computing layer 20, and a reconfigurable layer 30 stacked sequentially. The logic layer 10, the memory computing layer 20, and the reconfigurable layer 30 are interconnected. The logic layer 10 is used to transmit computing signals and computing data to the memory computing layer 20, and to transmit configuration data and configuration signals to the reconfigurable layer 30. The memory computing layer 20 is used to perform matrix multiplication or addition calculations on the computing data under the control of the computing signals, and output the calculation results. The reconfigurable layer 30 is used to perform reconfigurable processing on the calculation results according to the configuration data under the control of the configuration signals.

[0024] In some examples, the logic layer 10 described above is a logic layer based on complementary metal-oxide-semiconductor, the in-memory computing layer 20 described above is an in-memory computing layer based on resistive random access memory, and the reconfigurable layer 30 is a reconfigurable layer based on carbon nanotube field-effect transistor field-programmable gate array.

[0025] The monolithic 3D integrated chip 1 of the above embodiments of this application introduces a reconfigurable layer 30 and interconnects it with the logic layer 10 and the in-memory computing layer 20. Due to the nanometer-level interlayer spacing, it possesses excellent bandwidth and energy efficiency. The computation results of the in-memory computing layer 20 can be directly reconfigured in the reconfigurable layer 30, eliminating the need for data to travel to and from an external processor, thus reducing data movement, lowering latency and energy consumption, and improving throughput. Simultaneously, the reconfigurable processing of the reconfigurable layer 30 can be completed online in a closed loop, allowing deviations caused by device non-ideals to be offset in real time. Its inference accuracy remains stable even under long-term operation and under temperature drift and aging conditions, enabling a task-level trade-off between accuracy and energy efficiency. Through the structure of this monolithic 3D integrated chip 1, the chip can be given flexible programmability and reconfigurability without sacrificing the high energy efficiency characteristics of the in-memory computing layer 20, thereby solving the problem that existing architectures cannot quickly adapt to different application scenarios. Furthermore, the reconfigurable layer 30 can also serve as a carrier for redundant scheduling and secure computation, improving the system's reliability and adaptability.

[0026] It is understandable that the aforementioned in-memory computing layer 20 includes a DAC circuit, an RRAM array, and an ADC circuit, used to perform in-memory computation operations for matrix calculations and output analog or digital signals. The RRAM in-memory computing layer 20 mainly performs matrix calculations. The DAC circuit is generally a current-type or successive approximation type, used to convert the digital input into a current signal to drive the RRAM array; the RRAM array itself is a cross-switching structure, with each unit being a variable resistor device, which can simultaneously perform storage and computation; the ADC circuit is responsible for converting the array output current into a digital signal, and successive approximation or Σ-Δ ADCs are commonly used.

[0027] like Figure 2 As shown, the reconfigurable layer 30 includes a logic array block 31, a switching matrix 32, a programmable interconnect network 33, and a configuration memory 34. The logic array block 31 includes multiple logic units used to implement basic logic functions. The switching matrix 32 provides interconnection paths between different logic units. The programmable interconnect network 33 is used to construct complex data paths, primarily for inter-layer data transmission. The configuration memory 34 stores configuration information to control the logic blocks and interconnection methods. Data from the in-memory computing layer 20 can be input into the reconfigurable layer 30 and processed through the logic modules and interconnection network. The logic layer 10 provides global data configuration data and configuration signals to the reconfigurable layer 30 for overall scheduling and task allocation, thereby enabling the collaborative operation of the three-layer structure.

[0028] In some embodiments, such as Figure 3 As shown, the reconfigurable layer 30 performs a lookup or linear calculation based on the calculation result to obtain the first result; the logic layer 10 compares the first result with the reference value to obtain the error; and the reconfigurable layer 30 performs parameter compensation for the lookup or linear calculation based on the error.

[0029] In some embodiments, such as Figure 4 As shown, the logic layer 10 also includes a configuration control circuit, a reference data register, and an error calculation unit; the reconfigurable layer 30 also includes a calibration control unit, a lookup table module, and a linear compensation module; the configuration control circuit sends a calculation signal to the in-memory computing layer 20, which performs calculations based on the calculation data to obtain the calculation result; the lookup table module performs mapping based on the calculation result to obtain a mapped value, or the linear compensation module performs linear calculation based on the calculation result to obtain a calculated value; the calibration control unit controls the lookup table module to compare the mapped value with the reference value in the reference data memory to obtain a first comparison error, or the calibration control unit controls the linear compensation module to compare the calculated value with the reference value in the reference data module to obtain a second comparison error; the calibration control unit controls the lookup table module to update parameters based on the first comparison error, or controls the linear compensation module to update parameters based on the second comparison error.

[0030] Understandably, the configuration control circuit mainly consists of a configuration interface and a state mechanism, responsible for receiving external commands and issuing control signals. The error calculation unit typically consists of digital adders / subtractors, comparators, and accumulator circuits, capable of comparing reference values ​​with actual mapped or calculated values ​​and generating error signals. The reference data register often uses D flip-flop arrays or small-scale SRAM circuits to temporarily store reference data or compensation parameters for use during closed-loop calibration. The calibration control unit internally contains a finite state machine and configuration registers, which can determine which calibration mode to use based on control signals from logic layer 10. The lookup table module relies on on-chip BRAM storage and multiplexers to implement lookup table calibration or nonlinear function mapping; the linear compensation module consists of comparators, programmable multipliers, shifters, and adders, used to perform piecewise linear or gain adjustment operations.

[0031] The monolithic 3D integrated chip 1 in the above embodiment completes the entire process from signal emission, matrix calculation, error detection and dynamic compensation through the cooperation of these three layers. It utilizes the high-density storage and computing characteristics of the in-memory computing layer 20, and combines the flexibility of the reconfigurable layer 30 and the control capability of the logic layer 10 to achieve online accuracy maintenance and long-term stable computing.

[0032] In some embodiments, such as Figure 5 As shown, the logic layer 10 is also used to construct operator paths for the calculation results; the reconstruction layer is also used to perform operator calculations on the calculation results based on the operator paths.

[0033] In some embodiments, such as Figure 6 As shown, the logic layer 10 also includes a configuration control circuit, an operator scheduling unit, and a configuration parameter register; the reconfigurable layer 30 also includes multiple operator modules; the operator scheduling unit is used to select operator paths in the reconfigurable layer, and the configuration control circuit sends control signals to the operator units in the logic array block based on the operator paths; the configuration parameter register is used to store operator parameters; the operator modules are used to perform reconfigurable operator calculations on the calculation results of the in-memory computation layer 20 based on the operator parameters in the configuration parameter register, and the reconfigurable operator calculations include table lookup activation, normalization / scaling, and pooling / downsampling.

[0034] Understandably, the operator scheduling unit is usually composed of control logic and finite state mechanisms, which can select the operator path to be enabled according to the needs of the model; the configuration parameter memory is generally a register file or a small SRAM, used to store activation function lookup parameters, normalization coefficients, scaling factors or pooling window parameters, etc.

[0035] Understandably, within the reconfigurable layer 30, the processing functions of different operators are implemented by different circuit modules. The operator modules include a lookup table module, a normalization / scaling module, and a pooling / downsampling module. The lookup table module, relying on on-chip memory and multiplexers, is used to implement lookup operations for activation functions, such as ReLU (Revised Linear Unit), Sigmoid (Logistic Function), and tanh (Hyperbolic Tangent Function). The normalization / scaling module consists of multipliers, adders, shifters, and accumulators, used to implement mean and variance adjustment and scaling operations in BatchNorm (batch normalization) or LayerNorm (layer normalization). The pooling / downsampling module includes a sliding window controller, a comparator tree, and accumulation and shifting circuits, and supports configurable step sizes.

[0036] Based on the above embodiments, the logic layer 10 issues control signals and parameters, the resistive random access memory layer provides array computation output, and the reconfigurable layer 30 flexibly executes different post-processing operators. The combination of these three elements enables a single-chip 3D integrated circuit to perform key nonlinear and data reduction operations in deep learning on-chip, significantly improving inference efficiency and flexibility.

[0037] In some embodiments, such as Figure 7 As shown, the logic layer 10 is also used to transmit programming signals and first data to the in-memory computing layer 20; the reconfigurable layer 30 is also used to monitor the data writing process and generate a redundancy check code based on the first data; the logic layer 10 is also used to send a check control signal to the reconfigurable layer 30 to control the reconfigurable layer 30 to perform redundancy check according to the redundancy check code and generate a redundancy check result; the logic layer 10 is also used to generate a repair trigger signal according to the redundancy check result to control the in-memory computing layer 20 to rewrite the first data.

[0038] In some embodiments, such as Figure 8 As shown, the logic layer 10 also includes a configuration control circuit, an error detection feedback unit, and a verification instruction register; the in-memory computing layer 20 also includes a programming circuit and a resistive random access memory (RRAM) array; the reconfiguration layer also includes a redundancy generation module and a redundancy verification module; the programming circuit is used to write first data according to the instructions of the configuration control circuit; and to apply a programming signal to the RRAM array, which outputs read data based on the first data under the control of the programming signal; the verification instruction register is used to issue verification instructions to the redundancy generation module and the redundancy verification module; the redundancy generation module generates a redundancy code based on the first data under the control of the verification instructions; the redundancy verification module determines whether the read data is correct based on the redundancy code under the control of the verification instructions; and feeds back the judgment result to the error detection feedback unit; the error feedback unit controls the programming circuit and the RRAM array to rewrite the first data according to the judgment result.

[0039] Understandably, the error detection and feedback unit typically consists of a comparator, a counter, and logic control circuitry, used to receive error flags from the upper layer and generate repair trigger signals. The verification instruction memory uses a register set or a small static random access memory to store verification modes, redundancy strategies, and related configuration parameters. The programming circuit mainly consists of a write driver and a current pulse generator, used to apply programming voltage or current to the RRAM array. The RRAM array itself is a crosspoint structure, storing weight data and undertaking calculation tasks. The redundancy generation module consists of an encoder, registers, and logic circuitry, which can generate redundancy check codes during data writing. The redundancy verification module includes a decoder, a comparator, and error detection logic, used to compare redundancy information and identify errors when reading data.

[0040] In some embodiments, such as Figure 9 As shown, the logic layer 10 is also used to transmit programming signals and first data to the in-memory computing layer 20; the reconfigurable layer 30 is also used to monitor the process of writing the first data to the in-memory computing layer 20 and generate a redundancy check code based on the first data; the logic layer 10 is also used to send a check control signal to the reconfigurable layer 30 to control the reconfigurable layer 30 to perform redundancy check according to the redundancy check code and generate a redundancy check result; the logic layer 10 is also used to generate a repair trigger signal according to the redundancy check result to control the in-memory computing layer 20 to perform bypass repair.

[0041] In some embodiments, such as Figure 10 As shown, the logic layer 10 further includes an error detection feedback unit and a verification instruction register; the in-memory computing layer 20 further includes a programming circuit, a resistive random access memory (RRAM) array, and a bypass switch circuit; the reconfiguration layer further includes a redundancy generation module, a redundancy verification module, and an error flag fault-tolerant mapping module; the programming circuit is used to write first data according to the instructions of the configuration control circuit; and to apply a programming signal to the RRAM array, which outputs read data based on the first data under the control of the programming signal; the verification instruction register is used to issue verification instructions to the redundancy generation module and the redundancy verification module; the redundancy generation module generates a redundancy code based on the first data under the control of the verification instructions; the redundancy verification module determines whether the read data is correct based on the redundancy code under the control of the verification instructions; and feeds back the judgment result to the error detection feedback unit; the error feedback unit triggers the bypass switch circuit to work according to the judgment result. The error flag fault-tolerant mapping module is used to transmit the input data of the programming circuit to the bypass switch circuit as the input data of the bypass switch circuit, and transmit the output data of the bypass switch circuit to the programming circuit as the output data of the programming circuit.

[0042] It is understandable that the bypass switch circuit described above is composed of a programmable switch matrix or a multiplexer, which can switch to a backup storage unit or a healthy channel when a failed unit is detected.

[0043] It is understandable that the above Figures 7-10 In the embodiment described, logic layer 10 is responsible for issuing programming and verification signals. In-memory computing layer 20 performs array programming operations based on the programming signals and rewrites or bypasses upon receiving error information. Reconfigurable layer 30 generates redundant information during programming, performs redundancy verification during data reading, and feeds back error information to in-memory computing layer 20 when an error is detected, thereby triggering programming rewriting or bypass repair. The overall system coordination mechanism is as follows: CMOS logic layer 10 issues control and verification commands; RRAM layer performs programming and in-memory computing operations and bypasses when necessary; FPGA layer generates redundant codes and performs error detection, then feeds back the error information. Through this three-layer architecture, the reliability of the RRAM array is improved, and failed units can be dynamically repaired or replaced during operation, thereby extending system life and ensuring computational accuracy.

[0044] The reconfigurable layer 30 incorporates redundant coding and verification, error flag generation, cross-layer remapping, and bypass repair. When the in-memory computing layer 20 degrades or fails, it can quickly locate the issue on-chip and map it to a healthy cell using logical addresses, achieving uninterrupted self-healing. Combined with partial reconfiguration, operators and pathways can be hot-switched, significantly improving system robustness and lifecycle output. Thus, this chain of improvements—from architecture and methodology to interconnects and reliability—results in verifiable simultaneous enhancements in performance, energy efficiency, accuracy, and reliability, directly addressing and resolving the three core shortcomings of existing technologies.

[0045] In some embodiments, the reconfigurable layer 30 performs reconfigurable processing on computational data, including reconfigurable data paths, online calibration and linearization, sparse / pruning support, precision / quantization reconstruction, nonlinear activation, normalization / scaling, pooling / downsampling, attention post-processing, convolutional equivalent rearrangement, integer / bit order computation, encryption / decryption / hashing, error correction, fault-tolerant remapping, wavelet, filtering, and multiplication and addition operations.

[0046] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A monolithic three-dimensional integrated chip, characterized by, The monolithic 3D integrated chip includes a logic layer, a memory computing layer, and a reconfigurable layer stacked sequentially, with interconnections between the logic layer, the memory computing layer, and the reconfigurable layer. The logic layer is used to transmit computing signals and computing data to the in-memory computing layer, and to transmit configuration data and configuration signals to the reconfigurable layer. The in-memory computing layer is used to perform matrix multiplication or addition on the computation data under the control of the computation signal, and output the computation results. The reconfigurable layer is used to perform reconfigurable processing on the calculation results according to the configuration data under the control of the configuration signal.

2. The monolithic three-dimensional integrated chip of claim 1, wherein, The reconfigurable layer obtains the first result by looking up a table or performing linear calculations based on the calculation results. The logic layer obtains the error by comparing the first result with the reference value; The reconfigurable layer performs parameter compensation for table lookup or linear calculation based on the error.

3. The monolithic three-dimensional integrated chip of claim 2, wherein, The logic layer also includes a configuration control circuit, a reference data register, and an error calculation unit; the reconfigurable layer also includes a calibration control unit, a lookup table module, and a linear compensation module. The configuration control circuit is used to send a calculation signal to the in-memory computing layer, and the in-memory computing layer performs calculations based on the calculation data to obtain the calculation result. The lookup table module maps the results to obtain a mapping value, or the linear compensation module performs linear calculations based on the results to obtain a calculated value. The calibration control unit controls the lookup table module to compare the mapped value with the reference value in the reference data memory to obtain a first comparison error; or, the calibration control unit controls the linear compensation module to compare the calculated value with the reference value in the reference data module to obtain a second comparison error. The calibration control unit controls the lookup table module to update parameters based on the first comparison error, or controls the linear compensation module to update parameters based on the second comparison error.

4. The monolithic three-dimensional integrated chip according to claim 1, characterized in that, The logic layer is further configured to construct operator paths for the calculation results; the reconstruction layer is further configured to perform operator calculations on the calculation results based on the operator paths.

5. The monolithic three-dimensional integrated chip according to claim 4, characterized in that, The logic layer also includes a configuration control circuit, an operator scheduling unit, and a configuration parameter register; the reconfigurable layer also includes multiple operator modules. The operator scheduling unit is used to select the operator path in the reconstruction layer, and the configuration control circuit sends control signals to multiple operator modules in the reconstruction layer based on the operator path; The configuration parameter register is used to store operator parameters; The operator module is used to reconstruct the calculation results of the in-memory computing layer based on the operator parameters in the configuration parameter register.

6. The monolithic three-dimensional integrated chip according to claim 1, characterized in that, The logic layer is also used to transmit programming signals and first data to the in-memory computing layer; The reconfigurable layer is also used to monitor the process of writing first data to the in-memory computing layer, and generate a redundancy check code based on the first data; the logic layer is also used to send a check control signal to the reconfigurable layer to control the reconfigurable layer to perform redundancy check according to the redundancy check code and generate a redundancy check result; the logic layer is also used to generate a repair trigger signal according to the redundancy check result to control the in-memory computing layer to rewrite the first data.

7. The monolithic three-dimensional integrated chip according to claim 6, characterized in that, The logic layer also includes a configuration control circuit, an error detection feedback unit, and a verification instruction register; the in-memory computing layer also includes a programming circuit and a resistive random access memory array; the reconfiguration layer also includes a redundancy generation module and a redundancy verification module. The programming circuit is used to write first data according to the instructions of the configuration control circuit; and to apply a programming signal to the resistive random access memory array, wherein the resistive random access memory array outputs read data based on the first data under the control of the programming signal; The verification instruction register is used to issue verification instructions to the redundancy generation module and the redundancy verification module; the redundancy generation module generates redundancy codes based on the first data under the control of the verification instructions. Under the control of the verification instruction, the redundancy verification module determines whether the read data is correct based on the redundancy code and feeds back the judgment result to the error detection feedback unit. Based on the judgment result, the error feedback unit controls the programming circuit and the resistive random access memory array to rewrite the first data.

8. The monolithic three-dimensional integrated chip according to claim 1, characterized in that, The logic layer is also used to transmit programming signals and first data to the in-memory computing layer; The reconfigurable layer is also used to monitor the process of writing first data to the in-memory computing layer, and generate a redundancy check code based on the first data; the logic layer is also used to send a check control signal to the reconfigurable layer to control the reconfigurable layer to perform redundancy check according to the redundancy check code and generate a redundancy check result. The logic layer is also used to generate a repair trigger signal based on the redundancy check result, so as to control the in-memory computing layer to perform bypass repair.

9. The monolithic three-dimensional integrated chip according to claim 8, characterized in that, The logic layer also includes a configuration control circuit, an error detection feedback unit, and a verification instruction register; the in-memory computing layer also includes a programming circuit, a resistive variable memory array, and a bypass switch circuit; the reconfiguration layer also includes a redundancy generation module, a redundancy verification module, and an error flag fault-tolerant mapping module. The programming circuit is used to write first data according to the instructions of the configuration control circuit; and to apply a programming signal to the resistive random access memory array, wherein the resistive random access memory array outputs read data based on the first data under the control of the programming signal; The verification instruction register is used to issue verification instructions to the redundancy generation module and the redundancy verification module; the redundancy generation module generates redundancy codes based on the first data under the control of the verification instructions. Under the control of the verification instruction, the redundancy verification module determines whether the read data is correct based on the redundancy code and feeds back the judgment result to the error detection feedback unit. The error feedback unit triggers the bypass switch circuit to operate based on the judgment result; The error flag fault-tolerant mapping module is used to transmit the input data of the programming circuit to the bypass switch circuit as the input data of the bypass switch circuit, and transmit the output data of the bypass switch circuit to the programming circuit as the output data of the programming circuit.

10. The monolithic three-dimensional integrated chip according to claim 1, characterized in that, The reconfigurable layer performs reconfigurable processing on the computational data, including reconfigurable data paths, online calibration and linearization, sparse / pruning support, precision / quantization reconstruction, nonlinear activation, normalization / scaling, pooling / downsampling, attention post-processing, convolutional equivalent rearrangement, integer / bit order computation, encryption / decryption / hashing, error correction, fault-tolerant remapping, wavelet, filtering, and multiplication and addition operations.

Images