Display driver circuit and display panel

Abstract

This invention proposes a display driving circuit and a display panel. The display driving circuit includes a gate start signal access module and a gate driving module. The gate start signal access module includes multiple pre-charge units and multiple switching units. By setting the switching units to control the start terminal of the gate driving module to be grounded when the clock signal is valid, the gate driving module is avoided from being affected by both the clock signal and the gate start signal simultaneously, reducing the occurrence of leakage problems. At the same time, since each gate driving module avoids leakage problems caused by the superposition of the clock signal and the gate start signal, the difference in charging rate caused by inconsistent pre-charging conditions between the gate driving modules is avoided, thus improving the uniformity of the display.

Description

Technical Field

[0001] This invention relates to the field of display devices, and more particularly to a display driving circuit and a display panel. Background Technology

[0002] In the display panel, the GOA (Gate On Array) corresponding to the initial certain number of pixel rows is directly triggered by the gate-activated signal STV, and the GOA of subsequent rows is triggered by cascading with the previous row.

[0003] For GOAs directly triggered by STV, since STV needs to satisfy the triggering of multiple GOAs, the effective time of STV covers the scan signal output of multiple GOAs. When the scan signal is output, the clock signal CK is effective. At this time, the STV signal and the CK signal are effective at the same time, which leads to the problem of leakage at the Q point. At the same time, since the overlap time of the STV signal and the CK signal is different in different rows, there are differences in the leakage between different pixel rows, resulting in brightness differences between different pixel rows and affecting the uniformity of the image. Summary of the Invention

[0004] The main objective of this invention is to provide a display driving circuit and a display panel, which aims to solve the problem of uneven screen display caused by different leakage current conditions of GOAs in different rows in the prior art.

[0005] To achieve the above objectives, the present invention provides a display driving circuit, comprising a gate start signal access module and a gate driving module; the gate start signal access module includes multiple pre-charge units and multiple switching units; the control terminal of the pre-charge unit is connected to the gate start signal line, the output terminal of the pre-charge unit is connected to the start terminal of the corresponding gate driving module, the start terminal of the gate driving module is also grounded through the switching units, and the control terminal of the switching units is connected to the clock signal line corresponding to the gate driving module; wherein: The precharge unit is used to precharge the voltage and output the corresponding row start signal to the corresponding row's gate drive module based on the gate start signal transmitted by the gate start signal line. The switching unit is used to ground the start-up terminal of the gate drive module of the corresponding row when the clock signal of the corresponding row is valid.

[0006] Optionally, the pre-charge unit includes a charging sub-unit, wherein: The input terminal of the charging sub-unit is connected to the gate start signal line, the control terminal of the charging sub-unit is connected to the gate start signal line, and the output terminal of the charging sub-unit is connected to the start terminal of the gate drive module.

[0007] Optionally, the effective period of the gate start signal includes a continuously set charging phase and an effective phase; the effective phase is time-consistent with the pre-charging phase of the gate drive module, and during the charging phase, the pre-charging unit charges to the effective voltage of the gate start signal.

[0008] Optionally, the pre-charge unit includes a charging subunit and a switching subunit; wherein: The input terminal of the charging subunit is connected to the power signal line, the control terminal of the charging subunit is connected to the power signal line, the output terminal of the charging subunit is connected to the start terminal of the gate drive module through the switching subunit, and the control terminal of the switching subunit is connected to the gate start signal line.

[0009] Optionally, the switching subunit includes a first switching transistor; wherein: The control terminal of the first switch is connected to the gate start signal line, the input terminal of the first switch is connected to the output terminal of the charging subunit, and the output terminal of the first switch is connected to the start terminal of the gate drive module.

[0010] Optionally, the charging subunit includes a charging component and a buffer component, wherein: The input terminal of the charging component serves as the input terminal of the charging sub-unit, and the output terminal of the charging component is connected to the charging terminal of the buffer component, with the charging terminal of the buffer component serving as the output terminal of the charging sub-unit.

[0011] Optionally, the charging component includes a second switching transistor, wherein: The input terminal of the second switch is used as the input terminal of the charging component, the control terminal of the second switch is connected to the input terminal of the second switch, and the output terminal of the second switch is used as the output terminal of the charging component.

[0012] Optionally, the buffer assembly includes a first capacitor; wherein: The first terminal of the first capacitor serves as the charging terminal of the buffer component, and the second terminal of the first capacitor is grounded.

[0013] Optionally, the switching unit includes a third switching transistor; wherein: The control terminal of the third switch is connected to the clock signal line, the input terminal of the third switch is connected to the start terminal of the gate drive module, and the output terminal of the third switch is grounded.

[0014] In addition, to achieve the above objectives, the present invention also provides a display panel, the display panel including a gate start signal line, a clock signal line and a display driving circuit, the display driving circuit being configured as described above.

[0015] This invention proposes a display driving circuit and a display panel. The display driving circuit includes a gate start signal access module and a gate driving module. The gate start signal access module includes multiple pre-charge units and multiple switching units. The control terminal of the pre-charge unit is connected to the gate start signal line, and the output terminal of the pre-charge unit is connected to the start terminal of the corresponding gate driving module. The start terminal of the gate driving module is also grounded through the switching units. The control terminal of the switching units is connected to the clock signal line corresponding to the gate driving module. The pre-charge unit is used to pre-charge the voltage and output a corresponding row start signal to the corresponding row's gate driving module based on the gate start signal transmitted through the gate start signal line. The switching unit is used to ground the start terminal of the corresponding row's gate driving module when the clock signal of the corresponding row is valid. By setting the switching unit to ground the start-up terminal of the gate drive module when the clock signal is valid, the gate drive module is prevented from being affected by both the clock signal and the gate start-up signal at the same time, thus reducing the occurrence of leakage problems. At the same time, since each gate drive module avoids leakage problems caused by the superposition of the clock signal and the gate start-up signal, the difference in charging rate caused by the inconsistency of pre-charging conditions between the gate drive modules is avoided, thus improving the uniformity of the display. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 This is a functional block diagram of an embodiment of the display driving circuit of the present invention; Figure 2 This is a circuit structure diagram of an embodiment of the gate driving circuit in the display driving circuit of the present invention; Figure 3 This is a schematic diagram of the triggering method of the gate driving circuit in the display driving circuit of the present invention; Figure 4 This is a schematic diagram of the structure of an embodiment of the display driving circuit of the present invention; Figure 5 This is a schematic diagram of another embodiment of the display driving circuit of the present invention.

[0018] Figure 6 This is a schematic diagram of the structure of the display panel of the present invention.

[0019] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0020] Explanation of icon numbers: Detailed Implementation

[0021] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0023] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0024] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0025] This invention provides a display driving circuit 10, applied in a display panel. Please refer to [link / reference]. Figure 1 , Figure 1This is a functional block diagram of an embodiment of the display driving circuit 10 of the present invention. In this embodiment, the display driving circuit 10 includes a gate start signal access module 100 and a gate driving module 200; the gate start signal access module 100 includes multiple precharge units 110 and multiple switching units 120; the control terminal of the precharge unit 110 is connected to the gate start signal line STV, the output terminal of the precharge unit 110 is connected to the start terminal of the corresponding gate driving module 200, the start terminal of the gate driving module 200 is also grounded through the switching unit 120, and the control terminal of the switching unit 120 is connected to the clock signal line CK corresponding to the gate driving module 200; wherein: The precharge unit 110 is used to precharge the voltage and output the corresponding row start signal to the corresponding row gate drive module 200 based on the gate start signal STV transmitted by the gate start signal line STV. The switching unit 120 is used to ground the start-up terminal of the gate driving module 200 of the corresponding row when the clock signal CK of the corresponding row is valid.

[0026] The gate driving module 200 is used to output scanning signals to the pixel row; the specific structure of the gate driving module 200 can be set according to actual needs, such as 4T1C (4 TFTs + 1 capacitor), 7T1C, etc.; it should be noted that the gate driving module 200 referred to in this application is the gate driving module 200 that is directly triggered by the STV signal.

[0027] For ease of explanation, a typical gate drive module 200 structure is used for illustration; see [link to documentation]. Figure 2 , 3 The gate drive module 200 includes a first drive switch TF1, a second drive switch TF2, and a third drive switch TF3; wherein: The gate of the first driving switch TF1 is connected to the gate start signal line STV. The input terminal of the first driving switch TF1 is connected to the STV signal line. The output terminal of the first driving switch TF1 is connected to the gate of the second driving switch TF2 and the gate of the third driving switch TF3. The input terminals of the second driving switch TF2 and the third driving switch TF3 are connected to the clock signal line CK. The output terminal of the second driving switch TF2 is connected to the start terminal of the next-stage gate driving module 200. The output terminal of the third driving switch TF3 is connected to the in-plane pixel row. The output terminal of the third driving switch TF3 outputs the scan signal. The output of the first driving switch TF1 is connected to point Q, and point Q is used to charge the charging capacitor.

[0028] When the gate start signal STV is valid, the first drive switch TF1 is turned on and charges the charging capacitor. After the charging reaches the start voltage of the second drive switch TF2 and the third drive switch TF3, the second drive switch TF2 and the third drive switch TF3 are turned on. When the clock signal CK is valid, the clock signal CK outputs a trigger signal to the next stage through the second drive switch TF2, and the clock signal CK outputs a scan signal through the third drive switch TF3. At this time, if the gate start signal STV and the clock signal CK are valid at the same time, the voltage at point Q will leak out through the first drive switch TF1, resulting in insufficient charging of the charging capacitor.

[0029] For the gate driving module 200 in this embodiment, its startup terminal is the gate of the first driving switch TF1 and is connected to the gate startup signal line STV; for the gate driving module 200 after the gate driving module 200 in this embodiment, its startup terminal is the gate of the first driving switch TF1 and is connected to the output terminal of the second driving switch TF2 in the gate driving module 200 cascaded in front.

[0030] In this embodiment, the number of gate drive modules 200 directly connected to the gate start signal line STV can be set based on the actual needs of the display panel. In this embodiment and subsequent embodiments, the number of gate drive modules 200 is 4 as an example for illustration.

[0031] The switching unit 120 is used to prevent the gate start signal STV and the clock signal CK from being active simultaneously in the same gate drive module 200.

[0032] It is understood that a gate start signal line STV is directly or indirectly connected to the start terminals of multiple gate drive modules 200, and these gate drive modules 200 are connected to different clock signal lines CK. The effective period of the clock signal CK in the different clock signal lines CK is different, so that the different gate drive modules 200 output scan signals sequentially. Therefore, the switching unit 120 in this embodiment is configured for the corresponding gate drive module 200 and clock signal line CK; for example, it currently includes the first to fourth gate drive modules 200, the first to fourth clock signal lines CK; and the input of the second drive switch TF2 and the third drive switch TF3 in the first gate drive module 200. The input terminals of the first gate drive module 200 are connected to the first clock signal line CK1. The input terminals of the second drive switch transistor TF2 and the third drive switch transistor TF3 in the second gate drive module 200 are connected to the second clock signal line CK2, and so on. At this time, four switch units 120 are set, namely the first switch unit 120 to the fourth switch unit 120. The start-up terminal of the first gate drive module 200 is grounded through the first switch unit 120, and the control terminal of the first switch unit 120 is connected to the first clock signal line CK1. The start-up terminal of the second gate drive module 200 is grounded through the second switch unit 120, and the control terminal of the second switch unit 120 is connected to the second clock signal line CK2, and so on. The ground signal is provided by the ground signal line VSS.

[0033] When the clock signal CK is valid, the switching unit 120 grounds the start-up terminal of the corresponding gate drive module 200, thereby turning off the first drive switch TF1 in the gate drive module 200 and making the gate start signal STV ineffective in the gate drive module 200. This avoids the gate start signal STV and the clock signal CK being valid in the gate drive module 200 at the same time, and avoids leakage of the Q point voltage through the first drive switch TF1; thus achieving the leakage prevention effect.

[0034] However, since multiple gate drive modules 200 are connected to the same gate start signal line STV, when the switch unit 120 grounds the start terminal of the gate drive module 200, the start terminals of other gate drive modules 200 will also be grounded, causing the gate start signal STV of all gate drive modules 200 to fail and the pre-charge operation to be unable to be performed. In order to solve this problem, a pre-charge unit 110 is provided in this embodiment.

[0035] The precharge unit 110 is charged through the gate start signal line STV. After charging is completed, the precharge unit 110 itself can provide a voltage equivalent to the gate start signal STV to the gate drive module 200. It can be understood that the precharge unit 110 and the gate drive module 200 are set in a one-to-one correspondence. For example, there are first to fourth precharge units 110. The control terminals of the four precharge units 110 are all connected to the gate start signal line STV. The output terminal of the first precharge unit 110 is connected to the start terminal of the first gate drive module 200, the output terminal of the second precharge unit 110 is connected to the start terminal of the second gate drive module 200, and so on.

[0036] When a precharge unit 110 is set, if a certain switch unit 120 grounds the start terminal of the gate drive module 200, the corresponding precharge unit 110 is grounded through the switch unit 120 and is discharged. However, the other precharge units 110 are set independently. Therefore, the other precharge units 110 can still provide row start signals to the corresponding gate drive module 200 as needed, realizing the independent leakage prevention effect of the gate drive modules 200 in different rows.

[0037] The row start signal is a signal sent from the precharge unit 110 to the start terminal of the gate drive module 200 to realize the gate start signal STV function.

[0038] In this embodiment, by setting the switch unit 120 to ground the start-up terminal of the gate drive module 200 when the clock signal CK is valid, the gate drive module 200 is prevented from being affected by both the clock signal CK and the gate start-up signal STV simultaneously, thus reducing the occurrence of leakage problems. At the same time, since each gate drive module 200 avoids leakage problems caused by the superposition of the clock signal CK and the gate start-up signal STV, the charging rate difference caused by the inconsistency of the pre-charging conditions between the gate drive modules 200 is avoided, thus improving the uniformity of the screen display.

[0039] Further, see Figure 4 The pre-charge unit 110 includes a charging subunit 111, wherein: The input terminal of the charging sub-unit 111 is connected to the gate start signal line STV, the control terminal of the charging sub-unit 111 is connected to the gate start signal line STV, and the output terminal of the charging sub-unit 111 is connected to the start terminal of the gate drive module 200.

[0040] In this embodiment, the gate start signal STV serves as both the control source and the power source for the precharge unit 110.

[0041] When the gate start signal STV is invalid, the charging sub-unit 111 discharges.

[0042] When the gate start signal STV is valid, the gate start signal STV charges the charging sub-unit 111, and the charging sub-unit 111 provides a row start signal to the start terminal of the gate drive module 200 based on the charging status.

[0043] Furthermore, the effective period of the gate start signal STV includes a continuously set charging phase and an effective phase; the effective phase is time-consistent with the pre-charging phase of the gate drive module 200, and during the charging phase, the pre-charging unit 110 charges to reach the effective voltage of the gate start signal STV.

[0044] It is understandable that when the gate start signal STV serves as both the control source and the power source for the precharge unit 110, compared to the prior art, the gate start signal STV needs to charge the precharge unit 110 first within its effective period, and then the precharge unit 110 provides the row start signal to the gate drive module 200. However, during the period before the precharge unit 110 completes charging, it can only provide a row start signal with a voltage lower than that of the gate start signal STV, which may result in insufficient precharging of the gate drive module 200. To solve this problem, the effective period of the gate start signal STV is adjusted in this embodiment.

[0045] The effective phase is the effective phase set by the gate start signal STV based on its functional requirements, specifically corresponding to the pre-charge phase of the gate drive module 200. In this embodiment, the gate start signal STV is set to be effective in advance before the effective phase, and the phase between the time of early effectiveness and the effective phase is the charging phase. By making the gate start signal STV effective in advance, the gate start signal STV can charge the pre-charge unit 110 in advance, and the pre-charge unit 110 can be fully charged before the effective phase. Thus, in the effective phase, the pre-charge unit 110 can provide a row start signal that meets the gate start requirements to the gate drive module 200, thereby achieving the desired effect of the gate start signal STV and ensuring the pre-charge effect of the gate drive module 200.

[0046] The specific length of the charging phase can be set based on the parameters of the pre-charge unit 110, so that the pre-charge unit 110 can complete charging during the charging phase, and the output row start signal reaches the effective voltage of the gate start signal STV or the voltage required for the start-up terminal of the gate drive module 200.

[0047] Further, see Figure 5 The pre-charge unit 110 includes a charging subunit 111 and a switching subunit 112; wherein: The input terminal of the charging subunit 111 is connected to the power signal line, the control terminal of the charging subunit 111 is connected to the power signal line, the output terminal of the charging subunit 111 is connected to the start terminal of the gate drive module 200 through the switching subunit 112, and the control terminal of the switching subunit 112 is connected to the gate start signal line STV.

[0048] In this embodiment, the gate start signal STV is used only as the control source for the precharge unit 110; in addition, a power signal line is provided as the power source for the precharge unit 110.

[0049] The power signal line provides the power supply voltage VDD to maintain the charging sub-unit 111, so that the charging sub-unit 111 can complete charging before the gate start signal STV is valid; When the gate start signal STV is invalid, the switching subunit 112 is not turned on, and the charging subunit 111 cannot output voltage to the gate drive module 200.

[0050] When the gate start signal STV is valid, the gate start signal STV triggers the switch subunit 112 to turn on, and the charging subunit 111 outputs the row start signal to the gate drive module 200.

[0051] Since the charging subunit 111 completes charging when the gate start signal STV is valid and can output the required row start signal, in this embodiment, the effective period of the gate start signal STV does not need to be increased by a charging phase. It is sufficient to ensure the pre-charging of the gate drive module 200 by being valid only during the effective phase.

[0052] Furthermore, the switching subunit 112 includes a first switching transistor Q1; wherein: The control terminal of the first switch Q1 is connected to the gate start signal line STV, the input terminal of the first switch Q1 is connected to the output terminal of the charging sub-unit 111, and the output terminal of the first switch Q1 is connected to the start terminal of the gate drive module 200.

[0053] In this embodiment, a switching transistor is used to realize the switching function of the switching subunit 112.

[0054] When the gate start signal STV is invalid, the first switch Q1 is turned off, and the voltage of the charging sub-unit 111 cannot be output to the gate drive module 200 through the first switch Q1.

[0055] When the gate-start signal STV is valid, the first switch Q1 is turned on, and the voltage of the charging sub-unit 111 is output to the gate drive module 200 through the first switch Q1.

[0056] Furthermore, the charging subunit 111 includes a charging component 1111 and a buffer component 1112, wherein: The input terminal of the charging component 1111 serves as the input terminal of the charging subunit 111, and the output terminal of the charging component 1111 is connected to the charging terminal of the buffer component 1112. The charging terminal of the buffer component 1112 serves as the output terminal of the charging subunit 111.

[0057] The charging component 1111 is used to control the charging behavior of the buffer component 1112.

[0058] The buffer component 1112 is used to perform charging and output the line start signal.

[0059] In an embodiment where the pre-charge unit 110 includes a charging subunit 111 but does not include a switching subunit 112: When the gate start signal STV is invalid, the charging component 1111 does not charge the buffer component 1112; when the gate start signal STV is valid, the charging component 1111 charges the buffer component 1112 through the gate start signal STV; the buffer component 1112 provides a row start signal to the gate drive module 200 based on the charging status.

[0060] In an embodiment where the pre-charge unit 110 includes a charging subunit 111 and a switching subunit 112: When the gate start signal STV is invalid, the charging component 1111 charges the buffer component 1112 through the power signal line; when the gate start signal STV is valid, the buffer component 1112 outputs a row start signal to the gate drive module 200 through the switch subunit 112.

[0061] Furthermore, the charging component 1111 includes a second switching transistor Q2, wherein: The input terminal of the second switch Q2 serves as the input terminal of the charging component 1111, the control terminal of the second switch Q2 is connected to the input terminal of the second switch Q2, and the output terminal of the second switch Q2 serves as the output terminal of the charging component 1111.

[0062] In this embodiment, a second switch Q2 is used to control the charging component 1111.

[0063] In an embodiment where the pre-charge unit 110 includes a charging subunit 111 but does not include a switching subunit 112: When the gate start signal STV is invalid, the second switch Q2 is turned off and the buffer component 1112 is not charged; when the gate start signal STV is valid, the second switch Q2 is turned on and the gate start signal STV charges the buffer component 1112 through the second switch Q2.

[0064] In an embodiment where the pre-charge unit 110 includes a charging subunit 111 and a switching subunit 112: The second switch Q2 is turned on by the power supply signal and charges the buffer component 1112 through the power supply signal.

[0065] Furthermore, the buffer assembly 1112 includes a first capacitor C1; wherein: The first terminal of the first capacitor C1 serves as the charging terminal of the buffer component 1112, and the second terminal of the first capacitor C1 is grounded.

[0066] In this embodiment, a first capacitor C1 is provided to charge the buffer component 1112.

[0067] When there is a voltage input at the first terminal of the first capacitor C1, the first capacitor C1 is charged, and a start signal with a charging voltage equivalent to the output voltage is output through the first terminal of the first capacitor C1.

[0068] Furthermore, the switching unit 120 includes a third switching transistor Q3; wherein: The control terminal of the third switch Q3 is connected to the clock signal line CK, the input terminal of the third switch Q3 is connected to the start terminal of the gate drive module 200, and the output terminal of the third switch Q3 is grounded.

[0069] In this embodiment, a third switch Q3 is set to realize the switching function of the switching unit 120.

[0070] When the clock signal CK is invalid, the third switch Q3 is turned off, and the start-up terminal of the gate drive module 200 is not grounded; when the clock signal CK is valid, the third switch Q3 is turned on, the start-up terminal of the gate drive module 200 is grounded, and the gate drive module 200 is not controlled by the STV signal to avoid leakage.

[0071] The overall implementation principle of this application is explained below: In an embodiment where the pre-charge unit 110 includes a charging subunit 111 and a switching subunit 112: When the gate start signal STV is invalid, the second switch Q2 is turned off, the first capacitor C1 is not charged, there is no row start signal input at the start terminal of the gate drive module 200, the clock signal CK is invalid, the third switch Q3 is turned off, and the start terminal of the gate drive module 200 is not de-grounded.

[0072] After the gate start signal STV is triggered and becomes valid: 1. The second switch Q2 turns on, the first capacitor C1 begins to charge, and the voltage of the first capacitor C1 gradually increases, and the voltage at the start-up terminal of the gate drive module 200 gradually increases; 2. When the voltage of the first capacitor C1 rises to the effective voltage of the gate start signal STV, it enters the effective stage, the voltage at the start-up terminal of the gate drive module 200 reaches the effective voltage of the gate start signal STV, the gate drive module 200 is in the pre-charging stage, the clock signal CK is invalid, and the third switch Q3 is turned off; 3. When the clock signal CK is triggered and becomes valid, the third switch Q3 turns on, the start-up terminal of the gate drive module 200 is grounded, the row start signal in the gate drive module 200 is invalid, and the clock signal CK triggers the output of the scan signal; 4. After the clock signal CK becomes invalid, the third switch Q3 is turned off, and the voltage of the first capacitor C1 is connected to the start-up terminal of the gate drive module 200 again, but the row in this frame does not involve the output of the scan signal; 5. The gate start signal STV becomes invalid, the second switch Q2 is turned off, and the first capacitor C1 gradually discharges.

[0073] In an embodiment where the pre-charge unit 110 includes a charging subunit 111 and a switching subunit 112: When the gate-start signal STV is invalid, the second switch Q2 is turned on under the action of the power supply signal and charges the first capacitor C1. When the first switch Q1 is turned off, the voltage of the first capacitor C1 cannot be output to the gate drive decoupling library. After the gate start signal STV is triggered and becomes valid: 1. The first switch Q1 is turned on, and the voltage of the first capacitor C1 is output as the row start signal to the start terminal of the gate drive module 200. The gate drive module 200 is in the pre-charging stage, the clock signal CK is invalid, and the third switch Q3 is turned off; 2. When the clock signal CK is triggered and becomes valid, the third switch Q3 is turned on, the start terminal of the gate drive module 200 is grounded, the row start signal in the gate drive module 200 is invalid, and the clock signal CK triggers the output of the scan signal; 3. After the clock signal CK becomes invalid, the third switch Q3 is turned off, and the start terminal of the gate drive module 200 is connected to the voltage of the first capacitor C1 again, but the row in this frame does not involve the output of the scan signal; 4. The gate start signal STV becomes invalid, and the first switch Q1 is turned off.

[0074] The overall scheme of this application is described below: The explanation will take the gate drive module 200 in the first row as an example. Example 1: By modifying the mechanism of direct access of the gate start signal STV, a charging component 1111, a buffer component 1112, and a switching unit 120 are added.

[0075] At this time, when the gate start signal STV enters a high level, positive charge enters the first capacitor C1 of the buffer component 1112 and the first gate drive module 200 that was previously connected to the gate start signal STV after passing through the second switch Q2 of the charging component 1111. When the charge of the buffer component 1112 and the Q-point signal voltage of all gate drive modules 200 directly connected to the gate start signal line STV rise to the gate high voltage VGH and cannot be increased further, the first clock signal CK enters a high level. At this time, the first switch Q1 of the switching unit 120 will release the charge on the gate of the first drive switch TF1 of the first gate drive module 200 and the charge on the first capacitor C1 of the buffer component 1112 to turn off the first drive switch TF1. This prevents leakage current from the Q-point voltage of the first gate drive module 200, thereby maintaining the Q-point at a high voltage and avoiding affecting the output of the scan signal. Similarly, for the other gate drive modules 200, when the second clock signal CK, the third clock signal CK, and the fourth clock signal CK enter a high level, the gate start signal STV of the corresponding gate drive module 200 can be interrupted by the first switch Q1 in the switch unit 120, thereby controlling the Q point so that the position is not affected by leakage current.

[0076] Furthermore, to prevent the voltage of the gate start signal STV from being released along with the voltage of the first capacitor C1 in other rows when the switching unit 120 is turned on, the second switch Q2 in the charging component 1111 should not be set too large. Specifically, the size of the second switch Q2 can be set based on the actual circuit parameters.

[0077] Furthermore, given the size of the second switch Q2, in order to ensure that the gate drive module 200 is fully precharged during the precharge phase, the distance between the rising edge of the gate start signal STV and the rising edge of the first clock signal CK can be appropriately increased.

[0078] Example 2: Based on Example 1, the access signal of the charging component 1111 is changed to DC VDD voltage, and a switch subunit 112 is added and controlled by the gate start signal STV.

[0079] First, the VDD signal continuously charges the charging subunit 111 through the charging component 1111, ensuring that the first capacitor C1 of the buffer component 1112 is fully charged before the gate start signal STV is turned on. At this time, the gate start signal STV enters a high level, and the switching subunit 112 is turned on simultaneously. The charge on the first capacitor C1 of the buffer component 1112 enters the first gate drive module 200, gradually increasing the Q-point signal voltage of all gate drive modules 200 directly connected to the gate start signal line STV until VGH cannot be increased further. Then, the first clock signal CK enters a high level. At this time, the first switch Q1 of the switching unit 120 releases the charge on the gate of the first drive switch TF1 of the first gate drive module 200 and the charge on the first capacitor C1 of the buffer component 1112 to turn off the first drive switch TF1. This prevents leakage at the Q-point voltage of the first gate drive module 200, maintaining the Q-point at a high voltage and avoiding any impact on the scan signal output. Similarly, for the other gate drive modules 200, when the second clock signal CK, the third clock signal CK, and the fourth clock signal CK enter a high level, the gate start signal STV of the corresponding gate drive module 200 can be interrupted by the first switch Q1 in the switch unit 120, thereby controlling the Q point so that the position is not affected by leakage current.

[0080] Furthermore, to prevent the voltage of the gate start signal STV from being released along with the voltage of the first capacitor C1 in other rows when the switching unit 120 is turned on, the second switch Q2 in the charging component 1111 should not be set too large. Specifically, the size of the second switch Q2 can be set based on the actual circuit parameters.

[0081] Furthermore, since the charging component 1111 is connected to the VDD signal, the gate start signal STV is only responsible for controlling the voltage output of the buffer component 1112. Therefore, there is no need to specifically change the interval between the rising edge of the gate start signal STV and the rising edge of the first clock signal CK, and the signal encoding Code requirement remains unchanged.

[0082] This invention also protects a display panel, see [link to relevant documentation]. Figure 6 The display panel includes a gate start signal line, a clock signal line, and a display driver circuit 10. The structure of the display driver circuit 10 can be referred to in the above embodiment, and will not be repeated here. Therefore, since the display panel of this embodiment adopts the technical solution of the above-described display driver circuit 10, the display panel has all the beneficial effects of the above-described display driver circuit 10.

[0083] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0084] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A display driving circuit, characterized in that, The display driving circuit includes a gate start signal access module and a gate driving module; the gate start signal access module includes multiple pre-charge units and multiple switching units; the control terminal of the pre-charge unit is connected to the gate start signal line, the output terminal of the pre-charge unit is connected to the start terminal of the corresponding gate driving module, the start terminal of the gate driving module is also grounded through the switching unit, and the control terminal of the switching unit is connected to the clock signal line corresponding to the gate driving module; wherein: The precharge unit is used to precharge the voltage and output the corresponding row start signal to the corresponding row's gate drive module based on the gate start signal transmitted by the gate start signal line. The switching unit is used to ground the start-up terminal of the gate drive module of the corresponding row when the clock signal of the corresponding row is valid.

2. The display driving circuit as described in claim 1, characterized in that, The pre-charge unit includes a charging sub-unit, wherein: The input terminal of the charging sub-unit is connected to the gate start signal line, the control terminal of the charging sub-unit is connected to the gate start signal line, and the output terminal of the charging sub-unit is connected to the start terminal of the gate drive module.

3. The display driving circuit as described in claim 2, characterized in that, The effective period of the gate start signal includes a continuously set charging phase and an effective phase; the effective phase is time-consistent with the pre-charging phase of the gate drive module, and during the charging phase, the pre-charging unit charges to the effective voltage of the gate start signal.

4. The display driving circuit as described in claim 1, characterized in that, The pre-charge unit includes a charging subunit and a switching subunit; wherein: The input terminal of the charging subunit is connected to the power signal line, the control terminal of the charging subunit is connected to the power signal line, the output terminal of the charging subunit is connected to the start terminal of the gate drive module through the switching subunit, and the control terminal of the switching subunit is connected to the gate start signal line.

5. The display driving circuit as described in claim 4, characterized in that, The switching subunit includes a first switching transistor; wherein: The control terminal of the first switch is connected to the gate start signal line, the input terminal of the first switch is connected to the output terminal of the charging subunit, and the output terminal of the first switch is connected to the start terminal of the gate drive module.

6. The display driving circuit as described in any one of claims 2 to 5, characterized in that, The charging subunit includes a charging component and a buffer component, wherein: The input terminal of the charging component serves as the input terminal of the charging sub-unit, and the output terminal of the charging component is connected to the charging terminal of the buffer component, with the charging terminal of the buffer component serving as the output terminal of the charging sub-unit.

7. The display driving circuit as described in claim 6, characterized in that, The charging component includes a second switching transistor, wherein: The input terminal of the second switch is used as the input terminal of the charging component, the control terminal of the second switch is connected to the input terminal of the second switch, and the output terminal of the second switch is used as the output terminal of the charging component.

8. The display driving circuit as described in claim 6, characterized in that, The buffer assembly includes a first capacitor; wherein: The first terminal of the first capacitor serves as the charging terminal of the buffer component, and the second terminal of the first capacitor is grounded.

9. The display driving circuit as described in claim 1, characterized in that, The switching unit includes a third switching transistor; wherein: The control terminal of the third switch is connected to the clock signal line, the input terminal of the third switch is connected to the start terminal of the gate drive module, and the output terminal of the third switch is grounded.

10. A display panel, characterized in that, The display panel includes a gate start signal line, a clock signal line, and a display driving circuit as described in any one of claims 1 to 9.

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