A novel switching topology and decoding device for resistor-string DACs

Abstract

This invention discloses a novel switching topology and decoding device suitable for resistor string DACs, including a resistor array, a switch array, and a decoding circuit. The resistor array consists of N identical unit resistors connected in series, with the top end of the resistor array connected to a high-order reference potential Vref+ and the bottom end connected to a low-order reference potential Vref-. The decoding circuit is used to convert the input code of the resistor string DAC into a one-hot code to control the switch array. The switch array includes an MSB control switch and an LSB control switch. The MSB control switch is connected to a node of the resistor array, and the LSB control switch is connected to the output node of the device. This invention enables two-way switching when adjacent binary code values ​​are switched. L -1 / 2 L The probability of switching is only 2 LSB switches, which greatly reduces the probability of multiple switches switching, which helps to improve the accuracy and reliability of the circuit, reduce the power consumption of the switches, and is suitable for high-precision application scenarios.

Description

Technical Field

[0001] This invention relates to the field of resistive digital-to-analog converter technology, and specifically to a novel switching topology and decoding device suitable for resistor string DACs. Background Technology

[0002] Resistive DACs were among the earliest commercially available DAC architectures. They utilize the voltage divider properties of a resistor network to convert digital code into analog voltage. The top of the resistor network is connected to a high-order reference voltage, and the bottom is connected to a low-order reference voltage. The output analog voltage is determined by the ratio of the resistance between the node connected to the output node and the low-order reference voltage to the total resistance. For N-bit DACs, at least 2... N One unit resistance and 2 N A resistive DAC is simple in structure and low in cost, generally consisting of three parts: a resistor array, control switches, and a decoding circuit. Its simplified logic makes it suitable for mass production. Furthermore, the biggest advantage of a resistive DAC is its excellent linearity and monotonicity. Even with resistor mismatch, the DAC output remains monotonic, achieving low INL and DNL, ​​inherently possessing monotonicity. The control switches in resistive DACs mostly use NMOS transistors. The accuracy of a resistive DAC is affected by the on-resistance and parasitic capacitance of the NMOS transistors. Therefore, when designing a resistive DAC, it is necessary to select appropriate switch sizes that meet the signal settling time requirements while minimizing the impact of parasitic capacitance. In the design of the resistive DAC switch topology, it is necessary to reduce the number of control switches and the number of control switches directly connected to the output.

[0003] For resistor divider DACs formed by connecting unit resistors in series, there are currently three main switching methods. The first method directly uses binary codes for switching control, forming a tree-structured switch array, such as... Figure 1 As shown; the advantage of this switch control method is that it eliminates the need for a decoding circuit, but the disadvantage is that the switch array is too large; for an N-bit DAC, a total of 2... N - Two switches are not suitable for high-precision applications. The second type is a full decoding method, such as... Figure 2 As shown, the binary code is converted to Gray code by a decoder, and each voltage divider value is transmitted by only one switch, which minimizes the total on-resistance and parasitic capacitance, and only requires 2 N The first method involves a single switch, but its drawback is the complexity of the decoding circuit and its unsuitability for high-precision applications. The third method is a compromise between the first two, rationally dividing the binary code into MSB and LSB for separate decoding. This requires first decoding the binary code into Gray code, and then decoding the Gray code into one-hot code, such as... Figure 3 As shown, the horizontal axis represents L-bit LSB decoding, and the vertical axis represents M-bit MSB decoding, where N = M + L. An N-bit DAC requires 2... M (2 L With +1) switches, the advantage is that it appropriately reduces the number of switches and the decoding difficulty, making it suitable for medium-to-high precision applications. The disadvantage is that there are 2... when switching between adjacent code values. L -1 / 2 L The probability is 2 L+1 Even without forming a circuit, multiple LSB switches can cause voltage disturbances due to charge injection, and they also result in power loss. Summary of the Invention

[0004] The purpose of this invention is to address the aforementioned problems by providing a novel switching topology and decoding device suitable for resistor-string DACs, capable of switching between adjacent binary code values, with 2 L -1 / 2 L The probability of switching is only 2 LSB switches, which greatly reduces the probability of multiple switches switching, which helps to improve the accuracy and reliability of the circuit, reduce the power consumption of the switches, and is suitable for high-precision application scenarios.

[0005] The technical solution adopted in this invention is as follows: A novel switching topology and decoding device suitable for resistor-string DACs, the device comprising a resistor array, a switch array, and a decoding circuit; The resistor array comprises multiple resistors connected in series to form a resistor array. The top of the resistor array is connected to the high-level reference potential Vref+, and the bottom of the resistor array is connected to the low-level reference potential Vref-. The decoding circuit is used to convert the resistor string DAC input code into a one-hot code to control the switch array; The switch array includes an MSB control switch and an LSB control switch. The MSB control switch is connected to the resistor array node, and the LSB control switch is connected to the device output node.

[0006] Furthermore, the resistor array comprises N identical unit resistors connected in series, used to divide the Vref+-Vref- voltage into 2... N A series of differential voltages.

[0007] Furthermore, in the decoding circuit, the resistor string DAC input code is a binary code divided into an Mbit MSB part and an Lbit LSB part. The Mbit MSB binary code is decoded into 2... M A one-hot code for 2^3 π, where M < 2^3 π. M -1:0>, LbitMSB binary code decoded as 2 L A one-hot code for a given number of bits, where L<2. L -1:0>.

[0008] Furthermore, N = M + L, and when N is even, M = L = N / 2.

[0009] Furthermore, the switch array includes 2 M 2 MSB unique hot codes control L Group control switches, a total of 2 M+L One MSB control switch, 2 L 2 LSB one-hot codes control L One LSB control switch.

[0010] Furthermore, in the decoding circuit, let D... <n-1:0>For an N-bit binary code, split the binary code into an M-bit MSB code and an L-bit LSB code, including the high-order binary code D. <n-1:n-m>and the low-order binary code D <n-m-1:0>; Among them, the high-order MSB code is converted into binary code D by a binary code-one-hot code decoder. <n-1:n-m>Decoded as a one-hot code M<2 M -1:0> controls the switches connected to the resistor array nodes; The low-order binary code D <n-m-1:0>With the high-order binary code D <n-1:n-m>The least significant bit D <n-m>Perform a NOR operation, then decode the binary code to a one-hot code, resulting in a one-hot code L<2. L -1:0> The switch connected to the output node of the control device.

[0011] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: This invention discloses a novel switching topology and decoding device suitable for resistor-string DACs. When the input changes between adjacent binary codes, i.e., when adjacent binary code values ​​switch, there are 2... L -1 / 2 L The probability of switching between only two switches is 1 / 2. L The probability needs to be switched to 2. L+1 There are 2 switches compared to the third option. L -1 / 2 L The probability needs to be switched to 2. L+1 There are 1 / 2 switches. L The probability of needing to switch two switches is greatly reduced, significantly decreasing the probability of multiple switch switching, improving reliability while reducing power consumption, and making it suitable for high-precision designs. Attached Figure Description

[0012] Figure 1 This is the switch control diagram of the existing first scheme, which is a tree structure. Figure 2 This is the control diagram for the fully decoded switch in the second existing scheme; Figure 3 The control diagram for the segmented decoding switch in the existing third scheme; Figure 4 This is a diagram of the resistor string DAC structure in the device of the present invention; Figure 5 This is a schematic diagram of the decoding circuit in the device of the present invention; Figure 6 This is a schematic diagram of a 4-bit resistor string DAC in the verification example of this invention. Detailed Implementation

[0013] The present invention will now be described in detail with reference to the accompanying drawings.

[0014] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0015] Example This embodiment provides a novel switching topology and decoding device suitable for resistor-string DACs, such as... Figure 4 As shown, the N-bit resistor string DAC structure in this embodiment includes three parts: a resistor array, a switch array, and a decoding circuit. The resistor array consists of N identical unit resistors connected in series. The top of the array is connected to the high-order reference potential Vref+, and the bottom is connected to the low-order reference potential Vref-. The voltage Vref+ - Vref- is divided into two voltage levels by resistor voltage division. N A series of differential voltages: Vref-, (Vref+-Vref-) (Vref+-Vref-), ... (Vref+-Vref-); In practical applications, the selection of the unit resistor value needs to take into account resistor mismatch, DAC noise, and the magnitude of the static current in the resistor series.

[0016] In this embodiment, the decoding circuit converts the N-bit resistor string DAC input code into a one-hot code to control the switch array. For high-precision resistor string DACs, the N-bit binary code needs to be decoded separately into an M-bit MSB and an L-bit LSB to reduce decoding complexity. In this embodiment, N = M + L. When N is even, M = L = N / 2. The specific allocation depends on the application scenario. The M-bit MSB binary code is decoded into 2... M A one-hot code for 2^3 π, where M < 2^3 π. M -1:0>, LbitLSB binary code decoded as 2 L A one-hot code for a given number of bits, where L<2. L -1:0>.

[0017] The switch array consists of two parts: an MSB control switch and an LSB control switch. The MSB control switch is directly connected to the resistor string node, and there are a total of 2 M 2 MSB unique hot codes control L Group control switches, a total of 2 M+L Each MSB controls the switch, for example, counting from the high-order reference voltage, the intermediate node between the first and second resistors, the intermediate node between the second and third resistors, and the second... L The resistor and the 2nd L +1 resistor intermediate node directly connected to 2 L Each switch is made up of M<2 M -1> Signal control: When this bit is 1, the switch is closed; when this bit is 0, the switch is open. Next group 2... L Each MSB switch is configured with M<2 M -2> Signal control, and so on, the last group 2 L Each MSB switch is made by M <0> Signal control: The LSB control switch is directly connected to the output node, with a total of 2. L 2 LSB one-hot codes control L A control switch, such as Figure 4 As shown, the first switch of the LSB control switch from left to right is L<2 L -1> control, the second switch is controlled by L<2 L -2> Control, and so on, with the last switch controlled by L. <0> control.

[0018] In this embodiment, the switch array structure has 2 when switching between adjacent binary code values. L -1 / 2 L The probability of switching between only two switches is 1 / 2. L The probability needs to be switched to 2. L+1 There are 2 switches compared to the third option. L -1 / 2 L The probability needs to be switched to 2. L+1 The single switch significantly reduces the probability of switching between multiple switches, improving reliability while reducing power consumption.

[0019] like Figure 5 As shown, in the decoding circuit of the resistor string DAC in this embodiment, let D... <n-1:0>For an N-bit binary code, split the binary code into an M-bit MSB code and an L-bit LSB code, that is, D <n-1:0>Split into high-order D <n-1:n-m>and low position D <n-m-1:0>The high-order MSB code is directly converted into binary code D by a binary code-one-hot code decoder. <n-1:n-m>Decoded as a one-hot code M<2 M -1:0>, controls the switch directly connected to the resistor string node; low-order binary code D <n-m-1:0>It needs to be compared with the high-order binary code D. <n-1:n-m>The least significant bit D <n-m>Perform a NOR operation, then decode the binary code to a one-hot code. The one-hot code L < 2. L -1:0> The switch directly connected to the control and output is used to ensure the correctness of the resistor series DAC function.

[0020] Verification Example like Figure 6 As shown, taking a 4-bit resistor string DAC as an example, the 4-bit resistor string DAC is divided into 2-bit MSB and 2-bit LSB for decoding. The high two bits of the input binary code, i.e., the MSB, are decoded into a one-hot code M<3:0>, which controls the switch directly connected to the resistors. The low two bits of the input binary code, i.e., the LSB, are decoded into a one-hot code L<3:0> through the resistor array, which controls the switch directly connected to the output. Figure 6 In the 4-bit resistor string DAC shown, there are a total of 2 N =2 4 =16 unit resistance, 2 M+L +2 L =20 control switches, of which 2 M+L =16 switches are MSB controlled switches, 2 L =4 switches are LSB control switches; when the MSB remains unchanged and the LSB changes, only one LSB switch is open and one LSB switch is closed. For example, when the input binary code changes from 0000 to 0001, only switch L is controlled. <3> Disconnect, L <2> Closed; when the input binary code changes from 0000 to 0011, only switch L is controlled. <3> Disconnect, L <0> Closed; In the existing third scheme, the 4-bit resistor string DAC, when the MSB remains unchanged and the LSB changes, there are at least 4 LSB switches open and 4 LSB switches closed.

[0021] In summary, the switching topology of this invention minimizes the number of switching actions when the LSB changes. When the input binary code changes continuously, it effectively reduces the number of switching changes, thereby reducing the switching power consumption of the resistor string DAC and improving reliability.

[0022] This article uses specific embodiments to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A novel switching topology and decoding device suitable for resistor-string DACs, characterized in that, The device includes a resistor array, a switch array, and a decoding circuit. The resistor array comprises multiple resistors connected in series to form a resistor array. The top of the resistor array is connected to the high-level reference potential Vref+, and the bottom of the resistor array is connected to the low-level reference potential Vref-. The decoding circuit is used to convert the resistor string DAC input code into a one-hot code to control the switch array; The switch array includes an MSB control switch and an LSB control switch. The MSB control switch is connected to the resistor array node, and the LSB control switch is connected to the device output node.

2. The novel switching topology and decoding device suitable for resistor-string DACs according to claim 1, characterized in that, The resistor array consists of N identical unit resistors connected in series, used to divide the Vref+-Vref- voltage into 2... N A series of differential voltages.

3. The novel switching topology and decoding device suitable for resistor-string DACs according to claim 2, characterized in that, In the decoding circuit, the resistor string DAC input code is a binary code divided into an MbitMSB part and an LbitLSB part. The MbitMSB binary code is decoded as 2. M A one-hot code for 2^3 π, where M < 2^3 π. M -1:0>, LbitMSB binary code decoded as 2 L A one-hot code for a given number of bits, where L<2. L -1:0>.

4. A novel switching topology and decoding device suitable for resistor-string DACs according to claim 3, characterized in that, N = M + L. When N is even, M = L = N / 2.

5. A novel switching topology and decoding device suitable for resistor-string DACs according to claim 3, characterized in that, The switch array includes 2 M 2 MSB unique hot codes control L Group control switches, a total of 2 M+L One MSB control switch, 2 L 2 LSB one-hot codes control L One LSB control switch.

6. A novel switching topology and decoding device suitable for resistor-string DACs according to claim 5, characterized in that, In the decoding circuit, let D <n-1:0>For an N-bit binary code, split the binary code into an M-bit MSB code and an L-bit LSB code, including the high-order binary code D. <n-1:n-m>and the low-order binary code D <n-m-1:0> ；< / n-m-1:0> Among them, the high-order MSB code is converted into binary code D by a binary code-one-hot code decoder. <n-1:n-m>Decoded as a one-hot code M<2 M -1:0> controls the switches connected to the resistor array nodes; The low-order binary code D <n-m-1:0>With the high-order binary code D <n-1:n-m>The least significant bit D <n-m>Perform a NOR operation, then decode the binary code to a one-hot code, resulting in a one-hot code L<2. L -1:0> The switch connected to the output node of the control device.

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