Image processing methods and systems

Abstract

This invention discloses an image processing method and system, relating to the field of image processing, comprising: acquiring an original image, extracting texture features, grayscale types, or color distribution features of the original image, and assigning the original image to one of at least two preset complexity levels based on a comparison between the texture feature values, grayscale types, or color distribution features and a preset threshold; adaptively configuring DSC compression parameters according to the complexity level and generating a compressed bitstream; reliably transmitting the bitstream and control commands to an FPGA through separate UDP data and command channels; after verification by the FPGA, dynamically scheduling cache resources according to image attributes, parsing data, and adaptively matching display timing, ultimately driving the display device. This invention, through intelligent decision-making and a hierarchical architecture, achieves dynamic optimization of compression strategies, improved transmission reliability and resource utilization, effectively solving problems such as poor compression adaptability and unstable transmission in high-resolution image processing.

Description

Technical Field

[0001] This invention belongs to the field of image processing technology, and particularly relates to an image processing method and system. Background Technology

[0002] With the rapid development of display technology, the demand for high frame rate video transmission and display is increasing daily. High-resolution, high-refresh-rate images require extremely high transmission bandwidth, posing a significant challenge to transmission links and display interfaces. The display stream compression standard developed by VESA, as a visually lossless compression technology, can effectively reduce bandwidth requirements.

[0003] Currently, the main solutions for implementing DSC image processing and display include: using the parallel processing capabilities of FPGA to implement the DSC algorithm. However, traditional FPGA solutions have high hardware costs and high power consumption, and the compression parameters are fixed, making it difficult to flexibly adapt to different image content and display scenarios. At the same time, the solution of using a host computer to compress and then transmit the data is prone to problems such as poor transmission reliability, low utilization efficiency of cache resources, and mismatch of display timing.

[0004] Therefore, the present invention provides an image processing method and system. Summary of the Invention

[0005] The purpose of this invention is to solve the problems in the prior art, and to propose an image processing method and system.

[0006] This invention first discloses an image processing method, comprising the following steps: (1) After acquiring the original image, extract the texture features, grayscale types, or color distribution features of the original image, and according to the comparison results of the texture feature values, grayscale types, or color distribution features with the preset threshold, assign the original image to one of at least two preset complexity levels; (2) Based on the preset complexity level of the original image, configure the DSC compression parameters corresponding to the preset complexity level, generate a visually lossless DSC bit stream, and record the corresponding compression parameters; (3) Uploading the DSC bit stream data and control commands to the receiving and processing module through dual channels using different network protocol ports or logical links, including: A UDP data channel is used to transmit the DSC bit stream, and the DSC bit stream carries consecutive frame sequence numbers and CRC32 checksums. The UDP command channel synchronously transmits the compression parameters, control commands, and transmission status feedback information of the DSC bit stream to the receiving and processing module.

[0007] In the above method, at least two preset complexity levels include a first complexity level, a second complexity level, and a third complexity level; In step (2), based on the preset complexity level of the original image, DSC compression parameters corresponding to the preset complexity level are configured, including: A first set of compression parameters is selected for the first complexity level, and the first set of compression parameters is configured with a first preset size of encoding slice, multiple prediction mode and a first compression ratio; A second set of compression parameters is selected for the second complexity level. The second set of compression parameters is configured with a second preset size of encoding slices larger than the first preset size, a balanced prediction mode, and a second compression ratio greater than the first compression ratio. A third set of compression parameters is selected for the third complexity level. The third set of compression parameters is configured with a third preset size encoding slice that is larger than the second preset size, a simplified prediction mode, and a third compression ratio that is larger than the second compression ratio.

[0008] In the above method, the receiving and processing module is an FPGA processing module; the image processing method further includes: (4) Verify the CRC32 checksum to ensure the validity of the input data; (5) Allocate a corresponding level of buffer area based on the preset complexity level of the original image; (6) Perform format parsing and preprocessing on the received DSC bit stream, convert the compressed bit stream into the pixel data format of the display driver; write the parsed DSC bit stream into the DDR buffer for display.

[0009] In the above method, the UDP command channel and the receiving processing module have a response mechanism, including: When a command packet containing compression parameters and control instructions is sent to the receiving and processing module through the UDP command channel; If the receiving and processing module successfully receives and parses the command packet, it returns an acknowledgment response through the UDP command channel; If the sending end does not receive the confirmation response within the preset time, or; When the receiving processing module detects packet loss or CRC check failure, it retransmits the command packet when sending a negative response to the sending end via the UDP command channel.

[0010] In the above method, step (5), which allocates a corresponding level of buffer based on the preset complexity level of the original image, specifically includes: Based on the resolution and refresh rate of the original image and the current storage load status of the DDR cache module, storage blocks of different sizes and access priorities are dynamically allocated to images of different complexity levels; among them, low-latency, high-bandwidth storage areas are preferentially allocated to image content with high complexity and high refresh rate.

[0011] The above method further includes: (7) Through the display adaptation unit of the FPGA processing module, actively read the extended display identification data EDID of the display module, and automatically obtain the optimal resolution, refresh rate and color depth parameters supported by the display module; (8) Based on the obtained EDID information, dynamically configure the pixel clock, horizontal synchronization pulse, and vertical synchronization pulse timing parameters of the MIPI DSI interface; (9) Pack the pixel data after format parsing and preprocessing according to the configured MIPI DSI timing parameters and drive the display module to display it.

[0012] In a second aspect, the present invention discloses an image processing system for performing the image processing method as described in any one of claims 1 to 6, comprising: The host computer module includes: Image acquisition unit, used to acquire raw image data; The image complexity analysis unit is used to extract the texture features, and / or grayscale types, and / or color distribution features of the original image, and divide the image into at least two preset complexity levels according to a preset threshold. The DSC compression strategy unit is used to adaptively configure DSC compression parameters according to the preset complexity level and generate a visually lossless DSC bitstream. A dual-channel transmission and verification unit is configured to transmit data and commands via dual channels, including: A UDP data channel is used to transmit a DSC bit stream, which carries a frame sequence number and a CRC32 checksum. The UDP command channel is used to transmit compression parameters, control commands, and status feedback information. The receiving and processing module is communicatively connected to the host computer module.

[0013] In the above system, the image complexity analysis unit divides the image into at least two preset complexity levels, including a first complexity level, a second complexity level, and a third complexity level, based on a preset threshold. The DSC compression strategy unit adaptively configures DSC compression parameters according to the preset complexity level, including: selecting a first compression parameter set for the first complexity level, wherein the first compression parameter set is configured with a first preset size encoding slice, multiple prediction mode and a first compression ratio; A second set of compression parameters is selected for the second complexity level. The second set of compression parameters is configured with a second preset size of encoding slices larger than the first preset size, a balanced prediction mode, and a second compression ratio greater than the first compression ratio. A third set of compression parameters is selected for the third complexity level. The third set of compression parameters is configured with a third preset size encoding slice that is larger than the second preset size, a simplified prediction mode, and a third compression ratio that is larger than the second compression ratio.

[0014] In the above system, the receiving and processing module adopts an FPGA processing module, and specifically includes: The network port receiving unit is used to receive the DSC bit stream and control commands, and perform CRC32 verification. The real-time cache scheduling unit is used to dynamically allocate DDR storage resources based on image resolution, refresh rate, and storage status. The data processing unit is used to perform format parsing and preprocessing on the DSC bit stream; The storage control unit is used for data read and write interaction with the DDR storage module; The display adaptation unit is used to read the EDID information of the display module and adaptively configure the timing of the display interface; The real-time buffer scheduling unit dynamically adjusts the transmission rate of the host computer module based on the buffer status fed back by the FPGA processing module to prevent buffer overflow at the receiving end.

[0015] In the above system, the system further includes: The display module is used for final image display. The MIPI interface module is used to convert the compressed bitstream output by the receiving and processing module into a signal that conforms to the MIPI DSI protocol and drive the display module to work. The DDR storage module is connected to the receiving and processing module and is used to cache data.

[0016] In the above system, the real-time cache scheduling unit is configured as follows: Monitor the current load and fragmentation of the DDR storage module; Based on the resolution, refresh rate, and image complexity level defined by the image complexity analysis unit, the size and location of storage blocks are dynamically divided and allocated. Allocate contiguous storage space with high access priority for high refresh rate video data.

[0017] In the above system, the display adaptation unit is configured as follows: Read the EDID information of the display module; The EDID information is parsed to obtain the physical resolution, supported refresh rate range, color format, and power timing requirements of the display module. Based on the analysis results, the pixel clock frequency, line and field synchronization timing parameters, and physical layer driving voltage of the MIPI interface unit are dynamically generated and configured.

[0018] In the above system, an error control unit is provided between the dual-channel transmission and verification unit and the network port receiving unit, including: When the network port receiving unit detects data packet loss or CRC32 check failure, it sends a retransmission request containing the lost frame sequence number or slice sequence number to the host computer intelligent decision layer through the UDP command channel. Upon receiving a retransmission request, the dual-channel transmission and verification unit retransmits the specified data packet.

[0019] This invention reduces the requirements for FPGA hardware performance and logic resources by placing DSC compression and strategy decision-making tasks on the host computer, thereby reducing system cost and power consumption. At the same time, this solution designs an adaptive compression strategy based on image content complexity, which optimizes compression efficiency and bandwidth usage while ensuring visual losslessness. It adopts a dual-channel reliable transmission mechanism that separates commands and data, combined with CRC check and acknowledgment retransmission, to ensure the integrity and correctness of data transmission. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of dual-channel data and command processing in an image processing method disclosed in this invention; Figure 2 This is a flowchart illustrating the workflow of the FGPA module in an image processing method disclosed in this invention. Figure 3 This is a flowchart illustrating the process of driving the display module in an image processing method disclosed in this invention. Figure 4 This is a model diagram of a basic image processing system disclosed in this invention. Detailed Implementation

[0021] To facilitate understanding of this application and to make the aforementioned objectives, features, and advantages of this application more apparent, a detailed description of specific embodiments of this application is provided below in conjunction with the accompanying drawings. Numerous specific details are set forth in the following description to provide a thorough understanding of this application, and preferred embodiments are shown in the accompanying drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application. This application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. In the description of this application, "several" means at least one, such as one, two, etc., unless otherwise explicitly specified. It should be noted that when an element is referred to as being "fixed to" another element, it can be directly attached to the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementations. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is only for describing particular implementations and is not intended to limit the scope of this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0022] Reference Figure 1-4 An image processing method, the method comprising: (1) After acquiring the original image, extract the texture features, grayscale types, or color distribution features of the original image, and according to the comparison results of the texture feature values, grayscale types, or color distribution features with the preset threshold, assign the original image to one of at least two preset complexity levels; This step involves acquiring raw, uncompressed image data via an external device or file system, and supports multi-resolution image input. Input source: Industrial cameras are used to capture images in real time via interfaces such as Camera Link and USB3 Vision.

[0023] Storage devices: Load still images (such as BMP, PNG, RAW formats) from hard drives or memory.

[0024] Software generation: Test images are generated by graphics software or simulation tools.

[0025] Among the supported formats and parameters: Resolution: Supports 2K (2048×1080), 4K (3840×2160), etc.

[0026] Color depth: Supports 8 / 10 / 12-bit RGB or YCbCr 4:4:4 (2) Based on the preset complexity level of the original image, configure the DSC compression parameters corresponding to the preset complexity level, generate a visually lossless DSC bit stream, and record the corresponding compression parameters; (3) Uploading the DSC bit stream data and control commands to the receiving and processing module through dual channels using different network protocol ports or logical links, including: A UDP data channel is used to transmit the DSC bit stream, and the DSC bit stream carries consecutive frame sequence numbers and CRC32 checksums. The UDP command channel synchronously transmits the compression parameters, control commands, and transmission status feedback information of the DSC bit stream to the receiving and processing module. In step (1), at least two preset complexity levels are included: a first complexity level, a second complexity level, and a third complexity level. The first complexity level can be referred to as low complexity, the second complexity level as medium complexity, and the third complexity level as high complexity. The goal is to quickly and accurately predict the "difficulty" of an image when compressed by DSC without performing full compression coding. The higher the difficulty, the more conservative the parameters are needed to ensure visual losslessness; the lower the difficulty, the more aggressive the parameters can be used to save bandwidth.

[0027] The distinction between the above levels is derived from the image's texture features and / or grayscale types and / or color distribution features.

[0028] Taking an 8-bit image as an example, when classifying the complexity level by grayscale types, images with fewer than 50 grayscale types can be classified as low-complexity images, images with 50 to 150 grayscale types can be classified as medium-complexity images, and images with 150 to 255 grayscale types can be classified as high-complexity images.

[0029] When classifying images into predefined complexity levels based on color distribution characteristics, images containing only a single color are classified as low complexity, images containing multiple colors that are evenly distributed are classified as medium complexity, and images containing multiple colors that are mixed without any pattern are classified as high complexity.

[0030] Optionally, color distribution characteristics can be analyzed from the following three aspects: 1. Assess color richness and dispersion by statistically analyzing the entropy of the image color histogram or the number of different color values; 2. Calculate the proportion of the dominant color tone to determine the color concentration; 3. Analyze the gradients or variances of the Cb and Cr chromaticity components separately in the YCbCr color space to capture the degree of change in the chromaticity plane.

[0031] When classifying images into predefined complexity levels based on texture features, images with dense and complex textures, such as fine hairs, forests, or noise, are classified as high-complexity images. Images with simple textures, no complex textures, or flat areas are classified as medium-complexity images. All other images are classified as medium-complexity images.

[0032] Optionally, two calculation modes can be used. The first calculation mode quantifies the spatial texture density and sharpness by calculating the gradient magnitude and variance of the image in the horizontal and vertical directions. For example, the Sobel operator can be used for calculation. Images with larger gradient magnitude and variance are high-complexity images, which are characterized by complex textures, while images with gradient magnitude and variance close to zero are low-complexity images, which are characterized by relatively flat areas in most regions of the image. In the second calculation mode, the relationship between each pixel and its neighborhood is analyzed using a local binary model, and the regularity and complexity of the texture are reflected by the entropy value of its histogram.

[0033] When performing complexity classification, if a threshold determination rule is used, one or more of the extracted feature values ​​can be used to perform the classification using a threshold determination rule or a lightweight machine learning classifier. The threshold determination is a preset threshold that is set empirically based on actual product data. The following specific steps are used to determine the threshold for image complexity classification: Step 1: Set empirical thresholds for multiple parameters of the image, including: high frequency energy, gradient variance, color entropy, and set empirical thresholds. Each parameter has two preset thresholds, high and low. Step 2: After setting the preset threshold, set the specific rules for image complexity classification. In this embodiment, when the high-frequency energy, gradient variance and color entropy all exceed the preset high threshold, the image is classified as high complexity. When the high-frequency energy, gradient variance, and color entropy are all below a preset low threshold, the image is classified as low complexity. All other cases are classified as medium complexity. Step 3: Complete the image complexity classification using the specific rules described above.

[0034] When using a machine learning classifier to classify complexity, sample images are required. Features of the above parameters are extracted and complexity labels are manually assigned. Then, a classifier is trained to classify image complexity. The classifier can be a decision tree or a small neural network. The above method is more intelligent and can handle complex nonlinear relationships between features.

[0035] In step (2), based on the preset complexity level of the original image, DSC compression parameters corresponding to the preset complexity level are configured, including: A first set of compression parameters is selected for the first complexity level, and the first set of compression parameters is configured with a first preset size of encoding slice, multiple prediction mode and a first compression ratio; A second set of compression parameters is selected for the second complexity level. The second set of compression parameters is configured with a second preset size of encoding slices larger than the first preset size, a balanced prediction mode, and a second compression ratio greater than the first compression ratio. A third set of compression parameters is selected for the third complexity level. The third set of compression parameters is configured with a third preset size encoding slice that is larger than the second preset size, a simplified prediction mode, and a third compression ratio that is larger than the second compression ratio.

[0036] The purpose of the above steps is to dynamically configure the compression parameter set of the DSC encoder according to the classification of image complexity, so as to achieve the optimal balance between bandwidth and image quality without visual loss. The compression parameter set mainly includes slice size, prediction mode and quantization parameters. Regarding slice size: For highly complex images, a smaller slice size, such as 128 pixels, is used to reduce spatial prediction distance, more finely adapt to local texture changes, and ensure detail preservation; for low-complexity images, a larger slice size, such as 256 pixels, is used to significantly reduce slice header overhead and improve overall compression efficiency and throughput; for medium-complexity images, a compromise default size, such as 192 pixels / slice, is used.

[0037] Regarding the selection of prediction modes: for highly complex images, enable all intra-frame prediction modes, such as block prediction, median prediction, and adaptive color prediction, and increase the search weight of complex modes to reduce prediction residuals; for low-complexity images, disable some complex modes or prioritize simple and efficient modes such as median prediction to reduce computational load.

[0038] Regarding the adjustment of quantization parameters (QP): set a stricter upper limit for quantization parameters for highly complex images to prevent texture blurring or blockiness caused by overly coarse quantization; allow a more relaxed range of quantization parameters for low-complexity images to reduce the bit rate to a greater extent in areas that are not visually perceptible.

[0039] In step (3), the UDP command channel and the receiving processing module have a response mechanism, including: When a command packet containing compression parameters and control instructions is sent to the receiving and processing module through the UDP command channel; If the receiving and processing module successfully receives and parses the command packet, it returns an acknowledgment response through the UDP command channel; If the sending end does not receive the confirmation response within the preset time, or; When the receiving processing module detects packet loss or CRC check failure, it retransmits the command packet when sending a negative response to the sending end via the UDP command channel.

[0040] In this invention, data and commands are transmitted through dual channels. The UDP data channel encapsulates frame sequence numbers, slice sequence numbers, and CRC32 checksums in its data packets. The UDP command channel is responsible for transmitting compression parameter set numbers, synchronization control commands, and possible dynamic quality adjustment commands. The acknowledgment mechanism used in this channel ensures that critical commands are correctly received by the receiving and processing module, thus effectively reducing the transmission error rate. When the receiving and processing module detects packet loss, it sends a NACK (negative acknowledgment) and retransmission request to the host computer through the command channel, indicating the lost frame / slice sequence number. Upon receiving the request, the host computer can quickly initiate a retransmission command, solving the problems of packet loss and bitstream corruption in traditional single-channel transmission.

[0041] In one embodiment, the receiving and processing module is an FPGA processing module; the image processing method further includes: (4) Verify the CRC32 checksum to ensure the validity of the input data; (5) Based on the preset complexity level of the original image, allocate a corresponding level of cache area. According to the resolution, refresh rate of the original image and the current storage load status of the DDR cache module, dynamically allocate storage blocks of different sizes and access priorities for images of different complexity levels; wherein, low-latency and high-bandwidth storage areas are preferentially allocated for image content with high complexity level and high refresh rate. (6) Perform format parsing and preprocessing on the received DSC bit stream, convert the compressed bit stream into the pixel data format of the display driver; write the parsed DSC bit stream into the DDR buffer for display.

[0042] (7) Through the display adaptation unit of the FPGA processing module, actively read the extended display identification data EDID of the display module, and automatically obtain the optimal resolution, refresh rate and color depth parameters supported by the display module; (8) Based on the obtained EDID information, dynamically configure the pixel clock, horizontal sync pulse, and vertical sync pulse timing parameters of the MIPI DSI interface to ensure that the signal is perfectly matched with the display module; (9) Pack the pixel data after format parsing and preprocessing according to the configured MIPI DSI timing parameters and drive the display module to display it, so as to adapt to different cable lengths and panel loads and ensure signal integrity.

[0043] In a second aspect, the present invention provides an image processing system for performing the above-described image processing method, comprising: The host computer module includes: Image acquisition unit, used to acquire raw image data; The image complexity analysis unit is used to extract the texture features, and / or grayscale types, and / or color distribution features of the original image, and divide the image into at least two preset complexity levels according to a preset threshold. The DSC compression strategy unit is used to adaptively configure DSC compression parameters according to the preset complexity level and generate a visually lossless DSC bitstream. A dual-channel transmission and verification unit is configured to transmit data and commands via dual channels, including: A UDP data channel is used to transmit a DSC bit stream, which carries a frame sequence number and a CRC32 checksum. The UDP command channel is used to transmit compression parameters, control commands, and status feedback information. The receiving and processing module is communicatively connected to the host computer module.

[0044] The image complexity analysis unit divides the image into at least two preset complexity levels, including a first complexity level, a second complexity level, and a third complexity level, based on a preset threshold. These are respectively represented as low complexity level, medium complexity level, and high complexity level.

[0045] The goal of the image complexity analysis unit is to quickly and accurately predict the difficulty of DSC compression of an image without performing full compression encoding. When the difficulty is higher, it is classified as high complexity and more conservative parameters are set to ensure visual losslessness. When the difficulty is lower, it is classified as low complexity and more aggressive parameters are used to save bandwidth.

[0046] The DSC compression strategy unit adaptively configures DSC compression parameters according to the preset complexity level, including: selecting a first compression parameter set for the first complexity level, wherein the first compression parameter set is configured with a first preset size encoding slice, multiple prediction mode and a first compression ratio; A second set of compression parameters is selected for the second complexity level. The second set of compression parameters is configured with a second preset size of encoding slices larger than the first preset size, a balanced prediction mode, and a second compression ratio greater than the first compression ratio. A third set of compression parameters is selected for the third complexity level. The third set of compression parameters is configured with a third preset size encoding slice that is larger than the second preset size, a simplified prediction mode, and a third compression ratio that is larger than the second compression ratio.

[0047] The DSC compression strategy unit dynamically configures the core compression parameter set of the DSC encoder based on the labels output by the image complexity analysis unit, achieving the optimal balance between bandwidth and image quality without visual loss. The core compression parameter set includes slice size, prediction mode, and quantization parameters.

[0048] In the dual-channel transmission and verification unit, the UDP data channel is responsible for transmitting the DSC compressed bit stream. Each data packet encapsulates a frame sequence number, a slice sequence number, and a CRC32 checksum. The receiving and processing module reassembles the data based on the frame / slice sequence number and uses CRC32 to verify data integrity. The UDP command channel is responsible for transmitting compression parameter set numbers, synchronization control commands, and possible dynamic quality adjustment commands. This channel employs an acknowledgment mechanism to ensure that critical commands are correctly received by the FPGA.

[0049] In one feasible embodiment, the receiving and processing module employs an FPGA processing module, and specifically includes: The network port receiving unit is used to receive the DSC bit stream and control commands, and perform CRC32 verification. A real-time cache scheduling unit is used to dynamically allocate DDR storage resources based on image resolution, refresh rate, and storage status. The real-time cache scheduling unit is configured as follows: Monitor the current load and fragmentation of the DDR storage module; Based on the resolution, refresh rate, and image complexity level defined by the image complexity analysis unit, the size and location of storage blocks are dynamically divided and allocated. Allocate contiguous storage space with high access priority for high refresh rate video data. The data processing unit is used to perform format parsing and preprocessing on the DSC bit stream; The storage control unit is used for data read and write interaction with the DDR storage module; The display adaptation unit is used to read the EDID information of the display module and adaptively configure the timing of the display interface. The display adaptation unit is configured as follows: Read the EDID information of the display module; The EDID information is parsed to obtain the physical resolution, supported refresh rate range, color format, and power timing requirements of the display module. Based on the analysis results, the pixel clock frequency, line and field synchronization timing parameters, and physical layer driving voltage of the MIPI interface unit are dynamically generated and configured.

[0050] In one feasible embodiment, an error control unit is provided between the dual-channel transmission and verification unit and the network port receiving unit, including: When the network port receiving unit detects data packet loss or CRC32 check failure, it sends a retransmission request containing the lost frame sequence number or slice sequence number to the host computer intelligent decision layer through the UDP command channel. Upon receiving a retransmission request, the dual-channel transmission and verification unit retransmits the specified data packet.

[0051] The FPGA processing module is also equipped with a real-time buffer scheduling unit, which dynamically adjusts the transmission rate of the host computer module based on the buffer status fed back by the receiving processing module to prevent buffer overflow at the receiving end.

[0052] In one feasible embodiment, the system further includes a display module for final image display; The MIPI interface module is used to convert the compressed bitstream output by the receiving and processing module into a signal that conforms to the MIPI DSI protocol and drive the display module to work. The DDR storage module is connected to the receiving and processing module and is used to cache data.

[0053] Specific analysis using real-world examples. Case 1: An aerial photograph of a city with a resolution of 3840 x 2160 and a color depth of 8-bit RGB bitmap. When processing this image, several features are first extracted, including: Texture feature extraction: Calculate its gradient magnitude / variance. Through calculation, it was found that building edges, window details, road markings, etc. generated a large number of high-frequency components, the gradient values ​​in the horizontal and vertical directions were high, and the overall gradient variance was large.

[0054] Color distribution characteristics: The image has rich and continuous colors, and its color histogram entropy value is high. After converting the image to the YCbCr space, the changes in Cb and Cr components are also more obvious, and the chromaticity gradient value is high.

[0055] Therefore, based on the above feature analysis, this image is classified as a high-complexity image.

[0056] After receiving highly complex tags, the encoder adopts a conservative parameter configuration that prioritizes image quality.

[0057] Tile Size: Use smaller tiles, choosing 128 pixels / tile. Divide each row of 3840 pixels into 30 independent tiles for encoding. This increases tile header overhead but makes spatial predictions within each tile more accurate, better capturing local details of dense buildings and roads, and preventing errors from propagating across tiles. Value | Prediction Mode: Enable all intra-frame prediction modes, including block prediction, median prediction, adaptive color prediction, etc. In the mode decision unit, increase the search weight of complex modes such as adaptive color prediction, making them more proactive in searching for the best prediction in color-changing regions (such as the boundary between rooftops and the sky) to minimize residuals. Compression Result: Ultimately, this 4K image was compressed with high fidelity. Although the bitrate is relatively high due to the conservative strategy employed, it successfully preserved all critical visual details, achieving the goal of lossless visual reproduction and meeting the requirements for high-quality display.

[0058] Case 2: A cartoon or anime-style character illustration with the following characteristics: clear character outline, smooth solid color or simple gradient background, large monochrome areas in the character's clothing, resolution of 1920 x 1080, and 8-bit RGB color depth. When processing this image, several features are first extracted, including: Texture feature extraction: Gradient magnitude / variance calculation for this image: Calculation revealed that the main gradients are concentrated along the clear character outlines. Most areas of the image are relatively flat, with gradient values ​​close to zero. The overall gradient variance is low.

[0059] Color distribution characteristics: The number of colors is limited, mainly consisting of large blocks of pure color. The color histogram entropy value is very low. In the YCbCr space, except at the outline edge, the Cb and Cr components in the large areas change very gently.

[0060] The image's texture features and color distribution features are compared with a preset threshold. Since both are lower than the preset low complexity threshold, the image is classified as a low complexity image.

[0061] The encoder located in the host computer module receives the "low complexity" tag, and therefore enables a more aggressive parameter configuration in order to save bandwidth. It includes the following specific parameter configurations: Slice size: Choose a larger 256 pixels / slice. Dividing each row of 1920 pixels into 8 slices reduces slice header overhead, improving overall compression efficiency and encoder throughput. Prediction within large slices is also very effective due to the flatness of the image.

[0062] Prediction Mode: Simplified prediction mode disables some computationally complex prediction modes and uses simple modes such as median prediction, reducing the logic operation load and power consumption of the FPGA.

[0063] Ultimately, the image was efficiently compressed. Thanks to the parameter configuration strategy described above, the compressed bitrate is very low, yet the image quality remains good, ensuring a good viewing experience while saving significant bandwidth resources for data transmission and storage.

[0064] As is known from common technical knowledge, this invention can be implemented through other embodiments that do not depart from its spirit or essential characteristics. Therefore, the disclosed embodiments described above are merely illustrative and not exhaustive. All modifications within the scope of this invention or its equivalents are included in this invention.

Claims

1. An image processing method, characterized in that, The method includes: (1) After acquiring the original image, extract the texture features, grayscale types, or color distribution features of the original image, and according to the comparison results of the texture feature values, grayscale types, or color distribution features with the preset threshold, assign the original image to one of at least two preset complexity levels; (2) Based on the preset complexity level of the original image, configure the DSC compression parameters corresponding to the preset complexity level, generate a visually lossless DSC bit stream, and record the corresponding compression parameters; (3) Uploading the DSC bit stream data and control commands to the receiving and processing module through dual channels using different network protocol ports or logical links, including: A UDP data channel is used to transmit the DSC bit stream, and the DSC bit stream carries consecutive frame sequence numbers and CRC32 checksums. The UDP command channel synchronously transmits the compression parameters, control commands, and transmission status feedback information of the DSC bit stream to the receiving and processing module.

2. The image processing method according to claim 1, characterized in that, At least two preset complexity levels are included, namely, a first complexity level, a second complexity level, and a third complexity level; In step (2), based on the preset complexity level of the original image, DSC compression parameters corresponding to the preset complexity level are configured, including: A first set of compression parameters is selected for the first complexity level, and the first set of compression parameters is configured with a first preset size of encoding slice, multiple prediction mode and a first compression ratio; A second set of compression parameters is selected for the second complexity level. The second set of compression parameters is configured with a second preset size of encoding slices larger than the first preset size, a balanced prediction mode, and a second compression ratio greater than the first compression ratio. A third set of compression parameters is selected for the third complexity level. The third set of compression parameters is configured with a third preset size encoding slice that is larger than the second preset size, a simplified prediction mode, and a third compression ratio that is larger than the second compression ratio.

3. The image processing method according to claim 1, characterized in that, The receiving and processing module is an FPGA processing module; the image processing method further includes: (4) Verify the CRC32 checksum to ensure the validity of the input data; (5) Allocate a corresponding level of buffer area based on the preset complexity level of the original image; (6) Perform format parsing and preprocessing on the received DSC bit stream, convert the compressed bit stream into the pixel data format of the display driver; write the parsed DSC bit stream into the DDR buffer for display.

4. The image processing method according to claim 1, characterized in that, The UDP command channel has a response mechanism with the receiving and processing module, including: When a command packet containing compression parameters and control instructions is sent to the receiving and processing module through the UDP command channel; If the receiving and processing module successfully receives and parses the command packet, it returns an acknowledgment response through the UDP command channel; If the sending end does not receive the confirmation response within the preset time, or; When the receiving processing module detects packet loss or CRC check failure, it retransmits the command packet when sending a negative response to the sending end via the UDP command channel.

5. The image processing method according to claim 1, characterized in that, In step (5), a corresponding level of buffer is allocated based on the preset complexity level of the original image, specifically including: Based on the resolution and refresh rate of the original image and the current storage load status of the DDR cache module, storage blocks of different sizes and access priorities are dynamically allocated to images of different complexity levels; among them, low-latency, high-bandwidth storage areas are preferentially allocated to image content with high complexity and high refresh rate.

6. The image processing method according to claim 3, characterized in that, The method also includes: (7) Through the display adaptation unit of the FPGA processing module, actively read the extended display identification data EDID of the display module, and automatically obtain the optimal resolution, refresh rate and color depth parameters supported by the display module; (8) Based on the obtained EDID information, dynamically configure the pixel clock, horizontal synchronization pulse, and vertical synchronization pulse timing parameters of the MIPI DSI interface; (9) Pack the pixel data after format parsing and preprocessing according to the configured MIPI DSI timing parameters and drive the display module to display it.

7. An image processing system, characterized in that, The system is used to perform the image processing method as described in any one of claims 1 to 6, comprising: The host computer module includes: Image acquisition unit, used to acquire raw image data; The image complexity analysis unit is used to extract the texture features, and / or grayscale types, and / or color distribution features of the original image, and divide the image into at least two preset complexity levels according to a preset threshold. The DSC compression strategy unit is used to adaptively configure DSC compression parameters according to the preset complexity level and generate a visually lossless DSC bitstream. A dual-channel transmission and verification unit is configured to transmit data and commands via dual channels, including: A UDP data channel is used to transmit a DSC bit stream, which carries a frame sequence number and a CRC32 checksum. The UDP command channel is used to transmit compression parameters, control commands, and status feedback information. The receiving and processing module is communicatively connected to the host computer module.

8. The system according to claim 7, characterized in that, The image complexity analysis unit classifies images into at least two preset complexity levels based on preset thresholds, including a first complexity level, a second complexity level, and a third complexity level. The DSC compression strategy unit adaptively configures DSC compression parameters according to the preset complexity level, including: selecting a first compression parameter set for the first complexity level, wherein the first compression parameter set is configured with a first preset size encoding slice, multiple prediction mode and a first compression ratio; A second set of compression parameters is selected for the second complexity level. The second set of compression parameters is configured with a second preset size of encoding slices larger than the first preset size, a balanced prediction mode, and a second compression ratio greater than the first compression ratio. A third set of compression parameters is selected for the third complexity level. The third set of compression parameters is configured with a third preset size encoding slice that is larger than the second preset size, a simplified prediction mode, and a third compression ratio that is larger than the second compression ratio.

9. The system according to claim 7, characterized in that, The receiving and processing module employs an FPGA processing module and specifically includes: The network port receiving unit is used to receive the DSC bit stream and control commands, and perform CRC32 verification. The real-time cache scheduling unit is used to dynamically allocate DDR storage resources based on image resolution, refresh rate, and storage status. The data processing unit is used to perform format parsing and preprocessing on the DSC bit stream; The storage control unit is used for data read and write interaction with the DDR storage module; The display adapter unit is used to read the EDID information of the display module and adaptively configure the timing of the display interface. The real-time buffer scheduling unit dynamically adjusts the transmission rate of the host computer module based on the buffer status fed back by the FPGA processing module to prevent buffer overflow at the receiving end.

10. The system according to claim 9, characterized in that, The system also includes: The display module is used for final image display. The MIPI interface module is used to convert the compressed bitstream output by the receiving and processing module into a signal that conforms to the MIPI DSI protocol and drive the display module to work. The DDR storage module is connected to the receiving and processing module and is used to cache data.

11. The system according to claim 10, characterized in that, The real-time cache scheduling unit is configured as follows: Monitor the current load and fragmentation of the DDR storage module; Based on the resolution, refresh rate, and image complexity level defined by the image complexity analysis unit, the size and location of storage blocks are dynamically divided and allocated. Allocate contiguous storage space with high access priority for high refresh rate video data.

12. The system according to claim 10, characterized in that, The display adaptation unit is configured as follows: Read the EDID information of the display module; The EDID information is parsed to obtain the physical resolution, supported refresh rate range, color format, and power timing requirements of the display module. Based on the analysis results, the pixel clock frequency, line and field synchronization timing parameters, and physical layer driving voltage of the MIPI interface unit are dynamically generated and configured.

13. The system according to claim 7, characterized in that, An error control unit is provided between the dual-channel transmission and verification unit and the network port receiving unit, including: When the network port receiving unit detects data packet loss or CRC32 check failure, it sends a retransmission request containing the lost frame sequence number or slice sequence number to the host computer intelligent decision layer through the UDP command channel. Upon receiving a retransmission request, the dual-channel transmission and verification unit retransmits the specified data packet.

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