Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and its fabrication method are provided. The semiconductor device includes: a substrate; transistor structures stacked on the substrate along a first direction, the transistor structures including an active layer, the first direction intersecting the substrate; word line structures at least partially disposed in the transistor structures along the first direction as gates, the multiple corresponding transistor structures sharing the word line structure; bit line structures disposed on the same layer as the transistor structures and connected to the active layer; memory nodes disposed on the same layer as the transistor structures and connected to the active layer; the bit line structures and memory nodes are located at opposite ends of the transistor structures along a second direction, the second direction being parallel to the substrate; the active layer is a doped oxide semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology

[0002] The development of dynamic memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As the size of semiconductor device structures shrinks, the technological barriers encountered by existing structures are becoming increasingly apparent. Therefore, developing more novel structures based on existing structures is a powerful means to break through existing technological barriers.

[0003] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM that includes multilayer horizontal cell (MHC), typically comprising multiple transistors stacked on a substrate, has met the above requirements.

[0004] In the current 3D DRAM structure, in order to balance the fabrication process and product performance, oxide semiconductor materials have been introduced as active layer materials, and new process methods and material compositions are constantly being developed to obtain high-performance transistors. Summary of the Invention

[0005] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising: Substrate; transistor structure, the transistor structure being stacked on the substrate along a first direction, the transistor structure including an active layer, the first direction intersecting the substrate; word line structure, the word line structure being at least partially disposed in the transistor structure along the first direction as a gate, the multiple corresponding transistor structures sharing the word line structure; bit line structure, the bit line structure being disposed on the same layer as the transistor structure and connected to the active layer; memory node, the memory node being disposed on the same layer as the transistor structure and connected to the active layer; the bit line structure and the memory node being located at opposite ends of the transistor structure along a second direction, the second direction being parallel to the substrate; the active layer material being a doped oxide semiconductor layer.

[0006] In some embodiments, an active layer surrounds the word line structure.

[0007] In some embodiments, the doped oxide semiconductor layer is a doped indium gallium zinc oxide layer.

[0008] In some embodiments, the doped indium gallium zinc oxide layer is an indium gallium zinc oxide and MOx stack, wherein M is selected from one or two of indium, gallium or tin.

[0009] In some embodiments, MOx is indium tin oxide, and the doped indium gallium zinc oxide layer is a multilayer indium gallium zinc oxide and MOx. x Alternating layers.

[0010] In some embodiments, in the indium gallium zinc oxide and MOx stack, the MOx layer accounts for 1% to 50% of the total thickness.

[0011] In some embodiments, the thickness of the indium gallium zinc oxide and MOx stack is 4 nm to 10 nm.

[0012] In some embodiments, the tin content in the MOx layer is between 10% and 50%.

[0013] In some embodiments, the doped indium gallium zinc oxide layer is a fluorine-doped indium gallium zinc oxide layer.

[0014] In some embodiments, the transistor structure further includes a gate insulating layer disposed between the active layer and the word line structure. The gate insulating layer is selected from a hafnium oxide and aluminum oxide stack, a silicon oxide and aluminum oxide stack, or a hafnium oxide silicon layer; and the dielectric constant of the gate insulating layer is between 4 and 22.

[0015] According to a second aspect of the present disclosure, a method for fabricating a semiconductor device is provided, comprising: providing a substrate; forming a stacked structure on the substrate; forming a bit line structure in the stacked structure; forming a memory node in the stacked structure; forming an active layer in the stacked structure, the active layer connecting the bit line structure and the memory node on the same layer; forming a word line structure in the stacked structure that passes through multiple layers and at least partially overlaps with the active layer, the portion of the word line structure overlapping with the active layer and the active layer constituting a transistor structure; wherein the active layer is a doped indium gallium zinc oxide layer.

[0016] In some embodiments, the doped indium gallium zinc oxide layer is an indium gallium zinc oxide and MOx stack, wherein M is selected from one or two of indium, gallium or tin; the step of forming the active layer includes forming an indium gallium zinc oxide layer and a MOx layer sequentially.

[0017] In some embodiments, the doped indium gallium zinc oxide layer is a fluorine-doped indium gallium zinc oxide layer; the step of forming the active layer includes: forming an indium gallium zinc oxide layer, and doping the indium gallium zinc oxide layer with fluorine by initiation chemical vapor deposition and annealing.

[0018] In some embodiments, a gate insulating layer is formed between the active layer and the word line structure. The gate insulating layer is selected from a hafnium oxide and aluminum oxide stack, a silicon oxide and aluminum oxide stack, or a hafnium oxide silicon layer. The dielectric constant of the gate insulating layer is controlled between 4 and 22 by adjusting the composition ratio.

[0019] The technical solution disclosed herein provides a superior oxide transistor with better performance and a superior fabrication method for semiconductor structures with high aspect ratios. Attached Figure Description

[0020] Figure 1 This is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment; Figures 2-8 This is a schematic cross-sectional view of a semiconductor device along D2-D3 through the transistor structure location in a fabrication method according to an exemplary embodiment. Detailed Implementation

[0021] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0022] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0023] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0024] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0025] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0026] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0027] In some related technologies, oxide semiconductors are easier to fabricate and offer more flexible process routes compared to single-crystal silicon in large-scale integrated circuits, facilitating the fabrication of complex structures. Especially in three-dimensional multilayer horizontal structures, oxide semiconductors are more likely to form highly integrated multilayer structures compared to single-crystal silicon channels, which require time-consuming and inefficient epitaxial growth to create stacked structures. However, due to the inherent properties of oxide semiconductor materials, their mobility and carrier concentration are primarily determined by the number of oxygen vacancies in the thin film. Fewer oxygen vacancies result in lower turn-on current, while a higher number leads to poor stability. Therefore, improving the performance and stability of oxide semiconductor transistors is a pressing issue that needs to be addressed.

[0028] According to a first aspect of the embodiments of this disclosure, such as Figure 1 As shown, a first direction D1 intersects the substrate, a second direction D2 is parallel to the substrate, and a third direction D3 is parallel to the substrate and intersects the second direction. A semiconductor device 10 includes: a substrate 100; a transistor structure 800, which is stacked on the substrate along the first direction and includes an active layer 200; a word line structure 400, which is at least partially disposed in the transistor structure along the first direction as a gate, and the multiple corresponding transistor structures share the word line structure; a bit line structure 500, which is disposed on the same layer as the transistor structure and connected to the active layer; and a memory node 600, which is disposed on the same layer as the transistor structure and connected to the active layer; the bit line structure and the memory node are located at opposite ends of the transistor structure along the second direction; the active layer is a doped oxide semiconductor layer.

[0029] In some embodiments, the storage node is selected from one or more of the following: storage capacitor, phase change memory, magnetoresistive memory, or ferroelectric memory.

[0030] In some embodiments, the active layer surrounds the word line structure, and the transistor structure further includes a gate insulating layer disposed between the active layer and the word line structure to form a channel all-around structure (CAA). The active layer in contact with the bit line structure and the memory node acts as the source and drain. The active layer between the source and drain forms a channel structure, that is, both sides of the annular active layer in contact with the bit line structure and the memory node are channel structures.

[0031] In some embodiments, the bit line structure extends along a third direction to connect multiple transistor structures disposed on the same layer, and the bit line structure has a lead-out structure in the lead-out region.

[0032] In some embodiments, a multilayer bitline structure connects multiple transistor structures and memory nodes to form a stacked array, and two adjacent stacked arrays are arranged in a mirror image with respect to the plane passing through D1-D3.

[0033] In some embodiments, the semiconductor device is part of a dynamic random access memory (DRAM), which includes a differential amplifier and a sub-word line driver. The differential amplifier is electrically connected to the lead-out structure of the bit line structure via leads, and the sub-word line driver is electrically connected to the word line structure via leads.

[0034] In some embodiments, the doped oxide semiconductor layer is a doped indium gallium zinc oxide (IGZO) layer.

[0035] In some embodiments, the doped indium gallium zinc oxide layer is indium gallium zinc oxide and MO. x The stack-up, where M is selected from one or two of indium (In), gallium (Ga), or tin (Sn). The layer in the active layer stack that contacts the bit line structure and memory node is an indium gallium zinc oxide layer.

[0036] In some embodiments, the doped indium gallium zinc oxide layer is indium gallium zinc oxide and MO. x A stack of active layers, wherein M is selected from one or two of indium, gallium, or tin. The layer in the stack of active layers that contacts the bit line structure and memory node is MO. x layer.

[0037] In some embodiments, MO x It is indium tin oxide (ITO), and the doped indium gallium zinc oxide layer is a stack of indium gallium zinc oxide and indium tin oxide layers. The stack of indium gallium zinc oxide and indium tin oxide layers can be a single layer of indium gallium zinc oxide and a single layer of indium tin oxide; or it can be a stack of multiple layers of indium gallium zinc oxide and multiple layers of indium tin oxide spaced apart.

[0038] In some embodiments, MO x It is indium tin oxide (ITO), and the doped indium gallium zinc oxide layer is a multilayer indium gallium zinc oxide and MO. x Alternating stacked layers. As can be seen from Table 1, when the thickness of the active layer is less than 10 nm, the turn-on current is highest when two layers of indium gallium zinc oxide and two layers of indium tin oxide are stacked alternately.

[0039] In some embodiments, the layer in the active layer stack that contacts the bit line structure and the memory node is an indium tin oxide layer.

[0040] In some embodiments, indium gallium zinc oxide and MO x In the stack, MO x The layer accounts for 1% to 50% of the total thickness. MO x Increasing the thickness of the active layer leads to increased conductivity, carrier number, and carrier mobility, which improves the turn-on current of the transistor structure. However, it also degrades the stability of the transistor structure, causing electrical drift. Therefore, the MO in the active layer stack... x A transistor structure with better performance can be obtained by controlling the thickness of the layer to be between 1% and 50% of the total thickness.

[0041] In some embodiments, indium gallium zinc oxide and MO x The thickness of the stacked layers is 4 nanometers to 10 nanometers, MO x The tin content in the active layer ranges from 10% to 50%. As the tin content increases, the conductivity of the active layer increases, leading to an increase in carrier number and carrier mobility, which in turn increases the turn-on current of the transistor structure. However, this also degrades the stability of the transistor structure, causing electrical drift. Therefore, MO... x A transistor structure with a tin content between 10% and 50% in the layer will achieve better performance.

[0042] In some embodiments, the active layer is a stack of indium gallium zinc oxide (IGNOW) and indium tin oxide (ITO). In the active layer stack, as the ITO layer's total thickness increases, the conductivity, carrier number, and carrier mobility of the active layer increase, leading to a higher transistor turn-on current. However, this also degrades the transistor's stability, causing electrical drift. Therefore, controlling the ITO layer thickness in the active layer stack to between 1% and 50% yields a transistor structure with better performance.

[0043] Table 1

[0044] In some embodiments, the doped indium gallium zinc oxide layer is a fluorine (F) doped indium gallium zinc oxide layer. Fluorine doping can improve the electrical properties of the indium gallium zinc oxide layer, increase the turn-on current, cause a positive shift in the threshold voltage, and reduce the subthreshold swing.

[0045] In some embodiments, the doped indium gallium zinc oxide layer is fluorine-doped indium gallium zinc oxide and MO. x A stack, wherein M is selected from one or two of indium (In), gallium (Ga), or tin (Sn).

[0046] In some embodiments, MO x It is indium tin oxide (ITO), and the doped indium gallium zinc oxide layer is a multilayer fluorine-doped indium gallium zinc oxide and MO. x Alternating layers.

[0047] In some embodiments, the gate insulating layer is selected from a hafnium oxide and aluminum oxide stack, a silicon oxide and aluminum oxide stack, or a hafnium oxide silicon layer; and the dielectric constant of the gate insulating layer is between 4 and 22. A high dielectric constant material is used as the gate insulating layer to ensure a high turn-on current. However, an excessively high dielectric constant can lead to excessive parasitic capacitance in the word line structure, affecting the device read speed. Therefore, a suitable dielectric constant value can yield a transistor structure with superior performance.

[0048] In some embodiments, the gate insulating layer is a hafnium oxide and aluminum oxide stack, wherein the thickness of the hafnium oxide layer is between 1 nm and 3 nm, and the thickness of the aluminum oxide layer is between 5 nm and 10 nm. Contact between the hafnium oxide and the active layer in the stack improves device performance and reliability.

[0049] In some embodiments, the gate insulating layer is a silicon oxide and aluminum oxide stack, wherein the thickness of the silicon oxide layer is between 1 nm and 5 nm, and the thickness of the aluminum oxide layer is between 5 nm and 10 nm. Contact between the silicon oxide and the active layer in the stack improves device performance and reliability.

[0050] In some embodiments, the gate insulating layer is a hafnium silicon oxide layer, wherein the silicon content is between 5% and 50% in molar percentage.

[0051] According to a second aspect of the embodiments of this disclosure, such as Figures 1-8 A method for fabricating a semiconductor device is provided, comprising: providing a substrate; In some embodiments, the substrate may be made of semiconductor materials such as single-crystal silicon, germanium silicon, silicon carbide, and silicon-on-insulator, and may include other pre-fabricated structures, such as transistors disposed in the substrate.

[0052] A multilayer structure is formed on the substrate; In some embodiments, a stacked structure is formed on the substrate, the stacked structure being composed of alternating material layers M1 and M2, where material layers M1 and M2 represent two different selected materials. The stacked structure may be selected from alternatingly deposited silicon nitride and silicon oxide, or from single-crystal silicon and single-crystal silicon germanium fabricated by epitaxial growth, or from alternating preparation of two different thin film materials with high etching selectivity.

[0053] In some embodiments, the stacked structure is composed of two alternating materials, which are replaced by an etching process and a deposition process to form a stacked structure consisting of material layer M1 and material layer M2.

[0054] In some embodiments, the etching process for fabricating a multilayer structure includes anisotropic etching or isotropic etching, such as dry etching or wet etching.

[0055] In some embodiments, the deposition process for fabricating the layered structure includes physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, epitaxial growth (EPI), etc.

[0056] Forming bitline structures in stacked structures; A first line trench is formed at the corresponding position in the stacked structure, and the material layer M2 is etched laterally along the first line trench to form a first line groove, and a bit line structure is formed in the first line groove.

[0057] In some embodiments, the method for forming the first line trench can be through a patterning process. Specifically, the patterning process includes forming photoresist on a substrate, exposing and developing the photoresist to form a pre-defined pattern of photoresist, and etching the stacked structure with the patterned photoresist to form the first line trench. Optionally, the etching process includes anisotropic etching or isotropic etching, such as dry etching or wet etching.

[0058] In some embodiments, the patterning process further includes forming a hard mask on a substrate, forming photoresist on the hard mask, exposing and developing the photoresist to form a preset pattern, etching the hard mask with the patterned photoresist to transfer the preset pattern onto the hard mask, stripping the photoresist, and etching the stacked structure with the patterned hard mask to form a first line trench.

[0059] In some embodiments, as semiconductor fabrication processes advance, integration density increases and dimensions shrink. A single patterning process cannot form the desired width of the active region and isolation trenches, necessitating multiple patterning processes. Examples include two-times-expose and etched (LELE) process, self-aligned dual patterning (SADP) process, and self-aligned quad patterning (SAQP) process.

[0060] In some embodiments, the method for lateral etching of material layer M2 can be a liquid phase etching process. Optionally, the etching rate of the etchant in the liquid phase etching process on material layer M2 is greater than the etching rate of the etchant on material layer M1.

[0061] In some embodiments, the step of forming a bit line structure in the first bit line groove includes forming a bit line material layer in the first bit line trench, wherein the bit line material layer fills the first bit line groove and covers the sidewall of the first bit line trench.

[0062] In some embodiments, the material of the bit line material layer is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the bit line material layer is a stack of titanium nitride (TiN) and tungsten (W). The method for forming the bit line material layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the method for forming the bit line material layer is atomic layer deposition (ALD).

[0063] In some embodiments, the bit line material layer on the sidewall of the first bit line trench is removed, the bit line material layer in the remaining first bit line groove forms a bit line, and the first bit line protective layer P1 is filled in the first bit line trench.

[0064] In some embodiments, the process for removing the bit line material layer from the sidewall of the first bit line trench is an anisotropic etching process, including dry etching, plasma etching, etc.

[0065] In some embodiments, the material of the first line guard layer P1 is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. Preferably, the first line guard layer P1 is a stack of silicon oxide and silicon nitride. Optionally, the method for forming the first line guard layer P1 is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, rapid thermal oxidation, etc. Preferably, the deposition method of the first line guard layer P1 is chemical vapor deposition (CVD).

[0066] In some embodiments, the method of forming the first line guard layer P1 further includes: removing the portion of the first line guard layer P1 that extends beyond the first lead-out trench when forming the first line guard layer P1, such that the upper surface of the first line guard layer P1 is flush with the first line trench. The method for removing the gate insulating layer material from the substrate surface is selected from etching processes and chemical mechanical polishing (CMP).

[0067] Storage nodes are formed in the stacked structure; In some embodiments, the storage node is selected from one or more of the following: storage capacitor, phase-change memory, magnetoresistive memory, or ferroelectric memory. Taking a storage capacitor as an example, the storage capacitor includes a lower electrode, a dielectric layer, and a top electrode. The lower electrode of the storage capacitor is connected to the active layer of the transistor structure. The dielectric layer covers the lower electrode, and the top electrode covers the dielectric layer. Multiple storage capacitors share the top electrode.

[0068] In some embodiments, a first capacitor trench is formed at a corresponding position in the stacked structure, and a material layer M2 is etched laterally along the first capacitor trench to form a first capacitor recess, in which a storage capacitor is formed.

[0069] In some embodiments, the method of forming the first capacitor trench may be to prepare it by a patterning process, and the method of forming the first capacitor groove by lateral etching is similar to that described above, and will not be repeated here.

[0070] In some embodiments, the method of forming a storage capacitor includes first forming a lower electrode, then forming a dielectric layer, and finally forming a top electrode. It is understood that the lower electrode, dielectric layer, and top electrode can be formed in consecutive fabrication steps, or fabrication steps for other structures can be added in between. For example, the lower electrode may be formed first, then a lower electrode protective layer may be filled, then other structures may be fabricated, and after the other structures are completed, the lower electrode protective layer may be removed before continuing to fabricate the dielectric layer and top electrode.

[0071] In some embodiments, a lower electrode material layer is formed in the first capacitor trench, the lower electrode material layer filling the first capacitor trench and covering the sidewalls of the first capacitor trench. The material of the lower electrode is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the material of the lower electrode is titanium nitride (TiN). The method for forming the lower electrode material layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the method for forming the lower electrode is atomic layer deposition (ALD). The lower electrode material layer on the sidewall of the first capacitor trench is removed, and the remaining lower electrode material layer in the first capacitor trench forms the lower electrode. The lower electrode covers the first capacitor trench to form the second capacitor trench. The process for removing the lower electrode material layer on the sidewall of the first capacitor trench is an anisotropic etching process, including dry etching, plasma etching, etc.

[0072] In some embodiments, such as Figure 2 As shown, a lower electrode 601 is formed in the stacked structure, and then a lower electrode protective layer is filled. The material of the lower electrode protective layer is selected from polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. Preferably, the lower electrode protective layer is polycrystalline silicon. Optionally, the method for forming the lower electrode protective layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, rapid thermal oxidation, etc.

[0073] In some embodiments, a capacitor dielectric layer is formed in a first capacitor trench, and the capacitor dielectric layer fills a second capacitor recess and covers the sidewalls of the first capacitor trench. The material of the capacitor dielectric layer is selected from at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, or includes at least one of, for example, hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The method for forming the capacitor dielectric layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. The dielectric layer on the sidewall of the first capacitor trench can be removed or retained. The dielectric layer covers the second capacitor trench to form a third capacitor trench. The first capacitor trench retains the dielectric layer to form the second capacitor trench.

[0074] In some embodiments, an upper electrode material layer is formed in the first capacitor trench, and the upper electrode material layer fills the third capacitor groove and covers the sidewalls of the first capacitor trench. The material of the upper electrode is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the material of the upper electrode is titanium nitride (TiN). The method for forming the upper electrode material layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the method for forming the lower electrode is atomic layer deposition (ALD). The top electrode material layer, excluding the first capacitor trench and the third capacitor recess, is removed. The remaining top electrode material layer forms the top electrode, which covers the third capacitor recess to form the fourth capacitor recess. The first capacitor trench, retaining the top electrode, forms the third capacitor trench. The process for removing the top electrode material layer is anisotropic etching, including dry etching and plasma etching.

[0075] In some embodiments, an upper electrode material layer is formed in the second capacitor trench, and the upper electrode material layer fills the third capacitor groove and covers the sidewalls of the second capacitor trench. The material of the upper electrode is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the material of the upper electrode is titanium nitride (TiN). The method for forming the upper electrode material layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the method for forming the lower electrode is atomic layer deposition (ALD). The top electrode material layer, excluding the second and third capacitor trenches, is removed, leaving the remaining top electrode material layer to form the top electrode. This top electrode covers the third capacitor trench, forming the fifth capacitor trench. The second capacitor trench, retaining the top electrode, forms the fourth capacitor trench. The process for removing the top electrode material layer is anisotropic etching, including dry etching and plasma etching.

[0076] In some embodiments, a filling layer is formed in the third capacitor trench, and the filling layer fills the fourth capacitor groove. The material of the filling layer is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum titanium nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), aluminum tantalum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the material of the filling layer is doped or undoped polycrystalline silicon. The method for forming the filling layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0077] In some embodiments, a filling layer is formed in the fourth capacitor trench, and the filling layer fills the fifth capacitor groove. The material of the filling layer is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum titanium nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), aluminum tantalum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the material of the filling layer is doped or undoped polycrystalline silicon. The method for forming the filling layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0078] An active layer is formed in the stacked structure, and the active layer connects the bit line structure and memory node in the same layer; Specifically, such as Figure 3 As shown, a first transistor hole V1 is formed at a corresponding position between the bit line and the memory node. The first transistor hole passes through the stacked structure material layers M1 and M2 to the substrate. To ensure that the material layers M1 and M2 are completely removed, appropriate over-etching can be performed to remove part of the substrate. The sidewall of the first transistor hole exposes part of the bit line structure and part of the lower electrode.

[0079] In some embodiments, the first transistor hole is formed by a patterning process, which is similar to that described above and will not be repeated here.

[0080] In some embodiments, the first transistor hole is completed by etching once to expose part of the bit line structure and part of the lower electrode, or the first transistor hole is formed by back-side etching to expose part of the bit line structure and part of the lower electrode.

[0081] An active layer material layer M3 is formed in the first transistor hole, such as... Figure 4 As shown, the active layer material layer covers the bottom and sidewalls of the first transistor hole to form the second transistor hole V2. The active layer material layer can be formed using methods such as physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, and furnace tube deposition. The active layer material layer can be a single layer or a stack of multiple sublayers, such as... Figure 4 As shown in the enlarged view, the stack is formed by the alternating deposition of sublayers M3-1 and M3-2.

[0082] In some embodiments, sublayers M3-1 and M3-2 are formed by alternating depositions twice.

[0083] In some embodiments, the active layer material is a doped oxide semiconductor layer.

[0084] In some embodiments, the active layer material is a doped indium gallium zinc oxide layer.

[0085] In some embodiments, the active layer material is indium gallium zinc oxide and MO. x A stack, wherein M is selected from one or both of indium, gallium or tin.

[0086] In some embodiments, MO x It is indium tin oxide, and the active layer is a multilayer indium gallium zinc oxide and MO. x Alternating layers.

[0087] In some embodiments, the active layer material is indium gallium zinc oxide and MO. x Stacked, and MO x The layer accounts for 1% to 50% of the total thickness.

[0088] In some embodiments, the active layer material is indium gallium zinc oxide and MO. x The thickness of the stacked layers is between 4 nanometers and 10 nanometers.

[0089] In some embodiments, the active layer material is indium gallium zinc oxide and MO. x Stacked layers, where MO x The tin content in the layer ranges from 10% to 50%.

[0090] In some embodiments, the active layer material is a fluorine-doped indium gallium zinc oxide layer. For example... Figure 8 As shown, the method for preparing a fluorine-doped indium gallium zinc oxide (IGaZ) layer includes first forming an IGaZ layer, then forming a fluorine-containing polymer layer T1 in a second transistor aperture using an initiation chemical vapor deposition (ICVDC) method, and forming a masking layer T2 on the surface of the fluorine-containing polymer layer T1. The material of the masking layer T2 is selected from metal oxides, such as aluminum oxide. The stacked structure with the fluorine-containing polymer layer T1 and the masking layer T2 is annealed to remove the fluorine-containing polymer layer T1 and the masking layer T2, thus forming the fluorine-doped IGaZ layer. With the increasing integration density of semiconductor devices, the number of layers in the stacked structure increases, resulting in a larger aspect ratio of the formed second transistor aperture. Traditional doping methods are not effective for high aspect ratio structures; however, the fluorine doping method disclosed in this paper can achieve a better doping effect.

[0091] In some embodiments, an active layer material layer other than the active layer material layer located at the same layer position as the bit line structure and the lower electrode is removed, and the remaining active layer material layer forms an active layer. The active layer is annular, surrounds the sidewall covering the first transistor hole, and contacts the bit line structure and the lower electrode.

[0092] In some embodiments, after forming the active layer material layer, the active layer material layer in the first transistor aperture is not removed, and the gate insulating layer material layer is directly deposited, such as... Figure 5 As shown, a gate insulating layer material layer M4 is formed in the second transistor hole, and the second transistor hole covered with the gate insulating layer material layer forms a third transistor hole V3. The gate insulating layer material layer can be formed using methods such as physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, and furnace tube deposition. The gate insulating layer material layer is a hafnium oxide and aluminum oxide stack, a silicon oxide and aluminum oxide stack, or a hafnium oxide-silicon oxide layer. Understandably, the stack is formed through multiple deposition processes.

[0093] In some embodiments, the gate insulating layer material is a hafnium oxide and aluminum oxide stack or a silicon oxide and aluminum oxide stack, and the dielectric constant value can be controlled between 4 and 22 by adjusting the deposition thickness of each layer.

[0094] In some embodiments, the gate insulating layer material is a hafnium silicon oxide layer, and the dielectric constant value can be controlled between 4 and 22 by controlling the amount of each component.

[0095] In a stacked structure, a word line structure is formed that passes through multiple layers and at least partially overlaps with the active layer, such as... Figures 6-7 As shown, a word line material layer M5 is formed in the third transistor aperture. The word line material layer outside the third transistor aperture is removed to form a word line structure 400. The word line material layer is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum titanium nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), aluminum tantalum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. The method for forming the word line material layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. The method for removing the word line material layer outside the third transistor aperture includes etching or chemical mechanical polishing (CMP).

[0096] In some embodiments, it may be understood that removing the word line material layer outside the third transistor hole includes removing the word line material layer on the surface of the stacked structure, while removing the gate insulating layer material layer on the surface of the stacked structure to form a gate insulating layer, and removing the active layer material layer on the surface of the stacked structure.

[0097] In some embodiments, after the character line structure is created, such as Figure 7As shown, it also includes removing the material layer M1 in the stacked structure, namely the material layer M1 between the bit line structures and the material layer M1 between the lower electrode, exposing the active layer material layer in part of the first transistor hole, removing the exposed active layer material layer, and the remaining active layer material layer forming the active layer.

[0098] The portion of the word line structure that overlaps with the active layer forms a transistor structure together with the active layer.

[0099] The various semiconductor devices illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase-Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0100] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A transistor structure, wherein the transistor structure is stacked on the substrate along a first direction, the transistor structure including an active layer, and the first direction intersects the substrate; A word line structure, wherein the word line structure is at least partially disposed in the transistor structure along the first direction as a gate, and the multiple corresponding transistor structures share the word line structure; Bit line structure, wherein the bit line structure is disposed on the same layer as the transistor structure and is connected to the active layer; A storage node, wherein the storage node is disposed on the same layer as the transistor structure and is connected to the active layer; The bit line structure and the memory node are located at opposite ends of the transistor structure along a second direction, which is parallel to the substrate. The active layer is a doped oxide semiconductor layer.

2. The semiconductor device according to claim 1, characterized in that, The active layer surrounds the word line structure.

3. The semiconductor device according to any one of claims 1-2, characterized in that, The doped oxide semiconductor layer is a doped indium gallium zinc oxide layer.

4. The semiconductor device according to claim 3, characterized in that, The doped indium gallium zinc oxide layer is indium gallium zinc oxide and MO. x A stack, wherein M is selected from one or both of indium, gallium or tin.

5. The semiconductor device according to claim 4, characterized in that, The MO x It is indium tin oxide, and the doped indium gallium zinc oxide layer is a multilayer indium gallium zinc oxide and MO. x Alternating layers.

6. The semiconductor device according to claim 4, characterized in that, The indium gallium zinc oxide and MO x In the stack, the MO x The layer accounts for 1% to 50% of the total thickness.

7. The semiconductor device according to claim 4, characterized in that, The indium gallium zinc oxide and MO x The thickness of the stack is 4 nanometers to 10 nanometers.

8. The semiconductor device according to claim 4, characterized in that, The MO x The tin content in the layer ranges from 10% to 50%.

9. The semiconductor device according to claim 3, characterized in that, The doped indium gallium zinc oxide layer is a fluorine-doped indium gallium zinc oxide layer.

10. The semiconductor device according to claim 3, characterized in that, The transistor structure further includes a gate insulating layer disposed between the active layer and the word line structure. The gate insulating layer is selected from hafnium oxide and aluminum oxide stack, silicon oxide and aluminum oxide stack, or hafnium oxide silicon layer; and the dielectric constant of the gate insulating layer is between 4 and 22.

11. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A multilayer structure is formed on the substrate; A bitline structure is formed in the stacked structure; Storage nodes are formed in the stacked structure; An active layer is formed in the stacked structure, and the active layer connects the bit line structure and the memory node in the same layer; In the stacked structure, a word line structure is formed that passes through multiple layers and at least partially overlaps with the active layer, wherein the portion of the word line structure that overlaps with the active layer constitutes a transistor structure with the active layer; The active layer is a doped indium gallium zinc oxide layer.

12. The method for fabricating the semiconductor device according to claim 11, characterized in that, The doped indium gallium zinc oxide layer is indium gallium zinc oxide and MO. x A stack, wherein M is selected from one or two of indium, gallium, or tin; The step of forming the active layer includes sequentially forming the indium gallium zinc oxide layer and the MO. x layer.

13. The method for fabricating the semiconductor device according to claim 11, characterized in that, The doped indium gallium zinc oxide layer is a fluorine-doped indium gallium zinc oxide layer; The steps for forming the active layer include: The indium gallium zinc oxide layer is formed. The indium gallium zinc oxide layer was doped with fluorine by initiation chemical vapor deposition and annealing.

14. The method for fabricating a semiconductor device according to claim 11, characterized in that, It also includes forming a gate insulating layer between the active layer and the word line structure, wherein the gate insulating layer is selected from a hafnium oxide and aluminum oxide stack, a silicon oxide and aluminum oxide stack, or a hafnium oxide silicon layer; the dielectric constant of the gate insulating layer is controlled between 4 and 22 by adjusting the composition ratio.

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