Semiconductor structure, semiconductor structure fabrication method and electronic device

Abstract

This invention relates to a semiconductor structure, a method for fabricating the semiconductor structure, and an electronic device. The semiconductor structure includes a substrate and a source / drain contact layer disposed on the substrate. The source / drain contact layer includes a first metal nitride layer and a second metal nitride layer stacked in a direction away from the substrate. The atomic percentage of nitrogen in the first metal nitride layer is less than the atomic percentage of nitrogen in the second metal nitride layer. This invention uses stacked metal nitrides to form the source / drain contact layer, which can reduce the resistance of the source / drain contact layer, improve semiconductor performance, and reduce costs.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for fabricating a semiconductor structure, and an electronic device. Background Technology

[0002] Thin-film integrated circuits (TFT-ICs) are power components and their wiring fabricated using thin-film technology and then packaged. Due to the wide parameter range, high precision, and good temperature and frequency characteristics of components fabricated using thin-film circuits, they are widely used in emerging fields such as 3D storage, flexible displays, the Internet of Things (IoT), and wearable electronic devices. However, thin-film transistors still face technical challenges in terms of performance and miniaturization. Summary of the Invention

[0003] Therefore, it is necessary to provide a semiconductor structure, a semiconductor structure fabrication method, and an electronic device to address the problem of the difficulty in miniaturizing thin-film transistors in the prior art.

[0004] To achieve the above objectives, in one aspect, this disclosure provides a semiconductor structure, which includes: a substrate and a source / drain contact layer disposed on the substrate; wherein,

[0005] The source / drain contact layer includes: a first metal nitride layer and a second metal nitride layer stacked in a direction away from the substrate; the atomic percentage of nitrogen in the first metal nitride layer is less than the atomic percentage of nitrogen in the second metal nitride layer.

[0006] In some embodiments, the nitrogen element in the first metal nitride layer has an elemental ratio of greater than or equal to 0.6 and less than 1 with any other element.

[0007] In some embodiments, the nitrogen element in the second metal nitride layer has an elemental ratio greater than 1 and less than or equal to 1.3 with any other element.

[0008] In some embodiments, the thickness of the first metal nitride layer is greater than the thickness of the second metal nitride layer.

[0009] In some embodiments, the ratio of the thickness of the first metal nitride layer to the thickness of the second metal nitride layer ranges from 6:1 to 50:1.

[0010] In some embodiments, the source / drain contact layer includes a first source / drain contact layer and a second source / drain contact layer spaced apart in a direction perpendicular to the substrate; the semiconductor structure also includes:

[0011] An interlayer dielectric layer is located between the first source / drain contact layer and the second source / drain contact layer; the second source / drain contact layer is located on the side of the interlayer dielectric layer opposite to the first source / drain contact layer; the orthographic projections of the second source / drain contact layer and the interlayer dielectric layer on the substrate are both located within the orthographic projection of the first source / drain contact layer on the substrate.

[0012] The semiconductor layer covers the sidewalls of the second source / drain contact layer, the interlayer dielectric layer, and part of the top surface of the first source / drain contact layer.

[0013] In some embodiments, the second source / drain contact layer further includes: a sidewall covering the sidewalls of the second metal nitride layer and the first metal nitride layer;

[0014] The sidewalls are made of the same material as the second metal nitride layer.

[0015] In some embodiments, the semiconductor structure further includes:

[0016] The gate dielectric layer covers the surface of the semiconductor layer and the first source / drain contact layer that is not covered by the semiconductor layer;

[0017] The gate is located on the surface of the gate dielectric layer away from the sidewalls of the semiconductor layer that extend in a direction perpendicular to the substrate.

[0018] Secondly, this disclosure also provides a method for preparing a semiconductor structure, the method comprising:

[0019] Provide substrate;

[0020] A source / drain contact layer is formed on a substrate; the source / drain contact layer includes: a first metal nitride layer and a second metal nitride layer stacked in a direction away from the substrate; the atomic percentage of nitrogen in the first metal nitride layer is less than the atomic percentage of nitrogen in the second metal nitride layer.

[0021] In some embodiments, the source / drain contact layer includes a first source / drain contact layer and a second source / drain contact layer spaced apart in a direction perpendicular to the substrate; forming the source / drain contact layer on the substrate includes:

[0022] A first metal nitride layer, a second metal nitride layer, an interlayer dielectric material layer, a first metal nitride layer, and a second metal nitride layer are sequentially stacked on a substrate.

[0023] A first metal nitride layer and a second metal nitride layer are patterned above the interlayer dielectric material layer to form a second source / drain contact layer;

[0024] An interlayer dielectric layer is formed by self-aligning etching of the interlayer dielectric material layer based on the second source / drain contact layer.

[0025] A semiconductor layer is formed covering the sidewalls of the second source / drain contact layer, the interlayer dielectric layer, and part of the top surface of the first source / drain contact layer.

[0026] In some embodiments, a first metal nitride layer and a second metal nitride layer above a patterned interlayer dielectric material layer form a second source / drain contact layer, including:

[0027] A first metal nitride layer and a second metal nitride layer are patterned above the interlayer dielectric material layer to form an initial second source / drain contact layer;

[0028] Based on the initial second source / drain contact layer, a sidewall is formed by self-alignment to cover the sidewalls of the second metal nitride layer and the first metal nitride layer, thereby obtaining the second source / drain contact layer;

[0029] The sidewalls are made of the same material as the second metal nitride layer.

[0030] In some embodiments, the preparation method further includes:

[0031] A gate dielectric layer is formed on the surface of the semiconductor layer and the first source / drain contact layer that is not covered by the semiconductor layer;

[0032] A gate is formed on the sidewall surface of the gate dielectric layer away from the semiconductor layer, and the gate extends in a direction perpendicular to the substrate.

[0033] In some embodiments, the preparation method further includes:

[0034] Self-aligned doping is performed on the first source / drain contact layer and the second source / drain contact layer to form the doped first source / drain contact layer and the doped second source / drain contact layer.

[0035] In some embodiments, the preparation method further includes:

[0036] A gate lead-out electrode is formed on the surface of the gate that is away from the substrate;

[0037] A first source / drain electrode is formed on the surface of the first source / drain contact layer that is away from the substrate;

[0038] A second source / drain electrode is formed on the surface of the second source / drain contact layer that is away from the substrate.

[0039] Thirdly, this disclosure also discloses an electronic device that includes the semiconductor structure proposed in the first aspect above, or includes a semiconductor structure prepared by the method for preparing the semiconductor structure based on the semiconductor structure in the second aspect above.

[0040] In the aforementioned semiconductor structure, semiconductor structure fabrication method, and electronic device, the semiconductor structure includes a substrate and a source / drain contact layer disposed on the substrate. The source / drain contact layer includes a first metal nitride layer and a second metal nitride layer stacked along a direction away from the substrate. The atomic percentage of nitrogen in the first metal nitride layer is less than the atomic percentage of nitrogen in the second metal nitride layer. The semiconductor structure disclosed herein provides two metal nitride layers in the source / drain contact layer, and the nitrogen content in the two metal nitride layers is different. This allows for both improvements in the conductivity of the source / drain contact layer (higher nitrogen content in the first metal nitride layer, thus reducing its resistance) and improvements in the strength and oxidation resistance of the source / drain contact layer (higher nitrogen content in the second metal nitride layer), thereby improving the semiconductor performance. Electronic devices formed using the above semiconductor structure can have their size continuously reduced due to the lower resistance of the source / drain contact layer, improving the performance of the electronic device and reducing costs. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0043] Figure 2 This is a schematic cross-sectional view of a source / drain contact layer formed on a substrate in one embodiment;

[0044] Figure 3 This is a cross-sectional schematic diagram of a first source / drain contact layer, an interlayer dielectric material layer, and an initial second source / drain contact layer in one embodiment.

[0045] Figure 4 This is a schematic cross-sectional view of the formation of the second source / drain contact layer in one embodiment;

[0046] Figure 5 This is a schematic cross-sectional view of the interlayer dielectric layer after etching in one embodiment;

[0047] Figure 6 This is a schematic cross-sectional view of a semiconductor layer formed in one embodiment;

[0048] Figure 7 This is a schematic cross-sectional view of a self-aligned doping embodiment;

[0049] Figure 8This is a schematic cross-sectional view of a solution after the gate dielectric layer and gate are formed in one embodiment;

[0050] Figure 9 This is a schematic cross-sectional view of a semiconductor structure planarized in one embodiment;

[0051] Figure 10 This is a schematic cross-sectional view of the electrode after it is led out in one embodiment.

[0052] Explanation of reference numerals in the attached figures:

[0053] 100, Substrate; 210, First metal nitride layer; 220, Second metal nitride layer; 230, Sidewall; 310, First source / drain contact layer; 320, Second source / drain contact layer; 400, Interlayer dielectric layer; 410, Interlayer dielectric material layer; 500, Semiconductor layer; 610, Gate dielectric layer; 620, Gate; 700, Capping layer. Detailed Implementation

[0054] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0056] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0057] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0058] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0059] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0060] Existing products using thin-film transistors still have shortcomings in terms of performance and miniaturization. Therefore, this disclosure provides a semiconductor structure including a stacked source / drain contact layer composed of metal nitrides to improve conductivity and reduce the resistance of the semiconductor structure.

[0061] Please see Figure 1 In some embodiments, this disclosure provides a method for fabricating a semiconductor structure, including steps S100-S200.

[0062] S100 provides a substrate.

[0063] S200, a source / drain contact layer is formed on the substrate; the source / drain contact layer includes: a first metal nitride layer and a second metal nitride layer stacked in a direction away from the substrate; the atomic percentage of nitrogen in the first metal nitride layer is less than the atomic percentage of nitrogen in the second metal nitride layer.

[0064] like Figure 2 As shown, the substrate 100 can be a single-layer structure or a multilayer structure. The substrate 100 in this embodiment can be any suitable substrate material known in the art. For example, it can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or it can be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz, or a glass substrate, etc., which are not limited in this disclosure.

[0065] Metal nitride layers are sequentially deposited on substrate 100 to form source / drain contact layers. The source / drain contact layers are used to bring out the source / drain terminals of the transistors, and each transistor has two independent, non-shared source / drain contact layers. In this disclosure, the source / drain contact layers include a first metal nitride layer 210 and a second metal nitride layer 220 sequentially deposited on substrate 100. The first metal nitride layer 210 is deposited on substrate 100, and the second metal nitride layer 220 is deposited on the side of the first metal nitride layer 210 facing away from substrate 100.

[0066] The metal nitride disclosed herein may be titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), etc. Furthermore, the atomic percentage of nitrogen in the first metal nitride layer 210 is less than the atomic percentage of nitrogen in the second metal nitride layer 220. That is, the material of the first metal nitride layer 210 is a low-nitrogen metal nitride, and the material of the second metal nitride layer 220 is a nitrogen-rich metal nitride.

[0067] This disclosure provides two metal nitride layers with different nitrogen contents in the source / drain contact layer. The second metal nitride layer 220 with a high nitrogen content can improve the strength and oxidation resistance of the source / drain contact layer, while the first metal nitride layer 210 with a low nitrogen content can improve the conductivity of the source / drain contact layer, thereby reducing the resistance of the source / drain contact layer and improving the performance of the semiconductor.

[0068] Please see Figures 3 to 6 In some specific embodiments, the source / drain contact layer includes a first source / drain contact layer 310 and a second source / drain contact layer 320 spaced apart in the direction perpendicular to the substrate 100. The formation of the source / drain contact layer on the substrate in step S200 may include the following steps S210-S240.

[0069] S210, a first metal nitride layer, a second metal nitride layer, an interlayer dielectric material layer, a first metal nitride layer, and a second metal nitride layer are sequentially stacked on the substrate.

[0070] S220, a first metal nitride layer and a second metal nitride layer are patterned above the interlayer dielectric material layer to form a second source / drain contact layer.

[0071] S230, based on the self-aligned etching of the interlayer dielectric material layer of the second source / drain contact layer, forms an interlayer dielectric layer.

[0072] S240, forming a semiconductor layer covering the sidewalls of the second source / drain contact layer, the interlayer dielectric layer, and a portion of the top surface of the first source / drain contact layer.

[0073] Please see Figures 3 to 5 The source / drain contact layer formed in this disclosure includes a first source / drain contact layer 310 and a second source / drain contact layer 320 sequentially deposited on a substrate 100, and an interlayer dielectric layer 400 isolating the first source / drain contact layer 310 and the second source / drain contact layer 320. The first source / drain contact layer 310, the interlayer dielectric layer 400, and the second source / drain contact layer 320 are all deposited in a direction perpendicular to the substrate 100. Both the first source / drain contact layer 310 and the second source / drain contact layer 320 include a stacked first metal nitride layer 210 and a second metal nitride layer 220.

[0074] Please continue reading. Figure 3 and Figure 4 During fabrication, a first metal nitride layer 210 and a second metal nitride layer 220 corresponding to the first source / drain contact layer 310 are first sequentially stacked on the substrate 100. Then, an interlayer dielectric material layer 410 is deposited, and then the first metal nitride layer 210 and the second metal nitride layer 220 corresponding to the second source / drain contact layer 320 are formed on the interlayer dielectric material layer 410.

[0075] The second source / drain contact layer 320 is patterned so that its length is less than that of the first source / drain contact layer 310. The patterning process may include exposure, development, photolithography, etching, and other procedures to process the second source / drain contact layer 320 to obtain the desired pattern. The orthographic projection of the patterned second source / drain contact layer 320 onto the substrate 100 lies within the orthographic projection of the first source / drain contact layer 310 onto the substrate 100. It should be noted that... Figure 3 The source / drain contact layer obtained in this process is the initial second source / drain contact layer. For example... Figure 4 As shown, after etching the stacked first metal nitride layer 210 and second metal nitride layer 220 to form an initial second source / drain contact layer, a second source / drain contact layer 320 is formed after forming a sidewall 230 covering the sidewalls of the second metal nitride layer 220 and the first metal nitride layer 210 in the initial second source / drain contact layer.

[0076] Please continue reading. Figures 4 to 5 The interlayer dielectric material layer 410 is etched along the sidewall of the second source / drain contact layer 320 to obtain the interlayer dielectric layer 400 for supporting the second source / drain contact layer 320.

[0077] Please continue reading. Figure 6 A semiconductor layer 500 is deposited on the first source / drain contact layer 310, the interlayer dielectric layer 400, and the second source / drain contact layer 320 to form a channel. For example... Figure 6 As shown, a self-aligned deposition technique can be used to deposit semiconductor layer material, such that the deposited semiconductor layer 500 covers the sidewalls of the second source / drain contact layer 320, the interlayer dielectric layer 400, and part of the top surface of the first source / drain contact layer 310. The semiconductor layer 500 is formed vertically and is in contact with the second metal nitride layer 220, which has a high nitrogen content in the source / drain contact layer.

[0078] The semiconductor material of semiconductor layer 500 can be indium gallium zinc oxide (IGZO). It should be noted that the material of semiconductor layer 500 can also be indium tin oxide (ITO), indium tungsten oxide (IWO), or ZnO. x InO x In₂O₃, InWO₂, SnO₂, TiO₂ x InS n O x Zn x O y N z Mg x Zn y O z In xZn y O z In x Ga y Zn z O a Zr x In y Zn z O a Hf x In y Zn z O a Sn x In y Zn z O a Al x Sn y In z Zn a O d Si x In y Zn z O a Zn x Sn y O z Al x Zn y Sn z O a Ga x Zn y Sn z O a Zr x Zn y Sn z O a InGaSiO, Indium aluminum zinc oxide (IAZO), Indium gallium oxide (IGO), Indium zinc oxide (IZO), IZO x Materials, etc.

[0079] Please continue reading. Figures 3 to 4 In some further embodiments, the above step S220 forming the second source / drain contact layer 320 includes the following steps S221-S222.

[0080] S221, a first metal nitride layer and a second metal nitride layer are patterned above the interlayer dielectric material layer to form an initial second source / drain contact layer.

[0081] S222, based on the initial second source / drain contact layer, a sidewall is formed by self-alignment to cover the sidewalls of the second metal nitride layer and the first metal nitride layer, thereby obtaining the second source / drain contact layer. The sidewall is made of the same material as the second metal nitride layer.

[0082] After stacking and forming the first metal nitride layer 210 and the second metal nitride layer 220 corresponding to the second source / drain contact layer 320, the second source / drain contact layer 320 is patterned such that the orthographic projection of the etched second source / drain contact layer 320 on the substrate 100 is smaller than the orthographic projection of the first source / drain contact layer 310 on the substrate 100. The resulting source / drain contact layer is the initial second source / drain contact layer.

[0083] Based on the initial second source / drain contact layer, a sidewall 230 covering the second metal nitride layer 220 and the sides of the first metal nitride layer 210 is formed using a self-aligned technique to obtain the second source / drain contact layer 320. The sidewall 230 is made of the same material as the second metal nitride layer 220, which is a metal nitride material with a high nitrogen content.

[0084] Please see Figure 7 In some embodiments, the preparation method further includes: performing self-aligned doping on the first source / drain contact layer 310 and the second source / drain contact layer 320 to form the doped first source / drain contact layer 310 and the doped second source / drain contact layer 320.

[0085] For example, self-aligned doping can be achieved using argon plasma sputtering technology. In a high vacuum environment, Ar atoms are dissociated to generate secondary electrons and Ar ions. The negative potential on the target material is then used to accelerate the Ar ions to bombard the target material, causing the metal on the target material to be deposited on the first source / drain contact layer 310 and the second source / drain contact layer 320.

[0086] Please see Figure 8 In some embodiments, the preparation method further includes the following steps S310-S320.

[0087] S310, a gate dielectric layer is formed on the surface of the semiconductor layer and the first source / drain contact layer that is not covered by the semiconductor layer.

[0088] S320, a gate is formed on the sidewall surface of the gate dielectric layer away from the semiconductor layer, and the gate extends in a direction perpendicular to the substrate.

[0089] Please continue to refer to Figure 8A dielectric layer material is deposited on the surfaces of the semiconductor layer 500 and the first source / drain contact layer 310 that are not covered by the semiconductor layer 500 to form a gate dielectric layer 610. For example, the dielectric layer material may be made of, but is not limited to, silicon oxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2) or other insulating materials, so that the gate dielectric layer 610 has a high dielectric constant and good insulating properties.

[0090] Then, gate material is deposited on the sidewall surface of the gate dielectric layer 610 away from the semiconductor layer 500 to form gate 620. For example... Figure 8 As shown, the gate 620 extends along a direction perpendicular to the substrate 100. Exemplarily, the material of the gate 620 may include, but is not limited to, titanium nitride (TiN).

[0091] Please refer to Figure 9 In some other embodiments, a capping layer 700 is deposited on the formed semiconductor structure. The material of the capping layer 700 may include, but is not limited to, silicon dioxide. The semiconductor structure after depositing the capping layer 700 is then planarized.

[0092] Please refer to Figure 10 In some embodiments, the preparation method further includes the following steps S410-S420.

[0093] S410 forms a gate lead-out electrode on the surface of the gate that is away from the substrate.

[0094] S420, a first source / drain lead-out electrode is formed on the surface of the first source / drain contact layer away from the substrate.

[0095] S430, a second source / drain electrode is formed on the surface of the second source / drain contact layer away from the substrate.

[0096] A transistor is formed using a gate electrode, a first source-drain electrode, and a second source-drain electrode. The first source-drain electrode and the second source-drain electrode serve as the source and drain electrodes, respectively. That is, if the first source-drain electrode is used as the source, then the second source-drain electrode is the drain; if the first source-drain electrode is used as the drain, then the second source-drain electrode is the source.

[0097] Please continue reading. Figure 10 The present invention also provides a semiconductor structure. The semiconductor structure includes a substrate 100 and a source / drain contact layer disposed on the substrate 100. The source / drain contact layer includes a first metal nitride layer 210 and a second metal nitride layer 220 stacked in a direction away from the substrate 100. The atomic percentage of nitrogen in the first metal nitride layer 210 is less than the atomic percentage of nitrogen in the second metal nitride layer 220.

[0098] like Figure 10 As shown, the substrate 100 can be a single-layer structure or a multilayer structure. The substrate 100 in this embodiment can be any suitable substrate material known in the art. For example, it can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or it can be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz, or a glass substrate, etc., which are not limited in this disclosure.

[0099] The source / drain contact layer is used to bring out the source / drain of the transistor. The source / drain contact layer of this disclosure includes a first metal nitride layer 210 in contact with the substrate 100, and a second metal nitride layer 220 formed on the side of the first metal nitride layer 210 away from the substrate 100.

[0100] The metal nitride can be titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), etc. In this disclosure, the atomic percentage of nitrogen in the first metal nitride layer 210 is less than the atomic percentage of nitrogen in the second metal nitride layer 220. That is, the material of the first metal nitride layer 210 is a low-nitrogen metal nitride, and the material of the second metal nitride layer 220 is a nitrogen-rich metal nitride. This disclosure provides two metal nitride layers with different nitrogen contents in the source / drain contact layer. This allows the strength and oxidation resistance of the source / drain contact layer to be improved by the second metal nitride layer 220 with a high nitrogen content, while the conductivity of the source / drain contact layer to be improved by the first metal nitride layer 210 with a low nitrogen content. This, in turn, reduces the resistance of the source / drain contact layer and improves the performance of the semiconductor.

[0101] In some embodiments, the elemental ratio of nitrogen to any other element in the first metal nitride layer 210 is greater than or equal to 0.6 and less than 1.

[0102] For example, the elemental ratio of nitrogen to any other metal element in the first metal nitride 210 can be 0.6, 0.7, 0.8, or 0.9. The metal nitride in the first metal nitride layer 210 can be titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), etc. It is understood that the metal nitride can also be other metal elements. In the first metal nitride layer 210, the elemental ratio of nitrogen to any other element is greater than or equal to 0.6 and less than 1. That is, the first metal nitride layer 210 is a nitrogen-poor nitride layer. Because the nitrogen content in the first metal nitride layer 210 is low, the corresponding metal element content is high. The increased metal element content is beneficial to the movement of charge carriers, resulting in better conductivity of the first metal nitride layer 210.

[0103] In other embodiments, the nitrogen element in the second metal nitride layer 220 has an elemental ratio greater than 1 and less than or equal to 1.3 with any other element.

[0104] For example, the elemental ratio of nitrogen to any metal element in the second metal nitride layer 220 can be 1.1, 1.2 or 1.3.

[0105] The second metal nitride layer 220 is similar to the first metal nitride layer 210. The metal nitride can be titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), or nitrides of other metal elements. In the second metal nitride layer 220, the elemental ratio of nitrogen to any other element is greater than 1 and less than or equal to 1.3. That is, the second metal nitride layer 220 is a high-nitrogen nitride layer. Due to the high nitrogen content in the second metal nitride layer 220, the corresponding metal element content is low. The increase in nitrogen content leads to changes in the crystal structure, increasing electron scattering, resulting in lower electrical conductivity of the second metal nitride layer 220 compared to the first metal nitride layer 210. However, the second metal nitride layer 220 has higher hardness, wear resistance, and oxidation resistance, and good thermal stability.

[0106] In some further embodiments, the thickness of the first metal nitride layer 210 is greater than the thickness of the second metal nitride layer 220.

[0107] In the source / drain contact layer of this disclosure, the thickness of the first metal nitride layer 210 is greater than the thickness of the second metal nitride layer 220, that is, the thickness of the metal nitride layer with a high nitrogen content is less than the thickness of the metal nitride layer with a low nitrogen content. The source / drain contact layer of this disclosure exhibits better conductivity while ensuring strength and strong oxidation resistance, thereby reducing the resistance of the source / drain contact layer and further miniaturizing the semiconductor device.

[0108] In some specific embodiments, the ratio of the thickness of the first metal nitride layer 210 to the thickness of the second metal nitride layer 220 ranges from 6:1 to 50:1.

[0109] For example, the thickness of the first metal nitride layer 210 can be 30nm-50nm, such as 30nm, 35nm, 40nm, 45nm or 50nm. The thickness of the second metal nitride layer 220 can be 1nm-5nm, such as 1nm, 2nm, 3nm, 4nm or 5nm.

[0110] Please continue reading. Figure 10 In some embodiments, the source / drain contact layer includes a first source / drain contact layer 310 and a second source / drain contact layer 320 spaced apart in a direction perpendicular to the substrate 100, and an interlayer dielectric layer 400 located between the first source / drain contact layer 310 and the second source / drain contact layer 320. The second source / drain contact layer 320 is located on the side of the interlayer dielectric layer 400 opposite to the first source / drain contact layer 310. The orthographic projections of the second source / drain contact layer 320 and the interlayer dielectric layer 400 on the substrate 100 are both located within the orthographic projection of the first source / drain contact layer 310 on the substrate 100.

[0111] The semiconductor structure also includes a semiconductor layer 500, which covers the sidewalls of the second source / drain contact layer 320, the interlayer dielectric layer 400, and a portion of the top surface of the first source / drain contact layer 310. The semiconductor layer 500 is formed vertically and is in contact with a second metal nitride layer 220, which has a high nitrogen content in the source / drain contact layer.

[0112] The semiconductor material of semiconductor layer 500 can be indium gallium zinc oxide (IGZO). It should be noted that the material of semiconductor layer 500 can also be indium tin oxide (ITO), indium tungsten oxide (IWO), or ZnO. x InO x In₂O₃, InWO₂, SnO₂, TiO₂ x InS n O x Zn x O y N z Mg x Zn y O z In x Zn y O z In x Ga y Zn z O a Zrx In y Zn z O a Hf x In y Zn z O a Sn x In y Zn z O a Al x Sn y In z Zn a O d Si x In y Zn z O a Zn x Sn y O z Al x Zn y Sn z O a Ga x Zn y Sn z O a Zr x Zn y Sn z O a InGaSiO, Indium aluminum zinc oxide (IAZO), Indium gallium oxide (IGO), Indium zinc oxide (IZO), IZO x Materials, etc.

[0113] The source / drain contact layer disclosed herein includes two independent, non-shared first source / drain contact layers 310 and 320 for leading out the source / drain of the transistor. The first source / drain contact layer 310 and the second source / drain contact layer 320 are isolated by an interlayer dielectric layer 400. It should be noted that... Figure 10 In the semiconductor structure shown, the first source / drain contact layer 310 is used as the drain contact and the second source / drain contact layer 320 is used as the source contact as an example. In practical applications, both the first source / drain contact layer 310 and the second source / drain contact layer 320 can be used as either source or drain contacts, and this disclosure does not limit this.

[0114] In some further embodiments, please refer to... Figure 10The second source / drain contact layer 320 also includes a sidewall 230 covering the sidewalls of the second metal nitride layer 220 and the first metal nitride layer 210.

[0115] The sidewalls 230 of the second source / drain contact layer 320 can be formed by self-aligned etching. In this embodiment, the sidewalls 230 are made of the same material as the second metal nitride layer 220. That is, the material of the sidewalls 230 is also a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), or nitrides of other metal elements. For example, in this embodiment, the nitrogen element in the sidewalls 230 has an elemental ratio greater than 1 and less than or equal to 1.3 with any other element.

[0116] Furthermore, the thickness of the sidewall 230 is the same as that of the second metal nitride layer 220. For example, the thickness of the sidewall 230 can be 1nm-5nm, such as 1nm, 2nm, 3nm, 4nm or 5nm.

[0117] In this embodiment, a sidewall 230 of the same material as the second metal nitride layer 220 is formed on the sidewall of the second source / drain contact layer 320, thereby improving the durability of the second source / drain contact layer 320 and improving the performance of the device.

[0118] Please continue reading. Figure 10 In some embodiments, the semiconductor structure of this disclosure further includes a gate dielectric layer 610 and a gate 620. The gate dielectric layer 610 covers the surface of the semiconductor layer 500 and the first source / drain contact layer 310 that is not covered by the semiconductor layer 500. The gate 620 is located on the surface of the gate dielectric layer 610 opposite to the sidewalls of the semiconductor layer 500 that extend in a direction perpendicular to the substrate 100.

[0119] Both the gate dielectric layer 610 and the gate 620 can be formed by deposition. The material of the gate dielectric layer 610 can be, but is not limited to, silicon oxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), or other insulating materials, giving the gate dielectric layer 610 a high dielectric constant and good insulating properties. The material of the gate 620 can be, but is not limited to, titanium nitride (TiN).

[0120] This disclosure also provides an electronic device, such as a data storage device, a photocopier, a network device, a home appliance, an instrument, a mobile phone, or a computer. This electronic device may include the semiconductor structure described in some of the above embodiments, or may be fabricated using the semiconductor structure fabrication methods described in some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited in this disclosure.

[0121] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0122] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate and a source / drain contact layer disposed on the substrate; wherein, The source / drain contact layer includes: a first metal nitride layer and a second metal nitride layer stacked in a direction away from the substrate; the atomic percentage of nitrogen in the first metal nitride layer is less than the atomic percentage of nitrogen in the second metal nitride layer.

2. The semiconductor structure according to claim 1, characterized in that, In the first metal nitride layer, the elemental ratio of nitrogen to any other element is greater than or equal to 0.6 and less than 1.

3. The semiconductor structure according to claim 1, characterized in that, In the second metal nitride layer, the elemental ratio of nitrogen to any other element is greater than 1 and less than or equal to 1.

3.

4. The semiconductor structure according to claim 1, characterized in that, The thickness of the first metal nitride layer is greater than the thickness of the second metal nitride layer.

5. The semiconductor structure according to claim 4, characterized in that, The ratio of the thickness of the first metal nitride layer to the thickness of the second metal nitride layer ranges from 6:1 to 50:

1.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that, The source / drain contact layer includes a first source / drain contact layer and a second source / drain contact layer spaced apart in a direction perpendicular to the substrate; The semiconductor structure also includes: An interlayer dielectric layer is located between the first source / drain contact layer and the second source / drain contact layer; the second source / drain contact layer is located on the side of the interlayer dielectric layer opposite to the first source / drain contact layer; the orthogonal projections of the second source / drain contact layer and the interlayer dielectric layer on the substrate are both located within the orthogonal projection of the first source / drain contact layer on the substrate. A semiconductor layer covering the second source / drain contact layer, the sidewalls of the interlayer dielectric layer, and a portion of the top surface of the first source / drain contact layer.

7. The semiconductor structure according to claim 6, characterized in that, The second source / drain contact layer further includes: a sidewall covering the sidewalls of the second metal nitride layer and the first metal nitride layer; The sidewall is made of the same material as the second metal nitride layer.

8. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure also includes: A gate dielectric layer covers the surface of the semiconductor layer and the first source / drain contact layer that is not covered by the semiconductor layer; The gate is located on the surface of the gate dielectric layer opposite to the sidewalls of the semiconductor layer that extend in a direction perpendicular to the substrate.

9. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A source / drain contact layer is formed on the substrate; The source / drain contact layer includes: a first metal nitride layer and a second metal nitride layer stacked in a direction away from the substrate; the atomic percentage of nitrogen in the first metal nitride layer is less than the atomic percentage of nitrogen in the second metal nitride layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The source / drain contact layer includes a first source / drain contact layer and a second source / drain contact layer spaced apart in a direction perpendicular to the substrate; The formation of the source / drain contact layer on the substrate includes: A first metal nitride layer, a second metal nitride layer, an interlayer dielectric material layer, a first metal nitride layer, and a second metal nitride layer are sequentially stacked on the substrate. Patterning the first metal nitride layer and the second metal nitride layer above the interlayer dielectric material layer to form the second source / drain contact layer; Based on the second source / drain contact layer, the interlayer dielectric material layer is etched by self-alignment to form an interlayer dielectric layer; A semiconductor layer is formed covering the sidewalls of the second source / drain contact layer, the interlayer dielectric layer, and a portion of the top surface of the first source / drain contact layer.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, The patterning of the first metal nitride layer and the second metal nitride layer above the interlayer dielectric material layer to form the second source / drain contact layer includes: Patterning the first metal nitride layer and the second metal nitride layer above the interlayer dielectric material layer to form an initial second source / drain contact layer; Based on the initial second source / drain contact layer, a sidewall is formed by self-alignment, covering the sidewalls of the second metal nitride layer and the first metal nitride layer, to obtain the second source / drain contact layer; The sidewall is made of the same material as the second metal nitride layer.

12. The method for preparing a semiconductor structure according to claim 10, characterized in that, The preparation method further includes: A gate dielectric layer is formed on the surface of the semiconductor layer and the first source / drain contact layer that is not covered by the semiconductor layer; A gate is formed on the sidewall surface of the gate dielectric layer opposite to the semiconductor layer, and the gate extends in a direction perpendicular to the substrate.

13. The method for preparing a semiconductor structure according to claim 10, characterized in that, The preparation method further includes: The first source / drain contact layer and the second source / drain contact layer are self-aligned doped to form the doped first source / drain contact layer and the doped second source / drain contact layer.

14. The method for preparing a semiconductor structure according to claim 12, characterized in that, The preparation method further includes: The gate lead-out electrode is formed on the surface of the gate that is opposite to the substrate; A first source / drain electrode is formed on the surface of the first source / drain contact layer that is away from the substrate; A second source / drain electrode is formed on the surface of the second source / drain contact layer that is away from the substrate.

15. An electronic device, characterized in that, Includes the semiconductor structure as described in any one of claims 1-7, or the semiconductor structure prepared based on the method for preparing the semiconductor structure as described in any one of claims 8-14.

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