A same-side electrode plant lighting chip and a manufacturing method thereof

Abstract

The present application relates to the technical field of chip, specifically to a same-side electrode plant lighting chip and a manufacturing method thereof.The chip comprises, from bottom to top, an aluminum nitride substrate, a bonding layer, an oxide composite reflection layer, a graphene heat dissipation channel layer, an AZO transparent conductive layer, a P-face electrode, a GaP window layer, a P-type semiconductor layer, a light-emitting layer, an N-type semiconductor layer, a roughening layer, a passivation layer, a GaAs contact layer, and an N-face electrode.The present application is reasonably designed from the chip structure and manufacturing process, the P / N electrodes are made into a nested cladding structure, and a composite material mirror reflection layer is designed, so that the obtained LED chip has extremely high heat conduction performance, good mechanical strength and high temperature resistance, low cost, and the optical performance, conversion efficiency, heat dissipation effect are improved, and the service life is prolonged.

Description

Technical Field

[0001] This invention relates to the field of chip technology, specifically to a same-side electrode plant lighting chip and its manufacturing method. Background Technology

[0002] Plant lighting chips are LED chips specifically designed for plant growth, providing the specific spectrum required for plant development. With the rapid development of science and technology, the plant lighting market continues to grow, along with increasing technology and demand. This has led to the widespread application of red LED chips in plant lighting, presenting a significant market prospect. Faced with growing market demand and constantly evolving application scope and scenarios, the performance, cost, and reliability requirements for plant lighting chips are becoming increasingly stringent. Furthermore, conventional red LED chips generally suffer from low photoelectric conversion efficiency, high thermal efficiency, and high chip cost. Therefore, it is essential to design a single-electrode red LED chip for plant lighting that boasts high conversion efficiency, reliable and stable performance, strong heat dissipation, and low production cost. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides a same-side electrode plant lighting chip and its manufacturing method. This plant lighting chip is an improvement on conventional red LEDs, which can greatly enhance the conversion efficiency, heat dissipation, mechanical strength, and high-temperature resistance of the same-side electrode red LED chip, thereby extending the chip's lifespan.

[0004] This invention provides a same-side electrode plant lighting chip, which, from bottom to top, includes an aluminum nitride substrate, a bonding layer, an oxide composite reflective layer, a graphene heat dissipation channel layer, an AZO transparent conductive layer, a P-side electrode, a GaP window layer, a P-type semiconductor layer, a light-emitting layer, an N-type semiconductor layer, a roughening layer, a passivation layer, a GaAs contact layer, and an N-side electrode.

[0005] The P-side electrode is composed of a partial AZO transparent conductive layer, a P-side copper conductive layer, and a P-side nickel-titanium alloy electrode layer.

[0006] The N-side electrode consists of an ITO transparent conductive layer, an N-side copper conductive layer, and an N-side nickel-titanium alloy electrode layer.

[0007] This invention employs a rational design of the chip structure to create a nested, encapsulated P / N electrode structure. The outer layer is a nickel-titanium alloy electrode layer, which improves the electrode's resistance to deformation and corrosion, and serves as a support layer. Copper acts as the intermediate layer, enhancing electrode conductivity and providing a current injection channel, forming a highly conductive layer. ITO and AZO transparent conductive layers serve as ohmic contact layers for the N and P electrodes, respectively, reducing the use of gold and lowering manufacturing costs. Furthermore, the design incorporates an aluminum nitride substrate, an oxide composite reflective layer, a graphene heat dissipation channel layer, and an AZO transparent conductive layer, utilizing the aluminum nitride substrate... As a supporting substrate, it can improve the overall mechanical strength of the chip and form a good heat transfer substrate with the graphene heat dissipation channel layer, resulting in good heat dissipation. The oxide composite reflective layer, as an intermediate mirror reflective layer and bonding layer, can offset the stress brought by the epitaxial layer and provide good reflection effect. The AZO transparent conductive layer, as a P-side ohmic contact material, has good conductivity and high light transmittance. The graphene heat dissipation channel layer, as a heat dissipation layer, is nested on the outer ring of the mirror layer, providing a heat conduction channel for the chip, reducing the accumulation of thermal effects in the center of the chip, and improving the chip conversion efficiency. The final chip has high conversion efficiency, good heat dissipation, high mechanical strength, and long service life.

[0008] Furthermore, in the above technical solution, the N-type semiconductor layer includes an N-type epitaxial confinement layer and an N-type current spreading layer.

[0009] Furthermore, in the above technical solution, the oxide composite reflective layer is a structural layer that alternates between silicon oxide and titanium oxide five times, ending with silicon oxide; the graphene heat dissipation channel layer is nested in the outer ring of the composite mirror reflective layer composed of the bonding layer, the oxide composite reflective layer, and the AZO transparent conductive layer. In this technical solution, the oxide composite reflective layer is designed with an alternating structure of silicon oxide and titanium oxide, which can act as a mirror reflective layer and bonding layer to offset the stress brought by the epitaxial layer and provide a good reflection effect; the graphene heat dissipation channel layer is set in the outer ring of the composite mirror reflective layer, which can provide a heat conduction channel for the chip, reduce the accumulation of thermal effects in the center of the chip, and improve the chip conversion efficiency.

[0010] Furthermore, in the above technical solution, the copper purity of both the P-side copper conductive layer and the N-side copper conductive layer is 99.99%.

[0011] The present invention also provides a method for manufacturing the above-mentioned same-side electrode plant lighting chip, comprising the following steps:

[0012] S1. Provide a GaAs substrate, and epitaxially grow an etching stop layer, a GaAs contact layer, a roughening layer, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and a GaP window layer in sequence;

[0013] S2. An AZO transparent conductive layer is sputtered onto the GaP window layer by magnetron sputtering;

[0014] S3. An oxide composite reflective layer is deposited on the AZO transparent conductive layer;

[0015] S4. The back side of the epitaxial wafer with the deposited oxide composite reflective layer is attached to the ceramic disk with paraffin wax and then polished.

[0016] S5. Take an aluminum nitride substrate, deposit silicon oxide on its surface as a bonding layer, and attach it to a ceramic disk with paraffin wax on its back side and polish it.

[0017] S6. After activating the polished epitaxial wafer and aluminum nitride substrate, the bonding layers are placed face to face and bonded together in a bonding machine;

[0018] S7. The GaAs substrate of the chip is removed by wet etching to expose the etching stop layer;

[0019] S8. By wet etching, the corrosion stop layer is removed, a patterned GaAs contact layer is fabricated on the exposed GaAs contact layer, and the patterned GaAs contact layer is removed to expose the roughened layer.

[0020] S9. Create a patterned ITO pattern on the GaAs contact layer at the position corresponding to the N-side electrode, and then deposit a transparent conductive ITO layer by magnetron sputtering.

[0021] S10. Use photoresist to create P-side contact patterns on the chip roughening layer and etch out the P-side electrode contact area;

[0022] S11. Using photoresist, a nested three-layer electrode pattern is fabricated in the contact area between the chip's ITO transparent conductive layer and the P-side electrode.

[0023] S12. A copper conductive layer is sputtered inside a nested three-layer electrode pattern by magnetron sputtering;

[0024] S13. Using photoresist to fabricate a nested three-layer electrode pattern on a copper conductive layer;

[0025] S14. A nickel-titanium alloy layer is sputtered into the nested three-layer electrode pattern two by magnetron sputtering to complete the fabrication of the P-side electrode and the N-side electrode.

[0026] S15. The first dicing pattern is created on the chip roughening layer using photoresist, and the first dicing is etched using a dry etching process until the GaP window layer is cut off.

[0027] S16. A heat dissipation layer channel pattern is created using photoresist in the first dicing channel, and a dry etching process is used to etch the first dicing channel to the bonding layer cutoff point to form a heat dissipation layer channel.

[0028] S17. Graphene is sputtered into the heat dissipation layer channel by magnetron sputtering to form a graphene heat dissipation channel layer;

[0029] S18. Deposit a passivation layer on the chip surface;

[0030] S19. Pattern the remaining roughening layer using photoresist, and roughen the patterned roughening layer by wet etching to obtain a roughened surface;

[0031] S20. Thinning of the aluminum nitride substrate using a polishing method;

[0032] S21. Using a laser to cut and split along the second cutting path, the chip is separated to obtain a single chip.

[0033] Furthermore, in the above technical solution S2, the thickness of the AZO transparent conductive layer is 1500±20 angstroms; the magnetron sputtering conditions are: power 500±20W, oxygen 8±1sccm introduced.

[0034] Furthermore, in the above technical solution, in S3, the light control mode of the Optical 1500 optical coating machine is used to vapor-deposit an oxide composite reflective layer. The oxide composite reflective layer is formed by alternating cyclic deposition of silicon oxide and titanium oxide, with an alternating cycle of 5 times. Finally, a 3±0.1μm silicon oxide layer is deposited as a substrate bonding layer.

[0035] Furthermore, in the above technical solutions S4 and S5, a silicon oxide polishing slurry is used for polishing until the surface layer reaches the nanoscale.

[0036] Furthermore, in the above technical solution S6, the bonding conditions are: temperature 500±20℃, pressure 32000±500kgf.

[0037] Furthermore, in the above technical solution S18, the passivation layer is fabricated as follows: first, benzocyclobutene is spin-coated on the front side of the chip, and protective patterns are made on the side of the chip and the first dicing channel using photoresist; then, the photoresist and benzocyclobutene in other areas are washed away with a developer, and then the photoresist on the side of the chip and the benzocyclobutene on the first dicing channel is removed by a stripper; finally, the chip is placed in an RTA furnace and treated at a temperature of 250±10℃ for 15±2s, and argon gas is introduced to solidify the benzocyclobutene on the side and the dicing channel, forming a passivation layer.

[0038] Compared with the prior art, the present invention has the following advantages:

[0039] This invention, through rational design of the chip structure, creates a nested encapsulation structure for the P / N electrodes. Utilizing the high strength and corrosion resistance of nickel-titanium alloy, it serves as a support layer for the electrodes, improving their resistance to deformation and corrosion. The electrical and thermal conductivity of copper enhances the electrode's conductivity. The conductivity and high light transmittance of the ITO and AZO transparent conductive layers serve as ohmic contact layers for the N and P electrodes, respectively, reducing the use of gold and lowering manufacturing costs while ensuring the chip's optical performance. The bonding layer, oxide composite reflective layer, and AZO transparent conductive layer are combined into a composite mirror reflective layer. As an intermediate mirror reflective layer and bonding layer, it can offset the stress brought by the epitaxial layer and provide a good reflection effect; the AZO transparent conductive layer has good conductivity and high light transmittance; at the same time, the graphene heat dissipation channel layer, as a heat dissipation layer, is nested in the outer ring of the composite mirror reflective layer, which can not only provide a heat conduction channel for the chip and reduce the accumulation of heat effect in the center of the chip, but also improve the chip conversion efficiency. The combination of the above four factors ultimately achieves the purpose of improving the chip's optical performance, conversion efficiency, and heat dissipation capacity; in addition, using an aluminum nitride substrate as a support substrate can improve the overall mechanical strength of the chip and form a good heat transfer substrate with the graphene heat dissipation channel layer, further improving the heat dissipation effect.

[0040] The chip prepared by the method of this invention not only has extremely high thermal conductivity, good mechanical strength and high temperature resistance, and low cost, but also has improved optical performance, conversion efficiency, heat dissipation effect, and extended service life. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the structure of the same-side electrode plant lighting chip of the present invention;

[0042] Figure 2 This is a schematic diagram of the cutting path of the plant lighting chip with the same side electrode of the present invention.

[0043] Explanation of the labels in the diagram:

[0044] 1. Aluminum nitride substrate; 2. Bonding layer; 3. Oxide composite reflective layer; 4. Graphene heat dissipation channel layer; 5. AZO transparent conductive layer; 6. P-side copper conductive layer; 7. P-side nickel-titanium alloy electrode layer; 8. GaP window layer; 9. P-type semiconductor layer; 10. Light-emitting layer; 11. N-type epitaxial confinement layer; 12. N-type current spreading layer; 13. Roughening layer; 14. Passivation layer; 15. GaAs contact layer; 16. ITO transparent conductive layer; 17. N-side copper conductive layer; 18. N-side nickel-titanium alloy electrode layer; 19. First dicing track; 20. Second dicing track. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this application or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0046] In the description of this application, it should be understood that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application.

[0047] In the description of this application, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0048] Please see Figures 1 to 2 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0049] In some specific embodiments of the present invention, a plant lighting chip with a same-side electrode is provided, the structural schematic diagram of which is shown below. Figure 1 As shown, the chip, from bottom to top, includes an aluminum nitride substrate 1, a bonding layer 2, an oxide composite reflective layer 3, a graphene heat dissipation channel layer 4, an AZO transparent conductive layer 5, a P-side electrode, a GaP window layer 8, a P-type semiconductor layer 9, a light-emitting layer 10, an N-type semiconductor layer, a roughening layer 13, a passivation layer 14, a GaAs contact layer 15, and an N-side electrode.

[0050] Furthermore, the P-side electrode consists of a partially AZO transparent conductive layer, a P-side copper conductive layer 6, and a P-side nickel-titanium alloy electrode layer 7.

[0051] Furthermore, the N-side electrode is composed of an ITO transparent conductive layer 16, an N-side copper conductive layer 17, and an N-side nickel-titanium alloy electrode layer 18.

[0052] Furthermore, the N-type semiconductor layer consists of an N-type epitaxial confinement layer 11 and an N-type current spreading layer 12 from bottom to top.

[0053] Furthermore, the oxide composite reflective layer is a structural layer that alternates between silicon oxide and titanium oxide five times and ends with silicon oxide. This alternating cyclic structure can serve as a mirror reflective layer and bonding layer to offset the stress brought by the epitaxial layer and can provide a good reflective effect.

[0054] Furthermore, the graphene heat dissipation channel layer is nested in the outer ring of the composite mirror reflective layer composed of the bonding layer, oxide composite reflective layer, and AZO transparent conductive layer. This provides a heat conduction channel for the chip, reduces the accumulation of thermal effects in the center of the chip, and improves the chip conversion efficiency.

[0055] Some embodiments of the present invention also provide a method for manufacturing a plant lighting chip with a same-side electrode, comprising the following steps:

[0056] S1. Provide a GaAs substrate, and sequentially grow an etching stop layer, a GaAs contact layer, a roughening layer, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and a GaP window layer; specifically, provide a GaAs substrate as a chip growth substrate, first set the program on the MOCVD (metal-organic chemical vapor deposition) machine, and sequentially grow an etching stop layer, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and a GaP window layer on the GaAs substrate; wherein, the N-type semiconductor layer is, according to the epitaxial wafer growth method, an N-type epitaxial confinement layer and an N-type current spreading layer.

[0057] S2. Sputter an AZO transparent conductive layer on the GaP window layer by magnetron sputtering; specifically, a 1500±20 angstrom transparent conductive layer is sputtered on the patterned GaP window layer by magnetron sputtering with a power of 500±20W and an oxygen flow of 8±1 sccm.

[0058] S3. An oxide composite reflective layer is deposited on the AZO transparent conductive layer; specifically, different layers of silicon oxide and titanium oxide reflective layers are deposited by light control mode of the Optical 1500 optical coating machine, alternating 5 times, and finally a 3±0.1μm silicon oxide layer is deposited as a substrate bonding layer.

[0059] S4. The back side of the epitaxial wafer with the deposited oxide composite reflective layer is attached to a ceramic disk with paraffin wax and polished. Specifically, the silicon oxide bonding layer of the chip is polished at a uniform speed and pressure on a polishing machine using silicon oxide polishing slurry. 2μm of silicon oxide is removed by polishing, so that the flatness of the chip surface reaches the nanometer level.

[0060] S5. Take an aluminum nitride substrate, deposit silicon oxide as a bonding layer on its surface, and attach it to a ceramic disk with paraffin wax on its back side and polish it. Specifically, use silicon oxide polishing slurry to polish the silicon oxide bonding layer on the substrate surface at a uniform speed and pressure on a polishing machine, polishing to remove 2μm of silicon oxide, so that the surface flatness of the aluminum nitride substrate reaches the nanometer level.

[0061] S6. After activating the polished epitaxial wafer and the aluminum nitride substrate, the bonding layers are placed face to face and bonded together in a bonding machine. Specifically, a silicon oxide activating solution is used to activate the silicon oxide on the polished epitaxial wafer and the substrate surface to improve surface activity. Then, the activated chip and the substrate silicon oxide face to face are placed, and the epitaxial wafer and the aluminum nitride substrate are bonded together using a high-temperature and high-pressure bonding machine under high temperature and high pressure (500±20℃, 32000±500kgf).

[0062] S7. The GaAs substrate of the chip is removed by wet etching to expose the etching stop layer; specifically, the solution used for wet etching is a mixed solution of ammonia and hydrogen peroxide in any proportion to remove the GaAs substrate of the bonded chip and expose the etching stop layer.

[0063] S8. By wet etching, the etching stop layer is removed, and a patterned GaAs contact layer is fabricated on the exposed GaAs contact layer. The patterned GaAs contact layer is then removed to expose the roughened layer. Specifically, the solution used for wet etching is a mixture of phosphoric acid and hydrochloric acid in any proportion to remove the etching stop layer. Then, a patterned GaAs contact layer is fabricated using photoresist, and a gallium arsenide etching solution (a mixture of phosphoric acid, hydrogen peroxide, and water) is used to remove the GaAs contact layer except for the patterned layer, exposing the roughened layer.

[0064] S9. Create a patterned ITO fabrication pattern on the GaAs contact layer at the position corresponding to the N-side electrode, and then magnetron sputter a layer of ITO transparent conductive layer; specifically, magnetron sputter a layer of ITO transparent conductive layer with a thickness of 1500±20 angstroms at the patterned position by using a power of 500±20W and introducing oxygen at 8±1 sccm.

[0065] S10. Use photoresist to create a P-side contact pattern on the chip roughening layer and etch out the P-side electrode contact area; specifically, set the ICP parameters and use a dry etching process to etch the exposed roughening layer down to the etched GaP window layer.

[0066] S11. A nested three-layer electrode pattern is fabricated in the contact area between the chip's ITO transparent conductive layer and the P-side electrode using photoresist; specifically, the ITO transparent conductive layer corresponds to the N-side electrode, and the P-side electrode contact area corresponds to the P-side electrode.

[0067] S12. A copper conductive layer is sputtered in the nested three-layer electrode pattern by magnetron sputtering; specifically, the copper material selected for the copper conductive layer is copper with a purity of 99.99%, and the sputtered copper conductive layer is stripped of metal and the excess photoresist is cleaned with acetone.

[0068] S13. Using photoresist, a nested three-layer electrode pattern is fabricated on a copper conductive layer.

[0069] S14. Sputter nickel-titanium alloy into the nested three-layer electrode pattern two by magnetron sputtering to complete the fabrication of P-side electrode and N-side electrode; specifically, the nickel-titanium alloy is a metal compound with nickel and titanium each accounting for 50%, and the sputtered nickel-titanium alloy electrode layer is stripped of metal and cleaned with acetone to remove excess photoresist.

[0070] S15. A first dicing pattern is fabricated on the chip roughening layer using photoresist, and the first dicing 19 is etched using a dry etching process; specifically, the first dicing is etched to the GaP window layer, as shown below. Figure 2 As shown.

[0071] S16. A heat dissipation layer channel pattern is created using photoresist in the first dicing channel, and a dry etching process is used to etch the first dicing channel to the bonding layer cutoff point to form a heat dissipation layer channel.

[0072] S17. Graphene is sputtered into the heat dissipation layer channel by magnetron sputtering to form a graphene heat dissipation channel layer; specifically, the magnetron sputtering process is: power 500±20W, oxygen 8±1sccm; and the graphene in other areas is peeled off by a peeling method, and excess photoresist on the surface is removed by photoresist removal solution.

[0073] S18. Deposit a passivation layer on the chip surface; specifically, first spin-coat benzocyclobutene on the front side of the chip, and use photoresist to create a protective pattern on the chip side and the first dicing track. Then, wash the photoresist and benzocyclobutene in other areas with a developer, and then remove the photoresist on the chip side and the benzocyclobutene on the first dicing track by cleaning with a stripper. Finally, place the chip in an RTA furnace at a temperature of 250±10℃ for 15±2s, and introduce argon gas to solidify the benzocyclobutene on the side and the dicing track to form a passivation layer.

[0074] S19. Pattern the remaining roughening layer using photoresist, and roughen the patterned roughening layer by wet etching to obtain a roughened surface.

[0075] S20. The aluminum carbide substrate is thinned by using a grinding method.

[0076] S21. Using a laser to cut and split along the second cutting track 20, the chip is separated to obtain a single chip.

[0077] In summary, this invention, through rational design of chip structure and manufacturing process, creates a nested encapsulation structure for P / N electrodes and designs a composite material mirror reflective layer. The resulting LED chip has extremely high thermal conductivity, good mechanical strength and high temperature resistance, low cost, and improved optical performance, conversion efficiency, heat dissipation effect, and extended service life.

[0078] Finally, it should be emphasized that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A plant lighting chip with same-side electrodes, characterized in that, The chip, from bottom to top, includes an aluminum nitride substrate, a bonding layer, an oxide composite reflective layer, a graphene heat dissipation channel layer, an AZO transparent conductive layer, a P-side electrode, a GaP window layer, a P-type semiconductor layer, a light-emitting layer, an N-type semiconductor layer, a roughening layer, a passivation layer, a GaAs contact layer, and an N-side electrode. The P-side electrode is composed of a partial AZO transparent conductive layer, a P-side copper conductive layer, and a P-side nickel-titanium alloy electrode layer. The N-side electrode is composed of an ITO transparent conductive layer, an N-side copper conductive layer, and an N-side nickel-titanium alloy electrode layer. The oxide composite reflective layer is a structural layer that ends with silicon oxide after five alternating cycles of silicon oxide and titanium oxide; the graphene heat dissipation channel layer is nested in the outer ring of the composite material mirror reflective layer composed of the bonding layer, the oxide composite reflective layer, and the AZO transparent conductive layer.

2. The same-side electrode plant lighting chip according to claim 1, characterized in that, The N-type semiconductor layer includes an N-type epitaxial confinement layer and an N-type current spreading layer.

3. The same-side electrode plant lighting chip according to claim 1, characterized in that, The copper purity of both the P-side copper conductive layer and the N-side copper conductive layer is 99.99%.

4. A method for manufacturing a plant lighting chip with a same-side electrode according to any one of claims 1-3, characterized in that, Includes the following steps: S1. Provide a GaAs substrate, and epitaxially grow an etching stop layer, a GaAs contact layer, a roughening layer, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and a GaP window layer in sequence; S2. An AZO transparent conductive layer is sputtered onto the GaP window layer by magnetron sputtering; S3. An oxide composite reflective layer is deposited on the AZO transparent conductive layer; S4. The back side of the epitaxial wafer with the deposited oxide composite reflective layer is attached to the ceramic disk with paraffin wax and then polished. S5. Take an aluminum nitride substrate, deposit silicon oxide on its surface as a bonding layer, and attach it to a ceramic disk with paraffin wax on its back side and polish it. S6. After activating the polished epitaxial wafer and aluminum nitride substrate, the bonding layers are placed face to face and bonded together in a bonding machine; S7. The GaAs substrate of the chip is removed by wet etching to expose the etching stop layer; S8. By wet etching, the corrosion stop layer is removed, a patterned GaAs contact layer is fabricated on the exposed GaAs contact layer, and the patterned GaAs contact layer is removed to expose the roughened layer. S9. Create a patterned ITO pattern on the GaAs contact layer at the position corresponding to the N-side electrode, and then deposit a transparent conductive ITO layer by magnetron sputtering. S10. Use photoresist to create P-side contact patterns on the chip roughening layer and etch out the P-side electrode contact area; S11. Using photoresist, a nested three-layer electrode pattern is fabricated in the contact area between the chip's ITO transparent conductive layer and the P-side electrode. S12. A copper conductive layer is sputtered inside a nested three-layer electrode pattern by magnetron sputtering; S13. Using photoresist to fabricate a nested three-layer electrode pattern on a copper conductive layer; S14. A nickel-titanium alloy layer is sputtered into the nested three-layer electrode pattern two by magnetron sputtering to complete the fabrication of the P-side electrode and the N-side electrode. S15. The first dicing pattern is created on the chip roughening layer using photoresist, and the first dicing is etched using a dry etching process until the GaP window layer is cut off. S16. A heat dissipation layer channel pattern is created using photoresist in the first dicing channel, and a dry etching process is used to etch the first dicing channel to the bonding layer cutoff point to form a heat dissipation layer channel. S17. Graphene is sputtered into the heat dissipation layer channel by magnetron sputtering to form a graphene heat dissipation channel layer; S18. Deposit a passivation layer on the chip surface; S19. Pattern the remaining roughening layer using photoresist, and roughen the patterned roughening layer by wet etching to obtain a roughened surface; S20. The aluminum nitride substrate is thinned by a grinding method; S21. Using a laser to cut and split along the second cutting path, the chip is separated to obtain a single chip.

5. The manufacturing method according to claim 4, characterized in that, In S2, the thickness of the AZO transparent conductive layer is 1500±20 angstroms; the magnetron sputtering conditions are: power 500±20W, oxygen 8±1sccm.

6. The manufacturing method according to claim 4, characterized in that, In S3, the light control mode of the Optical 1500 optical coating machine is used to deposit an oxide composite reflective layer. The oxide composite reflective layer is formed by alternating cyclic deposition of silicon oxide and titanium oxide, with an alternating cycle of 5 times. Finally, a 3±0.1μm silicon oxide layer is deposited as a substrate bonding layer.

7. The manufacturing method according to claim 4, characterized in that, In S4 and S5, a silicon oxide polishing slurry is used for polishing until the surface layer reaches the nanoscale.

8. The manufacturing method according to claim 4, characterized in that, In S6, the bonding conditions are: temperature 500±20℃, pressure 32000±500kgf.

9. The manufacturing method according to claim 4, characterized in that, In S18, the passivation layer is fabricated as follows: first, benzocyclobutene is spin-coated on the front side of the chip, and photoresist is used to create protective patterns on the chip side and the first dicing track; then, the photoresist and benzocyclobutene in other areas are washed away with a developer, and then the photoresist on the chip side and the benzocyclobutene on the first dicing track is removed by a stripper; finally, the chip is placed in an RTA furnace and treated at a temperature of 250±10℃ for 15±2s, and argon gas is introduced to solidify the benzocyclobutene on the side and the dicing track, forming a passivation layer.

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