Semiconductor packages

Abstract

A semiconductor package may include: a base wafer; a plurality of lower core wafers stacked on the base wafer; an upper core wafer on the plurality of lower core wafers; an oxide structure covering side surfaces of the plurality of lower core wafers and the upper core wafer; and a molded structure configured to cover the side surfaces of the oxide structure and spaced apart from the plurality of lower core wafers and the upper core wafer, the oxide structure being inserted between the molded structure and the plurality of lower core wafers and the upper core wafer. Each of the base wafer and the plurality of lower core wafers may include a through electrode, and the upper core wafer may include an insulating layer disposed on its bottom surface and pads disposed in the insulating layer. The oxide structure may expose an edge portion of the top surface of the base wafer.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0167421, filed on November 21, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor package, and more particularly, to a semiconductor package comprising a plurality of stacked semiconductor chips. Background Technology

[0004] The rapid development of the electronics industry has led to an increased demand for higher-performance electronic devices. To achieve these higher performance, the need for methods of arranging multiple semiconductor chips is constantly growing. To meet this demand, a semiconductor packaging technology has been proposed in which multiple vertically stacked semiconductor chips are connected using through-substrate vias (TSVs). Summary of the Invention

[0005] An embodiment of the present invention provides a semiconductor package with improved structural stability.

[0006] According to embodiments of the present invention, a semiconductor package may include: a base wafer; a plurality of lower core wafers stacked on the base wafer; and an upper core wafer on the plurality of lower core wafers;

[0007] An oxide structure that covers the side surfaces of multiple lower core wafers and the side surfaces of upper core wafers;

[0008] The system includes a molded structure configured to cover the side surfaces of the oxide structure and spaced apart from a plurality of lower and upper core wafers, with the oxide structure inserted between the molded structure and the plurality of lower and upper core wafers. Each of the base wafer and the plurality of lower core wafers may include a through electrode, and the upper core wafer may include an insulating layer disposed on its bottom surface and pads disposed in the insulating layer. The oxide structure may expose an edge portion of the top surface of the base wafer.

[0009] According to embodiments of the present invention, a semiconductor package may include: a base wafer; a plurality of lower core wafers stacked on the base wafer; an upper core wafer on the plurality of lower core wafers; an oxide structure covering the side surfaces of the plurality of lower core wafers and the side surfaces of the upper core wafer; and a molded structure on the side surfaces of the oxide structure. The width of the oxide structure in the horizontal direction may be constant and independent of the horizontal plane, and the horizontal plane of the top surface of the upper core wafer may be substantially equal to the horizontal plane of the top surface of the oxide structure.

[0010] According to embodiments of the present invention, a semiconductor package may include: a package substrate; an insert substrate on the package substrate; a logic chip on the insert substrate; and a plurality of chip stacks spaced apart from each other in a first direction parallel to the top surface of the package substrate, with the logic chip inserted between the plurality of chip stacks. One of the plurality of chip stacks may include: a base wafer; a plurality of lower core wafers stacked on the base wafer; an upper core wafer on the plurality of lower core wafers; an oxide structure covering the side surfaces of the plurality of lower core wafers and the side surfaces of the upper core wafer; and a molded structure covering the side surfaces of the oxide structure. The width of the oxide structure on the upper core wafer in the first direction may be substantially equal to the width of the oxide structure on one of the plurality of lower core wafers in the first direction. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view illustrating a semiconductor package according to an embodiment of the concept of the present invention.

[0012] Figure 2 This is a cross-sectional view illustrating a semiconductor package according to an embodiment of the concept of the present invention.

[0013] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 This is a cross-sectional view illustrating the process of manufacturing a semiconductor package according to an embodiment of the present invention.

[0014] Figure 17 This is a cross-sectional view illustrating a portion of the process for manufacturing a semiconductor package according to an embodiment of the present invention.

[0015] Figure 18 This is a plan view illustrating a semiconductor package according to an embodiment of the concept of the present invention.

[0016] Figure 19 It is along Figure 18 A cross-sectional view taken from line A-A'. Detailed Implementation

[0017] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are shown.

[0018] Figure 1This is a cross-sectional view illustrating a semiconductor package according to an embodiment of the concept of the present invention.

[0019] Reference Figure 1 The semiconductor package 10 may be, for example, a high-bandwidth memory (HBM). In this specification, the semiconductor package 10 may be referred to as a chip stack 10.

[0020] The semiconductor package 10 may include a base wafer 100, a plurality of lower core wafers 300, an upper core wafer 400, an oxide structure 450, and a molded structure 500.

[0021] The base chip 100 may be disposed in the lower part of the semiconductor package 10. In this specification, the base chip 100 may be referred to as a logic chip, logic chip, base chip, buffer chip, buffer wafer, or memory controller. The base chip 100 can be used as a logic chip to increase data transmission efficiency and reduce power consumption.

[0022] In this specification, the first direction D1 can be defined as a direction parallel to the top surface of the base wafer 100. The second direction D2 can be defined as a direction parallel to the top surface of the base wafer 100 and perpendicular to the first direction D1. The third direction D3 can be defined as a direction perpendicular to the top surface of the base wafer 100.

[0023] The base wafer 100 may include a first semiconductor substrate 110, a first upper insulating layer 131, a first upper pad 132, a first through electrode 150, a first lower insulating layer 121, and a first lower pad 122.

[0024] The first semiconductor substrate 110 may be formed of or comprise a semiconductor material (e.g., silicon or germanium). A first penetrating electrode 150 may be configured to penetrate the first semiconductor substrate 110. The first penetrating electrodes 150 may be spaced apart from each other in a first direction D1. The first penetrating electrodes 150 may be formed of or comprise a conductive material (e.g., copper). A diffusion-preventing pattern (e.g., tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), or tungsten (W)) may be disposed between the first penetrating electrodes 150 and the first semiconductor substrate 110.

[0025] A first lower insulating layer 121 may be disposed on the bottom surface of the first semiconductor substrate 110. Although not shown, interconnect patterns and circuit layers may be disposed in the first lower insulating layer 121. A first lower pad 122 may be disposed in the first lower insulating layer 121.

[0026] A first upper insulating layer 131 may be disposed on the top surface of the first semiconductor substrate 110. A first upper pad 132 may be disposed in the first upper insulating layer 131. The first lower insulating layer 121 and the first upper insulating layer 131 may be made of silicon oxide (SiO2), silicon nitride (Si3N4), and silicon oxynitride (SiO2). x N y At least one of silicon oxide (SiO2), silicon nitride (Si3N4), and silicon oxynitride (SiO2) forms or includes silicon oxide (SiO2). x N y At least one of the following.

[0027] First connection terminals 180 may be disposed on first lower pads 122. First connection terminals 180 may include solder balls or solder bumps. First connection terminals 180 may be formed of or include at least one of silver, copper, tin, and alloys thereof.

[0028] The lower core chip 300 may be disposed on the base chip 100. Each of the lower core chips 300 may be a memory chip. As an example, the lower core chip 300 may be one of DRAM, SRAM and NAND flash memory devices.

[0029] Each of the lower core chips 300 may include a second semiconductor substrate 310, a second upper insulating layer 331, a second upper pad 332, a second through electrode 350, a second lower insulating layer 321, and a second lower pad 322.

[0030] The second semiconductor substrate 310 may be formed of or include at least one of semiconductor materials (e.g., silicon (Si)). The second penetrating electrode 350 may be configured to penetrate the second semiconductor substrate 310. The second penetrating electrodes 350 may be spaced apart from each other in the first direction D1. The second penetrating electrodes 350 may be formed of or include at least one of conductive materials (e.g., copper). A diffusion-preventing pattern (e.g., tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), or tungsten (W)) may be disposed between the second penetrating electrodes 350 and the second semiconductor substrate 310.

[0031] A second lower insulating layer 321 may be disposed on the bottom surface of the second semiconductor substrate 310. Although not shown, interconnect patterns and circuit layers may be disposed in the second lower insulating layer 321. A second lower pad 322 may be disposed in the second lower insulating layer 321. Here, the second lower insulating layer 321 of the lower core wafer 300B, which is the lowermost lower core wafer in the lower core wafer 300, may be connected to the first upper insulating layer 131 of the base wafer 100 to form a hybrid bonding structure. In this specification, a hybrid bonding structure may refer to a bonding structure formed of two materials of the same type that are fused together at their interface. The second lower pad 322 of the lower core wafer 300B, which is the lowermost lower core wafer in the lower core wafer 300, may contact the first upper pad 132 of the base wafer 100.

[0032] The second upper insulating layer 331 may be disposed on the top surface of the second semiconductor substrate 310. The second upper pad 332 may be disposed within the second upper insulating layer 331. The second lower insulating layer 321 and the second upper insulating layer 331 may be made of silicon oxide (SiO2), silicon nitride (Si3N4), and silicon oxynitride (SiO2). x N y At least one of silicon oxide (SiO2), silicon nitride (Si3N4), and silicon oxynitride (SiO2) forms or includes silicon oxide (SiO2). x N y At least one of the following.

[0033] A second upper insulating layer 331 included in one of the lower core wafers 300 may be connected to a second lower insulating layer 321 of another lower core wafer 300 thereon. A second upper pad 332 in one of the lower core wafers 300 may contact a second lower pad 322 in another lower core wafer 300 thereon.

[0034] The upper core chip 400 may be disposed on the lower core chip 300. The upper core chip 400 may include a third semiconductor substrate 410, a third lower insulating layer 421, and a third lower pad 422. The thickness 400TH of the upper core chip 400 may be greater than the thickness 300TH of each of the lower core chips 300.

[0035] The third semiconductor substrate 410 may be formed of or comprise at least one semiconductor material (e.g., silicon (Si)). Unlike the base wafer 100 and the lower core wafer 300, the third semiconductor substrate 410 may not include a through electrode. The thickness of the third semiconductor substrate 410 in the third direction D3 may be greater than the thickness of the second semiconductor substrate 310 in the third direction D3. In an embodiment, the thickness of the third semiconductor substrate 410 in the third direction D3 may be in the range of 50 μm to 300 μm.

[0036] A third lower insulating layer 421 may be disposed on the bottom surface of the third semiconductor substrate 410. A third lower pad 422 may be disposed in the third lower insulating layer 421. Here, the second upper insulating layer 331 of the lower core wafer 300U, which is the uppermost lower core wafer in the lower core wafer 300, may be connected to the third lower insulating layer 421 of the upper core wafer 400 to form a hybrid bonding structure. The second upper pad 332 of the uppermost lower core wafer 300U may contact the third lower pad 422 of the upper core wafer 400.

[0037] The oxide structure 450 may be disposed on the top surface of the base wafer 100. Specifically, the oxide structure 450 may be configured to expose the edge portion of the top surface of the base wafer 100.

[0038] The oxide structure 450 may cover the side surfaces of the lower core wafer 300 and the upper core wafer 400. That is, the oxide structure 450 may be configured to surround the opposing side surfaces of the lower core wafer 300 and the upper core wafer 400. The level of the top surface 400t of the upper core wafer 400 may be substantially equal to the level of the top surface 450t of the oxide structure 450. The expression "substantially equal to a level" may mean that it is at the same level relative to a level being compared with, and allows for approximations, inaccuracies, and measurement limitations under the relevant circumstances as understood by those skilled in the art. The expression "substantially equal to a level" may indicate that the level being compared with (which is intended to be the same) has some variation due to imperfections in the process or allowances, errors, or tolerances in manufacturing or measurement that are recognized by those skilled in the art.

[0039] The oxide structure 450 may have a first width W1 in the first direction D1. The first width W1 may be constant and independent of the horizontal. As an example, the first width W1 of the oxide structure 450 on the upper core wafer 400 may be substantially equal to the first width W1 of the oxide structure 450 on one of the lower core wafers 300. The expression "substantially equal to" another value may indicate that the two values ​​are the same, or that the two values ​​are nearly the same, but there are some variations due to imperfections in the process or in the manufacturing or measurement, such as allowances, errors, or tolerances, as recognized by those skilled in the art. In one or more aspects, it may indicate an industrially acceptable tolerance for the two values, such as a tolerance of ±1%, ±5%, or ±10% of the actual value, or other suitable tolerances. In embodiments, the first width W1 may be in the range of 20 μm to 50 μm. The oxide structure 450 may be formed of or comprise silicon oxide.

[0040] A molding structure 500 may be disposed on the base wafer 100. The bottom surface of the molding structure 500 may contact the top surface of the base wafer 100. The molding structure 500 may be disposed on the outer surface of the oxide structure 450 to cover the side surface of the oxide structure 450. The oxide structure 450 may be disposed between the upper core wafer 400 and the molding structure 500. That is, the molding structure 500 may be spaced apart from the lower core wafer 300 and the upper core wafer 400, and the oxide structure 450 may be inserted between the molding structure 500 and the lower core wafer 300 and the upper core wafer 400. The level of the top surface 450t of the oxide structure 450 may be substantially equal to the level of the top surface 500t of the molding structure 500.

[0041] The molded structure 500 may have a second width W2 in the first direction D1. The second width W2 may be constant and independent of the horizontal direction. The first width W1 of the oxide structure 450 may be greater than the second width W2 of the molded structure 500. In embodiments, the ratio between the first width W1 and the second width W2 may be in the range of 6:4 to 7:3.

[0042] The molded structure 500 may include an insulating material, and the insulating material may include an epoxy molding compound or an adhesive material.

[0043] Figure 2 This is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. For the sake of brevity, the previous reference was made to... Figure 1 The described elements may be identified by the same reference numerals without repeating their descriptions.

[0044] Reference Figure 2 The semiconductor package 10 may further include a dummy board DM. The dummy board DM may be disposed on the upper core chip 400. Here, the upper core chip 400 may have a third width W3 in the first direction D1. The dummy board DM may have a fourth width W4 in the first direction D1. The fourth width W4 may be greater than the third width W3.

[0045] A portion of the bottom surface of the dummy plate DM can contact the oxide structure 450. Due to the addition of the dummy plate DM, the level of the top surface 500t of the molded structure 500 can be higher than the level of the top surface 450t of the oxide structure 450. The side surfaces of the dummy plate DM can be aligned with the outer surface of the oxide structure 450.

[0046] For example, the dummy board DM can be a silicon substrate. The dummy board DM may not include devices (e.g., integrated circuits), interconnect patterns, and through electrodes. In an embodiment, the dummy board DM and the upper core wafer 400 can be interconnected with each other through a natural oxide layer.

[0047] In one embodiment, the semiconductor package may include a lower core wafer, an upper core wafer, and an oxide structure on a buffer wafer. Here, the oxide structure may be disposed on the top surface of the buffer wafer to cover the side surfaces of the lower and upper core wafers. Therefore, deformation or bending of the lower and upper core wafers can be prevented, and delamination of the lower core wafer from the top surface of the buffer wafer can be prevented. As a result, the structural stability of the semiconductor package can be improved.

[0048] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 This is a cross-sectional view illustrating the process of manufacturing a semiconductor package according to an embodiment of the present invention. In detail, Figures 3 to 16 It shows the manufacturing process. Figure 1 A cross-sectional view of the process of the semiconductor package 10.

[0049] Reference Figure 3 A first carrier substrate CR1 can be provided. A plurality of initial lower core wafers 300P can be disposed on the first carrier substrate CR1. An adhesive member can be disposed between the first carrier substrate CR1 and the initial lower core wafers 300P. The initial lower core wafers 300P can be spaced apart from each other in a first direction D1.

[0050] The initial lower core chip 300P may include a second semiconductor substrate 310, a second penetrating electrode 350, a second lower insulating layer 321, and a second lower pad 322. The second penetrating electrode 350 may be configured to penetrate a portion of the second semiconductor substrate 310.

[0051] Reference Figure 4 A grinding process can be performed on the initial lower core wafer 300P. The grinding process can be performed to expose the top surface of the second penetrating electrode 350. As a result of the grinding process, the level of the top surface of the second semiconductor substrate 310 can be reduced.

[0052] Next, a second upper insulating layer 331 and a second upper pad 332 can be formed on the top surface of the second semiconductor substrate 310. By performing a grinding process and forming the second upper insulating layer 331 and the second upper pad 332, the lower core wafer 300 can be formed from the initial lower core wafer 300P.

[0053] Reference Figure 5A first oxide layer 450a may be formed on the first carrier substrate CR1. The formation of the first oxide layer 450a may include forming a first oxide layer 450a on the first carrier substrate CR1 to have a top surface at the same level as the top surface of the lower core wafer 300. The first oxide layer 450a may be configured to surround the side surface of the lower core wafer 300. In an embodiment, the first oxide layer 450a may be formed by a chemical vapor deposition process.

[0054] Reference Figure 6 Another lower core wafer 300 and a first oxide layer 450a surrounding the side surfaces of the lower core wafer 300 can be formed on the second carrier substrate CR2. This can be achieved by referring to... Figures 3 to 5 The process described is similar to that used to perform the formation of the lower core wafer 300 and the first oxide layer 450a on the second carrier substrate CR2.

[0055] Reference Figure 7 A third carrier substrate CR3 can be provided. The third carrier substrate CR3 can be placed on... Figure 6 The lower core chip 300 is placed on and attached to the top surface of the lower core chip 300. That is, the lower core chip 300 can be placed between the second carrier substrate CR2 and the third carrier substrate CR3.

[0056] Reference Figure 8 The second carrier substrate CR2 can then be removed. Afterwards, the lower core wafer 300 and the first oxide layer 450a on the third carrier substrate CR3 can be connected... Figure 5 The lower core wafer 300 and the first oxide layer 450a are on the first carrier substrate CR1.

[0057] In detail, the second upper pad 332 in the lower core wafer 300 on the first carrier substrate CR1 can contact the second lower pad 322 in the lower core wafer 300 on the third carrier substrate CR3.

[0058] Reference Figure 9 The third carrier substrate CR3 can then be removed. Next, a first sawing process can be performed on the first oxide layer 450a. As an example, a dicing BL can be used to perform the first sawing process. As another example, plasma can be used to perform the first sawing process.

[0059] As a result of the first sawing process, the first oxide layer 450a can be configured as a plurality of portions spaced apart from each other in the first direction D1. Each of the first oxide layers 450a can be configured as a side surface surrounding each of the lower core wafers 300 spaced apart from each other in the first direction D1.

[0060] Reference Figure 10It can provide a 100P wafer. The 100P wafer may include a first semiconductor substrate 110, a first upper insulating layer 131, a first upper pad 132, a first through electrode 150, a first lower insulating layer 121, and a first lower pad 122.

[0061] Next, it can be made from Figure 9 The lower core wafer 300 and the first oxide layer 450a formed by the steps are separated from the first carrier substrate CR1, and the lower core wafer 300 and the first oxide layer 450a can be stacked on wafer 100P. This process can then be repeated. Figures 3 to 9 The process.

[0062] As a result, a lower core wafer 300 stacked on a third direction D3 and a first oxide layer 450a surrounding the side surface of the lower core wafer 300 can be formed on the wafer 100P. The lower core wafer 300 and the first oxide layer 450a can be configured to form a plurality of structures disposed on the wafer 100P and spaced apart from each other in the first direction D1.

[0063] Reference Figure 11 A fourth carrier substrate CR4 may be provided. Multiple upper core wafers 400 may be disposed on the fourth carrier substrate CR4. An adhesive member may be disposed between the fourth carrier substrate CR4 and the upper core wafers 400. The upper core wafers 400 may be spaced apart from each other in a first direction D1.

[0064] The upper core wafer 400 may include a third semiconductor substrate 410, a third lower insulating layer 421, and a third lower pad 422. Although not shown, the level of the top surface of the third semiconductor substrate 410 may be reduced by a grinding process.

[0065] Reference Figure 12 A second oxide layer 450b can be formed on the fourth carrier substrate CR4. The formation of the second oxide layer 450b may include forming a second oxide layer 450b on the fourth carrier substrate CR4 to have a top surface at the same level as the top surface of the upper core wafer 400. The second oxide layer 450b may be formed to surround the side surfaces of the upper core wafer 400. In an embodiment, the second oxide layer 450b may be formed by a chemical vapor deposition process.

[0066] Reference Figure 13 A fifth carrier substrate CR5 can be provided. The fifth carrier substrate CR5 can be placed on... Figure 12 The upper core chip 400 is attached to the top surface of the upper core chip 400. That is, the upper core chip 400 can be placed between the fourth carrier substrate CR4 and the fifth carrier substrate CR5.

[0067] Reference Figure 14The fourth carrier substrate CR4 can be removed. Next, a second sawing process can be performed on the fifth carrier substrate CR5 and the second oxide layer 450b. As an example, a dicing process BL can be used to perform the second sawing process. As another example, plasma can be used to perform the second sawing process.

[0068] As a result of the second sawing process, the fifth carrier substrate CR5 can be divided to form dummy boards DM spaced apart from each other. As a result of the second sawing process, the second oxide layer 450b can be divided into a plurality of portions spaced apart from each other in the first direction D1. Each of the second oxide layers 450b can be configured to surround the side surface of the upper core wafer 400 spaced apart from each other in the first direction D1.

[0069] Reference Figure 15 This can remove the virtual board DM. Afterwards, it can be... Figure 14 The core wafer 400 and the second oxide layer 450b formed by the steps are respectively stacked on Figure 10 The core wafer 300 is placed on the first oxide layer 450a. In this embodiment, the stacking process can be performed using a thermal processing technique.

[0070] In detail, stacking the upper core chip 400 on the lower core chip 300 may include connecting the third lower pad 422 in the upper core chip 400 to the second upper pad 332 in the uppermost lower core chip 300U.

[0071] Since the first oxide layer 450a is connected to the second oxide layer 450b, an oxide structure 450 can be formed. The oxide structure 450 can be configured to surround the side surfaces of the lower core wafer 300 and the upper core wafer 400.

[0072] Reference Figure 16 A molded structure 500 can be formed on the top surface of the wafer 100P. The molded structure 500 can cover the side surfaces of the oxide structure 450. The formation of the molded structure 500 can include forming the molded structure 500 to have a top surface at the same level as the top surface of the oxide structure 450.

[0073] Next, a third sawing process can be performed on wafer 100P and molding structure 500. As an example, the third sawing process can be performed using dicing BL. As another example, plasma can be used to perform the third sawing process. As a result of the third sawing process, a plurality of base wafers 100 (i.e., a plurality of buffer wafers 100) can be formed from wafer 100P.

[0074] Since the first connection terminal 180 is attached to the first lower pad 122 of the base wafer 100, the semiconductor package can be manufactured with Figure 1 The structure.

[0075] Figure 17 This is a cross-sectional view illustrating a portion of the manufacturing process of a semiconductor package according to an embodiment of the present invention. In detail, Figure 17 It shows the manufacturing process. Figure 2 A cross-sectional view of a portion of the process of a semiconductor package.

[0076] Reference Figure 14 and Figure 17 The dummy board DM does not need to be removed from the upper core chip 400. That is, the dummy board DM and the upper core chip 400 can be connected to each other. Then, the upper core chip 400 connected to the dummy board DM can be placed... Figure 10 On the lower core chip 300 and connect it Figure 10 The next core chip 300. Afterwards, it can execute similar functions as referenced. Figure 16 The described process is used to manufacture semiconductor packages according to embodiments of the present invention.

[0077] Figure 18 This is a plan view illustrating a semiconductor package according to an embodiment of the concept of the present invention. Figure 19 It is along Figure 18 The cross-sectional view taken by line A-A'. For simplicity, refer to the previous... Figure 1 The described elements may be identified by the same reference numerals without repeating their descriptions.

[0078] Reference Figure 18 and Figure 19 The semiconductor package 1000 may include a package substrate 40, an insert substrate 30, a logic chip 20, and a plurality of chip stacks 10. In an embodiment, Figure 18 and Figure 19 The chip stack 10 can correspond to the reference. Figure 1 The semiconductor package 10 is described.

[0079] The package substrate 40 may be, for example, a printed circuit board (PCB). Alternatively, although not shown, the package substrate 40 may have a structure in which insulating layers and interconnect layers are stacked alternately. The package substrate 40 may include a plurality of upper substrate pads 43 on its top surface and a plurality of lower substrate pads 42 on its bottom surface.

[0080] External connection terminals 48 can be respectively disposed on the lower substrate pad 42. The external connection terminals 48 can be electrically connected to the interconnect layer disposed in the package substrate 40 and the upper substrate pad 43 through the lower substrate pad 42.

[0081] External connection terminal 48 may include solder balls or solder bumps. External connection terminal 48 may be formed of or include at least one of silver, copper, tin and alloys thereof.

[0082] The insert substrate 30 may be disposed on the package substrate 40. The insert substrate 30 may include an insert core substrate 31, an insert via 35, an insert insulating layer 32, and an insert interconnect pattern 37.

[0083] The insert core substrate 31 may be a semiconductor substrate (e.g., a silicon substrate). The insert via 35 may be configured to penetrate the insert core substrate 31. The insert via 35 may be arranged in the first direction D1.

[0084] An insert insulating layer 32 may be disposed on the insert core substrate 31. The insert insulating layer 32 may include insert interconnect patterns 37 disposed therein. The insert interconnect patterns 37 may be electrically connected to insert vias 35. The insert insulating layer 32 may be formed of or comprise an insulating material (e.g., silicon oxide or silicon nitride). The insert interconnect patterns 37 may be formed of or comprise a metallic material (e.g., copper).

[0085] The second connection terminal 181 and the first underfill pattern UF1 may be disposed between the package substrate 40 and the insert substrate 30. The first underfill pattern UF1 may be configured to fill the space between the package substrate 40 and the insert substrate 30 and surround the side surface of each of the second connection terminals 181. The second connection terminal 181 may be formed of or comprise a conductive material (e.g., solder material). The first underfill pattern UF1 may be formed of or comprise, for example, epoxy resin.

[0086] Logic chip 20 and chip stack 10 may be disposed on insert substrate 30. In an embodiment, logic chip 20 may be placed on the central portion of insert substrate 30. Chip stack 10 may be spaced apart from each other in a first direction D1, with logic chip 20 inserted between chip stack 10. Figure 18 As shown, a pair of chip stacks 10 may be configured to be adjacent to one side surface of the logic chip 20, and another pair of chip stacks 10 may be configured to be adjacent to the opposite side surface of the logic chip 20. Adjacent chip stacks in the chip stacks 10 may be spaced apart from each other in a second direction D2. The arrangement of the logic chip 20 and the chip stacks 10 is not limited to the example shown, and various combinations and modifications are possible.

[0087] The logic chip 20 may be one of a central processing unit (CPU), a graphics processing unit (GPU), and an application-specific integrated circuit (ASIC). The logic chip 20 may be configured to send signals to or receive signals from the chip stack 10. The logic chip 20 may include chip pads 22 disposed therein. Third connection terminals 182 may be disposed on the chip pads 22. The third connection terminals 182 may be formed of or comprise conductive material (e.g., solder material).

[0088] The first connection terminal 180 of the chip stack 10 and the third connection terminal 182 of the logic chip 20 can contact pads on the top surface of the insert substrate 30. A second underfill pattern UF2 can be disposed between the logic chip 20 and the insert substrate 30. The second underfill pattern UF2 can be configured to fill the space between the third connection terminal 182. A third underfill pattern UF3 can be inserted between the chip stack 10 and the insert substrate 30. The third underfill pattern UF3 can be configured to fill the space between the first connection terminal 180. The second underfill pattern UF2 and the third underfill pattern UF3 can be formed of or include at least one of epoxy resin and resin compounds.

[0089] According to embodiments of the present invention, a semiconductor package may include a lower core wafer, an upper core wafer, and an oxide structure on a buffer wafer. Here, the oxide structure may be configured to surround the side surfaces of the lower and upper core wafers. Therefore, deformation or bending of the lower and upper core wafers can be prevented, and delamination of the top surfaces of the lower core wafer and the buffer wafer can be prevented. Thus, the structural stability of the semiconductor package can be improved.

[0090] Although exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: Base chip; Multiple lower core wafers stacked on the base wafer; The upper core chip on the plurality of lower core chips; An oxide structure covering the side surfaces of the plurality of lower core wafers and the side surfaces of the upper core wafer; as well as A molded structure is configured to cover the side surfaces of the oxide structure and is spaced apart from the plurality of lower core wafers and the upper core wafer, the oxide structure being inserted between the molded structure and the plurality of lower core wafers and the upper core wafer. Each of the base wafer and the plurality of lower core wafers includes a through electrode. The upper core wafer includes an insulating layer disposed on its bottom surface and solder pads disposed in the insulating layer, and The oxide structure exposes the edge portion of the top surface of the base wafer.

2. The semiconductor package as claimed in claim 1, wherein, The oxide structure includes silicon oxide.

3. The semiconductor package as claimed in claim 1, wherein, The top surface of the oxide structure is located at the same level as the top surface of the molded structure.

4. The semiconductor package as claimed in claim 1, wherein, The width of the oxide structure in a first direction parallel to the top surface of the base wafer is constant and independent of the horizontal direction.

5. The semiconductor package as claimed in claim 1, wherein, The oxide structure has a first width in the first direction. The molded structure has a second width in the first direction, and The first width is greater than the second width.

6. The semiconductor package of claim 5, wherein, The ratio of the first width to the second width is in the range of 6:4 to 7:

3.

7. The semiconductor package of claim 5, wherein, The first width ranges from 20 μm to 50 μm.

8. The semiconductor package of claim 1, wherein, The upper core wafer does not include a penetrating electrode.

9. A semiconductor package, comprising: Base chip; Multiple lower core wafers stacked on the base wafer; The upper core chip on the plurality of lower core chips; An oxide structure covering the side surfaces of the plurality of lower core wafers and the side surfaces of the upper core wafer; as well as The molded structure on the side surface of the oxide structure. The width of the oxide structure in the horizontal direction is constant and independent of the horizontal plane. The level of the top surface of the upper core wafer is equal to the level of the top surface of the oxide structure.

10. The semiconductor package of claim 9, wherein, The width of the molded structure in the horizontal direction is constant and independent of the horizontal plane.

11. The semiconductor package of claim 9, further comprising a dummy board on the upper core wafer. in, The dummy board has a first width in the horizontal direction. The upper core wafer has a second width in the horizontal direction, and The first width is greater than the second width.

12. The semiconductor package of claim 11, wherein, The top surface of the molded structure is at a higher level than the top surface of the oxide structure.

13. The semiconductor package of claim 11, wherein, The side surface of the dummy plate is aligned with the outer surface of the oxide structure.

14. The semiconductor package of claim 11, wherein, The upper core wafer also includes an insulating layer on its bottom surface and pads disposed in the insulating layer, and The upper core wafer and the dummy board have no penetrating electrodes.

15. A semiconductor package, comprising: Packaging substrate; The insert substrate on the packaging substrate; The logic chip on the insert substrate; as well as A plurality of chip stacks are spaced apart from each other in a first direction parallel to the top surface of the packaging substrate, and a logic chip is inserted between the plurality of chip stacks. One of the plurality of chip stacks includes: Base chip; Multiple lower core wafers stacked on the base wafer; The upper core chip on the plurality of lower core chips; An oxide structure covering the side surfaces of the plurality of lower core wafers and the side surfaces of the upper core wafer; and A molded structure that covers the side surfaces of the oxide structure. Wherein, the width of the oxide structure on the upper core wafer in the first direction is equal to the width of the oxide structure on one of the plurality of lower core wafers in the first direction.

16. The semiconductor package of claim 15, wherein, The oxide structure is disposed between the upper core wafer and the molded structure.

17. The semiconductor package of claim 15, wherein, The thickness of the upper core wafer is greater than the thickness of each of the plurality of lower core wafers.

18. The semiconductor package of claim 15, wherein, The bottom surface of the molded structure is in contact with the top surface of the base wafer.

19. The semiconductor package of claim 15, wherein, Each of the base wafer and the plurality of lower core wafers includes a through electrode, and The upper core wafer does not include a penetrating electrode.

20. The semiconductor package of claim 15, wherein, Each of the plurality of lower core wafers includes a first insulating layer on its top surface and a first pad disposed in the first insulating layer. The upper core wafer includes a second insulating layer on its bottom surface and a second pad disposed in the second insulating layer, and The first pad of the uppermost lower core chip in the plurality of lower core chips is in contact with the second pad of the upper core chip.

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