Scratch-proof electrical measurement method for circuit board

Abstract

The present application discloses a kind of circuit board's scratch-proof electrical measurement method, include: preliminary step, provide a panel, its surface is defined with multiple unit areas, and each described unit area forms a first gold surface;Dry film setting step, a dry film is set on the panel and shields multiple described unit areas;A windowing step, multiple first windows are formed on the dry film, and each described first gold surface is exposed to corresponding described first window;Cutting step, the panel and the dry film are cut along the junction of described unit area, to form multiple circuit boards and multiple sub dry films covered on multiple described circuit boards;Electrical measurement step, each described circuit board is electrically measured by the part of described first gold surface exposed to described first window;And removal step, remove described sub dry film.The present application discloses the scratch-proof electrical measurement method of circuit board can improve the problem that existing circuit board manufacturing method is prone to gold surface scratch in process.

Description

Technical Field

[0001] This invention relates to an electrical testing method for circuit boards, and more particularly to a scratch-resistant electrical testing method for circuit boards. Background Technology

[0002] Existing circuit board manufacturing processes do not provide sufficient protection for the gold-plated surfaces, making them prone to scratches during the manufacturing process. Summary of the Invention

[0003] This invention discloses a scratch-resistant electrical testing method for circuit boards, which is mainly used to improve the problem of gold surface scratches that are easily caused during the manufacturing process of existing circuit boards.

[0004] One embodiment of the present invention discloses a scratch-resistant electrical testing method for a circuit board, comprising: a pre-processing step of providing a panel, wherein a plurality of unit regions are defined on the surface of the panel, and each unit region forms a first gold surface; a dry film setting step of setting a dry film on the panel to shield the plurality of unit regions; a windowing step of forming a plurality of first windows on the dry film, and each first gold surface being exposed to a corresponding first window; a cutting step of cutting the panel and the dry film along the boundaries of the unit regions to form a plurality of circuit boards and a plurality of sub-dry films covering the plurality of circuit boards; an electrical testing step of performing electrical testing on each circuit board through the portion of the first gold surface exposed to the first window; and a removal step of removing the sub-dry films.

[0005] Optionally, in each unit area, the opening size of the first window is smaller than the area of ​​the first gold surface, and the first gold surface is partially exposed to the first window.

[0006] Optionally, the first length of each first window is between 2 mil and 6 mil, and the first width of each first window is between 2 mil and 6 mil.

[0007] Optionally, after the electrical testing step and before the removal step, the scratch-resistant electrical testing method for the circuit board further includes a stacking step, in which multiple circuit boards are stacked on top of each other in a stacking order on the sub-dry film of one circuit board without the sub-dry film.

[0008] Optionally, in the pre-step, each unit area also forms multiple second gold surfaces; in the windowing step, multiple second windows are also formed on the dry film, and each second gold surface is exposed to the corresponding second window; wherein, in the electrical testing step, electrical testing is performed on each circuit board through the portion of the first gold surface exposed to the first window and through the second gold surface exposed to the second window.

[0009] Optionally, in each unit region, the area of ​​the first gold surface is larger than the area of ​​each second gold surface.

[0010] Optionally, in each unit area, the opening size of each second window is not greater than the area of ​​the corresponding second gold surface.

[0011] Optionally, in each unit area, the opening size of each second window is smaller than the area of ​​the corresponding second gold surface, and the second gold surface is partially exposed to the second window.

[0012] Optionally, the second length of each second window is between 2 mil and 6 mil, and the second width of each second window is between 2 mil and 6 mil.

[0013] Optionally, the thickness of the dry film is between 25 micrometers and 50 micrometers.

[0014] In summary, the anti-scratch electrical testing method for circuit boards of the present invention can effectively improve the problem of gold surface scratches in existing circuit board manufacturing methods through the technical solutions of "the dry film setting step, setting the dry film that shields multiple unit areas on the panel", "the windowing step, forming multiple first windows on the dry film, and each first gold surface being exposed to the corresponding first window", and "the electrical testing step, performing electrical testing on each circuit board through the portion of the first gold surface exposed to the first window".

[0015] To further understand the features and technical content of this invention, please refer to the following detailed description and accompanying drawings. However, these descriptions and drawings are only for illustrating the invention and are not intended to limit the scope of protection of the invention in any way. Attached Figure Description

[0016] Figure 1 This is a flowchart of a scratch-resistant electrical testing method for a circuit board according to one embodiment of the present invention.

[0017] Figure 2 This is a top view of the panel in the preliminary step of the anti-scratch electrical testing method for a circuit board according to one embodiment of the present invention.

[0018] Figure 3 This is a perspective view of the panel in the preliminary step of the anti-scratch electrical testing method for a circuit board according to one embodiment of the present invention.

[0019] Figure 4 This is a schematic diagram of the dry film setting steps in a scratch-resistant electrical testing method for a circuit board according to one embodiment of the present invention.

[0020] Figure 5 This is a schematic diagram of the window opening step in the anti-scratch electrical testing method for a circuit board according to one embodiment of the present invention.

[0021] Figure 6This is a schematic diagram of the window opening step in a scratch-resistant electrical testing method for a circuit board according to another embodiment of the present invention.

[0022] Figure 7 This is a schematic diagram of the cutting steps of a scratch-resistant electrical testing method for a circuit board according to one embodiment of the present invention.

[0023] Figure 8 This is a schematic diagram of the stacking steps of a scratch-resistant electrical testing method for a circuit board according to one embodiment of the present invention.

[0024] Figure 9 This is a schematic diagram of the removal step in the anti-scratch electrical testing method for a circuit board according to one embodiment of the present invention. Detailed Implementation

[0025] The following specific embodiments illustrate the implementation of the "anti-scratch electrical testing method for circuit boards" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, it should be stated in advance that the accompanying drawings of this invention are for simple illustrative purposes only and are not depictions based on actual dimensions. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention.

[0026] It should be understood that while terms such as "first," "second," and "third" may be used in this document to describe various components or signals, these components or signals should not be limited by these terms. These terms are primarily used to distinguish one component from another, or one signal from another. Furthermore, the term "or" as used herein should, as appropriate, include any combination of one or more of the associated listed items.

[0027] Please see Figure 1 As shown, Figure 1 This is a flowchart illustrating a scratch-resistant electrical testing method for a circuit board according to one embodiment of the present invention. One embodiment of the present invention provides a scratch-resistant electrical testing method for a circuit board. The scratch-resistant electrical testing method for the circuit board includes a pre-processing step S110, a dry film setting step S120, a windowing step S130, a cutting step S140, an electrical testing step S150, and a removal step S160. Of course, the scratch-resistant electrical testing method for the circuit board may include other steps as needed.

[0028] Please see Figure 2 and Figure 3 As shown, Figure 2This is a top view of the panel in the preliminary step of the anti-scratch electrical testing method for a circuit board according to one embodiment of the present invention. Figure 3 This is a perspective view of the panel in the preliminary step of the anti-scratch electrical testing method for a circuit board according to one embodiment of the present invention.

[0029] In the preceding step S110, a panel P is provided, on which a plurality of unit regions P1 are defined, and each unit region P1 forms a first gold surface 1. Any two adjacent unit regions P1 can be uncut and connected to each other. Furthermore, in this embodiment, four unit regions P1 are used as an example, but the invention is not limited thereto. In other embodiments, the number of unit regions P1 can also be varied according to requirements.

[0030] Please see Figure 4 As shown, Figure 4 This is a schematic diagram of the dry film setting step in a scratch-resistant electrical testing method for a circuit board according to one embodiment of the present invention. In the dry film setting step S120, a dry film 2 is set on the panel P to cover a plurality of unit regions P1. Specifically, in the dry film setting step S120, the first gold surface 1 of each unit region P1 is covered by the dry film 2.

[0031] Please see Figure 5 As shown, Figure 5 This is a schematic diagram of the windowing step in a scratch-resistant electrical testing method for a circuit board according to one embodiment of the present invention. In the windowing step S130, a plurality of first windows 21 are formed on the dry film 2, and each of the first gold surfaces 1 is exposed to the corresponding first window 21. In other words, the position of the first window 21 on the dry film 2 corresponds to the first gold surface 1, and the number of first windows 21 can also correspond to the number of first gold surfaces 1.

[0032] In this embodiment, in each of the unit regions P1, the opening size of the first window 21 is smaller than the area of ​​the first gold surface 1, and the first gold surface 1 is partially exposed to the first window 21. In other words, in each of the unit regions P1, the first gold surface 1 is partially covered by the dry film 2, thereby reducing the risk of the first gold surface 1 being scratched during the process.

[0033] In this embodiment, the first length L1 of each of the first openings 21 can be between 2 mils and 6 mils, and the first width W1 of each of the first openings 21 can be between 2 mils and 6 mils, but the present invention is not limited thereto. Alternatively, the first length L1 of each of the first openings 21 can be between 3 mils and 5 mils, and the first width W1 of each of the first openings 21 can be between 3 mils and 5 mils.

[0034] In this embodiment, the first window 21 is generally rectangular in shape, but the invention is not limited to this. In other embodiments, the first window 21 may also be generally square or other shapes.

[0035] Please see Figure 7 As shown, Figure 7 This is a schematic diagram of the cutting steps in a scratch-resistant electrical testing method for a circuit board according to one embodiment of the present invention. In the cutting step S140, the panel P and the dry film 2 are cut along the boundary of the unit region P1 to form a plurality of circuit boards 100 and a plurality of sub-dry films 2' covering the plurality of circuit boards 100. In other words, in the cutting step S140, the dry film 2 can be cut from the surface away from the panel P to cut the dry film 2 into a plurality of sub-dry films 2' and the panel P into a plurality of circuit boards 100.

[0036] It is worth mentioning that in the cutting step S140, both the panel P and the dry film 2 can be cut simultaneously. Furthermore, in the cutting step S140, the panel P and the dry film 2 can be cut, for example, by laser cutting or mechanical cutting, but the present invention does not limit the cutting method in the cutting step S140.

[0037] In the electrical testing step S150, each circuit board 100 is electrically tested through the portion of the first gold surface 1 exposed to the first opening 21. Specifically, in the electrical testing step S150, multiple test probes (not shown in the figure) can contact the portion of the first gold surface 1 of each circuit board 100 exposed to the first opening 21 of the sub-dry film 2' to perform an open / short circuit test (i.e., an open / short test, O / S test). Furthermore, in the electrical testing step S150, each sub-dry film 2' remains disposed on the corresponding circuit board 100.

[0038] Please see Figure 9 As shown, Figure 9 This is a schematic diagram of the removal steps in a scratch-resistant electrical testing method for a circuit board according to one embodiment of the present invention. In the removal step S160, the sub-dry film 2' is removed. In the removal step S160, the sub-dry film 2' can be removed, for example, with the assistance of a chemical solution, such as sodium hydroxide or potassium hydroxide solution. However, the present invention does not limit the method of removing the sub-dry film 2'.

[0039] Please see Figure 8 As shown, Figure 8This is a schematic diagram of the stacking steps of a scratch-resistant electrical testing method for a circuit board according to one embodiment of the present invention. After the electrical testing step S150 and before the removal step S160, the scratch-resistant electrical testing method for the circuit board further includes a stacking step S151, in which multiple circuit boards 100 are stacked on top of each other in a stacking order where the surface of one circuit board 100 without the sub-dry film 2' is stacked on the sub-dry film 2' of another circuit board 100.

[0040] It should be noted that the stacking step S151 significantly reduces the area occupied by the multiple circuit boards 100 in the process. Furthermore, because the sub-dry film 2' is spaced between any two adjacent circuit boards 100, each circuit board 100 is less prone to scratches due to stacking or other processes. In addition, the thickness of the dry film 2 is between 25 micrometers and 50 micrometers, but the present invention is not limited to this. This further reduces the possibility of scratches on each circuit board 100.

[0041] Furthermore, in the preceding step S110, each of the unit regions P1 can also form multiple second gold surfaces 3. In the windowing step S130, multiple second windows 22 can also be formed on the dry film 2, and each second gold surface 3 is exposed to the corresponding second window 22. In the electrical testing step S150, each of the circuit boards 100 can be electrically tested through the portion of the first gold surface 1 exposed to the first window 21 and through the second gold surface 3 exposed to the second window 22. In each of the unit regions P1, the area of ​​the first gold surface 1 can be larger than the area of ​​each of the second gold surfaces 3. In each of the unit regions P1, the opening size of each of the second windows 22 is not larger than the area of ​​the corresponding second gold surface 3.

[0042] Specifically, such as Figure 5 As shown, in each of the unit regions P1, the openings of each of the second windows 22 can be substantially aligned with the periphery of the corresponding second gold surface 3. Please refer to... Figure 6 As shown, Figure 6 This is a schematic diagram of the windowing step in a scratch-resistant electrical testing method for a circuit board according to another embodiment of the present invention. Alternatively, the opening size of each of the second windows 22 is smaller than the area of ​​the corresponding second gold surface 3, and the second gold surface 3 is partially exposed to the second window 22, but the present invention is not limited thereto.

[0043] Furthermore, the second length L2 of each of the second openings 22 can be between 2 mils and 6 mils, and the second width W2 of each of the second openings 22 can be between 2 mils and 6 mils, but the invention is not limited thereto. Alternatively, the second length L2 of each of the second openings 22 can be between 3 mils and 5 mils, and the second width W2 of each of the second openings 22 can be between 3 mils and 5 mils.

[0044] In this embodiment, the second window 22 is generally rectangular in shape, but the invention is not limited to this. In other embodiments, the second window 22 may also be generally square or other shapes. Furthermore, in this embodiment, the size of the second window 22 may be substantially the same as the size of the first window 21, but the size of the second window 22 may be the same as or different from the size of the first window 21.

[0045] [Beneficial Effects of the Examples]

[0046] The scratch-resistant electrical testing method for circuit boards of the present invention can effectively improve the problem of gold surface scratches in the manufacturing process of existing circuit boards by means of the following technical solutions: "the dry film setting step, setting the dry film that shields multiple unit areas on the panel", "the window opening step, forming multiple first windows on the dry film, and exposing each first gold surface to the corresponding first window", and "the electrical testing step, performing electrical testing on each circuit board through the portion of the first gold surface exposed to the first window".

[0047] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Therefore, all equivalent technical changes made based on the description and drawings of the present invention are included within the protection scope of the present invention.

Claims

1. A scratch-resistant electrical testing method for a circuit board, characterized in that, The scratch-resistant electrical testing method for the circuit board includes: A preliminary step involves providing a panel, on the surface of which multiple unit regions are defined, and each unit region forms a first gold surface. A dry film setting step involves setting a dry film on the panel to cover multiple unit areas; In the first windowing step, a plurality of first windows are formed on the dry film, and each first gold surface is exposed to the corresponding first window; A cutting step involves cutting the panel and the dry film along the boundary of the unit region to form multiple circuit boards and multiple sub-dry films covering the multiple circuit boards; One electrical testing step involves performing electrical tests on each of the circuit boards through the portion of the first gold surface exposed by the first window. as well as The first step is to remove the sub-dry membrane.

2. The anti-scratch electrical testing method for circuit boards according to claim 1, characterized in that, In each of the unit regions, the opening size of the first window is smaller than the area of ​​the first gold surface, and the first gold surface is partially exposed to the first window.

3. The anti-scratch electrical testing method for circuit boards according to claim 1, characterized in that, The first length of each of the first openings is between 2 mils and 6 mils, and the first width of each of the first openings is between 2 mils and 6 mils.

4. The anti-scratch electrical testing method for circuit boards according to claim 1, characterized in that, After the electrical testing step and before the removal step, the scratch-resistant electrical testing method for the circuit board further includes a stacking step, in which multiple circuit boards are stacked on top of each other in a stacking order on the sub-dry film of one circuit board without the sub-dry film.

5. The anti-scratch electrical testing method for circuit boards according to claim 1, characterized in that, In the preceding step, each of the unit regions further forms a plurality of second gold surfaces; in the windowing step, a plurality of second windows are also formed on the dry film, and each of the second gold surfaces is exposed to the corresponding second window; wherein, in the electrical testing step, electrical testing is performed on each of the circuit boards through the portion of the first gold surface exposed to the first window and through the second gold surface exposed to the second window.

6. The anti-scratch electrical testing method for circuit boards according to claim 5, characterized in that, In each of the said unit regions, the area of ​​the first gold surface is larger than the area of ​​each of the second gold surfaces.

7. The anti-scratch electrical testing method for circuit boards according to claim 5, characterized in that, In each of the unit regions, the opening size of each second window is not greater than the area of ​​the corresponding second gold surface.

8. The anti-scratch electrical testing method for circuit boards according to claim 7, characterized in that, In each of the unit regions, the opening size of each second window is smaller than the area of ​​the corresponding second gold surface, and the second gold surface is partially exposed to the second window.

9. The anti-scratch electrical testing method for circuit boards according to claim 5, characterized in that, The second length of each of the second windows is between 2 mils and 6 mils, and the second width of each of the second windows is between 2 mils and 6 mils.

10. The anti-scratch electrical testing method for a circuit board according to claim 1, characterized in that, The thickness of the dry film is between 25 micrometers and 50 micrometers.

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