Dual-frequency image sonar analog front end and high-speed acquisition system

Abstract

The application provides a dual-frequency image sonar analog front end and high-speed acquisition system, which integrates 16 LNAs, TVGs, programmable gain amplification circuits (PGAs), low-pass filter circuits, high-speed acquisition circuits and the like in a single chip, greatly improving the integration of the image sonar receiving system; meanwhile, high-speed sampling and digital filtering are performed by using an FPGA, replacing a complex analog band-pass filter, so that the consistency of channel signals is improved, and the system can be applied to dual-frequency image sonars, and has a wide application prospect in various underwater small image sonar devices.

Description

Technical Field

[0001] This invention relates to the field of multibeam imaging sonar technology, specifically to a dual-frequency imaging sonar analog front-end and high-speed acquisition system. Background Technology

[0002] Multibeam imaging sonars come in many types and have a wide range of applications, including underwater environmental monitoring, dam seepage detection, forward-looking obstacle avoidance during navigation, and underwater counter-terrorism surveillance. Imaging sonars have multiple receiving array channels and operate at high signal frequencies, typically greater than 600kHz, and sometimes even reaching 1.2MHz. For ease of installation or single-person portability, imaging sonars require small size, light weight, and high system integration.

[0003] Current image sonar receiving systems mainly include low-noise preamplifier (LNA), variable gain amplifier (TVG), analog bandpass filter, and ADC acquisition circuit. The main problems are as follows: 1) The discrete circuits make the entire receiving system circuitry very large, which cannot meet the requirements for miniaturization of image sonar.

[0004] 2) The ADC acquisition circuit typically uses a SAR-type ADC with a sampling rate of no more than 2MHz. Although the bandpass sampling theorem can be used to acquire the signal, the insufficient sampling rate will increase the order of the analog bandpass filter circuit. The conventional 8th order analog bandpass filter circuit will severely degrade the amplitude and phase consistency between channels, resulting in a decrease in system performance.

[0005] 3) Due to the presence of the analog bandpass filter, the system cannot be applied to dual-frequency imaging sonar with multiple operating frequencies. Furthermore, when the system is applied to imaging sonar with other operating frequencies, a large number of resistors and capacitors need to be modified and soldered, which makes the equipment versatility of the conventional system weak.

[0006] Patent application CN118982451A discloses a Zynq-based handheld image sonar signal processing system, comprising: a Zynq module including an FPGA module and an ARM module; the FPGA module drives a transmission module to transmit signals within the observation range via a signal source module; a front-end conditioning module amplifies, filters, and samples the received sonar signals before transmitting them to a high-speed acquisition module; the high-speed acquisition module converts analog signals into digital signals and transmits them to the FPGA module; the FPGA module performs real-time signal processing based on the acquired digital signals to obtain beam data and transmits it to the ARM module; a power supply module provides power to the handheld image sonar signal processing system; a DA module controls the TVG gain of the front-end conditioning module based on the FPGA module to compensate for sonar propagation losses; and the ARM module controls a serial communication module, a network transmission module, a storage module, and a display module to complete image processing and display, and control the operating status of the handheld image sonar signal processing system. However, this patent cannot completely solve the existing technical problems, nor can it meet the needs of this invention. Summary of the Invention

[0007] To address the shortcomings of existing technologies, the purpose of this invention is to provide a dual-frequency image sonar simulation front-end and high-speed acquisition system.

[0008] The dual-frequency image sonar simulation front-end and high-speed acquisition system provided by the present invention includes: Analog front-end and high-speed acquisition module: used to receive multiple hydrophone analog signals and amplify, filter and convert them from analog to digital; FPGA module: connected to the analog front end and high-speed acquisition module, used to configure the working status of the analog front end and high-speed acquisition module, receive the digital signals output by them and perform preprocessing; Clock drive module: connected to the analog front end and high-speed acquisition module, used to provide the analog front end and high-speed acquisition module with a low-jitter differential clock signal; DA module: connected to the FPGA module and the analog front-end and high-speed acquisition module, used to adjust the gain in the analog front-end and high-speed acquisition module by outputting a variable voltage according to the control of the FPGA module; Power supply module: Used to provide stable power to the analog front-end, high-speed acquisition module, FPGA module, DA module, clock drive module and network transmission module; Network transmission module: connected to the FPGA module, used to transmit the preprocessed digital signal to the host computer and receive control commands issued by the host computer.

[0009] Preferably, the analog front-end and high-speed acquisition module includes multiple integrated chips, each integrated chip integrating multiple signal processing channels, each channel including: Low-noise preamplifier circuit: used to amplify the input hydrophone analog signal with low noise. Its input impedance can be configured to match the hydrophone output impedance, and the gain can be set to 12dB, 18dB or 24dB. Variable gain amplifier circuit: Its gain range is between -40dB and 0dB, and it is controlled by the voltage output of the DA module to compensate for sonar propagation loss; Programmable gain amplifier circuit: used to amplify the signal to an amplitude suitable for analog-to-digital conversion, with the gain set to 24dB or 30dB; Low-pass filter circuit: cutoff frequency is 10MHz, used to prevent signal aliasing above the sampling frequency; High-speed acquisition circuit: with a sampling rate of 20MHz, used to convert analog signals into digital signals.

[0010] Preferably, the FPGA module includes: SPI control module: used to configure the working state of the analog front end and the high-speed acquisition module through the SPI interface, including configuring the gain and input impedance of the low-noise preamplifier circuit, the gain of the programmable gain amplifier circuit, and the cutoff frequency of the low-pass filter circuit; Data interface module: used to receive digital signals output by the analog front end and the high-speed acquisition module through the high-speed serial LVDS interface, and to complete the synchronous acquisition of multi-channel underwater acoustic signals; Data preprocessing module: used to perform digital filtering and downsampling on the acquired data output by the data interface module.

[0011] Preferably, the data interface module includes: DCLK control module: connected to the bit clock DCLK output by the analog front end and high-speed acquisition module, used to delay DCLK, generate data acquisition clock bitclk and area clock clkdiv, and realize phase alignment between bitclk and DCLK through IDELAY, BUFIO, BUFR resources and ISERDES resources inside the FPGA. FCLK control module: connected to the frame clock FCLK output by the analog front end and high-speed acquisition module, used to perform serial-to-parallel conversion of FCLK through ISERDES resources, and to find and lock the correct character start position of 14-bit acquisition data through bitslip signal; The bitslip signal output by the FCLK control module controls the ISERDES resource for serial-to-parallel conversion of the differential data signal CHn_OUT, so as to output the correct multi-channel 14-bit acquired data to the data preprocessing module.

[0012] Preferably, the data preprocessing module performs the following processing steps in sequence: The 96 channels of input data are first subjected to a first-stage digital low-pass filter. There are 6 low-pass filters, each of which processes 16 channels. The operating clock is 320MHz, the input signal sampling rate is 20MHz, and the cutoff frequency is 1.25MHz. The low-pass filtered signal is downsampled by a factor of 6, resulting in a sampling rate of 3.33MHz. The output data from the six filters are then packaged and integrated into a single serial 96-channel data stream. The integrated data is subjected to a second-stage digital bandpass filter. The passband center frequency of the bandpass filter is configured to be 750kHz or 1.2MHz, and the bandwidth is 80kHz. The output data after bandpass filtering is downsampled again, packaged in channel order, and then output through the network transmission module.

[0013] Preferably, the DA module includes: TVG_RAM memory: used to pre-store gain control data corresponding to sonar propagation loss compensation; DAC controller: connected to the TVG_RAM memory and external DA conversion chip, used to read data in TVG_RAM and control the external DA conversion chip to output the corresponding analog voltage to the variable gain amplifier circuit of the analog front end and high-speed acquisition module; The data stored in the TVG_RAM is received and updated from the host computer through the network transmission module to adapt to different workloads or system self-test requirements.

[0014] Preferably, the clock driving module includes a clock driving chip, which receives a clock signal generated by an active crystal oscillator and outputs multiple 20MHz differential clock signals to drive the clock input terminals of multiple analog front-ends and high-speed acquisition modules in a one-to-one manner.

[0015] Preferably, the power module supports a wide voltage input from 9V to 17V and generates five digital power supplies (5VD, 3V3D, 2V5D, 1V8D, and 1V2D) through multiple DC-DC conversion chips. Among them, 2V5D is used to power HR_BANK in the FPGA module, and 1V8D is used to power HP_BANK in the FPGA module. The AVDD_H, AVDD_M, DVDD1V8, AVDD1V8, and DVDD1V2 power supplies required by the analog front-end and high-speed acquisition module are obtained from the corresponding outputs of the power supply module through ferrite beads.

[0016] Preferably, the workflow of this system is as follows: After the system is powered on, the SPI control module in the FPGA module initializes and configures the analog front-end and the high-speed acquisition module. The host computer sends a start command through the network transmission module; The multi-channel hydrophone analog signal is input to the analog front-end and high-speed acquisition module. After amplification, filtering and analog-to-digital conversion, it is output to the data interface module of the FPGA module through the LVDS interface. After the data interface module completes the synchronous reception of data, it sends the data to the data preprocessing module for digital low-pass filtering, band-pass filtering and downsampling processing. The processed data is packaged in channel order and uploaded to the host computer through the network transmission module.

[0017] Preferably, the analog front-end and high-speed acquisition module consists of 6 integrated chips, each chip integrating 16 signal processing channels, for a total of 96 channels; The system operates at frequencies of 750 kHz and 1.2 MHz, with a sampling rate of 20 MHz. The cutoff frequency of the low-pass filter circuit is configured to be 10 MHz. The passband center frequency of the second-stage digital bandpass filter is configured to be either 750 kHz or 1.2 MHz, and the bandwidth is configured to be 80 kHz.

[0018] Compared with the prior art, the present invention has the following beneficial effects: (1) This system utilizes the integrated amplification and filtering circuits on a single chip. The resistors and capacitors have higher precision than conventional discrete components. Furthermore, this system features high-speed sampling and digital filtering. The low-pass filter circuit on the analog end has a lower order and simpler structure than conventional band-pass filter circuits. Therefore, the amplitude and phase consistency between channels can be greatly improved. (2) This system utilizes the programmability of digital filters, and can be applied to various image sonars in different frequency bands, as well as dual-frequency image sonars with two working frequencies; (3) The analog front-end and high-speed acquisition module of this system adopt a single chip to integrate 16 LNA, TVG, PGA, low-pass filter circuit and high-speed acquisition circuit, which greatly improves the integration of the image sonar receiving circuit. Attached Figure Description

[0019] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is the overall framework diagram of the system; Figure 2Functional block diagram of the simulated front-end and high-speed acquisition module; Figure 3 This is a timing diagram for the serial LVDS data interface; Figure 4 Here is the flowchart for the DCLK control module; Figure 5 Here is the flowchart for the FCLK control module; Figure 6 This is a flowchart of the signal preprocessing process for this system; Figure 7 This is a schematic diagram of the power supply for the power module. Detailed Implementation

[0020] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0021] Example 1 This invention addresses the problem that existing multi-beam imaging sonar receiving systems suffer from large hardware scale, poor channel consistency, and inapplicability to technologies such as dual-frequency sonar. To solve these technical challenges, this paper presents a dual-frequency imaging sonar analog front-end and high-speed acquisition system. The system is as follows... Figure 1 As shown, it mainly includes: analog front-end and high-speed acquisition module, FPGA module, clock drive module, power supply module, DA module, network transmission module, etc.

[0022] The analog front-end and high-speed acquisition module are mainly responsible for amplifying and filtering the analog signals from multiple hydrophones through low noise, and finally completing the digital-to-analog conversion. It features multiple channels, high integration, and high-speed acquisition.

[0023] The FPGA module mainly includes an SPI control module, a data interface module, and a data preprocessing module.

[0024] The SPI control module is mainly responsible for configuring the working status of the analog front-end and the high-speed acquisition module.

[0025] The data interface module mainly includes a DCLK control module and an FCLK control module, which are responsible for receiving data from the analog front end and the high-speed acquisition module to complete the synchronous acquisition of multi-channel underwater acoustic signals.

[0026] The data preprocessing module utilizes the logic resources inside the FPGA to perform digital low-pass filtering and downsampling on the high-speed acquired signal, reducing the computational and storage requirements of data processing. Subsequently, digital band-pass filtering and downsampling are performed to reduce out-of-band noise interference and lower the data transmission rate. Finally, the data is transmitted to the host computer through the network transmission module.

[0027] The clock driving module provides a low-jitter differential clock source for both the analog front-end and the high-speed acquisition module.

[0028] The DA module converts the data pre-stored inside the FPGA into a voltage curve by controlling the DA, thereby controlling the TVG gain of the analog front-end and the high-speed acquisition module to compensate for the propagation loss of the sonar.

[0029] The power supply module mainly provides stable power to the analog front-end and high-speed acquisition module, FPGA module, DA module, network transmission module, clock drive module and other peripheral chips.

[0030] The network transmission module is based on the UDP protocol and transmits the acquired and preprocessed digital signals to the host computer, while simultaneously receiving the working status of the host computer control system.

[0031] Furthermore, the analog front-end and high-speed acquisition module consist of multiple AFE chips, each integrating multiple LNA, TVG, PGA, low-pass filter circuits, and high-speed acquisition circuits. Its first stage is a low-noise preamplifier circuit, which amplifies the analog signal received from the hydrophone with low noise; its input impedance is configurable and matched to the output impedance of the receiving hydrophone. The second stage is a variable gain amplifier circuit, controlled by the DA module, used to compensate for sonar propagation loss. The third stage is a programmable gain amplifier circuit, amplifying the signal to an amplitude suitable for the ADC. The fourth stage is a low-pass filter circuit to prevent aliasing of signals above the sampling rate. The final stage is a high-speed acquisition circuit, converting the analog signal into a digital signal.

[0032] Furthermore, the SPI control module, based on the instructions sent by the host computer, mainly including the operating range and operating frequency, can control the gain and input impedance of the low-noise preamplifier circuit, the gain of the programmable gain amplifier circuit, and the cutoff frequency of the low-pass filter circuit.

[0033] Furthermore, the analog front-end communicates with the high-speed acquisition module and data interface module via high-speed serial LVDS, primarily including the bit clock DCLK, frame clock FLCK, and differential data signal CHn_OUT. The DLCK control module delays the bit clock DCLK to generate the working clock bitclk for the data interface module, aligning the phases of bitclk and DCLK so that bitclk aligns with the most stable position of the FLCK and CHn_OUT signals. The FLCK control module performs serial-to-parallel conversion on the frame clock FLCK using ISERDES resources and uses the bitslip signal to find the correct character start position in the acquired data. The differential data signal CHn_OUT undergoes correct serial-to-parallel conversion using the bitslip signal output by the FLCK control module, ultimately obtaining correct and stable multi-channel acquired data, which is then transmitted to the data preprocessing module.

[0034] Furthermore, the bandpass filter parameters in the data preprocessing module can be changed according to the host computer to adapt to the needs of multiple frequency bands.

[0035] The system's workflow is as follows: After power-on, the SPI control module initializes and configures the analog front-end and high-speed acquisition module. When the host computer sends a start command, the analog signals from the multiple receiving hydrophones undergo low-noise amplification and filtering by the analog front-end and high-speed acquisition module, followed by digital-to-analog conversion. The data interface module receives the acquired data according to a stable timing sequence. Subsequently, the data preprocessing module performs signal preprocessing, and finally, the data is packaged and organized according to the channel order before being uploaded to the host computer via the network transmission module.

[0036] Example 2 Example 2 is a preferred example of Example 1.

[0037] The dual-frequency imaging sonar system has 96 input channels, operating at frequencies of 750kHz and 1.2MHz, with a sampling rate of 20MHz. The FPGA module used is the Xilinx XC7K325T, and the analog front-end and high-speed acquisition module is the TI AFE5818. Figure 1 This is the overall block diagram of the system. It mainly includes an analog front-end and high-speed acquisition module, an FPGA module, a clock driver module, a power supply module, a DA module, and a network transmission module.

[0038] The analog front-end and high-speed acquisition module consists of six AFE5818 chips. Each chip integrates 16 channels of LNA, TVG, PGA, low-pass filter circuit, and high-speed acquisition circuit. The functional block diagram of one channel is shown below. Figure 2As shown. The first stage is a low-noise preamplifier circuit, responsible for amplifying the analog signal from the receiving hydrophone with low noise. Its input impedance is configurable to match the output impedance of the receiving hydrophone, and its amplification factor can be set to 12, 18, or 24 dB. The second stage is a TVG amplifier circuit with an amplification factor of -40 to 0 dB, controlled by the DA module, used to compensate for sonar propagation loss. The third stage is a programmable gain amplifier (PGA) circuit, with an amplification factor that can be set to 24 or 30 dB, amplifying the signal to an amplitude suitable for the ADC. The fourth stage is a low-pass filter circuit with a cutoff frequency set to 10 MHz to prevent signals above the sampling rate from aliasing in. The final stage is a high-speed acquisition circuit with a sampling rate of 20 MHz, converting the analog signal into a digital signal.

[0039] The FPGA module mainly includes an SPI control module, a data interface module, and a data preprocessing module.

[0040] The SPI control module is primarily responsible for configuring the operating status of the analog front-end and the high-speed acquisition module. When the operating range is short-range, the gain of the low-noise preamplifier circuit can be set to 12dB; when the operating range is medium-range, the gain can be set to 18dB; and when the operating range is long-range, the gain can be set to 24dB.

[0041] The data interface module mainly includes the DCLK control module and the FCLK control module, responsible for receiving data from the analog front-end and the high-speed acquisition module, and completing the synchronous acquisition of multi-channel underwater acoustic signals. The analog front-end and the high-speed acquisition module communicate with the data interface module via high-speed serial LVDS, and their interface timing is as follows: Figure 3 As shown, it mainly includes the bit clock DCLK, the frame clock FLCK, and the differential data signal CHn_OUT.

[0042] The bit clock DLCK is connected to the FPGA's dedicated clock input pin SRCC and input to the DCLK control module. Its flowchart is as follows: Figure 4 As shown. The bit clock DLCK uses the IDELAY delay resource inside the FPGA to introduce a certain delay to DCLK. The output of the IDELAY delay resource then passes through BUFIO and BUFR to further generate a fixed delay, resulting in a 280MHz data clock bitclk and a 20MHz area clock clkdiv. The bit clock DCLK also enters the ISERDES resource for serial conversion. The control module continuously monitors the parallel data output of ISERDES. As the IDELAY delay changes, the output of ISERDES also changes. When the output of ISERDES is in a state that has both 0 and 1, bitclk and DLCK are in phase alignment. At this time, bitclk can be used as the acquisition clock for FCLK and data.

[0043] The flowchart of the FLCK control module is as follows: Figure 5 As shown, its function is to find the correct starting position of the 14-bit acquired data. The ISERDES resource is set to 14-bit DDR mode, which can be achieved by cascading two ISERDES. When the frame clock FCLK enters the ISERDES resource for serial-to-parallel conversion, the control module continuously adjusts the parallel data output of the ISERDES through the bitslip signal. When the output 14-bit data is all 0s or all 1s, the correct character starting position has been found. The bitslip signal output by the FCLK module also controls the ISERDES resource connected to the differential data signal CHn_OUT, ultimately obtaining correct and stable multi-channel 14-bit acquired data, which is then transmitted to the data preprocessing module.

[0044] The signal preprocessing process of the data preprocessing module is as follows: Figure 6 As shown in the diagram, the acquired multi-channel data is first subjected to low-pass filtering. There are six low-pass filters, each with 16 channels, a 320MHz clock speed, a 20MHz sampling rate, and a 1.25MHz cutoff frequency. After band-pass filtering, the signal is downsampled by a factor of 6, resulting in a sampling rate of 3.33MHz. The outputs of the six filters are then packaged into a single serial signal of 96 channels. Next, band-pass filtering is performed. The passband parameters can be set to either 750kHz or 1.2MHz, with a bandwidth of 80kHz, meeting the requirements of this dual-frequency image sonar system. The band-pass filter parameters can be modified at any time via the host computer to meet the requirements of other image sonar equipment. Finally, the band-pass filtered output data is downsampled again, packaged and organized according to channel order, and then uploaded to the host computer via a network transmission module.

[0045] The DA module mainly consists of internal memory (TVG_RAM) and a DAC controller. TVG_RAM pre-stores a data segment based on propagation loss parameters. Upon startup, the read address increments at corresponding time intervals. The data read from TVG_RAM is sent to the DAC controller, which then adjusts the output voltage of the peripheral DA module at appropriate intervals, thereby controlling the gain of the analog front-end and the high-speed acquisition module. For system flexibility, the data in TVG_RAM can also be modified via a network transmission module. Different TVG curves can be set for different operating ranges, or a fixed voltage can be directly output for system self-testing.

[0046] The clock drive module is mainly composed of the clock driver chip CDCLVC1212. The active crystal oscillator outputs six 20MHz differential clocks through the clock driver chip CDCLVC1212, driving six analog front-ends and high-speed acquisition modules in a one-to-one manner, providing a low-jitter, homogeneous clock.

[0047] The functional block diagram of the power module is as follows: Figure 7 As shown, the input supports a wide voltage range of 9~17V, which is converted into five power supplies (5VD, 3V3D, 2V5D, 1V8D, and 1V2D) by five TPS54620 DC-DC chips. The 2V5D supply power to the HR_BANK of the FPGA module, and the 1V8D supply power to the HP_BANK of the FPGA module, respectively meeting the requirements of LVDS25 and LVDS level standards. The analog front-end and high-speed acquisition module chips require a total of five power supplies: AVDD_H, AVDD_M, DVDD1V8, AVDD1V8, and DVDD1V2, which are obtained through FB bead filtering.

[0048] The system's workflow is as follows: After power-on, the SPI control module initializes and configures the analog front-end and high-speed acquisition module. When the host computer sends a start command, the analog signals from the multiple receiving hydrophones undergo low-noise amplification and filtering by the analog front-end and high-speed acquisition module, followed by digital-to-analog conversion. The data interface module receives the acquired data according to a stable timing sequence. Subsequently, the data preprocessing module performs signal preprocessing, and finally, the data is packaged and organized according to the channel order before being uploaded to the host computer via the network transmission module.

[0049] In summary, the analog front-end and high-speed acquisition system for dual-frequency image sonar provided by this invention can complete the conditioning, acquisition and transmission of multi-channel hydrophone signals, and has the advantages of high system integration, good consistency between channels and strong equipment versatility.

[0050] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0051] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A dual-frequency image sonar simulation front-end and high-speed acquisition system, characterized in that, include: Analog front-end and high-speed acquisition module: used to receive multiple hydrophone analog signals and amplify, filter and convert them from analog to digital; FPGA module: connected to the analog front end and high-speed acquisition module, used to configure the working status of the analog front end and high-speed acquisition module, receive the digital signals output by them and perform preprocessing; Clock drive module: connected to the analog front end and high-speed acquisition module, used to provide the analog front end and high-speed acquisition module with a low-jitter differential clock signal; DA module: connected to the FPGA module and the analog front-end and high-speed acquisition module, used to adjust the gain in the analog front-end and high-speed acquisition module by outputting a variable voltage according to the control of the FPGA module; Power supply module: Used to provide stable power to the analog front-end, high-speed acquisition module, FPGA module, DA module, clock drive module and network transmission module; Network transmission module: connected to the FPGA module, used to transmit the preprocessed digital signal to the host computer and receive control commands issued by the host computer.

2. The dual-frequency image sonar simulation front-end and high-speed acquisition system according to claim 1, characterized in that, The analog front-end and high-speed acquisition module include multiple integrated chips, each of which integrates multiple signal processing channels. Each channel includes, in sequence: Low-noise preamplifier circuit: used to amplify the input hydrophone analog signal with low noise. Its input impedance can be configured to match the hydrophone output impedance, and the gain can be set to 12dB, 18dB or 24dB. Variable gain amplifier circuit: Its gain range is between -40dB and 0dB, and it is controlled by the voltage output of the DA module to compensate for sonar propagation loss; Programmable gain amplifier circuit: used to amplify the signal to an amplitude suitable for analog-to-digital conversion, with the gain set to 24dB or 30dB; Low-pass filter circuit: cutoff frequency is 10MHz, used to prevent signal aliasing above the sampling frequency; High-speed acquisition circuit: with a sampling rate of 20MHz, used to convert analog signals into digital signals.

3. The dual-frequency image sonar simulation front-end and high-speed acquisition system according to claim 1, characterized in that, The FPGA module includes: SPI control module: used to configure the working state of the analog front end and the high-speed acquisition module through the SPI interface, including configuring the gain and input impedance of the low-noise preamplifier circuit, the gain of the programmable gain amplifier circuit, and the cutoff frequency of the low-pass filter circuit; Data interface module: used to receive digital signals output by the analog front end and the high-speed acquisition module through the high-speed serial LVDS interface, and to complete the synchronous acquisition of multi-channel underwater acoustic signals; Data preprocessing module: used to perform digital filtering and downsampling on the acquired data output by the data interface module.

4. The dual-frequency image sonar simulation front-end and high-speed acquisition system according to claim 3, characterized in that, The data interface module includes: DCLK control module: connected to the bit clock DCLK output by the analog front end and high-speed acquisition module, used to delay DCLK, generate data acquisition clock bitclk and area clock clkdiv, and realize phase alignment between bitclk and DCLK through IDELAY, BUFIO, BUFR resources and ISERDES resources inside the FPGA. FCLK control module: connected to the frame clock FCLK output by the analog front end and high-speed acquisition module, used to perform serial-to-parallel conversion of FCLK through ISERDES resources, and to find and lock the correct character start position of 14-bit acquisition data through bitslip signal; The bitslip signal output by the FCLK control module controls the ISERDES resource for serial-to-parallel conversion of the differential data signal CHn_OUT, so as to output the correct multi-channel 14-bit acquired data to the data preprocessing module.

5. The dual-frequency image sonar simulation front-end and high-speed acquisition system according to claim 3, characterized in that, The data preprocessing module performs the following processing steps in sequence: The 96 channels of input data are first subjected to a first-stage digital low-pass filter. There are 6 low-pass filters, each of which processes 16 channels. The operating clock is 320MHz, the input signal sampling rate is 20MHz, and the cutoff frequency is 1.25MHz. The low-pass filtered signal is downsampled by a factor of 6, resulting in a sampling rate of 3.33MHz. The output data from the six filters are then packaged and integrated into a single serial 96-channel data stream. The integrated data is subjected to a second-stage digital bandpass filter. The passband center frequency of the bandpass filter is configured to be 750kHz or 1.2MHz, and the bandwidth is 80kHz. The output data after bandpass filtering is downsampled again, packaged in channel order, and then output through the network transmission module.

6. The dual-frequency image sonar simulation front-end and high-speed acquisition system according to claim 1, characterized in that, The DA module includes: TVG_RAM memory: used to pre-store gain control data corresponding to sonar propagation loss compensation; DAC controller: connected to the TVG_RAM memory and external DA conversion chip, used to read data in TVG_RAM and control the external DA conversion chip to output the corresponding analog voltage to the variable gain amplifier circuit of the analog front end and high-speed acquisition module; The data stored in the TVG_RAM is received and updated from the host computer through the network transmission module to adapt to different workloads or system self-test requirements.

7. The dual-frequency image sonar simulation front-end and high-speed acquisition system according to claim 1, characterized in that, The clock driving module includes a clock driving chip, which receives clock signals generated by an active crystal oscillator and outputs multiple 20MHz differential clock signals to drive the clock input terminals of multiple analog front-ends and high-speed acquisition modules in a one-to-one manner.

8. The dual-frequency image sonar simulation front-end and high-speed acquisition system according to claim 1, characterized in that, The power module supports a wide voltage input from 9V to 17V and generates five digital power supplies (5VD, 3V3D, 2V5D, 1V8D, and 1V2D) through multiple DC-DC conversion chips. Among them, 2V5D is used to power HR_BANK in the FPGA module, and 1V8D is used to power HP_BANK in the FPGA module. The AVDD_H, AVDD_M, DVDD1V8, AVDD1V8, and DVDD1V2 power supplies required by the analog front-end and high-speed acquisition module are obtained from the corresponding outputs of the power supply module through ferrite beads.

9. The dual-frequency image sonar simulation front-end and high-speed acquisition system according to claim 1, characterized in that, The workflow of this system is as follows: After the system is powered on, the SPI control module in the FPGA module initializes and configures the analog front-end and the high-speed acquisition module. The host computer sends a start command through the network transmission module; The multi-channel hydrophone analog signal is input to the analog front-end and high-speed acquisition module. After amplification, filtering and analog-to-digital conversion, it is output to the data interface module of the FPGA module through the LVDS interface. After the data interface module completes the synchronous reception of data, it sends the data to the data preprocessing module for digital low-pass filtering, band-pass filtering and downsampling processing. The processed data is packaged in channel order and uploaded to the host computer through the network transmission module.

10. The dual-frequency image sonar simulation front-end and high-speed acquisition system according to claim 2, characterized in that, The analog front-end and high-speed acquisition module consists of 6 integrated chips, each chip integrating 16 signal processing channels, for a total of 96 channels; The system operates at frequencies of 750 kHz and 1.2 MHz, with a sampling rate of 20 MHz. The cutoff frequency of the low-pass filter circuit is configured to be 10 MHz. The passband center frequency of the second-stage digital bandpass filter is configured to be either 750 kHz or 1.2 MHz, and the bandwidth is configured to be 80 kHz.

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