Displayport output adapter and method of controlling its clock signal

Abstract

The present application provides a display port output adapter and a method for controlling a clock signal of the display port output adapter. The display port output adapter includes a clock generator, a storage device and a controller, wherein the storage device is coupled to the clock generator, and the controller is coupled to the clock generator and the storage device. The clock generator outputs the clock signal according to a control code, wherein the control code corresponds to a frequency of the clock signal. The storage device stores input data received by the display port output adapter from a display port source device, and transmits output data stored in the storage device to a display port sink device according to the clock signal. In addition, the controller controls the control code according to a data amount of the storage device.

Description

Technical Field

[0001] This invention relates to display port data transmission, and more particularly to a display port output adapter and a method for controlling a clock signal for the display port output adapter. Background Technology

[0002] When using a Universal Serial Bus 4 (USB4) cable to transmit DisplayPort (DP) signals, data transmission between the devices at both ends of the USB4 cable requires separate clock signals due to signal standard conversion. To ensure synchronization of data transmission between the devices at both ends of the USB4 cable, the DisplayPort input adapter located at the input end of the USB4 cable uses a 2... 21 A nanosecond (ns) is the number of cycles of the clock signal at the input of the USB4 cable. The counting result is transmitted to the display port output adapter at the output of the USB4 cable via a clock synchronization packet for the purpose of correcting the clock signal at the output of the USB4 cable.

[0003] However, the above correction method has some problems. If the clock signal is in the above 2 21 If the frequency deviates from its original frequency within a nanosecond period, the display port output adapter can only correct the clock signal upon receiving the next clock synchronization packet. This poses a risk of data overflow or underflow in the display port output adapter's temporary storage space. Furthermore, the display port output adapter's temporary storage space can also experience data overflow or underflow due to excessively high or low data reception speeds. In particular, data overflow or underflow in the display port output adapter's temporary storage space can lead to abnormal display (such as flickering or color deviation), or even prevent the screen from lighting up (such as a black screen).

[0004] Therefore, a novel clock correction method and related architecture are needed to solve the above problems with little or no side effects. Summary of the Invention

[0005] The purpose of this invention is to provide a DisplayPort (DP) output adapter and a method for controlling a clock signal of the DisplayPort output adapter to avoid data overflow or underflow in the temporary storage space of the DisplayPort output adapter.

[0006] At least one embodiment of the present invention provides a display port output adapter. The display port output adapter includes a clock generator, a storage device, and a controller, wherein the storage device is coupled to the clock generator, and the controller is coupled to both the clock generator and the storage device. The clock generator is used to output a clock signal according to a control code, wherein the control code corresponds to a frequency of the clock signal. The storage device is used to store input data received by the display port output adapter from a display port source device, and to transmit the output data stored in the storage device to a display port sink device according to the clock signal. Furthermore, the controller is used to control the control code according to a data volume in the storage device.

[0007] At least one embodiment of the present invention provides a method for controlling a clock signal of a display port output adapter. The method includes: using a clock generator of the display port output adapter to output a clock signal according to a control code, wherein the control code corresponds to a frequency of the clock signal; using a storage device of the display port output adapter to store input data received from a display port source device; using the storage device to transmit the output data stored in the storage device to a display port aggregation device according to the clock signal; and using a controller of the display port output adapter to control the control code according to a data volume in the storage device.

[0008] The display port output adapter and related method provided by embodiments of the present invention can control the frequency of the clock signal output by the clock generator by monitoring the level (e.g., the amount of data) of the temporary storage space (e.g., the storage space of the aforementioned storage device) in the display port output adapter, thereby controlling the speed at which the display port output adapter outputs data and preventing data overflow or underflow. Furthermore, embodiments of the present invention do not significantly increase additional costs. Therefore, the present invention can solve the problems of related technologies without or with minimal side effects. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a display port source device and a display port aggregation device connected via a fourth-generation universal serial bus connection device according to an embodiment of the present invention.

[0010] Figure 2 This is a schematic diagram of a display port output adapter according to an embodiment of the present invention.

[0011] Figure 3 This is a schematic diagram illustrating the workflow of a method for controlling a clock signal of a display port output adapter according to an embodiment of the present invention.

[0012] Figure 4According to an embodiment of the present invention Figure 3 The first control scheme of the method shown.

[0013] Figure 5 According to an embodiment of the present invention Figure 3 The second control scheme of the method shown.

[0014] Figure 6 According to an embodiment of the present invention Figure 3 The third control scheme of the method shown.

[0015] Figure 7 According to an embodiment of the present invention, it includes Figure 4 The first control scheme shown and Figure 6 The diagram shows the workflow of the clock correction method for the third control scheme.

[0016] Figure 8 According to an embodiment of the present invention, it includes Figure 5 The second control scheme shown and Figure 6 The diagram shows the workflow of the clock correction method for the third control scheme. Detailed Implementation

[0017] Figure 1This is a schematic diagram 120 illustrating the connection of DisplayPort (DP) source device 110 and DisplayPort sink device via a fourth-generation Universal Serial Bus 4 (USB4) connection device, such as routers 101, 102, and 103, according to an embodiment of the present invention. In this embodiment, router 101 is coupled to DisplayPort source device 110 via a DisplayPort connection, wherein the DisplayPort input adapter 101A in router 101 communicates with DisplayPort transmitter 110T in DisplayPort source device 110 via a DisplayPort connection for primary connection, auxiliary channel, and hot-plug detection. Similarly, router 103 is coupled to DisplayPort sink device 120 via a DisplayPort connection, wherein the DisplayPort output adapter 103A in router 103 communicates with DisplayPort receiver 120R in DisplayPort sink device 120 via a DisplayPort connection for primary connection, auxiliary channel, and hot-plug detection. Additionally, router 102 is coupled between routers 101 and 103 via a USB4 connection. Specifically, router 101 (e.g., display port input adapter 101A therein) can convert source data transmitted by display port source device 110 (e.g., display port transmitter 110T therein) from display port format to USB4 format, so that source data can be transmitted to router 103 through router 102 (e.g., USB4 cable), and router 103 (e.g., display port output adapter 103A therein) can convert source data transmitted by router 102 from USB4 format to display port format, so that display port aggregation device 120 (e.g., display port receiver 120R therein) can obtain source data through display port connection.

[0018] Since the process of transmitting source data from display port source device 110 to display port aggregation device 120 involves different types of transmission interfaces, such as display port connection and USB4 connection, the data transmission of display port transmitter 110T and the data reception of display port receiver 120R are performed based on their respective clock signals. Therefore, when the clock signal used by display port transmitter 110T when transmitting data is not synchronized with the clock signal used by display port receiver 120R when receiving data (e.g., having different frequencies), the data transmission speed of display port transmitter 110T and the data reception speed of display port receiver 120R will be inconsistent, causing the level (e.g., data volume) of the data buffer space in display port output adapter 103A to change, resulting in the risk of data overflow or underflow. To reduce the risk of data overflow or underflow in the data buffer space of display port output adapter 103A, the present invention can monitor the level of the data buffer space in display port output adapter 103A in real time and control the data output speed of display port output adapter 103A and the data reception speed of display port receiver 120R accordingly.

[0019] Figure 2 This is a schematic diagram of a display port output adapter 200 according to an embodiment of the present invention, wherein the display port output adapter 200 may be... Figure 1 The example shown is a display port output adapter 103A. For example... Figure 2 As shown, the display port output adapter 200 may include a clock generator such as a phase-locked loop 210, a storage device such as static random access memory (SRAM) 220, and a controller 230, wherein the SRAM 220 is coupled to the phase-locked loop 210, and the controller 230 is coupled to both the phase-locked loop 210 and the SRAM 220. In this embodiment, the phase-locked loop 210 is used to operate according to a control code D. FREQ Output a clock signal CLK, where the control code D FREQ This corresponds to the frequency of the clock signal CLK. The storage space of the static random access memory 220 can be an example of the data buffer space in the aforementioned display port output adapter 103A, where the static random access memory 220 is used to store data from a display port source device (e.g., the display port output adapter 200). Figure 1 The input data received by the display port source device 110 (e.g., via) Figure 1 The routers 101 and 102 shown obtain the source data output from the display port source device 110, and transmit the output data stored in the static random access memory 220 to a display port aggregation device (e.g., according to the clock signal CLK). Figure 1The display port aggregation device 120 shown. In particular, the controller 230 is used to generate control codes D based on a data quantity such as water level control (e.g., generating) from static random access memory 220. FREQ For example, water level code D WL This can be used to represent the amount of data in static random access memory 220, and the water level code D that the controller 230 can read from static random access memory 220. WL Based on water level code D WL Control code D FREQ .

[0020] In this embodiment, the operation of the controller 230 can be implemented using firmware. For example, the controller 230 may include a processing circuit 230P and a storage device 230M, wherein the storage device 230M may store program code 230C, and the processing circuit 230P may execute the operation of the controller 230 according to the program code 230C. In some embodiments, the operation of the controller 230 can be implemented using hardware (e.g., each operation of the controller 230 may be implemented using corresponding logic circuits).

[0021] In this embodiment, the amount of data in the static random access memory 220, such as the water level, can increase in response to an increase in the input data received from the display port source device 110, and can decrease in response to a decrease in the transmission of the output data to the display port aggregation device 120, wherein the speed at which the input data is received via the USB4 connection is determined by the clock signal of the USB4 connection (in... Figure 2 The frequency control (labeled "USB4 Connection Clock" for ease of understanding), and the speed at which the output data is transmitted via the display port connection are determined by the clock signal connected to the display port (in...). Figure 2 Frequency control (labeled "DP connection clock" for ease of understanding). In particular, the clock signal CLK output by the phase-locked loop 210 can be used as the clock signal for the display port connection, so the speed at which the output data is transmitted to the display port aggregation device 120 is controlled by the frequency of the clock signal CLK.

[0022] Figure 3 According to an embodiment of the present invention, a method for controlling a display port output adapter (e.g.) Figure 2 A clock signal (e.g., from the display port output adapter 200 shown) Figure 2 The diagram illustrates the workflow of the method using the clock signal CLK. It should be noted that... Figure 3 The illustrated workflow is for illustrative purposes only and is not intended to limit the invention. For example, one or more steps may be performed... Figure 3 The workflow shown has been added, deleted, or modified. Furthermore, these steps do not necessarily need to be followed exactly to achieve the same result. Figure 3 Execute in the order shown.

[0023] In step S310, the display port output adapter can use a clock generator within it to output a clock signal according to a control code, wherein the control code corresponds to a frequency of the clock signal.

[0024] In step S320, the display port output adapter may use a storage device therein to store input data received from a display port source device.

[0025] In step S330, the display port output adapter can use the storage device to transmit the output data stored in the storage device to a display port aggregation device according to the clock signal.

[0026] In step S340, the display port output adapter can use a controller within it to control the control code based on a data volume of the storage device.

[0027] Figure 4 According to an embodiment of the present invention Figure 3 The first control scheme of the method shown. In this embodiment, the controller 230 can control the data volume of the static random access memory 220 (e.g., water level code D). WL Whether the value is higher than a target value TL determines whether to adjust the control code D. FREQ To adjust the frequency of the clock signal CLK. For example, when the data quantity is such as water level code D... WL When the water level is higher than the target value TL, the water level code D WL Falling Figure 4 In the area RB1 shown, and the controller 230, the control code D can be adjusted. FREQ To reduce the amount of data, the frequency of the clock signal CLK is increased (e.g., by increasing the speed at which the output data is transmitted to the display port aggregation device 120). When the amount of data is such as the water level code D... WL When the water level is below the target value TL, the water level code D WL Falling Figure 4 In the area RA1 shown, and the controller 230, the control code D can be adjusted. FREQ To reduce the frequency of the clock signal CLK (e.g., to reduce the speed at which the output data is transmitted to the display port aggregation device 120 in an attempt to increase the amount of data). Figure 4 In the first control scheme shown, the controller 230 can maintain the amount of data in the static random access memory 220 at (e.g., close to) the target value TL by properly adjusting the frequency of the clock signal CLK (e.g., adjusting the speed at which the output data is transmitted to the display port aggregation device 120), thereby avoiding data overflow or data underflow.

[0028] Figure 5 According to an embodiment of the present invention Figure 3 The second control scheme of the method shown. In this embodiment, the controller 230 can control the amount of data in the static random access memory 220 (e.g., water level code D). WL Is it a target region R between an upper bound UB and a lower bound LB? FINAL The internal mechanism determines whether to adjust control code D. FREQ To adjust the frequency of the clock signal CLK. For example, when the data quantity is such as water level code D... WL When the water level is above the upper limit value UB, the water level code D WL Falling Figure 5 In the area RB2 shown, and the controller 230, the control code D can be adjusted. FREQ To reduce the amount of data, the frequency of the clock signal CLK is increased (e.g., by increasing the speed at which the output data is transmitted to the display port aggregation device 120). When the amount of data is such as the water level code D... WL When the water level is below the lower limit value LB, the water level code D WL Falling Figure 5 In the area RA2 shown, and the controller 230, the control code D can be adjusted. FREQ To reduce the frequency of the clock signal CLK (e.g., to reduce the speed at which the output data is transmitted to the display port aggregation device 120 in an attempt to increase the amount of data). Figure 5 The second control scheme shown allows the controller 230 to maintain the amount of data in the static random access memory 220 within the target region R by properly adjusting the frequency of the clock signal CLK (e.g., adjusting the speed at which the output data is transmitted to the display port aggregation device 120). FINAL This prevents data overflow or underflow.

[0029] Figure 6 According to an embodiment of the present invention Figure 3 The third control scheme of the method shown. In this embodiment, the controller 230 can determine whether to adjust the control code D based on the changing trend of the amount of data in the static random access memory 220. FREQ To adjust the frequency of the clock signal CLK. For example, when the data quantity is such as water level code D... WL (like Figure 6 The trend of the SRAM water level shown is an increasing trend (e.g., water level code D). WL The current value is greater than the water level code D. WL When the value is lower than the previous value, the controller 230 can adjust the control code D. FREQ To increase the frequency of the clock signal CLK (e.g., to increase the speed at which the output data is transmitted to the display port aggregation device 120 to reduce the rate of increase of the data amount). When the data amount is such as water level code D WL (like Figure 6The trend of the SRAM water level shown is a decreasing trend (e.g., water level code D). WL The current value is less than the water level code D. WL When the value is lower than the previous value, the controller 230 can adjust the control code D. FREQ To reduce the frequency of the clock signal CLK (e.g., to reduce the speed at which the output data is transmitted to the display port aggregation device 120, thereby reducing the rate of decrease in the data volume). Figure 6 The third control scheme shown allows the controller 230 to minimize the rate of change of the amount of data in the static random access memory 220 (e.g., keeping the amount of data constant) by properly adjusting the frequency of the clock signal CLK (e.g., adjusting the speed at which the output data is transmitted to the display port aggregation device 120), thereby preventing data overflow or underflow.

[0030] It should be noted that the first, second, and third control schemes mentioned above can be combined to further optimize the control of the amount of data in the static random access memory 220.

[0031] Figure 7 According to an embodiment of the present invention, it includes Figure 4 The first control scheme shown and Figure 6 The diagram illustrates the workflow of the clock correction method in the third control scheme. It should be noted that... Figure 7 The illustrated workflow is for illustrative purposes only and is not intended to limit the invention. For example, one or more steps may be performed... Figure 7 The workflow shown has been added, deleted, or modified.

[0032] In step S710, the storage device (e.g., static random access memory 220) in the display port output adapter 200 begins to receive and store the input data obtained via the USB4 connection.

[0033] In step S720, the controller 230 in the display port input adapter 200 first... Figure 4 The first control scheme shown tracks the water level of the storage device (e.g., water level code D). WL And the frequency of the control clock signal CLK.

[0034] In step S730, the water level of the storage device (e.g., water level code D) WL The target value TL is achieved due to the control of the first control scheme.

[0035] In step S740, the water level in the storage device (e.g., water level code D) WL After the target value TL is reached, the controller 230 in the display port input adapter 200 then... Figure 6The third control scheme shown tracks the water level of the storage device (e.g., water level code D). WL And the frequency of the control clock signal CLK.

[0036] Figure 8 According to an embodiment of the present invention, it includes Figure 5 The second control scheme shown and Figure 6 The diagram illustrates the workflow of the clock correction method in the third control scheme. It should be noted that... Figure 8 The illustrated workflow is for illustrative purposes only and is not intended to limit the invention. For example, one or more steps may be performed... Figure 8 The workflow shown has been added, deleted, or modified.

[0037] In step S810, the storage device (e.g., static random access memory 220) in the display port output adapter 200 begins to receive and store the input data obtained via the USB4 connection.

[0038] In step S820, the controller 230 in the display port input adapter 200 first... Figure 5 The second control scheme shown tracks the water level of the storage device (e.g., water level code D). WL And the frequency of the control clock signal CLK.

[0039] In step S830, the water level of the storage device (e.g., water level code D) WL Because of the control scheme of the second control scheme, it enters the target area R. FINAL .

[0040] In step S840, the water level in the storage device (e.g., water level code D) WL Entering the target area R FINAL Then, the controller 230 in the display port input adapter 200 then... Figure 6 The third control scheme shown tracks the water level of the storage device (e.g., water level code D). WL And the frequency of the control clock signal CLK.

[0041] In summary, the display port output adapter and method provided by the embodiments of the present invention can monitor the amount of data in its temporary storage space and control the data output speed accordingly, thereby maintaining the amount of data in the temporary storage space at a target value or within a target range. In this way, even if the frequency of the display port connection clock of the front-end display port transmitter changes and cannot transmit the display port clock synchronization packet in time, the display port output adapter can still adjust the frequency of the display port connection clock of the display port receiver according to the change in the amount of data in its temporary storage space, thereby avoiding data overflow or underflow. Furthermore, the embodiments of the present invention do not significantly increase additional costs. Therefore, the present invention can solve the problems of related technologies without or with minimal side effects.

[0042] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

[0043] [Symbol Explanation] 101, 102, 103: Router 101A: Display Port Input Adapter 103A: Display Port Output Adapter 110: Display port source device 110T: Display Port Transmitter 120: Display port aggregation device 120R: Display Port Receiver 200: Display Port Output Adapter 210: Phase-locked loop 220: Static Random Access Memory 230: Controller 230P: Processing circuit 230M: Storage device 230C: Program Code CLK: Clock signal D FREQ Control code D WL Water level code TL: Target value RB1, RA1: Region UB: Upper bound LB: Lower bound RB2, RA2: Regions R FINAL Final area S310~S340, S710~S740, S810~S840: Steps

Claims

1. A display port output adapter, characterized in that, Include: A clock generator is used to output a clock signal according to a control code, wherein the control code corresponds to a frequency of the clock signal; A storage device, coupled to the frequency generator, is used to store input data received by the display port output adapter from a display port source device, and to transmit the output data stored in the storage device to a display port aggregation device according to the clock signal; as well as A controller, coupled to the clock generator and the storage device, is used to control the control code based on a data quantity in the storage device.

2. The display port output adapter as described in claim 1, characterized in that, The amount of data in the storage device increases as the input data received from the display port source device increases and decreases as the output data is transmitted to the display port aggregation device, and the speed at which the output data is transmitted to the display port aggregation device is controlled by the frequency of the clock signal.

3. The display port output adapter as described in claim 2, characterized in that, The controller determines whether to adjust the frequency of the clock signal by adjusting the control code based on whether the amount of data exceeds a target value.

4. The display port output adapter as described in claim 3, characterized in that: When the data volume exceeds the target value, the controller adjusts the control code to increase the frequency of the clock signal; and When the amount of data is lower than the target value, the controller adjusts the control code to reduce the frequency of the clock signal.

5. The display port output adapter as described in claim 2, characterized in that, The controller determines whether to adjust the frequency of the clock signal by adjusting the control code based on whether the data volume is within a target range between an upper and a lower limit.

6. The display port output adapter as described in claim 5, characterized in that: When the data volume exceeds the upper limit, the controller adjusts the control code to increase the frequency of the clock signal; and When the data volume is below the lower limit, the controller adjusts the control code to reduce the frequency of the clock signal.

7. The display port output adapter as described in claim 2, characterized in that, The controller determines whether to adjust the frequency of the clock signal by adjusting the control code based on a trend in the amount of data.

8. The display port output adapter as described in claim 7, characterized in that: When the data volume shows an increasing trend, the controller adjusts the control code to increase the frequency of the clock signal; and When the data volume changes in a decreasing trend, the controller adjusts the control code to reduce the frequency of the clock signal.

9. A method for controlling a clock signal of a display port output adapter, characterized in that, Include: A clock generator using the display port output adapter outputs a clock signal according to a control code, wherein the control code corresponds to a frequency of the clock signal; The display port output adapter uses a storage device to store input data received from a display port source device; The storage device is used to transmit the output data stored in the storage device to a display port aggregation device according to the clock signal; as well as A controller using the display port output adapter controls the control code based on a data quantity of the storage device.

10. The method as described in claim 9, characterized in that, The amount of data in the storage device increases as the input data received from the display port source device increases and decreases as the output data is transmitted to the display port aggregation device, and the speed at which the output data is transmitted to the display port aggregation device is controlled by the frequency of the clock signal.

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