virtual static random access memory

Abstract

This invention provides a virtual static random access memory (VRAM) that can improve data transmission speed. The VRAM, in a first operation, performs input or output of data to storage units corresponding to the input column and row addresses after an initial delay starting from the input instruction and column address. It includes a control unit that, under certain conditions, controls the delay in a second operation following the first operation to be shorter than the initial delay.

Description

Technical Field

[0001] This invention relates to pseudo-static random access memory (pSRAM). Background Technology

[0002] pSRAM is a semiconductor memory device that includes an interface compatible with Static Random Access Memory (SRAM) (e.g., Patent Document 1: Japanese Patent Application Publication No. 2020-135914).

[0003] Figure 1 (a) is a time map of an example of the timing of signals in the existing pSRAM when a read instruction is displayed. Figure 1 (b) shows a timing diagram of the signals in the existing pSRAM when a write command is input. This example illustrates a clock-synchronous pSRAM that receives signals synchronously with the clock signal, and also an address-data multiplexing interface pSRAM. The address-data multiplexing interface pSRAM has address and data terminals configured to input each address signal and data signal. The pSRAM is configured to: begin a read or write operation when the chip select signal CS# transitions from invalid (high level) to valid (low level), and end the read or write operation and perform pre-charge when the chip select signal CS# transitions from valid (low level) to invalid (high level).

[0004] The chip select signal CS# is synchronized with the external clock signal CLK from the first to the third clock cycle after it transitions from invalid (high level) to valid (low level). Instructions (CMD), column addresses (RA), and column addresses (CA) are input via the address data terminals. Specifically, the instruction (CMD) is input on the rising edge of the first clock cycle of the external clock signal CLK, the column address (RA) is input on the rising and falling edges of the second clock cycle of the external clock signal CLK, and the row address (CA) is input on the rising and falling edges of the third clock cycle of the external clock signal CLK. An example is shown where an 8-bit signal is input at each clock edge.

[0005] exist Figure 1In (a), the word line (WL) becomes active (high level) after the column address is input, and the row select line (CSL) is switched after the row address (CA) is input. Then, after an initial delay starting from the input instruction (CMD) and column address (RA), data from the memory cells corresponding to the input column address (RA) and row address (CA) is read and output as data. Additionally, the word line (WL) is pre-charged when the chip select signal CS# transitions from active (low level) to inactive (high level). The initial delay is expressed as tCK (tCK is the display clock cycle) × delay number N (N is an integer greater than or equal to 1, representing the display delay number), with a delay number of 8 (N = 8) as an example. Furthermore, the delay number is dependent on the frequency of the external clock signal CLK; the higher the frequency of the external clock signal CLK, the larger the delay number becomes.

[0006] exist Figure 1 In (b), the word line (WL) becomes active (high level) after the column address is input. Then, when write data is input after an initial delay following the input instruction (CMD) and the column address (RA), the row select line (CSL) is switched. The length of the initial delay in the write operation is equal to the length of the initial delay in the read operation. Furthermore, the word line (WL) is pre-charged when the chip select signal CS# transitions from active (low level) to inactive (high level).

[0007] Because data cannot be input, output, read, or written until the initial delays in each operation, the time of each operation cannot be shortened, thus making it difficult to improve data transmission speed. Summary of the Invention

[0008] The present invention provides a virtual static random access memory. In a first operation, after an initial delay starting from the input instruction and column address, data is input or output to the storage cells corresponding to the input column address and row address. The first operation includes a control unit that, when certain conditions are met, controls the delay in a second operation following the first operation to be shorter than the initial delay.

[0009] The virtual static random access memory according to the present invention can improve data transfer speed. Attached Figure Description

[0010] Figure 1 (a) in the image is a time diagram of an example of the time history of the signals in the existing pSRAM when a read command is input. Figure 1 (b) in the figure is a time plot of an example of the timing of the signals in the existing pSRAM when the input write command is executed.

[0011] Figure 2This is a schematic diagram showing a pSRAM configuration example of a first embodiment of the present invention.

[0012] Figure 3 A schematic diagram illustrating an example of the relationship between the initial delay and short latency for each different clock cycle.

[0013] Figure 4 A schematic diagram illustrating an example of bit allocation for a display instruction.

[0014] Figure 5 (a) is a schematic diagram showing an example of the configuration of the pre-charge signal generation unit. Figure 5 (b) in the diagram is a schematic diagram showing an example of the configuration of the delayed signal generation unit.

[0015] Figure 6 (a) is a time graph of an example of the timing of signals in pSRAM when a read command is input, with the initial delay set. Figure 6 (b) is a time graph showing an example of the timing of signals in pSRAM when a read command is input under the condition of setting a short delay.

[0016] Figure 7 A time diagram showing an example of the signal timing when a write instruction is input to a temporary register in a pSRAM according to a second embodiment of the present invention.

[0017] Figure 8 A time diagram showing an example of the time history of signals within a pSRAM relating to a second embodiment of the present invention.

[0018] Figure 9 This is a schematic diagram showing a pSRAM configuration example of a third embodiment of the present invention.

[0019] Figure 10 A time diagram showing an example of the time history of signals within a pSRAM relating to a third embodiment of the present invention.

[0020] Figure 11 (a) in the diagram is a schematic diagram of an example of bit allocation for a display instruction. Figure 11 (b) in the figure is a time graph of an example of the time history of the signal when the input command is displayed.

[0021] Figure 12 This is a schematic diagram showing a pSRAM configuration example according to a fourth embodiment of the present invention.

[0022] Figure 13 (a) is a time plot showing an example of the timing of signals in pSRAM when no error is detected in the write instruction. Figure 13(b) in the figure is a time plot showing an example of the timing of the signals in the pSRAM when an error is detected in a write instruction.

[0023] [Symbol Explanation]

[0024] 10: Control Department

[0025] 20: Memory cell array

[0026] 101: Instruction Decoder

[0027] 102: Train Control Department

[0028] 103: Delay Counter

[0029] 104: Operations Control Department

[0030] 105: Pre-charge signal generation unit

[0031] 105a: Shift register

[0032] 105b: Inverter

[0033] 106: Pre-charge control unit

[0034] 107: Delayed Signal Generation Unit

[0035] 107a: Shift register

[0036] 107b, 107c, 107d: Inverters

[0037] 108: Column address [n] latch

[0038] 109: Column address [n-1] latch

[0039] 110: Comparator

[0040] 111: Inverter

[0041] 112: Write Data Latch Section

[0042] 113: Error Detection Department

[0043] 114: Inverter

[0044] ACT: Activation Signal

[0045] ADQ: 8-bit signal

[0046] CA: Row Address

[0047] CLK: External clock signal

[0048] / CLR: terminal

[0049] CMD command

[0050] CS#: Chip Select Signal

[0051] CSL: Row Selection Line

[0052] PRE: Precharge signal

[0053] PREEN: Precharge Enable / Disable Signal

[0054] CAS, NLTNCY, RACMP, SA: Signals

[0055] RA: Column Address

[0056] RD / WR: Read / Write Signal

[0057] WL: Character Line

[0058] WRDATA: Write data Detailed Implementation

[0059] (First Implementation Type)

[0060] Figure 2 This is a schematic diagram illustrating a pSRAM configuration example according to a first embodiment of the present invention. The pSRAM of this embodiment is configured to, in a first operation, perform data input or output to memory cells corresponding to the input column address and row address after an initial delay starting from the input instruction and column address. The pSRAM of this embodiment includes a control unit 10 and a memory cell array 20. The control unit 10 and the memory cell array 20 can each be configured with dedicated hardware devices or logic circuits. The memory cell array 20 includes a plurality of memory cells configured in a row-column arrangement.

[0061] When certain conditions are met, the control unit 10 controls the delay in the second operation following the first operation to be shorter than the aforementioned initial delay. In this embodiment, the specific conditions include inputting a specific instruction in the first operation, which is used to make the delay in the second operation shorter than the initial delay. In this embodiment, the specific instruction includes an instruction to instruct that precharging of the word lines corresponding to the input column address is not performed. In this embodiment, the specific instruction includes a read or write instruction.

[0062] The pSRAM of this embodiment is a clock-synchronized virtual static random access memory that is input or output in sync with a clock signal (e.g., an external clock signal CLK). Since the instruction signal, address signal, and data signal are input or output in sync with the clock signal (which is the external clock signal CLK), the delay length from the input of the instruction signal and address signal to the input or output of the data signal can be set according to the number of clock cycles.

[0063] The pSRAM of this embodiment is an address-data multiplexed virtual static random access memory with address and data terminals configured to input each address signal and data signal. Since each address signal and data signal is input via a common terminal (address and data terminal) instead of a separate terminal, it is possible to control the input of instructions, addresses, and data for other operations during operation, and to suppress delay control based on the input of other operations in the first and / or second operations.

[0064] The control unit 10 includes: an instruction decoder 101, a column control unit 102, a delay counter 103, a row control unit 104, a precharge signal generation unit 105, a precharge control unit 106, and a delay signal generation unit 107.

[0065] The instruction decoder 101, synchronized with the external clock signal CLK, decodes the instruction CMD (such as...) input via the address and data terminals when the chip select signal CS# from the external input changes from invalid (high level) to valid (low level). Figure 6 As shown in (a) in the diagram, internal instructions are generated. These generated internal instructions include, for example, an activation signal ACT, a read signal RD, and a write signal WR. Although not shown in the diagram, the instruction decoder 101 generates update signals, etc., as internal instructions.

[0066] The column control unit 102 controls the activation / deactivation of corresponding memory cells within the memory cell array 20 based on the activation signal ACT input from the instruction decoder 101. For example, when a valid (high-level) activation signal ACT is input from the instruction decoder 101, the column control unit 102 controls the activation / deactivation of corresponding memory cells within the memory cell array 20 via the address data terminal. Figure 6 As shown in (a), the signal WL corresponding to the activated character line is enabled (high level) and output to the memory cell array 20. Additionally, when the activated (high level) signal ACT is input from the instruction decoder 101, the column control unit 102 enables the signal SA of the activated induction amplifier and outputs it to the memory cell array 20.

[0067] When the column control unit 102 receives a valid (high-level) precharge signal PRE from the precharge control unit 106, after the operation ends (after the chip select signal CS# changes from valid (low-level) to invalid (high-level), it invalidates the signal WL (low-level) and outputs it to the memory cell array 20. Therefore, the activated word line is deactivated after the operation ends, and precharging of that word line is performed. On the other hand, when the column control unit 102 receives an invalid (low-level) precharge signal PRE from the precharge control unit 106, it also outputs the signal WL to the memory cell array 20 in a valid (high-level) state after the operation ends. The activation state of the word line is maintained, and precharging of that word line is not performed.

[0068] When the read signal RD or write signal WR is input from the instruction decoder 101, the delay counter 103 counts the number of pulses (dual-state trigger count) of the external clock signal CLK input from the outside. Then, when the number of pulses counted by the delay counter 103 reaches a specific delay value, it outputs the signal CAS, input via the address data terminal, to the row control unit 104. This signal CAS is used to specify the input row address CA (e.g., ...). Figure 6 (as shown in (a)).

[0069] The delay counter 103 is configured to set a counting delay value based on the signal NLTNCY input from the delay signal generation unit 107. For example, when the signal NLTNCY is active (high level), the delay counter 103 determines that the delay is an initial delay and sets the counting delay value to the value corresponding to the initial delay. Conversely, when the signal NLTNCY is inactive (low level), the delay counter 103 determines that the delay is a short delay shorter than the initial delay and sets the counting delay value to the value corresponding to the short delay (a value smaller than the value corresponding to the initial delay).

[0070] An example of the relationship between the initial delay value and the short delay value is shown in Figure 3 The values ​​corresponding to the initial delay and the short delay are set in each clock cycle (tCK). Furthermore, in each clock cycle, the initial delay value (the number of clock cycles of the external clock signal CLK) is set to a larger value than the short delay value (the number of clock cycles of the external clock signal CLK). Moreover, the values ​​corresponding to the initial delay and the short delay are set larger for shorter clock cycles (higher frequencies of the external clock signal CLK). Additionally, information displaying such relationships can be stored in a mode register, such as a pSRAM memory containing operating mode information (e.g., cluster length), and referenced by the delay counter 103.

[0071] Additionally, when the delay counter 103 is in its initial delay state (when the signal NLTNCY is active (high level)), the external clock (after the instruction CMD and column address RA input) is used. Figure 6 In the example shown in (a), the clock pulse count begins from the 3rd clock cycle. Furthermore, when the delay counter 103 has a short delay (when the signal NLTNCY is invalid (low level)), it counts the pulses of the external clock after the instruction CMD and the row address CA input. Figure 6 In the example shown in (a), the number of pulses of the clock begins to be counted at the 4th clock.

[0072] When the CAS signal is input from the delay counter 103, the row control unit 104 activates the signal of the row selection line corresponding to the row address CA specified by the CAS signal (high level) and outputs it to the memory cell array 20.

[0073] The precharge signal generation unit 105 generates a precharge enable / disable signal PREEN based on the instruction CMD input via the address data terminal, indicating whether precharge is allowed on the word line corresponding to the column address RA input via the address data terminal, and outputs it to the precharge control unit 106. Specifically, the precharge signal generation unit 105 generates the first external clock signal CLK during operation. Figure 6 When the value of the ADQ5 bit in the 8-bit signal ADQ[7:0] input at the rising edge of the first external clock signal CLK (shown as 1stCLK), a precharge enable / disable signal PREEN is generated and output to the precharge control unit 106.

[0074] Figure 4 This is a schematic diagram illustrating an example of the bit allocation for the instruction CMD. The instruction CMD consists of three bits: ADQ7, ADQ6, and ADQ5, from the 8-bit ADQ[7:0] signal input at the rising edge of the first external clock signal CLK during operation. The ADQ7 bit specifies the instruction type (fetch or write). When ADQ7 is 1, CMD is a fetch instruction; when ADQ7 is 0, CMD is a write instruction. The ADQ6 bit specifies the target of the instruction (memory unit or register). When ADQ6 is 1, instruction processing occurs on the register; when ADQ6 is 0, instruction processing occurs on the memory unit. The ADQ5 bit indicates whether pre-charging is performed on the word line corresponding to the column address RA input via the address data terminal. When the ADQ5 bit value is 1, the instruction CMD indicates that the word lines should not be precharged; when the ADQ5 bit value is 0, the instruction CMD indicates that the word lines should be precharged.

[0075] Figure 5Section (a) describes the configuration of the precharge signal generation unit 105. The precharge signal generation unit 105 includes a shift register 105a and an inverter 105b. When the first external clock signal CLK (1stCLK) is input as a clock signal during operation, the shift register 105a latches the ADQ5 bit of the 8-bit signal ADQ[7:0] input at the rising edge of the first external clock signal CLK and outputs it. The inverter 105b logically inverts the signal output from the shift register 105a and outputs the logically inverted signal as the precharge enable / disable signal PREEN to the precharge control unit 106 and the delay signal generation unit 107. In addition, a reset signal enable, generated by other circuits in the control unit 10, is applied to the / CLR terminal of the shift register 105a.

[0076] When the precharge approval signal PREEN indicates that precharging is in progress (when the precharge approval signal PREEN is active (high level)), the precharge control unit 106 controls the precharging of the word lines corresponding to the input column address. In this embodiment, when the chip select signal CS# is active (low level), the precharge control unit 106 generates a precharge signal PRE based on the precharge approval signal PREEN input from the precharge signal generation unit 105, and outputs the generated precharge signal PRE to the column control unit 102. For example, when the precharge approval signal PREEN is active (high level) (when precharging is in progress), the precharge control unit 106 makes the precharge signal PRE active (high level) and outputs it to the column control unit 102. Conversely, when the precharge approval signal PREEN is inactive (low level) (when precharging is not in progress), the precharge control unit 106 inactives the precharge signal PRE (low level) and outputs it to the column control unit 102.

[0077] When the precharge yes / no signal PREEN indicates that precharging is not performed (when the precharge yes / no signal PREEN is invalid (low level)), the delay signal generation unit 107 controls the delay in the second operation to be shorter than the initial delay (set as a short delay). In this embodiment, the delay signal generation unit 107 generates a signal NLTNCY based on the precharge yes / no signal PREEN input from the precharge signal generation unit 105, and outputs the generated signal NLTNCY to the delay counter 103. Furthermore, in this embodiment, the delay signal generation unit 107 is an example of the "delay control unit" of the present invention.

[0078] Figure 5Section (b) describes the configuration of the delay signal generation unit 107. The delay signal generation unit 107 includes a shift register 107a and inverters 107b, 107c, and 107d. When the chip select signal CS#, logically inverted by inverter 107c, is input as a clock signal, shift register 107a outputs a precharge enable signal PREEN, logically inverted by inverter 107b. Inverter 107d logically inverts the signal output from shift register 107a and outputs the logically inverted signal as the NLTNCY signal to the delay counter 103. Additionally, a reset signal enable, generated by other circuitry within the control unit 10, is applied to the / CLR terminal of shift register 107a.

[0079] The control unit 10 configured as described above is configured such that when the word line accessed in the previous operation (first operation) is activated (the precharge enable signal PREEN is invalid (low level)), when the word line is accessed in the subsequent operation (second operation), the column address RA in the address input in the subsequent operation is invalidated, and by making only the row address CA valid, the delay in the subsequent operation is shorter than the initial delay.

[0080] Figure 6 (a) is a time graph of an example of the timing of signals in pSRAM when a read command is input, with the initial delay set. Figure 6 (b) is a time graph showing an example of the timing of signals in pSRAM when a read command is input under the condition of setting a short delay.

[0081] First, let me explain Figure 6 The operation is shown in (a). The assumption is that before the read operation (first operation) begins, the precharge enable signal PREEN is active (high level) (precharge is performed), and the NLTNCY signal is active (high level) (the delay in the read operation is the initial delay).

[0082] By enabling the chip selection signal CS# (low level), after the read operation begins, when the instruction CMD is input synchronously with the external clock signal CLK, the precharge signal generation unit 105 generates a precharge enable / disable signal PREEN based on the instruction CMD. Alternatively, assuming the instruction CMD is a read instruction without precharge (the value of bit ADQ5 is 1), the precharge signal generation unit 105 disables the precharge enable / disable signal PREEN (low level) and outputs it to the precharge control unit 106 and the delay signal generation unit 107.

[0083] On the other hand, since the shift register 107a of the delay signal generation unit 107 is already valid (high level) because the signal input to the clock terminal (the logic inversion signal of the chip select signal CS#) is already valid (high level), it does not latch the logic inversion signal of the precharge enable / disable signal PREEN output from the precharge signal generation unit 105. Therefore, the delay signal generation unit 107 outputs the valid (high level) signal NLTNCY to the delay counter 103.

[0084] When a valid (high-level) signal NLTNCY is input, the delay counter 103 determines that the delay in this read operation is the initial delay and counts the number of pulses of the external clock signal CLK until the value corresponding to the initial delay is reached. In addition, during the initial delay period, the column control unit 102 activates the word line of the corresponding input column address RA.

[0085] Next, when the number of pulses of the external clock signal CLK reaches the value corresponding to the initial delay, the delay counter 103 outputs the CAS signal to the row control unit 104, allowing data to be read from the memory cells corresponding to the input column address RA and row address CA. Furthermore, the read operation is terminated by invalidating the chip select signal CS# (high-level). Additionally, during this read operation, since there is no pre-charge input (ADQ5 bit value is 1) for the read instruction, pre-charging of the word lines corresponding to the input column address RA is not performed, keeping the word lines active.

[0086] Next, let's explain. Figure 6 The operation is shown in (b) above. Assuming in... Figure 6 After the read operation shown in (a), proceed Figure 6 In the read operation (second operation) shown in (b), before the read operation begins, the precharge enable signal PREEN is invalid (low level), and the NLTNCY signal is valid (high level). Furthermore, since the input of column address RA becomes invalid in subsequent read operations, column address RA is omitted from the input column address.

[0087] By making the chip selection signal CS# valid (low level), after the read operation starts, when the instruction CMD is input synchronously with the external clock signal CLK, the precharge signal generation unit 105 generates a precharge yes / no signal PREEN according to the instruction CMD. Assuming that the instruction CMD is a read instruction with precharge (the value of the ADQ5 bit is 0), the precharge signal generation unit 105 makes the precharge yes / no signal PREEN valid and outputs it to the precharge control unit 106 and the delay signal generation unit 107.

[0088] On the other hand, the shift register 107a of the delay signal generation unit 107 latches the logic inversion signal of the precharge enable / disable signal PREEN during the timing when the chip select signal CS# is valid (low level). Additionally, during the timing when the chip select signal CS# is valid (low level), the precharge enable / disable signal PREEN is at a low level, and the logic inversion signal of the precharge enable / disable signal PREEN is at a high level. The delay signal generation unit 107 outputs the invalid (low level) signal NLTNCY to the delay counter 103.

[0089] When an invalid (low-level) signal NLTNCY is input, the delay counter 103 determines that the delay in this read operation is a short delay and counts the number of pulses of the external clock signal CLK until the value corresponding to the short delay is reached.

[0090] Next, when the number of pulses of the external clock signal CLK reaches the value corresponding to the short delay, the delay counter 103 outputs the signal CAS to the row control unit 104, allowing data to be read from the memory cell corresponding to the row address CA input in this read operation (second operation). Furthermore, the read operation ends by invalidating the chip select signal CS# (high-order level). In subsequent read operations (second operation), since a pre-charge (ADQ5 bit value is 0) read instruction is input, pre-charging is performed on the word line corresponding to the column address RA input in the first operation.

[0091] In this way, when a specific instruction (a read or write instruction without pre-charging) is entered in the preceding read operation (first operation), the latency in the subsequent read operation (second operation) can be shorter than the initial latency. Therefore, by shortening the time of the subsequent read operation, the data transfer speed in the subsequent read operation can be improved.

[0092] (Second Implementation Type)

[0093] Although the pSRAM of this embodiment has the same property as the first embodiment that the delay in the second operation is shorter than the initial delay when a specific instruction is input in the first operation, the specific instruction includes a register write instruction, which is different from the first embodiment.

[0094] Register write instructions are as follows Figure 7 As shown, it consists of an instruction, an address, and mode register (MR) data written to the mode register. The MR data contains information on one or more bits indicating whether precharging is to be performed. In addition, the register write instruction, as described in the first embodiment, is an instruction that sets the value of the ADQ6 bits in the 8-bit signal ADQ[7:0] input at the rising edge of the first external clock signal CLK to 1.

[0095] When a write command is input to the input register, the precharge signal generation unit 105 of the control unit 10 acquires precharge information from the write mode register. Then, when the write mode register displays information indicating precharge is being performed, the precharge enable / disable signal PREEN is enabled (high level) and outputs it to the precharge control unit 106 and the delay signal generation unit 107. Conversely, when the write mode register displays information indicating no precharge is being performed, the precharge enable / disable signal PREEN is disabled (low level) and outputs it to the precharge control unit 106 and the delay signal generation unit 107.

[0096] When the delay signal generation unit 107 of the control unit 10 writes a temporary register instruction during the first operation, it latches the precharge enable signal PREEN at the end of the second operation (read or write operation) following the first operation (the rising edge of the chip select signal CS#), and outputs the latched signal as the signal NLTNCY to the delay counter 103.

[0097] Figure 8 This displays a timing diagram of an example of the timing of signals within the pSRAM of this embodiment. Also, similar to the first embodiment, it is assumed that the same column address is accessed in each operation.

[0098] In the timing sequence before time t1, we will take the precharge enable signal PREEN as valid (high level) (precharge is performed) and the NLTNCY signal as valid (high level) (in the read operation, the delay is the initial delay) as an example for illustration.

[0099] When a write command to a register without precharge is input at time t1, the precharge signal generation unit 105, after referring to the precharge information written to the mode register, invalidates the precharge enable / disable signal PREEN (low level) and outputs it to the precharge control unit 106 and the delay signal generation unit 107. Furthermore, since the timing of latching the precharge enable / disable signal PREEN is not specified, the delay signal generation unit 107 outputs the valid (high level) signal NLTNCY to the delay counter 103.

[0100] At the start of a read or write operation at time t2, the delay counter 103 sets the operational delay as an initial delay based on the valid (high-level) signal NLTNCY. Then, by invalidating the chip select signal CS# (high-level), at the end of the read or write operation, the delay signal generation unit 107 latches the invalid (low-level) precharge enable / disable signal PREEN and outputs the invalid (low-level) signal NLTNCY to the delay counter 103.

[0101] At the start of a read or write operation at time t3, delay counter 103 sets the delay during the operation to a short delay based on the invalid (low-level) signal NLTNCY. Therefore, the time for this read or write operation becomes shorter than that of the previous read or write operation.

[0102] When a write command to a precharged register is input at time t4, the precharge signal generation unit 105, after referring to the precharge information in the write mode register, enables the precharge enable signal PREEN (high level) and outputs it to the precharge control unit 106 and the delay signal generation unit 107. Furthermore, since the timing of latching the precharge enable signal PREEN is not specified, the delay signal generation unit 107 outputs the invalid (low level) signal NLTNCY to the delay counter 103.

[0103] When a read or write operation begins at time t5, the delay counter 103 sets the delay during the operation to a short delay based on the invalid (low-level) signal NLTNCY. Then, when the read or write operation ends by invalidating the chip select signal CS# (high-level), the delay signal generation unit 107 latches the valid (high-level) precharge enable / disable signal PREEN and outputs the valid (high-level) signal NLTNCY to the delay counter 103.

[0104] When a read or write operation begins at time t6, the delay counter 103 sets the delay in operation to the initial delay based on the valid (high-level) signal NLTNCY.

[0105] In this way, based on the register write instruction entered in a specific operation (first operation), the delay in the subsequent operation (second operation) can be set to an initial delay or a short delay.

[0106] (Third Implementation Mode)

[0107] In this embodiment, although the delay in the second operation is set to be shorter than the initial delay when the control unit 10 meets certain conditions, this is the same as in the embodiments described above. However, the specific conditions include inputting the same column address RA in both the first and second operations, which is different from the embodiments described above.

[0108] The control unit 10 is configured to control the delay in each consecutive operation to be shorter than the initial delay during the period when the same column address RA is input in each consecutive operation after the second operation, when a specific condition is met.

[0109] Figure 9This is a schematic diagram illustrating the pSRAM configuration example of this embodiment. The control unit 10 includes: an instruction decoder 101; a column control unit 102; a delay counter 103; a row control unit 104; a column address [n] latch unit 108, latching the column address RA input in the nth operation (n is an integer greater than or equal to 1); a column address [n-1] latch unit 109, latching the column address RA input in the (n-1)th operation; a comparator 110; and an inverter 111. The configurations of the instruction decoder 101, column control unit 102, delay counter 103, and row control unit 104 are the same as in the first embodiment.

[0110] The column address [n] latch unit 108 latches the column address RA input during each operation. Then, the column address [n] latch unit 108 outputs a signal RA[n] that displays the value of the latched column address RA to the column address [n-1] latch unit 109, comparator 110, and memory cell array 20.

[0111] Each time a signal RA[n] is input from the column address [n] latch unit 109, it latches the input signal RA[n] and the signal RA[n-1] that was input as RA[n] in the previous operation. Then, the column address [n-1] latch unit 109 outputs the signal RA[n-1] to the comparator 110.

[0112] Comparator 110 compares the value of signal RA[n] input from column address [n] latch 108 with the value of signal RA[n-1] input from column address [n-1] latch 109. Then, when the two values ​​are equal, comparator 110 activates the signal RACMP displaying the comparison result (high level) and outputs it to inverter 111, and deactivates the precharge signal PRE (low level) and outputs it to column control unit 102. Conversely, when the two values ​​are different, comparator 110 deactivates the signal RACMP displaying the comparison result (low level) and outputs it to inverter 111, and activates the precharge signal PRE (high level) and outputs it to column control unit 102.

[0113] Inverter 111 logically inverts the signal RACMP output from comparator 110 and outputs the inverted signal as NLTNCY to delay counter 103. That is, when the signal RACMP displaying the comparison result shows that the column address input in operation n (the value of signal RA[n]) and the column address input in operation (the value of signal RA[n-1]) are the same (when signal RACMP is valid (high level), inverter 111 outputs the invalid (low level) signal NLTNCY to delay counter 103, thus controlling the delay in operation n to be shorter than the initial delay (set as short delay). Furthermore, in this embodiment, inverter 111 is an example of the "delay control unit" of the present invention.

[0114] Figure 10 A time diagram showing an example of the timing of signals within the pSRAM of this embodiment. Assume that during operations prior to time t11, a column address RA with a value of 0 is accessed, and with the word line of that column address RA active, the precharge signal PRE is inactive (low level) and the signal NLTNCY is active (high level).

[0115] At the start of the next operation at time t11, when the column address RA with a value of 1 is input, the column address [n] latch 108 outputs the signal RA[n] with a value of 1 to the column address [n-1] latch 109, comparator 110, and memory cell array 20. On the other hand, when the signal RA[n] with a value of 1 is input, the column address [n-1] latch 109 outputs the signal [n-1] with a value of 0 to comparator 110.

[0116] Comparator 110 compares the value of signal RA[n] with the value of signal RA[n-1]. Because there is a difference between the two values, signal RACMP is invalidated (low level) and output to inverter 111, while precharge signal PRE is valid (high level) and output to column control unit 102. At this time, column control unit 102 precharges the word lines corresponding to the column address RA input in the previous operation (the word lines corresponding to column address RA with a value of 0) and activates the word lines corresponding to column address RA with a value of 1.

[0117] Additionally, the delay counter 103 sets the operational delay to an initial delay based on the valid (high-level) signal NLTNCY. Furthermore, after the operation ends, the active state of the word line corresponding to the column address RA with a value of 1 is maintained.

[0118] At time t12, when the next operation begins and the column address RA with a value of 1 is input, the column address [n] latch 108 outputs the signal RA[n] with a value of 1 to the column address [n-1] latch 109, the comparator 110, and the memory cell array 20. On the other hand, when the signal RA[n] with a value of 1 is input, the column address [n-1] latch 109 outputs the signal [n-1] with a value of 1 to the comparator 110.

[0119] Comparator 110 compares the value of signal RA[n] with the value of signal RA[n-1]. Since the two values ​​are equal, it makes signal RACMP valid (high level) and outputs it to inverter 111, and makes precharge signal PRE invalid (low level) and output it to column control unit 102.

[0120] In addition, the delay counter 103 sets the delay in operation to a short delay based on the invalid (low level) signal NLTNCY, so that the operation time becomes shorter than the previous operation.

[0121] At time t13, when the next operation begins and the column address RA with a value of 1 is input, since the value of the input column address RA is equal to the value of RA input in the previous operation, the same operation is performed as the previous operation, and the delay in the operation is also set to a short delay.

[0122] At time t14, when the next operation begins and the column address RA with a value of 2 is input, the column address [n] latch 108 outputs the signal RA[n] with a value of 2 to the column address [n-1] latch 109, the comparator 110, and the memory cell array 20. On the other hand, when the signal RA[n] with a value of 2 is input, the column address [n-1] latch 109 outputs the signal [n-1] with a value of 1 to the comparator 110.

[0123] Comparator 110 compares the value of signal RA[n] with the value of signal RA[n-1]. Because there is a difference between the two values, signal RACMP is invalidated (low level) and output to inverter 111, while precharge signal PRE is valid (high level) and output to column control unit 102. At this time, column control unit 102 precharges the word lines corresponding to the column address RA input in the previous operation (the word lines corresponding to column address RA with a value of 1) and activates the word lines corresponding to column address RA with a value of 2.

[0124] Additionally, the delay counter 103 sets the operational delay to an initial delay based on the valid (high-level) signal NLTNCY. Furthermore, after the operation ends, the active state of the word line corresponding to the column address RA with a value of 2 is maintained.

[0125] As described above, in a subsequent operation (the second operation), when accessing the same column address RA as in the preceding operation (the first operation), the delay in the subsequent operation can be set to be shorter than the initial delay. Furthermore, in each consecutive operation following the subsequent operation (the second operation), during the period when the same column address RA as in the preceding operation (the first operation) is input, the delay in each consecutive operation following the subsequent operation can be set to be shorter than the initial delay.

[0126] Because it is configured to maintain the active state of the character line after the operation is completed, the instruction CMD is set to precharge the character line. Figure 11 Example of instruction data structure shown in (a) is that the instruction CMD is composed of three bits: ADQ7, ADQ6, and ADQ4 of the 8-bit signal ADQ[7:0] input at the rising edge of the first external clock signal CLK during operation. The contents of ADQ7 and ADQ6 are the same as in the first embodiment.

[0127] The ADQ4 bit is used to indicate whether precharging of the word line corresponding to the column address RA input in the previous operation is performed. For example, when the value of the ADQ4 bit is 1, precharging is performed. Additionally, when the instruction CMD is input to precharge the word line, such as... Figure 11 As shown in (b), only the instruction and address are entered, without entering any data.

[0128] (Fourth Implementation Mode)

[0129] In this embodiment of the pSRAM, although the control unit 10 sets the delay in the second operation to be shorter than the initial delay when a specific condition is met, which is the same as in the above embodiments, the specific condition includes detecting an error in the data written in the first operation, which is different from the above embodiments.

[0130] Figure 12 This is a schematic diagram illustrating the pSRAM configuration example of this embodiment. The control unit 10 includes: an instruction decoder 101, a column control unit 102, a delay counter 103, a row control unit 104, a precharge control unit 106, a write data latch unit 112, an error detection unit 113, and an inverter 114. The configuration of the instruction decoder 101, column control unit 102, delay counter 103, and row control unit 104 is the same as in the first embodiment.

[0131] When the chip select signal CS# is active (low level), the precharge control unit 106 disables the precharge signal PRE (low level) and outputs it to the column control unit 102 when the signal ERR, indicating an error detected from the write data WRDATA, is active (high level) when it is input from the error detection unit 113. On the other hand, when the signal ERR is active (low level) (no error is detected from the write data WRDATA) when it is input from the error detection unit 113, the precharge control unit 106 enables the precharge signal PRE (high level) and outputs it to the column control unit 102.

[0132] During each write operation, the write data latch unit 112 latches the write data input via the address data terminal and outputs the latched write data WRDATA to the error detection unit 113 and the memory cell array 20. In this embodiment, the write data input from the outside is input in the form of check data for error detection (such as a parity code or a Cyclic Redundancy Check (CRC) code).

[0133] When write data WRDATA and check data are input from write data latch unit 112, error detection unit 113 performs error detection processing on write data WRDATA using check data. When error detection unit 113 detects that write data WRDATA contains an error, it activates signal EER (high level) and outputs it to inverter 114 and precharge control unit 106, while simultaneously outputting it to the outside via error terminal. On the other hand, when error detection unit 113 detects that write data WRDATA does not contain an error, it deactivates signal EER (low level) and outputs it to inverter 114 and precharge control unit 106, while simultaneously outputting it to the outside via error terminal.

[0134] The inverter 114 logically inverts the signal EER output from the error detection unit 113 and outputs the logically inverted signal as the NLTNCY signal to the delay counter 103. That is, when the error detection unit 113 detects an error in the written data (when the signal ERR is valid (high level)), the inverter 114 outputs the invalid (low level) signal NLTNCY to the delay counter 103, thereby controlling the delay in the second operation to be shorter than the initial delay (set as a short delay). Furthermore, in this embodiment, the inverter 114 is an example of the "delay control unit" of the present invention.

[0135] Figure 13 (a) is a time plot showing an example of the timing of signals in pSRAM when no error is detected in the write instruction. Figure 13(b) in the diagram is a timing diagram showing an example of the timing of signals in pSRAM when an error is detected in a write instruction. It is also assumed that the same column address is accessed in each operation.

[0136] Reference Figure 13 In step (a), the error detection unit 113 detects whether the written data WRDATA contains errors when write data and check data are input. Then, if the error detection unit 113 detects that the written data WRDATA does not contain errors, it invalidates the signal ERR (low level) and outputs it to the inverter 114 and the precharge control unit 106, while simultaneously outputting it to the outside via the error terminal. At this time, the inverter 114 makes the signal NLTNCY valid (high level) and outputs it to the delay counter 103. Therefore, the delay in the next operation is set to the initial delay. Additionally, the precharge control unit 106 makes the precharge signal PRE valid (high level) and outputs it to the column control unit 102, precharging the word line after the write operation is completed.

[0137] Reference Figure 13 In (b), when the error detection unit 113 detects an error in the written data WRDATA, it activates the precharge signal ERR (high level) and outputs it to the inverter 114 and the precharge control unit 106, while simultaneously outputting it to the outside via the error terminal. At this time, the inverter 114 deactivates the signal NLTNCY (low level) and outputs it to the delay counter 103. Therefore, the delay in the next operation is set to a short delay. In addition, the precharge control unit 106 deactivates the signal PRE (low level) and outputs it low to the column control unit 102, maintaining the word line active state even after the write operation is completed.

[0138] As mentioned above, when an error is detected in the input write data WRDATA during a write operation, the delay in subsequent operations can be set to be shorter than the initial delay.

[0139] Additionally, similar to the third type, an instruction CMD is configured to maintain the active state of the character line after the operation of writing data WRDATA detects an error, and to precharge the character line. This instruction CMD is configured to... Figure 11 The structures shown are the same.

[0140] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit the invention. Therefore, the elements disclosed in the above embodiments are intended to include all design changes or equivalents that fall within the scope of the present invention.

[0141] In the above embodiments, although examples are given with specific instructions including read or write instructions and instructions indicating whether to precharge the character lines, the present invention is not limited thereto. For example, the specific instruction may be only either a read instruction or a write instruction. In this case, when the same column address RA is input in the first operation and the second operation, when a read instruction or a write instruction is input in the first operation, the delay in the second operation can be controlled to be shorter than the initial delay. In addition, the specific instruction may be only an instruction indicating whether to precharge the character lines. Furthermore, the specific instruction may be any instruction configured to set the delay in the subsequent operation (the second operation) to a short delay.

Claims

1. A virtual static random access memory, characterized in that, In the first operation, after an initial delay starting from the input instruction and column address, data is input or output to the memory cells corresponding to the input column address and row address, including: The control unit, when certain conditions are met, controls the delay in the second operation after the first operation to be shorter than the initial delay by not pre-charging the character lines corresponding to the input column address.

2. The virtual static random access memory as described in claim 1, characterized in that, The specific conditions include: in the first operation, inputting a specific instruction that causes the delay in the second operation to be shorter than the initial delay.

3. The virtual static random access memory as described in claim 2, characterized in that, The specific instructions include read or write instructions that indicate that precharging of the character lines corresponding to the input column address is not performed.

4. The virtual static random access memory as described in claim 3, characterized in that, The control unit also includes: The precharge signal generation unit generates a precharge yes / no signal based on the input instruction. The precharge yes / no signal indicates whether to perform precharge on the word line corresponding to the input column address. The pre-charge control unit, when the pre-charge enable / disable signal indicates that pre-charging is to proceed, controls the pre-charging of the word line corresponding to the input column address; and The delay control unit, when the pre-charge availability signal indicates that pre-charging will not be performed, will control the delay in the second operation to be shorter than the initial delay; When a register write instruction indicating that precharging should not be performed is input, the precharging signal generation unit outputs a precharging yes / no signal indicating that precharging should not be performed on the word line corresponding to the input column address to the precharging control unit and the delay control unit.

5. The virtual static random access memory as described in claim 2, characterized in that, The specific instructions include: register write instructions.

6. The virtual static random access memory as described in claim 5, characterized in that, The control unit also includes: The precharge signal generation unit generates a precharge yes / no signal based on the input instruction. The precharge yes / no signal indicates whether to perform precharge on the word line corresponding to the input column address. The pre-charge control unit, when the pre-charge enable / disable signal indicates that pre-charging is to proceed, controls the pre-charging of the word line corresponding to the input column address; and The delay control unit, when the pre-charge availability signal indicates that pre-charging will not be performed, will control the delay in the second operation to be shorter than the initial delay; When a read or write instruction indicating that precharging should not be performed is input, the precharging signal generation unit outputs a precharging yes / no signal indicating that precharging should not be performed on the word line corresponding to the input column address to the precharging control unit and the delay control unit.

7. The virtual static random access memory as described in claim 1, characterized in that, The specific conditions include: entering the same column address in both the first and second operations.

8. The virtual static random access memory as described in claim 7, characterized in that, When the specific condition is met, the control unit controls the delay in each consecutive operation to be shorter than the initial delay during the period when the same column address is input in each subsequent operation following the second operation.

9. The virtual static random access memory as described in claim 7 or 8, characterized in that, The control unit also includes: A comparator that compares the column address input in operation n with the column address input in operation (n-1) and outputs the comparison result, where n is an integer greater than or equal to 1; and When the comparison result shows that the column address input in the nth operation is the same as the column address input in the (n-1)th operation, the delay control unit controls the delay in the nth operation to be shorter than the initial delay.

10. The virtual static random access memory as described in claim 1, characterized in that, The specific conditions include: an error is detected in the data written that was input in the first operation.

11. The virtual static random access memory as described in claim 10, characterized in that, The control unit also includes: The error detection unit detects whether the written data input in the first operation contains errors; and The delay control unit controls the delay in the second operation to be shorter than the initial delay when the error detection unit detects that the written data contains an error.

12. The virtual static random access memory as described in claim 1, characterized in that, The virtual static random access memory is either one of the following: (i) a clock-synchronized virtual static random access memory that inputs or outputs signals in sync with a clock signal; or (ii) Address-data multiplexing interface type virtual static random access memory.

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