An abnormal reset processing method, an abnormal processing device and a storage medium
By writing the abnormal reset information into the flash memory after the MCU chip is reset, the problem of being unable to locate abnormalities caused by SRAM data clearing is solved, and the abnormal information is reliably saved and subsequently resolved, thus improving the stability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2020-08-21
- Publication Date
- 2026-05-22
AI Technical Summary
In existing technologies, when the software program of an MCU chip freezes, the SRAM data is cleared, making it impossible to locate and resolve the anomaly, which affects the stability of the device.
After the chip is reset and before the SRAM is initialized, the abnormal reset information is written into the flash memory through the minimum system to ensure that the information is not lost and to provide a basis for subsequent location and resolution of the abnormality.
It effectively saves abnormal reset information, ensuring that the information can be obtained in the event of a power failure, supporting the subsequent location and resolution of abnormalities, and improving equipment stability.
Smart Images
Figure CN114077512B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, specifically to a method, device, and storage medium for handling abnormal reset. Background Technology
[0002] Currently, wearable devices, Internet of Things (IoT) devices, and other similar devices all use microcontroller (MCU) chips to achieve low power consumption and other functions. However, software programs that operate on MCU chips are highly likely to experience runtime crashes or freezes during operation. In such cases, the software program may fail to recognize the system anomaly and thus be unable to reset and restore the MCU chip through methods such as active restart.
[0003] The MCU chip supports watchdog technology, meaning that if the software program does not clear the pulse timer within a preset time, the watchdog will overflow and trigger a reset of the MCU chip. After the MCU chip resets, the software program can resume normal operation. Please refer to [link to relevant documentation]. Figure 1 This is a flowchart of a watchdog reset MCU chip provided in the prior art. From... Figure 1 As can be seen, the MCU chip initializes the static random access memory (SRAM) and clears the data based on the system reset handler. After the SRAM initialization is complete, the system starts normally by running the main function. After the system starts normally, the MCU chip enables the watchdog timer and feeds it periodically. This periodic watchdog feeding can be understood as the software program clearing the pulse timer and performing other operations within a preset time. However, after the MCU chip enables the watchdog timer, if the aforementioned software program experiences abnormal phenomena such as freezing, but the data in the SRAM has already been cleared and initialized, the system cannot locate and resolve these abnormal phenomena after restarting, resulting in poor device stability.
[0004] Therefore, how to locate and resolve abnormal issues such as software program crashes after a system restart has become an urgent problem to be solved. Summary of the Invention
[0005] This application provides a method, apparatus, and storage medium for handling abnormal resets. It not only solves the problem that abnormal reset information is cleared after SRAM is initialized, but also writes the abnormal reset information into flash memory before it is cleared, which can provide a basis for subsequent abnormal location and resolution.
[0006] Firstly, embodiments of this application provide a method for handling abnormal resets. This method may include: acquiring abnormal reset information after a first chip is reset and before the Static Random Access Memory (SRAM) is initialized; and writing the abnormal reset information into a flash memory using an initialized minimum system, wherein the minimum system runs on the first chip and is a necessary driver for the flash memory. By using the initialized minimum system to write the abnormal reset information into the flash memory, the purpose is not only to activate the flash memory with fewer resources, enabling it to operate normally, but also to ensure that the flash memory, while in operation, retains the abnormal reset information, guaranteeing that the information is not lost even in the event of a power outage, thus ensuring the availability of the abnormal reset information for subsequent troubleshooting and resolution of abnormal reset problems.
[0007] Optionally, in conjunction with the first aspect above, in a first possible implementation, the method further includes: clearing an abnormal reset flag, the abnormal reset flag being used to indicate that the first chip has experienced an abnormal reset; after clearing the abnormal reset flag, sequentially adjusting the state of the system interrupt module, the state of the system real-time clock, the state of the system general-purpose input / output, the state of the flash memory driver, the state of the flash memory, and the state of the file system to their corresponding running states to obtain the initialized minimum system, wherein the system interrupt module, the system real-time clock, and the system general-purpose input / output correspond to the first chip, and the flash memory driver corresponds to the flash memory.
[0008] Optionally, in conjunction with the first aspect or the first possible implementation of the first aspect, in a second possible implementation, the method further includes: setting a header marker for the abnormal reset information, the header marker being used to reflect the abnormal situation of the abnormal reset information. By setting a header marker in the abnormal reset information in the above manner, a fast and convenient method can be provided for subsequently locating and resolving abnormal reset problems.
[0009] Optionally, in conjunction with the first aspect or the first to second possible implementations described above, in the third possible implementation, obtaining the abnormal reset information includes: obtaining the operating state of the first chip; when the operating state of the first chip reflects that an abnormality has occurred in the first chip based on the watchdog reset, obtaining the abnormal reset information.
[0010] Optionally, in conjunction with the first aspect or the first to second possible implementations described above, in the fourth possible implementation, before obtaining the abnormal reset information, the method further includes: determining whether the value of a preset flag bit has changed to a first value, the first value being used to indicate that the current startup state of the first chip has been identified; correspondingly, obtaining the abnormal reset information includes: obtaining the abnormal reset information when the value of the preset flag bit has not changed to the first value.
[0011] Optionally, in combination with the first to fourth possible implementations of the first aspect described above, in the fifth possible implementation, after writing the abnormal reset information into the flash memory, the method further includes: resetting the first chip again based on the system reset processing function.
[0012] Optionally, in conjunction with the first to fourth possible implementations of the first aspect described above, in the sixth possible implementation, after writing the abnormal reset information into the flash memory, the method further includes: triggering the normal system startup process based on the system reset processing function.
[0013] Secondly, embodiments of this application provide an exception handling device, which may include:
[0014] The acquisition unit is used to acquire abnormal reset information after the first chip is reset and before the static random access memory (SRAM) is initialized.
[0015] The writing unit is used to write the abnormal reset information into the flash memory through the initialized minimum system, wherein the minimum system runs on the first chip and is the necessary operating driver for the flash memory.
[0016] Optionally, in conjunction with the second aspect described above, in a first possible implementation, the exception handling apparatus further includes:
[0017] A clearing unit is used to clear the abnormal reset flag, which indicates that the first chip has experienced an abnormal reset.
[0018] An adjustment unit is used to, after clearing the abnormal reset flag, sequentially adjust the states of the system interrupt module, the system real-time clock, the system general-purpose input / output, the flash memory driver, the flash memory, and the file system to their corresponding running states to obtain the initialized minimum system. The system interrupt module, the system real-time clock, and the system general-purpose input / output correspond to the first chip, and the flash memory driver corresponds to the flash memory.
[0019] Optionally, in conjunction with the second aspect or the first possible implementation of the second aspect described above, in the second possible implementation, the exception handling device further includes:
[0020] A setting unit is used to set a header mark for the abnormal reset information, the header mark being used to reflect the abnormal situation of the abnormal reset information.
[0021] Optionally, in conjunction with the second aspect or the first to second possible implementations described above, in a third possible implementation, the acquiring unit includes:
[0022] The first acquisition module is used to acquire the operating status of the first chip;
[0023] The first acquisition module is used to acquire abnormal reset information when the operating state of the first chip is reflected as an abnormality occurring during watchdog reset of the first chip.
[0024] Optionally, in conjunction with the second aspect or the first to second possible implementations of the second aspect, in a fourth possible implementation, the exception handling device further includes:
[0025] The judgment unit is used to determine whether the value of the preset flag bit has changed to a first value before the abnormal reset information is obtained. The first value is used to indicate that the current startup state of the first chip has been identified.
[0026] Correspondingly, the acquisition unit includes:
[0027] The second acquisition module is used to acquire abnormal reset information when the value of the preset flag bit has not changed to the first value.
[0028] Optionally, in conjunction with the first to fourth possible implementations of the second aspect described above, in a fifth possible implementation, the exception handling device further includes:
[0029] The reset unit is used to reset the first chip again based on the system reset processing function after the abnormal reset information is written to the flash memory.
[0030] Optionally, in conjunction with the first to fourth possible implementations of the second aspect described above, in a sixth possible implementation, the exception handling device further includes:
[0031] The triggering unit is used to trigger the normal system startup process based on the system reset processing function after the abnormal reset information is written to the flash memory.
[0032] Thirdly, embodiments of this application provide a computer-readable storage medium including instructions that, when executed on a computer, cause the computer to perform a method as described in the first aspect or any possible implementation thereof.
[0033] Fourthly, embodiments of this application provide a computer program product containing instructions that, when run on a computer, cause the computer to perform a method as described in the first aspect or any possible implementation thereof.
[0034] Fifthly, embodiments of this application provide a chip system including a processor for supporting an exception handling device in implementing the functions involved in the first aspect or any possible implementation thereof. In one possible design, the chip system further includes a memory for storing program instructions and data necessary for an information generation device. This chip system may be composed of chips or may include chips and other discrete devices.
[0035] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:
[0036] In this embodiment, if the first chip experiences an abnormal reset before the SRAM is initialized, the abnormal reset information needs to be acquired first. Then, the necessary operating drivers running on the first chip, which are flash memory, need to be further initialized so that the flash memory is in a basic operating state. This allows the initialized minimum system to write the abnormal reset information into the flash memory. This method not only avoids the abnormal reset information generated when the first chip experiences an abnormal reset before the SRAM is initialized being cleared after SRAM initialization, but also, since SRAM clearing and data initialization are invisible by default, writing the abnormal reset information into the flash memory before it is cleared provides a basis for subsequent abnormal location and resolution. Attached Figure Description
[0037] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application.
[0038] Figure 1 A flowchart of a watchdog reset MCU chip provided in the prior art;
[0039] Figure 2 A schematic diagram of an embodiment of the abnormal reset processing method provided in this application;
[0040] Figure 3A schematic diagram of another embodiment of the abnormal reset processing method provided in this application;
[0041] Figure 4 This is a flowchart of an abnormal reset process provided in an embodiment of this application;
[0042] Figure 5 This is a schematic diagram of the hardware structure of the communication device provided in the embodiments of this application;
[0043] Figure 6 This is a schematic diagram of the structure of an exception handling device provided in an embodiment of this application;
[0044] Figure 7 This is a schematic diagram of another exception handling device provided in an embodiment of this application. Detailed Implementation
[0045] This application provides a method, apparatus, and storage medium for handling abnormal resets. It not only solves the problem that abnormal reset information is cleared after SRAM is initialized, but also writes the abnormal reset information into flash memory before it is cleared, which can provide a basis for subsequent abnormal location and resolution.
[0046] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0047] The technical solutions in this application will now be described with reference to the accompanying drawings.
[0048] Currently, watchdog timer technology can trigger a reset of an MCU chip exhibiting abnormal behavior. The MCU chip initializes the SRAM and clears the data based on its system reset function. After SRAM initialization, the main function runs to enable normal system startup. After normal system startup, the MCU chip enables the watchdog timer and feeds it periodically. However, if the software program freezes or encounters other abnormalities after the watchdog timer is enabled, and the data in the SRAM has already been cleared and initialized, the system cannot locate and resolve these abnormalities after restarting, resulting in poor device stability.
[0049] Therefore, to solve the above-mentioned technical problems, this application provides a method for handling abnormal resets. This method involves acquiring abnormal reset information after a first chip resets but before the SRAM is initialized, and then writing this information into a flash memory based on the initialized minimum system. This ensures that the data is saved in the power-off, non-volatile flash memory before the SRAM is initialized, providing a basis for subsequent abnormal location and resolution. It should be understood that the first chip described above may include, but is not limited to, an MCU chip, a Global Positioning System (GPS) chip, or other main chips including SRAM. Therefore, the abnormal reset handling method described above can be applied to MCU chips, GPS chips, or other main chips including SRAM, and specific applications will not be limited in this application. This application only uses an MCU chip as an example for illustration.
[0050] The following section describes the abnormal reset handling method in this application from a methodological perspective. Please refer to [link / reference needed]. Figure 2 The diagram shown is a schematic representation of an embodiment of the abnormal reset processing method provided in this application. The method may include:
[0051] 201. After the first chip is reset and before the static random access memory (SRAM) is initialized, obtain the abnormal reset information.
[0052] The described abnormal reset information indicates that the first chip experienced an abnormal stuck reset after the initial reset. Therefore, it is necessary to obtain the abnormal reset information before the SRAM in the first chip is initialized, in order to provide a basis for subsequent location and resolution of the abnormal reset problem.
[0053] For example, in some embodiments, the first chip may experience an abnormal reset when the watchdog timer resets it or when the software program fails to recognize the system startup state. Therefore, abnormal reset information can be obtained in the following two ways:
[0054] The first method involves obtaining the operating status of the first chip; when the operating status of the first chip indicates that an abnormality has occurred during the watchdog reset, abnormal reset information is obtained.
[0055] In this embodiment, the operating status of the first chip during operation can reflect its operational state. For example, slow operating speed, power consumption exceeding the normal range, or clock configuration exceeding the chip's main frequency operating range all indicate that the first chip's operational state is abnormal. Furthermore, the first chip's operational state can also reflect an anomaly caused by a watchdog timer reset. In other words, if an abnormal reset occurs during a watchdog timer reset, the abnormal operational state of the first chip is due to this anomaly. Therefore, by acquiring the first chip's operational state, and when the first chip's operational state reflects an anomaly caused by a watchdog timer reset, abnormal reset information can be obtained.
[0056] The second method further includes, before acquiring the abnormal reset information, determining whether the value of a preset flag bit has changed to a first value, wherein the first value is used to indicate that the current startup state of the first chip has been identified; correspondingly, acquiring the abnormal reset information includes acquiring the abnormal reset information when the value of the preset flag bit has not changed to the first value.
[0057] In this embodiment, if the software program cannot recognize the current startup state of the first chip, it indicates that the first chip has also experienced an abnormal reset. Therefore, a preset flag is first set, and the value of this preset flag is used as a criterion to determine whether the current startup state of the first chip is recognized by the software program. If the value of the preset flag does not change to the first value, it indicates that the current startup state of the first chip has not been recognized by the software program, and abnormal reset information can be obtained. Alternatively, it can be understood as determining whether the preset flag is set; if it is not set, it indicates that the current startup state of the first chip has not been recognized by the software program, further indicating that the first chip has experienced an abnormal reset, and abnormal reset information can be obtained.
[0058] It should be understood that the first value described above can be "1", "2", etc., and there is no specific limitation, as long as the first value can be used to indicate that the current startup state of the first chip has been identified. In addition, in practical applications, abnormal reset information can also be obtained based on other methods, which are not limited here.
[0059] Optionally, in other embodiments, the method further includes: setting a header marker for the abnormal reset information, the header marker being used to reflect the abnormal situation of the abnormal reset information.
[0060] In this embodiment, after obtaining abnormal reset information, a header marker can be set for this information. This header marker can reflect the abnormal situation of the abnormal reset, such as the location of the abnormal reset or specific detailed information. By setting a header marker in the abnormal reset information, a fast and convenient method can be provided for subsequent location and resolution of abnormal reset problems.
[0061] 202. Write the abnormal reset information into the flash memory through the initialized minimum system. The minimum system runs on the first chip and is a necessary driver for the operation of the flash memory.
[0062] In this embodiment, the flash memory includes internal storage devices within the first chip and external storage devices, and has the characteristic that data is not lost when power is off. The aforementioned minimum system can be understood as the necessary operating driver running on the first chip and within the flash memory. Writing the abnormal reset information into the flash memory using the initialized minimum system serves not only to activate the flash memory with fewer resources, enabling it to operate normally, but also to ensure that the flash memory, while in operation, retains the abnormal reset information, guaranteeing that it is not lost even during power loss and ensuring its availability for subsequent troubleshooting and resolution of abnormal reset issues.
[0063] For ease of understanding, in the above Figure 2 Based on the described embodiments, please refer to Figure 3 This is a schematic diagram of another embodiment of the abnormal reset processing method provided in this application. The method may include:
[0064] 301. After the first chip is reset and before the static random access memory (SRAM) is initialized, obtain the abnormal reset information.
[0065] In this embodiment, step 301 can refer to the above. Figure 2 The content described in step 201 should be understood, and will not be elaborated here.
[0066] 302. Clear the abnormal reset flag. The abnormal reset flag is used to indicate that an abnormal reset has occurred in the first chip.
[0067] In this embodiment, since the abnormal reset flag can be used to indicate that an abnormal reset has occurred in the first chip, regardless of whether the abnormal reset is due to the above... Figure 2In step 201, whether it is the first type of exception caused by the watchdog resetting the first chip, or the second type of exception caused by the software program being unable to recognize the current startup state of the first chip, the exception reset mark needs to be cleared after obtaining the aforementioned exception reset information. The purpose is to prevent the subsequent initialization of the minimum system and the writing of the exception reset information to the flash memory process when the system is restarted again, so that the exception reset information does not need to be stored multiple times.
[0068] 303. After clearing the abnormal reset flag, the states of the system interrupt module, the system real-time clock, the system general-purpose input / output, the flash memory driver, the flash memory, and the file system are sequentially adjusted to their corresponding running states to obtain the initialized minimum system. The system interrupt module, the system real-time clock, and the system general-purpose input / output correspond to the first chip, and the flash memory driver corresponds to the flash memory.
[0069] In this embodiment, the minimum system can be understood as consisting of a system interrupt module, a system real-time clock (RTC), system general-purpose input / output (GPIO), a flash memory driver, flash memory, and a file system (FS). However, the system interrupt module, system RTC, and GPIO in this minimum system differ depending on the type of first chip. Therefore, by corresponding the system interrupt module, system RTC, and GPIO in the minimum system to the first chip, the minimum system can operate stably on different first chips.
[0070] In addition, after clearing the abnormal reset flag, the states of the system interrupt module, the system real-time clock, the system general-purpose input / output, the flash memory driver, the flash memory itself, and the file system need to be sequentially adjusted to their corresponding running states. This is primarily to initialize the minimal system, enabling it to be activated and thus placed in a running state.
[0071] 304. Write the abnormal reset information into the flash memory through the initialized minimum system.
[0072] In this embodiment, since the file system runs on the first chip and is used to manage data in the flash memory, after obtaining the initial minimal system, abnormal reset information can be written into the flash memory through the initialized minimal system, enabling the file system to manage the abnormal reset information.
[0073] 305. Reset the first chip again based on the system reset processing function.
[0074] It is understandable that after saving the abnormal reset information to the file system in step 304 above, the first chip can be reset again based on the system reset processing function, thereby entering the normal system startup process and restoring the normal operation of the first chip.
[0075] Optionally, 306, trigger the normal system startup process based on the system reset processing function.
[0076] Alternatively, after saving the abnormal reset information to the file system in step 304 above, the normal system startup process can be triggered directly based on the system reset handling function.
[0077] It should be noted that the normal system startup process mentioned above can be understood as follows: the SRAM is initialized based on the system reset function, and the main function is run after the SRAM initialization is completed, so that the system can start normally and restore the normal operation of the first chip.
[0078] Additionally, please see Figure 4 This is a flowchart of an abnormal reset process provided in an embodiment of this application. From... Figure 4 As can be seen, when resetting the first chip based on the system reset processing function, it first determines whether an abnormal reset caused by a watchdog timer reset or an abnormal reset not recognized by the software program has occurred. If an abnormal reset caused by a watchdog timer reset or an abnormal reset not recognized by the software program has occurred, then the abnormal reset information is obtained, and the minimum system is initialized. Then, based on the initialized minimum system, the abnormal reset information is written to the flash memory. Finally, the system reset is performed again, or the normal system startup process is entered. Conversely, if no abnormal reset caused by a watchdog timer reset or an abnormal reset not recognized by the software program has occurred, then the normal system startup process is directly entered.
[0079] from Figure 4 It can also be seen that the initialization of the minimum system described above can be understood as follows: clearing the exception reset flag → initializing the system interrupt module → configuring the system clock → initializing the system real-time clock → initializing the system general-purpose input / output → initializing the flash memory driver → initializing the flash memory → initializing the file system. Among these, initializing the system interrupt module can be understood as registering all system interrupt modules from -14 to -1 as restart interfaces and redirecting the system interrupt vector table to the system interrupt table.
[0080] In addition, writing the abnormal reset information into the flash memory can also be understood as unlocking the file system, then opening the file handle of the abnormal reset information, and writing the abnormal reset information into the file system according to the clock information of the system's real-time clock.
[0081] In this embodiment, the abnormal reset information is written into the flash memory using the initialized minimum system. The purpose is not only to activate the flash memory with fewer resources so that the flash memory can be in a basic normal operating state, but also to ensure that the flash memory in the operating state can save the abnormal reset information, so that the abnormal reset information will not be lost even in the event of power failure, and to ensure the availability of the abnormal reset information when locating and solving the abnormal reset problem.
[0082] The foregoing primarily describes the solutions provided by the embodiments of this application from a methodological perspective. It is understood that the aforementioned exception handling apparatus, in order to achieve the above-described functions, includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, in conjunction with the functions described in the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0083] From the perspective of physical devices, the above-mentioned exception handling device can be an MCU chip or other main chip including SRAM. Specifically, it can be implemented by a single physical device, or by multiple physical devices, or it can be a logical functional unit within a physical device. This application does not specifically limit this.
[0084] For example, the above-mentioned anomaly handling device can be provided by Figure 5 It is implemented using communication devices. Figure 5 This is a schematic diagram of the hardware structure of a communication device provided in an embodiment of this application. The communication device includes at least one processor 501, a memory 502, and an input device 503.
[0085] The processor 501 can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (server IC), or one or more integrated circuits used to control the execution of the program in this application. The processor 501 is capable of determining whether an abnormal reset is caused by a watchdog timer or the software program failing to recognize the current startup state, and writing the abnormal reset information to a flash memory.
[0086] Input device 503, using any transceiver-like device, is used to communicate with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area networks (WLAN), etc. Input device 503 can be connected to processor 501, and can acquire abnormal reset information after the first chip is reset and before the SRAM is initialized.
[0087] Memory 502 may be a non-volatile memory, such as NOR flash or NAND flash, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. Memory 502 may exist independently or may be connected to processor 501. Memory 502 may also be integrated with processor 501. This memory 502 is capable of storing abnormal reset information.
[0088] The memory 502 stores computer execution instructions for implementing the scheme of this application, and its execution is controlled by the processor 501. The processor 501 executes the computer execution instructions stored in the memory 502, thereby implementing the abnormal reset processing method provided in the above-described method embodiments of this application.
[0089] In one possible implementation, the computer execution instructions in the embodiments of this application may also be referred to as application code, and the embodiments of this application do not specifically limit this.
[0090] In a specific implementation, as one example, the processor 501 may include one or more CPUs, for example... Figure 5 CPU0 and CPU1 in the CPU.
[0091] From the perspective of functional units, this application can divide the exception handling device into functional units according to the above method embodiments. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one functional unit. The integrated functional unit can be implemented in hardware or in software.
[0092] For example, when dividing the functional units using an integrated approach. Figure 6 A schematic diagram of an exception handling device provided in an embodiment of this application is shown. Figure 6 As shown, one embodiment of the exception handling apparatus 60 of this application may include:
[0093] The acquisition unit 601 is used to acquire abnormal reset information after the first chip is reset and before the static random access memory (SRAM) is initialized.
[0094] The writing unit 602 is used to write the abnormal reset information into the flash memory through the initialized minimum system, wherein the minimum system runs on the first chip and is the necessary operating driver for the flash memory.
[0095] Optionally, in the above Figure 6 Based on the described embodiments, Figure 7 A schematic diagram of another exception handling device provided in an embodiment of this application is shown. Figure 7 As shown, the exception handling apparatus 60 of this application may further include:
[0096] Clearing unit 603 is used to clear the abnormal reset mark, which is used to indicate that the first chip has experienced an abnormal reset;
[0097] The adjustment unit 604 is used to adjust the state of the system interrupt module, the state of the system real-time clock, the state of the system general-purpose input / output, the state of the flash memory driver, the state of the flash memory, and the state of the file system to the corresponding running states after clearing the abnormal reset flag, so as to obtain the initialized minimum system. The system interrupt module, the system real-time clock, and the system general-purpose input / output correspond to the first chip, and the flash memory driver corresponds to the flash memory.
[0098] In some embodiments of this application, the exception handling device 60 further includes: a setting unit, used to set a header mark for the exception reset information, the header mark being used to reflect the exception situation of the exception reset information.
[0099] In some embodiments of this application, the acquisition unit 601 includes: a first acquisition module, configured to acquire the operating state of the first chip; the first acquisition module is configured to acquire abnormal reset information when the operating state of the first chip reflects an abnormality in the first chip based on watchdog reset.
[0100] In some embodiments of this application, the exception handling device 60 further includes: a judgment unit, configured to determine whether the value of a preset flag bit has changed to a first value before acquiring the exception reset information, the first value being used to indicate that the current startup state of the first chip has been identified; correspondingly, the acquisition unit 601 includes: a second acquisition module, configured to acquire the exception reset information when the value of the preset flag bit has not changed to the first value.
[0101] In some embodiments of this application, the exception handling device 60 further includes a reset unit, configured to reset the first chip again based on a system reset processing function after writing the exception reset information into the flash memory.
[0102] In some embodiments of this application, the exception handling device 60 further includes a triggering unit, configured to trigger a normal system startup process based on a system reset processing function after the exception reset information is written to the flash memory. The exception handling device provided in this application embodiment is used to execute... Figures 2-4 The methods in the corresponding method embodiments are as follows, therefore the embodiments of this application can be referred to. Figures 2-4 The relevant parts of the corresponding method embodiments should be understood.
[0103] In this embodiment, the exception handling device is presented as an integrated unit divided into various functional units. Here, "functional unit" can refer to an application-specific integrated circuit (ASIC), a processor and memory executing one or more software or firmware programs, integrated logic circuits, and / or other devices that can provide the aforementioned functions. In a simple embodiment, those skilled in the art will understand that the display device can employ... Figure 5 As shown in the figure.
[0104] for example, Figure 5 The processor 501 can cause the display device to execute computer execution instructions stored in the memory 502. Figures 2-4 The method executed by the exception handling device in the corresponding method embodiment.
[0105] Specifically, Figure 6 The write unit 602 in the middle, Figure 7 The functions / implementation process of the clearing unit 603, adjustment unit 604, setting unit, judgment unit, reset unit, and trigger unit can be achieved through... Figure 5 The processor 501 in the memory 502 calls the computer execution instructions stored in the memory to achieve this.
[0106] Figure 6 The function / implementation process of the acquisition unit 601 can be achieved through... Figure 5 This is achieved through the input device 503.
[0107] In this application Figure 5The various components in the device are communicatively connected, that is, the processing unit (or processor), storage unit (or memory), and transceiver unit (transceiver) communicate with each other through internal connection paths to transmit control and / or data signals. The above-described method embodiments of this application can be applied to a processor, or the steps of the above-described method embodiments can be implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above-described method embodiments can be completed by the integrated logic circuit in the processor or by instructions in the form of software. The processor mentioned above may be a central processing unit (CPU), a network processor (NP) or a combination of CPU and NP, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in this application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in this application can be directly manifested as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules within the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the aforementioned method. Although only one processor is shown in the figure, the device may include multiple processors or the processor may include multiple processing units. Specifically, the processor can be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor.
[0108] Memory is used to store computer instructions executed by the processor. Memory can be non-volatile memory. Non-volatile memory can be read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, or flash memory. Memory can be independent of the processor or can be a storage unit within the processor; this is not limited here. Although only one memory is shown in the figure, the device may include multiple memories or the memory may include multiple storage units.
[0109] A transceiver is used to enable content interaction between the processor and other units or network elements. Specifically, the transceiver can be a communication interface of the device, a transceiver circuit or communication unit, or a transceiver transceiver. The transceiver can also be the processor's communication interface or transceiver circuit. Optionally, the transceiver can be a transceiver chip. The transceiver can also include a transmitting unit and / or a receiving unit. In one possible implementation, the transceiver can include at least one communication interface. In another possible implementation, the transceiver can also be a unit implemented in software. In various embodiments of this application, the processor can interact with other units or network elements through the transceiver. For example, the processor can acquire or receive content from other network elements through the transceiver. If the processor and the transceiver are physically separate components, the processor can interact with other units of the device without going through the transceiver.
[0110] In one possible implementation, the processor, memory, and transceiver can be interconnected via a bus. This bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, among others. The bus can be categorized as an address bus, data bus, control bus, etc.
[0111] In this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being better or more advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.
[0112] In the various embodiments of this application, numerous examples have been provided for ease of understanding. However, these examples are merely illustrations and do not imply the best way to implement this application.
[0113] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, they can be implemented in whole or in part in the form of a computer program product.
[0114] A computer program product includes one or more computer instructions. When these computer instructions are loaded and executed on a computer, they generate, in whole or in part, the processes or functions according to embodiments of this application. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).
[0115] The technical solutions provided in this application have been described in detail above. Specific examples have been used in this application to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A method for handling abnormal reset, characterized in that, include: After the first chip is reset and before the static random access memory (SRAM) is initialized, abnormal reset information is obtained, which is used to indicate that the first chip has experienced an abnormal stuck reset after the reset. The abnormal reset information is written to the flash memory through the initialized minimum system, wherein the minimum system consists of a system interrupt module, a system real-time clock, a system general-purpose input / output, a flash memory driver, a flash memory, and a file system; After writing the abnormal reset information into the flash memory, the first chip is reset again based on the system reset processing function.
2. The method according to claim 1, characterized in that, The method further includes: Clear the abnormal reset flag, which is used to indicate that the first chip has experienced an abnormal reset; After clearing the abnormal reset flag, the states of the system interrupt module, the system real-time clock, the system general-purpose input / output, the flash memory driver, the flash memory, and the file system are sequentially adjusted to their corresponding running states to obtain the initialized minimum system. The system interrupt module, the system real-time clock, and the system general-purpose input / output correspond to the first chip, and the flash memory driver corresponds to the flash memory.
3. The method according to claim 1 or 2, characterized in that, The method further includes: A header marker is set for the abnormal reset information, and the header marker is used to reflect the abnormal situation of the abnormal reset information.
4. The method according to any one of claims 1-2, characterized in that, The acquisition of abnormal reset information includes: Obtain the operating status of the first chip; When the operating status of the first chip is reflected as an abnormality occurring when the first chip is reset based on a watchdog timer, abnormal reset information is obtained.
5. The method according to any one of claims 1-2, characterized in that, Before obtaining the abnormal reset information, the method further includes: Determine whether the value of the preset flag bit has changed to the first value, the first value being used to indicate that the current startup state of the first chip has been identified; Correspondingly, obtaining the abnormal reset information includes: When the value of the preset flag bit is not changed to the first value, abnormal reset information is obtained.
6. The method according to any one of claims 1-2, characterized in that, After writing the abnormal reset information into the flash memory, the method further includes: The system's normal startup process is triggered based on the system reset handling function.
7. An anomaly handling device, characterized in that, include: The acquisition unit is used to acquire abnormal reset information after the first chip is reset and before the static random access memory (SRAM) is initialized. The abnormal reset information is used to indicate that the first chip has experienced an abnormal stuck reset after being reset. The write unit is used to write the abnormal reset information into the flash memory through the initialized minimum system, wherein the minimum system consists of a system interrupt module, a system real-time clock, a system general-purpose input / output, a flash memory driver, a flash memory, and a file system; The anomaly handling device further includes: The reset unit is used to reset the first chip again based on the system reset processing function after the abnormal reset information is written to the flash memory.
8. The anomaly handling device according to claim 7, characterized in that, The anomaly handling device further includes: A clearing unit is used to clear the abnormal reset flag, which indicates that the first chip has experienced an abnormal reset. An adjustment unit is used to, after clearing the abnormal reset flag, sequentially adjust the states of the system interrupt module, the system real-time clock, the system general-purpose input / output, the flash memory driver, the flash memory, and the file system to their corresponding running states to obtain the initialized minimum system. The system interrupt module, the system real-time clock, and the system general-purpose input / output correspond to the first chip, and the flash memory driver corresponds to the flash memory.
9. The anomaly handling device according to claim 7 or 8, characterized in that, The anomaly handling device further includes: A setting unit is used to set a header mark for the abnormal reset information, the header mark being used to reflect the abnormal situation of the abnormal reset information.
10. The anomaly handling apparatus according to any one of claims 7-8, characterized in that, The acquisition unit includes: The first acquisition module is used to acquire the operating status of the first chip; The first acquisition module is used to acquire abnormal reset information when the operating state of the first chip is reflected as an abnormality occurring during watchdog reset of the first chip.
11. The anomaly handling apparatus according to any one of claims 7-8, characterized in that, The anomaly handling device further includes: The judgment unit is used to determine whether the value of the preset flag bit has changed to a first value before the abnormal reset information is obtained. The first value is used to indicate that the current startup state of the first chip has been identified. Correspondingly, the acquisition unit includes: The second acquisition module is used to acquire abnormal reset information when the value of the preset flag bit has not changed to the first value.
12. The anomaly handling apparatus according to any one of claims 7-8, characterized in that, The anomaly handling device further includes: The triggering unit is used to trigger the normal system startup process based on the system reset processing function after the abnormal reset information is written to the flash memory.
13. An anomaly handling device, characterized in that, include: Processor, memory; The processor and the memory communicate with each other; The memory is used to store instructions; The processor is configured to execute the instructions in the memory, performing the method as described in any one of claims 1-6.
14. A computer-readable storage medium comprising instructions that, when executed on a computer, cause the computer to perform the method as claimed in any one of claims 1 to 6.