Combo driving structure adapting cphy and dphy

Abstract

The application discloses a Combo driving structure adapting to CPHY and DPHY, relates to the technical field of integrated circuits, and switches between CPHY mode and DPHY mode through driving control mode selection signals by configuring a unified Combo type driving architecture, so that the output of CPHY specifications and DPHY specifications can be met respectively only by using one set of driving structures, circuit scale is effectively inhibited, and chip area and power consumption are reduced; in the CPHY mode, the same power supply voltage is not subjected to voltage reduction processing, a voltage attenuator is added to the output end to meet the low-voltage output requirement in the DPHY mode; a reference resistance compensation structure is added, automatic adjustment and compensation of the reference resistance are realized when ZOS is adjusted, side effects caused by the introduction of the voltage attenuator are avoided, the precision of impedance adjustment is improved, and ideal impedance values are approached as much as possible.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a Combo driver structure adapted to CPHY and DPHY. Background Technology

[0002] In modern integrated circuit interface design, the combo PHY design, which can simultaneously adapt to both CPHY and DPHY specifications, is currently the advanced design direction due to the following three advantages:

[0003] From the user's perspective:

[0004] 1. It is compatible with the existing old DPHY interface ecosystem.

[0005] 2. It allows for flexible selection of bandwidth and power consumption (CPHY / DPHY optional) within a single hardware setup, supporting diverse applications.

[0006] For the development team:

[0007] 3. A single multi-mode chip (supporting CPHY / DPHY modes) can meet the needs of multiple users, effectively reducing R&D and BOM costs.

[0008] The key to combo PHY design lies in how to achieve the output of a single chip that meets the requirements of both CPHY and DPHY specifications. Since CPHY specification design is more complex, it is usually necessary to first design a circuit that meets the CPHY specification, and then perform compatibility adjustments to match the DPHY specification.

[0009] However, when CPHY and DPHY specifications are integrated, in the HS transmission mode of the PHY, the output requirements of both CPHY and DPHY specifications must meet the following two specifications: 1. DC specification of VOHHS (maximum output voltage in HS mode): 425mV for CPHY specifications and 360mV for DPHY specifications. 2. AC specification of ZOS (single-ended impedance of the driver): Ideally, it should be 50Ω for both CPHY and DPHY specifications.

[0010] In implementing a combo PHY and achieving the two aforementioned metrics, existing technologies suffer from the following problems: CPHY and DPHY modes each have their own dedicated driver structures to meet different output specifications, resulting in large chip area and high power consumption. It is difficult to implement a combo PHY using the same driver for both CPHY and DPHY (smaller area and lower cost). Summary of the Invention

[0011] The technical problem this invention aims to solve is how to integrate CPHY and DPHY under the output requirements of CPHY and DPHY specifications. The goal is to provide a Combo driver structure that adapts to both CPHY and DPHY. By configuring a unified Combo driver architecture that switches between CPHY and DPHY modes after selecting a drive control mode signal, only one driver structure is needed to meet the output requirements of both CPHY and DPHY specifications, effectively reducing circuit size, chip area, and power consumption. In CPHY mode, without voltage reduction processing, a voltage attenuator is added to the output to meet the low-voltage output requirements of DPHY mode under the same power supply voltage. A reference resistor compensation structure is added to automatically adjust and compensate the reference resistor when adjusting ZOS, avoiding the side effects of introducing a voltage attenuator and improving the accuracy of impedance adjustment to approach the ideal impedance value as closely as possible.

[0012] This invention is achieved through the following technical solution:

[0013] This invention provides a Combo driver structure adapted to CPHY and DPHY, comprising the following specific steps:

[0014] A unified Combo-type driver architecture is configured to switch between CPHY and DPHY modes after selecting a signal through the driver control mode.

[0015] The unified Combo-type drive architecture includes: a drive unit control module, a drive module, and an impedance adjustment module. The drive unit control module controls the drive module based on the impedance output by the impedance adjustment module.

[0016] The driving module includes:

[0017] Multiple parallel drive units and voltage attenuators set at the output of multiple parallel drive units, responsible for pulling the output low in DPHY mode;

[0018] The impedance adjustment module includes:

[0019] Impedance-adjustable comparator, external circuit equivalent resistance, and compensated adjustable reference resistor;

[0020] The equivalent resistance of the external circuit is switched between being connected to ground or to a power supply via signal control.

[0021] One end of the impedance adjustment comparator is connected to the output terminal of the drive module and the equivalent resistance of the external circuit, and the other end is connected to the compensated adjustable reference resistor. The output terminal of the impedance adjustment comparator outputs an impedance adjustment signal to the drive unit control module.

[0022] The driving unit control module:

[0023] Used to receive impedance adjustment signals, and control the number of switches of the drive unit of the drive module according to the impedance adjustment signals.

[0024] Furthermore, the impedance adjustment comparator includes:

[0025] Reference voltage source;

[0026] A MOSFET switch, the drain of which is connected to the reference voltage source, and the gate of which receives a cutoff control signal to keep the MOSFET switch in the off state.

[0027] A compensation resistor, one end of which is connected to the source of the MOSFET switch and the other end of which is connected to the drain of the MOSFET switch, so that the switch can control whether it is short-circuited.

[0028] The first sliding resistor has its upper end connected to the other end of the compensation resistor, and the sliding end serves as a voltage divider output node.

[0029] The second sliding resistor has its upper end connected in series with the lower end of the first adjustable resistor, and its lower end is grounded. The sliding end is used to fine-tune the output ratio.

[0030] Furthermore, when the unified Combo-type drive architecture selects the CPHY impedance adjustment mode signal through the drive control mode:

[0031] Keep the voltage attenuator off and the compensation resistor off;

[0032] Impedance calibration is performed on the high potential H, medium potential M, and low potential L of the CPHY mode respectively. By adjusting the number of PMOS and NMOS switches in the driving unit, the output impedance of each potential is matched with the target impedance value.

[0033] The number of drive unit switches after calibration at the three potentials (high potential H, medium potential M, and low potential L) is recorded and locked as a calibration code.

[0034] End calibration and switch to CPHY output mode.

[0035] Furthermore, when the CPHY mode is at a high potential H:

[0036] Adjust the PMOS transistor to be turned on and the NMOS transistor to be turned off. Configure an external circuit equivalent resistor between the ground terminal and the impedance adjustment comparator. Adjust the first sliding resistor and the second sliding resistor according to the equivalent resistor value. The ratio of the first sliding resistor value to the second sliding resistor value is 1:3.

[0037] Continue until the output impedance reaches the target impedance value, then store the H potential calibration code.

[0038] Furthermore, when the CPHY mode is at a low potential L:

[0039] Adjust the PMOS transistor to be off and the NMOS transistor to be on. Configure an external circuit equivalent resistor between the power supply and the impedance adjustment comparator. Adjust the first sliding resistor and the second sliding resistor. The ratio of the first sliding resistor value to the second sliding resistor value is 3:1.

[0040] Continue until the output impedance reaches the target impedance value, then store the L potential calibration code.

[0041] Furthermore, when the CPHY mode is at a high potential H:

[0042] The transmission unit is configured to the M potential state, and the PMOS and NMOS transistors are turned on simultaneously. The initial conduction ratio of the PMOS and NMOS is calculated based on the H potential calibration code and the L potential calibration code. An external circuit equivalent resistance is configured between the ground terminal and the impedance adjustment comparator. The first sliding resistor and the second sliding resistor are adjusted according to the equivalent resistance value. The ratio of the first sliding resistor value to the second sliding resistor value is 1:1.

[0043] Continue until the output impedance reaches the target impedance value, then store the M-potential calibration code.

[0044] Furthermore, the output impedance is:

[0045] ;

[0046] in, This represents the output impedance of a single driver unit. This represents the output impedance of the entire driver module. Indicates the number of parallel drives for the Unit. Indicates the process variation factor. This represents the voltage variation factor. This represents the temperature change factor.

[0047] Furthermore, when the unified Combo type drive architecture selects the DPHY impedance adjustment mode signal through the drive control mode:

[0048] During the calibration phase of driving the output high potential H, the voltage attenuator and the compensation resistor are turned on, and the number of on switches of the driving unit is adjusted so that the output impedance of the H potential matches the target impedance value.

[0049] During the calibration phase of driving the output low potential L, the voltage attenuator is kept on and the compensation resistor is closed, and the number of on / off switches of the driving unit is adjusted so that the output impedance of the L potential matches the target impedance value.

[0050] The number of drive unit switches after calibration of the H and L potentials is recorded and locked as a calibration code;

[0051] End calibration and switch to DPHY output mode.

[0052] Furthermore, when the output is at a low potential L, the NMOS is pulled down to keep the PMOS off and the NMOS on. The pull-down resistor is composed of the drive resistor and the voltage attenuator resistor connected in parallel, satisfying the following:

[0053] ;

[0054] Based on the pull-down resistor value, determine the overall output impedance of the voltage attenuator and the driver unit;

[0055] Adjust the driving resistor according to the number of driving units activated to perform impedance regulation;

[0056] When the output is at a high potential H, the PMOS transistor is pulled up to keep it on and the NMOS transistor off. The pull-up resistor is also a pull-down resistor, which is formed by connecting the drive resistor and the equivalent resistance of the external circuit in parallel, and then connecting them in parallel with the voltage attenuator resistor, satisfying the following conditions:

[0057] ;

[0058] In the pull-up state, by connecting a compensation resistor and a corresponding switching MOSFET in series between the sliding resistor and the power supply, the pull-down impedance that is reduced due to the addition of the voltage attenuator resistor is compensated.

[0059] in, Indicates pull-down resistor. This represents the equivalent resistance of the external circuit. Indicates pull-down resistor. This indicates the voltage attenuator resistor.

[0060] Furthermore, the compensation for the reduced pull-down impedance due to the incorporation of the voltage attenuator resistor includes:

[0061] ;

[0062] in, This represents the total resistance of the sliding rheostat. This is the total resistance when the driver is pulled up. The resistance value of the voltage attenuator. This represents the output impedance of the entire drive module.

[0063] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0064] This design achieves a shared drive structure for both CPHY and DPHY, reducing chip size and controlling or even lowering total static power consumption. Functionally, on one hand, a voltage attenuator is introduced at the output to meet the low-voltage output requirements of DPHY mode while maintaining the same power supply voltage as CPHY mode (without voltage reduction). On the other hand, based on the impedance adjustment mode with a reference resistor compensation structure, ZOS self-adjustment is achieved while avoiding the side effects of introducing a voltage attenuator. Furthermore, it offsets impedance deviations caused by PVT changes, better meeting industry-standard ZOS output impedance and improving chip yield in production.

[0065] The shared driver between CPHY and DPHY significantly reduces the size of the driver circuit, meaning a smaller chip area and an increased number of chips produced from a single wafer, directly lowering the manufacturing cost per chip. Smaller chip areas mean a lower probability of encountering fatal defects, resulting in higher yields, which further reduce costs. Additionally, smaller chips require smaller packages and less packaging material, reducing the complexity and cost of packaging processes. Testing time may also be slightly reduced due to the smaller chip size.

[0066] The reduction in chip size frees up space for more other functions. For example, in mobile devices and smart wearable devices, motherboard space is extremely precious. With a smaller chip size, a larger battery can be placed, functional modules that originally needed to be external can be integrated, or the device can be made lighter and thinner, which undoubtedly gives it greater market competitiveness compared to its competitors.

[0067] Smaller chip size means shorter internal interconnects, which reduces signal transmission delay and mutual interference, and improves the stability and reliability of the chip's internal operation. Attached Figure Description

[0068] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:

[0069] Figure 1 This is the technical approach in the embodiments of the present invention, which controls different drivers to output in CPHY and DPHY modes respectively;

[0070] Figure 2 This is the technical approach of integrating CPHY and DPHY into a unified COMBO type driver in the embodiments of the present invention;

[0071] Figure 3 This is a schematic diagram of the combo-type drive structure in an embodiment of the present invention;

[0072] Figure 4 This is a flowchart illustrating the workflow of the combo-type drive structure in an embodiment of the present invention.

[0073] Figure 5 This is a static schematic diagram of impedance adjustment in an embodiment of the present invention;

[0074] Figure 6 This is a schematic diagram of the L-potential impedance adjustment in CPHY mode according to an embodiment of the present invention;

[0075] Figure 7 This is a schematic diagram of the CPHY mode H potential impedance adjustment in an embodiment of the present invention;

[0076] Figure 8 This is a schematic diagram of the M-potential impedance adjustment in CPHY mode according to an embodiment of the present invention;

[0077] Figure 9 This is a schematic diagram of the CPHY transmission mode in an embodiment of the present invention;

[0078] Figure 10 This is a schematic diagram of the voltage attenuator operation in an embodiment of the present invention;

[0079] Figure 11 This is a schematic diagram of the L-potential impedance adjustment in DPHY mode according to an embodiment of the present invention;

[0080] Figure 12 This is a schematic diagram of the DPHY mode H potential impedance adjustment in an embodiment of the present invention;

[0081] Figure 13 This is a schematic diagram of the DPHY transmission mode in an embodiment of the present invention. Detailed Implementation

[0082] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of this invention are only for explaining this invention and are not intended to limit this invention.

[0083] like Figure 1 As shown, in the existing technology, CPHY and DPHY each have separate drivers, and are powered by the high-voltage power supply of CPHY and the low-voltage power supply of DPHY respectively, all connected to the same output PAD. When the circuit needs to output, the data is first input to the driver control module, which then switches modes according to the input, controlling different drivers to output in CPHY and DPHY modes respectively.

[0084] As one possible implementation method, such as Figure 2 As shown, this embodiment provides a Combo driver structure adapted to CPHY and DPHY. Under the technology proposed herein, CPHY and DPHY are integrated into a unified COMBO driver, using the same high-voltage power supply. The output flow remains unchanged, and the control module does not need to control the two drivers separately, effectively reducing circuit size, chip area, and power consumption.

[0085] like Figure 3 As shown, the main body of this embodiment consists of three parts: a driving module, an impedance adjustment module, and a driving unit control module. The output terminal is directly connected to the PAD.

[0086] The drive module consists of multiple drive units connected in parallel and a voltage attenuator responsible for pulling the output low in DPHY mode. The number of drive units is controlled by the drive unit control module on the left.

[0087] The impedance adjustment module consists of an impedance adjustment comparator, an external circuit equivalent resistor to simulate an external resistance, and a compensated adjustable reference resistor as a calibration reference source. The external circuit equivalent resistor can be switched between being connected to ground or to a power supply. One end of the comparator is connected to the output of the drive module and the external circuit equivalent resistor, while the other end is connected to the compensated adjustable reference resistor. By comparing the voltages at the two input terminals, an impedance adjustment signal is output to the drive unit control module, which adjusts the number of switches in the drive unit, thereby regulating the output impedance.

[0088] The driver unit control module is responsible for processing the input signal and controlling the driver output. It is also responsible for receiving feedback signals from the impedance adjustment comparator during impedance adjustment and controlling the number of driver units that are enabled.

[0089] In CPHY output mode, three of the aforementioned drive systems constitute a complete Trio. The decoder input signal is sent to the control module to control the Trio output. In DPHY output mode, two of the aforementioned drive systems constitute a complete Lane. The decoder input signal is sent to the control module to control the Lane output.

[0090] Since the combo-type drive structure described in this paper was initially developed based on the CPHY specification and then adjusted for compatibility with the DPHY specification, a voltage attenuator that pulls the output low in DPHY mode was introduced at the output of the drive module. Furthermore, to address the issue of the reference resistor being affected by the voltage attenuator, a compensation function was added at the reference resistor. The voltage attenuator and compensation function are only activated in DPHY mode.

[0091] like Figure 4 As shown, after power-on, the operating modes of CPHY and DPHY are selected first, and then each enters the impedance adjustment mode.

[0092] In CPHY impedance adjustment mode, the control module will uniformly control the voltage attenuator to turn off and the compensation resistor to turn off. Then, it will perform impedance calibration on the three potentials H, M and L of the CPHY specification respectively, record the number of switches of the drive unit after the three potentials are calibrated and lock them, and then end the calibration and enter CPHY output mode.

[0093] In DPHY impedance adjustment mode, the control module sequentially calibrates the impedance of both H and L potentials according to the DPHY specification. During H potential calibration (i.e., when the drive output is High), the voltage attenuator and compensation resistor are activated. During L potential calibration (i.e., when the drive output is Low), the voltage attenuator is activated, and the compensation resistor is deactivated. The on / off count of the drive unit after calibration for each potential is recorded and locked. Then, the calibration ends, and the system enters DPHY output mode.

[0094] like Figure 5 As shown, both CPHY and DPHY modes require ensuring that the ZOS impedance characteristics meet their respective protocol requirements, which necessitates adjusting the ZOS via the circuit shown in the diagram.

[0095] For CPHY mode, the current drive structure is designed with CPHY specifications in mind, so the voltage attenuator and sliding resistor compensation functions are not required and can be considered as R and compensation resistor Rcp being off in the diagram. With this circuit structure, adjusting the output impedance of the H, M, and L output potentials to the ideal 50Ω will activate the output mode.

[0096] For the DPHY, since it shares a drive structure with the CPHY and the power supply voltage is also the high voltage of the CPHY, the voltage attenuator and the compensation function of the sliding resistor will be activated in DPHY mode. This can be considered as Ratt and the compensation resistor Rcp being turned on in the diagram. With this circuit structure, adjusting the output impedance of the single-ended signal to the ideal 50Ω will activate the output mode.

[0097] like Figure 6 As shown, the impedance adjustment of the L potential in CPHY mode is as follows: When the L potential is output, the NMOS is pulled down, the PMOS is cut off, and the NMOS is turned on. An external circuit equivalent resistor with a resistance of 150Ω is configured between the power supply and the comparator. At the same time, the sliding rheostat is switched to the 150Ω:50Ω range.

[0098] Based on the voltage divider relationship, if the voltages across the comparator are the same, it indicates that the overall output impedance of the driver meets the 50Ω requirement. If the voltage at the driver output is less than the reference voltage, it indicates that the driver impedance is too low, and vice versa. The comparator output signal is then fed back to the control module to scan and switch the number of activated driver units until the voltages are the same, reaching the ideal value.

[0099] At this point, the impedance ZOS calculation formula for this type of drive, considering the P (process) V (voltage) T (temperature) deviation, can be regarded as:

[0100] ;

[0101] in, This represents the output impedance of a single driver unit. This represents the output impedance of the entire driver module. Indicates the number of parallel drives for the Unit. Indicates the process variation factor. This represents the voltage variation factor. This represents the temperature change factor.

[0102] like Figure 7 As shown, this is the CPHY mode _H potential impedance adjustment:

[0103] When the output potential H is reached, the PMOS is pulled up, the PMOS is turned on, and the NMOS is turned off. An external circuit equivalent resistance of 150Ω is configured between the ground terminal and the comparator, and the sliding rheostat is switched to the 50Ω:150Ω range.

[0104] Based on the voltage divider relationship, if the voltages across the comparator are the same, it indicates that the overall output impedance of the driver meets the 50Ω requirement. If the voltage at the driver output is less than the reference voltage, it indicates that the driver impedance is too low, and vice versa. The comparator output signal is then fed back to the control module to scan and switch the number of activated driver units until the voltages are the same, reaching the ideal value.

[0105] like Figure 8 As shown, the impedance adjustment of the M potential in CPHY mode is as follows: When the output M potential is reached, the PMOS pull-up and NMOS pull-down are activated simultaneously, the PMOS is turned on, and the NMOS is also turned on. External circuit equivalent resistors are configured between the power supply and the comparator, and between the ground terminal and the comparator, respectively. The ideal resistance value is 100Ω. At the same time, the sliding rheostat is switched to the 100Ω:100Ω range.

[0106] Based on the voltage divider relationship, if the voltages across the comparator are the same, it indicates that the overall output impedance of the driver meets the 50Ω requirement. If the voltage at the driver output is less than the reference voltage, it indicates that the driver impedance is too low, and vice versa. The comparator output signal is then fed back to the control module to scan and switch the number of activated driver units until the voltages are the same, reaching the ideal value.

[0107] like Figure 9 The diagram shows a schematic of CPHY mode transmission. In CPHY mode, three drivers form a group. Each driver adjusts the conduction and cutoff of the PMOS and NMOS to create the required H, M, and L potentials for CPHY, and the output impedance is adjusted to 50Ω. In operation, based on the standard MIPI RX receiver model, the current flow is represented by two gray dashed lines in the diagram, and the current in both paths is equal. The operating states of each driver in CPHY mode transmission are as follows:

[0108] Driven by the output potential H: PMOS is turned on, NMOS is turned off, and according to the voltage division relationship of the resistor, the output is 3 / 4 of the power supply voltage.

[0109] Driven by the output potential M: PMOS is turned on, and NMOS is also turned on. At this time, the impedance of the PMOS transistor path and the NMOS transistor are the same, about 100Ω. According to the voltage division relationship of the resistor, the output is 1 / 2 power supply voltage.

[0110] The output voltage L is driven by C: PMOS is cut off and NMOS is turned on. According to the voltage division relationship of the resistor, 1 / 4 of the power supply voltage is output.

[0111] The power supply voltage is 0.47V, and the voltages of H, M, and L are 0.3525V, 0.235V, and 0.1175V, respectively.

[0112] As mentioned above, the DC specification VOHHS (maximum output voltage in HS mode) is observed to be 425mV in CPHY mode and 360mV in DPHY mode.

[0113] In integrated circuit design, the impact of PVT (Power Transmission Threshold) must be considered, so a design margin must be left for the maximum output voltage during circuit design. When we set the ideal output value of DPHY mode to around 330mV (30mV margin), since two specifications need to be met in the same circuit, according to the voltage division relationship of the current circuit, the power supply voltage should be 440mV. Under DPHY, when the gate is set to 0V to ground, the PMOS Vgs = power supply voltage = 440mV. At this voltage, most low-voltage PMOS transistors using various processes struggle to operate in the saturation region. At this point, the PMOS Ron will be extremely unstable due to the influence of PVT, making it difficult to meet the impedance ZOS design requirements.

[0114] Therefore, the solution is to add a voltage attenuator that operates only in DPHY mode at the drive output. This can ensure the Vgs of the PMOS at the same higher supply voltage as the CPHY, while also meeting the VOHHS specification of the DPHY.

[0115] like Figure 10 As shown, a voltage attenuator controllable by a switch is connected to the output of the driver. The main structure of this voltage attenuator is a multi-position resistor, with the number of positions equal to the number of driver units (N) in a single driver. Its SW switch, like the driver unit, is controlled by the control signal output from the driver unit control module. Upon startup, the resistance value is in a fixed ratio to the driver resistance Rdrv, with the resistance value being Ratt. Through voltage division, the amplitude of the output voltage can be reduced proportionally. Simultaneously, Rdrv is also affected by the addition of Ratt. Furthermore, due to the addition of the voltage attenuator in DPHY mode, the voltage division ratio of the driver resistor will deviate during impedance adjustment, thus affecting the reference voltage. Therefore, a compensation function is added to the sliding rheostat providing the reference voltage.

[0116] like Figure 11 As shown, this is the DPHY mode_L potential impedance adjustment:

[0117] When the output potential L is reached, the NMOS pulls the circuit down, the PMOS is cut off, and the NMOS is turned on. However, the actual pull-down resistance Rdn changes due to the addition of [something], and the ratio of the pull-down resistance to the impedance of the external circuit is:

[0118] ;

[0119] During calibration, the pull-down impedance is considered as the overall impedance of the voltage attenuator and the driver as the output impedance. Since the driver impedance can be adjusted according to the number of activated driver units, the comparator can perform impedance adjustment normally and its function will not be affected by the addition. Only the number of activated units needs to be changed to adjust the driver impedance to the ideal value.

[0120] like Figure 12 As shown, the impedance adjustment for the H potential in DPHY mode is as follows: When the output H potential is reached, the PMOS is pulled up, turning on the PMOS and turning off the NMOS. At this point, compensation resistors are not considered. So, with the pull-up added, the actual pull-down resistor... because It was incorporated and changed. The pull-up can be seen as only... Let the total pull-down resistance be... The ratio of the two sides is:

[0121] ;

[0122] in, Indicates pull-down resistor. This represents the equivalent resistance of the external circuit. Indicates pull-down resistor. This indicates the voltage attenuator resistor.

[0123] Since the equivalent resistance of the external circuit is a fixed value of 150Ω, it is connected in parallel. Afterwards, the pull-down impedance will be less than 150Ω. Adjust it according to the 1:3 resistance ratio provided by the sliding rheostat. If so, it will lead to The value is too small. Therefore, to address this issue, an additional compensation resistor needs to be connected between the sliding resistor and the power supply. With the corresponding SW MOS transistor.

[0124] When the DPHY is in pull-up state, the SW MOSFET is cut off. Connected in series with the upper end of the sliding resistor, the reference voltage output of the sliding rheostat is raised, and feedback is used to... It increases in size to compensate for the decrease in size. In the DPHY pull-down state, then... The tube is conducting, but no current is flowing through it. No compensation will be provided.

[0125] The specific formula for calculating the resistance is as follows:

[0126] ;

[0127] in, This represents the total resistance of the sliding rheostat. This is the total resistance when the driver is pulled up. , The resistance value of the voltage attenuator. This represents the output impedance of the entire driver module. This indicates the number of parallel units driving the Unit.

[0128] because This is a constant value during circuit design, and at the same time The setting is related to the desired reduction in output voltage; the reduction is the ratio of the input to the output voltage under DPHY conditions. It is also a constant value. Therefore, It can also be used as a constant value.

[0129] Example: In the illustrated state, Given 200Ω, let Given 50Ω, let It is 500Ω, calculated as follows It is 5Ω.

[0130] like Figure 13 As shown, two identical drivers, A and B, are combined to form a LANE for DPHY output, producing a differential signal. In DPHY mode, due to the addition of [a specific driver], the output impedance ZOS is [a specific value]. Plus The overall AC impedance is adjusted to 50Ω using the impedance adjustment function described above. Simultaneously, the RX receiver also has an equivalent impedance of 50Ω, forming a path with a total impedance of 200Ω from power supply to ground after connection. The main current path is shown by the gray dashed line.

[0131] Let the power supply voltage be VDD, then:

[0132] ;

[0133] ;

[0134] It has been verified that, under typical conditions, the input power supply voltage is 0.47V. The highest output voltage (VOHHS) before and after the voltage attenuator was turned on was measured as shown in Table 1. The results are as follows: when the voltage attenuator was not turned on, VOHHS was about 354mV, which was very easy to exceed the specified value under PVT fluctuations. After the voltage attenuator was turned on, the output was about 328mV, which met the expected value of about 330mV.

[0135] Table 1 Output Test Results

[0136] Unit: mV Attenuator off Attenuator on High-terminal voltage 353.823 327.971 Low-end voltage 111.091 99.991

[0137] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A Combo driver structure adapted to CPHY and DPHY, characterized in that, The specific steps include the following: A unified Combo-type driver architecture is configured to switch between CPHY and DPHY modes after selecting a signal through the driver control mode. The unified Combo-type drive architecture includes: a drive unit control module, a drive module, and an impedance adjustment module; The driving module includes: Multiple parallel drive units and a voltage attenuator set at the output of the multiple parallel drive units and responsible for pulling down the output in DPHY mode; The impedance adjustment module includes: Impedance-adjustable comparator, external circuit equivalent resistance, and compensated adjustable reference resistor; The equivalent resistance of the external circuit is switched between being connected to ground or to a power supply via signal control. One end of the impedance adjustment comparator is connected to the output terminal of the drive module and the equivalent resistance of the external circuit, and the other end is connected to the compensated adjustable reference resistor. The output terminal of the impedance adjustment comparator outputs an impedance adjustment signal to the drive unit control module. The drive unit control module is used to receive impedance adjustment signals and control the number of switches of the drive unit of the drive module according to the impedance adjustment signals.

2. The Combo driver structure adapted for CPHY and DPHY according to claim 1, characterized in that, The impedance adjustment comparator includes: Reference voltage source; A MOSFET switch, the drain of which is connected to the reference voltage source, and the gate of which receives a cutoff control signal to keep the MOSFET switch in the off state. A compensation resistor, one end of which is connected to the source of the MOSFET switch and the other end of which is connected to the drain of the MOSFET switch, so that the switch can control whether it is short-circuited. The first sliding resistor has its upper end connected to the other end of the compensation resistor, and the sliding end serves as a voltage divider output node. The second sliding resistor has its upper end connected in series with the lower end of the first adjustable resistor, and its lower end is grounded. The sliding end is used to fine-tune the output ratio.

3. The Combo driver structure adapted for CPHY and DPHY according to claim 2, characterized in that, When the unified Combo type drive architecture selects the CPHY impedance adjustment mode signal through the drive control mode: Keep the voltage attenuator off and the compensation resistor off; Impedance calibration is performed on the high potential H, medium potential M, and low potential L of the CPHY mode respectively. By adjusting the number of PMOS and NMOS switches in the driving unit, the output impedance of each potential is matched with the target impedance value. The number of drive unit switches after calibration at the three potentials (high potential H, medium potential M, and low potential L) is recorded and locked as a calibration code. End calibration and switch to CPHY output mode.

4. The Combo driver structure adapted for CPHY and DPHY according to claim 3, characterized in that, When the CPHY mode is at high potential H: Adjust the PMOS transistor to be turned on and the NMOS transistor to be turned off. Configure an external circuit equivalent resistor between the ground terminal and the impedance adjustment comparator. Adjust the first sliding resistor and the second sliding resistor according to the equivalent resistor value. The ratio of the first sliding resistor value to the second sliding resistor value is 1:

3. Continue until the output impedance reaches the target impedance value, then store the H potential calibration code.

5. The Combo driver structure adapted for CPHY and DPHY according to claim 3, characterized in that, When the CPHY mode is at low potential L: Adjust the PMOS transistor to be off and the NMOS transistor to be on. Configure an external circuit equivalent resistor between the power supply and the impedance adjustment comparator. Adjust the first sliding resistor and the second sliding resistor. The ratio of the first sliding resistor value to the second sliding resistor value is 3:

1. Continue until the output impedance reaches the target impedance value, then store the L potential calibration code.

6. The Combo driver structure adapted for CPHY and DPHY according to claim 3, characterized in that, When the CPHY mode is at high potential H: The transmission unit is configured to the M potential state, and the PMOS and NMOS transistors are turned on simultaneously. The initial conduction ratio of the PMOS and NMOS is calculated based on the H potential calibration code and the L potential calibration code. An external circuit equivalent resistance is configured between the ground terminal and the impedance adjustment comparator. The first sliding resistor and the second sliding resistor are adjusted according to the equivalent resistance value. The ratio of the first sliding resistor value to the second sliding resistor value is 1:

1. Continue until the output impedance reaches the target impedance value, then store the M-potential calibration code.

7. The Combo driver structure adapted for CPHY and DPHY according to claim 3, characterized in that, The output impedance is: ； in, This represents the output impedance of a single driving unit. This represents the output impedance of the entire drive module. Indicates the number of parallel drives for the Unit. Indicates the process variation factor. This represents the voltage variation factor. This represents the temperature change factor.

8. The Combo driver structure adapted for CPHY and DPHY according to claim 2, characterized in that, When the unified Combo type drive architecture selects the DPHY impedance adjustment mode signal through the drive control mode: During the calibration phase of driving the output high potential H, the voltage attenuator and the compensation resistor are turned on, and the number of on switches of the driving unit is adjusted so that the output impedance of the H potential matches the target impedance value. During the calibration phase of driving the output low potential L, the voltage attenuator is kept on and the compensation resistor is closed, and the number of on / off switches of the driving unit is adjusted so that the output impedance of the L potential matches the target impedance value. The number of drive unit switches after calibration of the H and L potentials is recorded and locked as a calibration code; End calibration and switch to DPHY output mode.

9. The Combo driver structure adapted for CPHY and DPHY according to claim 8, characterized in that, When the output is at a low potential L, the NMOS is pulled down to keep the PMOS off and the NMOS on. The pull-down resistor is composed of the drive resistor and the voltage attenuator resistor connected in parallel, satisfying the following: ； Based on the pull-down resistor value, determine the overall output impedance of the voltage attenuator and the driver unit; Adjust the driving resistor according to the number of driving units activated to perform impedance regulation; When the output is at a high potential H, the PMOS transistor is pulled up to keep it on and the NMOS transistor off. The pull-up resistor is also a pull-down resistor, which is formed by connecting the drive resistor and the equivalent resistance of the external circuit in parallel, and then connecting them in parallel with the voltage attenuator resistor, satisfying the following conditions: ； In the pull-up state, by connecting a compensation resistor and a corresponding switching MOSFET in series between the sliding resistor and the power supply, the pull-down impedance that is reduced due to the addition of the voltage attenuator resistor is compensated. in, Indicates pull-down resistor. This represents the equivalent resistance of the external circuit. Indicates pull-down resistor. This indicates the voltage attenuator resistor.

10. The Combo driver structure adapted for CPHY and DPHY according to claim 9, characterized in that, The compensation for the reduced pull-down impedance due to the incorporation of the voltage attenuator resistor includes: ； in, This represents the total resistance of the sliding rheostat. This is the total resistance when the driver is pulled up. The resistance value of the voltage attenuator. This represents the output impedance of the entire drive module.

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