Method, system, device and medium for adjusting timing of signature condition of extended chip core

Abstract

The application discloses a timing adjustment method, system, device and medium for expanding core signature conditions, and belongs to the technical field of chip verification. The method comprises the following steps: determining the delay ratio of a typical device at different voltages based on the delay limit of the typical device on a chip clock line at different voltages; taking the delay ratio as a voltage conversion coefficient, determining the non-signature condition derating factor corresponding to a second voltage and a violation path under the non-signature condition based on the signature condition derating factor corresponding to a first voltage; reducing the receiving clock delay by replacing the device and / or removing the redundant buffer on the receiving clock path; increasing the transmitting clock delay by inserting a buffer on the transmitting clock path; and adjusting the clock path of the violation path. By calculating the voltage conversion coefficient between the non-signature condition and the signature condition, the conversion of the non-signature condition is completed, and then the timing adjustment under the non-signature condition is performed, thereby improving the chip yield.

Description

Technical Field

[0001] This invention relates to the field of chip verification technology, and specifically to a timing adjustment method, system, device, and medium for expanding chip verification conditions. Background Technology

[0002] With the continuous advancement of semiconductor process technology, the manufacturing complexity has increased exponentially after entering the ultra-deep submicron realm, leading to a corresponding increase in microscopic uncertainties during chip manufacturing. These uncertainties result in minute differences in the physical dimensions (such as channel length and width) and electrical parameters (such as threshold voltage Vth) of transistors. In practical chip applications, fluctuations in temperature and voltage can alter chip performance. For example, under "slow transistors" with relatively high threshold voltage Vth, the delay becomes increasingly slower in "slow process corners (low temperature and low voltage)," potentially preventing signal transmission within the specified clock cycle. Conversely, under "fast process corners (high temperature and high voltage)" where voltage rises and chip heat dissipation cannot keep up with temperature increases, "fast transistors" with low threshold voltage Vth experience faster delays, potentially changing the signal before the device recognizes it. All of these factors can lead to chip malfunctions, performance defects, and reduced chip yield.

[0003] Static Timing Analysis (STA) verification is an important means to improve chip yield. It verifies whether the chip is qualified by verifying whether the setup time and hold time of the timing path between every two flip-flops in the chip meet the functional requirements of the digital circuit under the conditions of approval.

[0004] The approval conditions are typically selected as the most representative and pessimistic (e.g., Slow-Slow Low-Voltage, SSLV). However, in some longer and more complex logic paths, where the delay variation of standard cells with different threshold voltages varies at different temperatures and voltages, timing issues can arise where timing is fine under the approval condition (SSLV) but occurs under non-approval conditions (e.g., Slow-Slow High-Voltage, SSHV). Since the timing states under non-approval conditions such as SSHV are not verified, these potential timing violations can lead to functional abnormalities in the manufactured chip, resulting in reduced chip yield. Summary of the Invention

[0005] The purpose of this invention is to provide a timing adjustment method, system, device, and medium for expanding chip approval conditions. By calculating the voltage conversion coefficient between the non-approval condition SSHV and the approval condition SSLV, and based on the approval condition derating factor and the voltage conversion coefficient, the corresponding non-approval condition derating factor is determined, thus generating the non-approval condition. Timing adjustment is then performed under this non-approval condition, solving the problem of low chip yield caused by incomplete coverage of approval conditions in the process library.

[0006] This invention is achieved through the following technical solution:

[0007] The first aspect of this application provides a timing adjustment method for expanding chip approval conditions, including:

[0008] Based on the delay limits of typical devices on the chip clock line at different voltages, the delay ratio of typical devices at the first voltage and the second voltage is determined; the delay limits are determined by verifying the timing characteristics of the typical devices at different voltages.

[0009] The delay ratio is used as the voltage conversion coefficient between the first voltage and the second voltage. Based on the derating factor of the approval condition corresponding to the first voltage and the voltage conversion coefficient, the derating factor of the non-approval condition corresponding to the second voltage is determined. The approval condition is a timing verification condition that exists in the preset process library, and the non-approval condition is a timing verification condition that does not exist in the process library.

[0010] Based on the voltage conversion coefficient and the delay deviation under the verification conditions, the violation path under the non-verification condition derating factor corresponding to the second voltage is determined; the delay deviation is the difference between the receive clock delay and the transmit clock delay on the clock path;

[0011] The receive clock delay is reduced by replacing devices and / or removing redundant buffers on the receive clock path; and the transmit clock delay is increased by inserting buffers on the transmit clock path; the clock path of the violation path is adjusted by replacing the device with a device with a smaller delay than the original device, and the original device is connected to the clock pin of at least one signal receiver on the violation path.

[0012] In one feasible implementation, the method further includes: for the violation paths that still exist after clock path adjustment, performing the following operation:

[0013] Grouping violation paths belonging to the same signal transmitter into at least one violation path group;

[0014] For one group, the number of buffers to be inserted after the data output pin of the signal transmitter is determined based on the ratio of the minimum establishment time margin of each violation path in the group to the maximum delay of the buffer; the number of buffers is inserted after the data output pin of the signal transmitter to perform data path adjustment.

[0015] In one feasible implementation, the method further includes: if, after the data path adjustment, there are still violating paths, then:

[0016] Using electronic design automation tools, a buffer is inserted before the data pin of the signal receiver.

[0017] In one feasible implementation, based on the voltage conversion coefficient and the delay deviation under the approval conditions, the violation path under the non-approval condition derating factor corresponding to the second voltage is determined, including:

[0018] Compare the delay deviation of each clock path under the verification conditions with the preset constraint value;

[0019] For clock paths that maintain time violations under non-approval conditions, if the delay deviation of the clock path is greater than the constraint value, then the clock path is a violation path.

[0020] The constraint value is determined based on the product of the voltage conversion coefficient and a predetermined delay deviation threshold.

[0021] In one feasible implementation, reducing the receive clock delay by replacing devices and / or removing redundant buffers on the receive clock path includes:

[0022] Traverse the signal receivers on the violation path and group the signal receivers whose clock pins are connected to the same device to determine at least one group of signal receivers.

[0023] For any signal receiver group, the following steps are performed: If the hold time margin of the corresponding clock path for each signal receiver in the group as a signal transmitter exceeds the set value, then it is initially determined that the device corresponding to the current group should be replaced; the area occupied by the buffer to be inserted when adjusting the data path of the violation path is calculated; if the area increased by replacing the device is less than the area occupied by the inserted buffer, then the device corresponding to the current group is replaced to reduce the receive clock delay; otherwise, the receive clock delay is reduced by removing redundant buffers on the receive clock path.

[0024] In one feasible implementation, reducing the receive clock delay by removing redundant buffers on the receive clock path includes:

[0025] Calculate the number of buffers that can be removed when the hold time of the next-level clock path of each signal receiver in the current group is not violated, the number of buffers that need to be inserted when the hold time of the current-level clock path of each signal receiver in the current group is not violated, and the number of buffers that need to be removed to make the delay deviation less than the constraint value. Select the minimum value from each number of buffers as the number of redundant buffers to be removed.

[0026] In one feasible implementation, increasing the transmit clock delay by inserting a buffer into the transmit clock path includes:

[0027] Traverse the signal transmitters on the violation path and group the signal transmitters whose clock pins are connected to the same device to determine at least one group;

[0028] For any group in the group, perform the following: calculate the number of buffers that can be inserted when the hold time of the previous stage clock path of each signal transmitter in the current group is not violated, the number of buffers that need to be inserted when the hold time of the current stage clock path of each signal transmitter in the current group is not violated, and the number of buffers that need to be inserted to make the delay deviation less than the constraint value. Select the minimum value from each number of buffers as the number of buffers that need to be inserted on the transmission clock path.

[0029] The second aspect of this application provides a timing adjustment system for expanding chip verification conditions, including:

[0030] The delay ratio determination unit determines the delay ratio of a typical device at a first voltage and a second voltage based on the delay limit of a typical device on the chip clock line at different voltages; the delay limit is determined by verifying the timing characteristics of the typical device at different voltages.

[0031] The condition conversion unit is used to use the delay ratio as a voltage conversion coefficient between the first voltage and the second voltage, and to determine the non-approval condition derating factor for the second voltage based on the approval condition derating factor corresponding to the first voltage and the voltage conversion coefficient; the approval condition is a timing verification condition existing in a preset process library, and the non-approval condition is a timing verification condition not existing in the process library.

[0032] The violation path determination unit determines the violation path under the non-signature condition derating factor corresponding to the second voltage based on the voltage conversion coefficient and the delay deviation under the signature condition; the delay deviation is the difference between the receive clock delay and the transmit clock delay on the timing path;

[0033] The clock path adjustment unit reduces the receive clock delay by replacing devices and / or removing redundant buffers on the receive clock path; and increases the transmit clock delay by inserting buffers on the transmit clock path; and adjusts the clock path of the violation path by replacing the device with a device with a smaller delay than the original device, wherein the original device is connected to the clock pin of at least one signal receiver on the violation path.

[0034] A third aspect of this application provides an electronic device, including: a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the above-described method.

[0035] A fourth aspect of this application provides a storage medium, comprising: storing a program or instructions on the storage medium, wherein the program or instructions, when executed by a processor, implement the steps of the above-described method.

[0036] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0037] This embodiment verifies the timing characteristics of typical devices on the chip clock line under different voltages to determine the voltage conversion coefficient between the non-signature condition SSHV (corresponding to the second voltage) and the signature condition SSLV (corresponding to the first voltage). Based on the signature condition derating factor and this voltage conversion coefficient, the corresponding non-signature condition derating factor is determined, thus generating the non-signature condition. Timing adjustments are then performed under this non-signature condition. Since this voltage conversion coefficient accurately quantifies the delay change ratio (delay ratio) of typical devices at high voltage (HV) and low voltage (LV) under slow process corner (SS), and this ratio can be directly mapped to the core parameter (derating factor derate) of STA verification, this embodiment enables timing adjustments for non-signature violation paths on the chip without increasing the signature condition in the process library. This avoids chip functional abnormalities caused by non-signature conditions in actual chip applications, improving chip yield. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:

[0039] Figure 1 A schematic diagram of the timing path for STA verification in existing technologies;

[0040] Figure 2 This is a schematic diagram illustrating the conditions under which timing violations occur in chips actually manufactured in the prior art.

[0041] Figure 3 A flowchart illustrating a timing adjustment method for expanding chip verification conditions provided in an embodiment of this application;

[0042] Figure 4 A schematic diagram of the STA condition conversion and violation path detection process in a timing adjustment method for expanding chip verification conditions provided in an embodiment of this application;

[0043] Figure 5 Schematic diagrams of different timing paths;

[0044] Figure 6 A schematic diagram of the clock path adjustment process in a timing adjustment method for expanding chip verification conditions provided in an embodiment of this application;

[0045] Figure 7 This is a schematic diagram of a data path structure;

[0046] Figure 8 A schematic diagram of the data path adjustment process in a timing adjustment method for expanding chip verification conditions provided in an embodiment of this application;

[0047] Figure 9 This application provides a schematic diagram of the structure of a timing adjustment system for expanding chip verification conditions;

[0048] Figure 10 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments and accompanying drawings. The illustrative embodiments and descriptions of this invention are for explanation only and are not intended to limit the invention. All other embodiments obtained by those skilled in the art based on the embodiments in this application without creative effort are within the scope of protection of this application.

[0050] As will be known to those skilled in the art, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0051] The terms “comprising” and “having”, and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, product, or apparatus.

[0052] To clearly explain this solution, the relevant existing technologies will first be described as follows:

[0053] like Figure 1 As shown, FF1 is the signal transmitter (transmitting FF) in this timing path, and FF2 is the signal receiver (receiving FF). The clock propagates from the source to FF1 and FF2. When it reaches FF1, FF1 transmits the data signal "data" to FF2. When the clock reaches FF2, FF2 receives the data signal, and the data signal needs to remain relative to the clock signal for a certain period of time upon reception; this time is called the hold time. FF2 also requires that the data signal of the next clock cycle can stabilize within a certain time before the arrival of the current clock cycle; this time is called the setup time. The setup time can also be understood as the minimum time that the input data signal (D terminal) of FF2 must stabilize before the trigger edge (rising / falling edge) of the clock signal (CK terminal) arrives. Simply put, for FF2 to correctly identify and latch the input data signal, the data signal and the clock signal trigger edge cannot arrive simultaneously; the data must be in place in advance and remain stable. This minimum advance time is the setup time.

[0054] The path from the clock source to the CK pin (Clock pin) of FF1 is called the transmit clock path, and its transmit clock delay is denoted as L_CLK latency. The path from the clock source to the CK pin of FF2 is the receive clock path, and its receive clock delay is denoted as C_CLK latency. The difference between the receive clock delay and the transmit clock delay is called the clock skew. The path between FF1 and FF2 is the data path. The signal transmission delay between the signal output pin (Q pin) of FF1 and the signal input pin (D pin) of FF2 is denoted as the data delay, and the clock period is T.

[0055] Below are the verification formulas for setup time and hold time in STA verification:

[0056] Establish the verification formula for time: L_CLK latency + data delay <C_CLK latency–Setup time+ T;

[0057] Setup slack = C_CLK latency – Setup time + T – (L_CLK latency + data delay);

[0058] The formula for verifying hold time is: L_CLK latency + data delay > C_CLK latency + Hold time;

[0059] Hold slack = L_CLK latency + data delay - (C_CLK latency + Holdtime);

[0060] clock skew=C_CLK latency-L_CLK latency.

[0061] The approval conditions in STA verification refer to the core PVT (Process, Voltage, Temperature) combination conditions that must be verified by the wafer foundry using a dedicated process library before the chip design company can fabricate the chip. These conditions serve as the timing verification baseline to ensure the basic functionality of the chip is up to standard. Chips that fail to pass the approval conditions verification cannot enter the production process and are also the basis for the subsequent expansion of non-approval conditions verification in this application.

[0062] Among them, the combined operating conditions usually select the most representative and pessimistic (worst operating conditions) PVT combination in the actual use of the chip to ensure that the chip works stably under the basic operating conditions of actual applications. The core signing condition in the solution is SSLV, which is a typical pessimistic operating condition under ultra-deep submicron process.

[0063] STA verification is typically performed on a limited number of process corners, as shown in Table 1 below. Taking the 22nm process as an example, the STA approval conditions usually include PVC condition (process voltage and temperature condition) and RC (resistance and capacitance) condition (parasitic capacitance and capacitance condition). The PVC condition includes the global slow process corner SSG, with a temperature of -40℃ and a voltage of 0.72V, and the global fast process corner FFG, with a temperature of 95℃ and a voltage of 0.90V. The RC condition includes the worst-case RC parasitic condition RCworst, with a temperature of 95℃, and the worst-case parasitic capacitance condition Cworst, with a temperature of -40℃.

[0064] Table 1. STA Approval Criteria:

[0065]

[0066] The approval conditions in Table 1 above assume that all transistors on the chip are simultaneously in the "fastest" or "slowest" state. However, in reality, transistors in different areas of the chip may be in different combinations of fast, slow, and typical states.

[0067] Furthermore, chip design needs to consider multiple operating modes (such as high-performance mode, low-power mode, and test mode), each with different voltage and frequency targets. In advanced processes (such as 7nm, 5nm, and below), the situation becomes even more complex. The resistance and capacitance on interconnects cannot be characterized by simple Cworst, Rworst, etc., but require corners like RCworst for a more comprehensive characterization. If all possible combinations of PVT, RC, and operating modes were generated into a single .lib file (the format used by process libraries), the number of possible combinations would be exponential and enormous. Moreover, the internal voltage, temperature, and crosstalk environment of the chip are design-dependent and cannot be predicted in advance. Providing too many unnecessary corners would also increase costs for both the fabrication plant (FAB) and the design company.

[0068] like Figure 2 The diagram illustrates the conditions under which timing violations occur in a manufactured chip. The horizontal axis represents RC conditions, including Cworst (worst parasitic capacitance) and Cbest (best parasitic capacitance); the vertical axis represents process technology, including SS (slow-slow) and FF (fast-fast); and the vertical axis represents voltage conditions, including LV (low voltage), TYP (Typical, referring to standard voltage in the diagram), and HV (high voltage). Points A1 and A2 represent STA (Standard Instrumented) approval conditions existing in the process library, while points B1 and B2 represent non-approved conditions not existing in the process library that also result in timing violations. It is evident that timing violations occur under SSHV (Slow-to-High Voltage) conditions.

[0069] Research on chips that exhibit timing violations after actual manufacturing reveals that, under non-certification conditions, timing violations typically exhibit the following four characteristics:

[0070] 1. The transmit clock delay of the violation path must be more than 1ns smaller than the receive clock delay, that is, the clock skew is greater than 1ns. In order to meet the Hold timing requirements, a large number of HVT (High Voltage Threshold) units will be inserted.

[0071] 2. Inconsistent use of Vth cells on the violation path: The data path uses a large number of HVT cells, while the clock path uses LVT (Low Voltage Threshold) cells; HVT cells with wide channel widths have large delay changes when the voltage changes, while SVT (Standard Voltage Threshold) and LVT cells have relatively small changes (different Vth cells have different voltage sensitivities, resulting in large differences in delay changes).

[0072] 3. The timing margin for the violation path under STA approval conditions is small;

[0073] 4. Advanced processes (55nm and below): As processes become more advanced, they become more sensitive to temperature / voltage, and delay variations in standard cells are more easily affected.

[0074] Based on the above background, this application proposes a method that, in addition to existing STA verification, adds verification under non-signature conditions. It uses the delay ratio of typical devices at different voltages under SS conditions as a coefficient to determine the impact of voltage variations on delay, converting existing signature conditions into non-signature conditions. This allows for early confirmation of the timing status under non-signature STA conditions (SSLV→SSHV, slow process low voltage→slow process high voltage). Subsequently, paths that do not meet timing requirements are detected and corrected using timing repair methods. This method improves chip yield by verifying timing under non-signature conditions without adding additional process library content.

[0075] This application performs SSLV->SSHV conditional conversion on the existing STA data. Compared to recreating the standard cell library for this condition, rereading the library, and then performing STA verification, it significantly improves both cost and efficiency. Furthermore, considering the increasing integration density of chips and the increasingly stringent power requirements, when repairing timing violations, based on the existing EDA (Electronic Design Automation) tools' automatic ECO (Engineering Change Order), and adhering to the principles of minimizing the increase in the number of devices (equivalent to suppressing an increase in area) and minimizing power consumption, a clock path adjustment system and a data adjustment system are added to improve the timing repair effect.

[0076] The present application will be described in detail below through specific embodiments.

[0077] Example 1:

[0078] Embodiment 1 of this application provides a timing adjustment method for expanding chip approval conditions to solve the problem of low chip yield caused by incomplete coverage of approval conditions in the process library.

[0079] The subject executing this method can be any computing device capable of implementing the method, such as a server, mobile phone, personal computer, smart wearable device, smart robot, etc.

[0080] Furthermore, the embodiments of this application do not limit the execution order of different steps. When using the method provided in the embodiments of this application, the execution order of different steps can be adjusted according to actual needs.

[0081] For ease of description, the following uses a timing adjustment device for expanding chip verification conditions as the execution subject of this method to provide a detailed description of the method provided in this application embodiment.

[0082] like Figure 3 The diagram shown is a flowchart illustrating the specific implementation of a timing adjustment method for expanding chip verification conditions according to an embodiment of this application, including the following steps S1-S4:

[0083] Step S1: Based on the delay limits of typical devices on the chip clock line at different voltages, determine the delay ratio of typical devices at the first voltage and the second voltage; the delay limits are determined by verifying the timing characteristics of the typical devices at different voltages.

[0084] Clock lines are metal interconnects within a chip used to transmit clock signals (belonging to the chip's interconnect layer, alongside power lines and signal lines). They serve as the chip's time reference transmission channel, responsible for distributing the synchronous clock signal generated by the clock source (such as a crystal oscillator) to all devices within the chip that require timing synchronization, ensuring that the entire chip's logic operations are executed according to a unified clock cycle.

[0085] Typical devices refer to independent devices in a chip that perform specific basic functions. They consist of one or more standard cells and dedicated interconnects. They can also be directly integrated from basic semiconductor devices (transistors, resistors, capacitors) processed by wafer fabrication. They are the basic functional modules that enable a chip to perform specific functions.

[0086] A standard cell refers to the smallest reusable unit in chip design that has undergone process verification, functional standardization, and layout standardization. It is the core reusable module from front-end design to back-end layout of integrated circuits. It consists of basic semiconductor devices (MOSFETs, resistors, capacitors) and internal interconnection traces. All standard cells have fixed heights and standardized pin positions (key features), and can be arbitrarily assembled and arranged in the layout like building blocks.

[0087] In step S1, the timing characteristics of the standard cell under different voltages are verified using standard cell models of typical devices on the clock line, such as buffers or inverters, to obtain the full-swing frequency Ffull-swing of the standard cell under different voltages. Based on the full-swing frequency obtained from the timing characteristic verification, and the inverse relationship between the full-swing frequency and the delay limit Tdelay, the delay limit Tdelay of the standard cell under different voltages is obtained, which is an optimal performance value of the physical characteristics of the standard cell under different voltages.

[0088] Full swing frequency refers to the frequency at which a signal can change from the starting point (0V) to the ending point (100% VDD, voltage drain voltage) within one cycle and have enough time to stabilize. In other words, it is the maximum frequency at which a signal completes a full, high-quality switching operation.

[0089] The full swing frequency is a direct reflection of the element delay under extreme conditions, and the element delay also determines the full swing frequency.

[0090] Cell delay refers to the time required for the output signal to change from its starting point (0V) to a logic threshold point (e.g., 50% VDD). In other words, it is the time required for the signal to undergo a logic transition, and the endpoint value is not necessarily 100% VDD.

[0091] Table 2 below shows the full-swing frequency Ffull-swing and limiting delay of the inverter at different voltages, obtained from timing characteristic verification of the inverter. The typical limiting delay Tdelay is 1 / Ffull-swing (the limiting delay trend, not the delay of the INV itself).

[0092] Table 2. Full swing frequency and limiting delay of inverters at different voltages:

[0093]

[0094] The delay ratio is calculated based on the limiting delays at different voltages in Table 2, as shown in Table 3 below. The delay ratio is the ratio of the limiting delays of the same standard unit at different voltages (such as the first voltage and the second voltage). The first voltage is any of the different voltages, and the second voltage is any voltage other than the first voltage. In this embodiment, the first voltage specifically refers to the low voltage, and the second voltage specifically refers to the high voltage. The low voltage and high voltage refer to the minimum and maximum operating voltages of a typical device, respectively.

[0095] Table 3, Limiting Delay and Delay Ratio Table:

[0096]

[0097] For example, if the voltage swing of a certain design is 0.72-0.81V, the standard cell H33 (Vth, H is the high threshold, 33 is the channel width) has a cell delay of 14.875 at 0.72V and a cell delay of 10.627 at 0.81V; then the delay ratio of H33 at the two voltages is: 10.627 / 14.857=0.715, and the voltage conversion factor of H33 is 0.715.

[0098] Step S2: Using the delay ratio as the voltage conversion coefficient between the first voltage and the second voltage, and based on the derating factor of the verification conditions corresponding to the first voltage and the voltage conversion coefficient, determine the derating factor of the non-verification conditions corresponding to the second voltage; the verification conditions are timing verification conditions existing in the preset process library, and the non-verification conditions are timing verification conditions not existing in the process library.

[0099] Based on step S1 above, the high-low voltage limit delay ratios of the standard cells of typical devices at each Vth (threshold voltage) are obtained, i.e., the voltage conversion coefficients of each Vth device. These coefficients can be reflected in the SSLV-condition environment by setting the derating factor (derate), and then another STA (Simultaneous Transition) is performed to obtain the timing under SSHV conditions, thus achieving the STA condition conversion from SSLV to SSHV. This solves the problem of simulating timing under SSHV conditions even without a library for SSHV conditions.

[0100] In this embodiment, the first voltage refers to low voltage, which corresponds to the signing condition of the first voltage, namely the SSLV condition. The second voltage refers to high voltage, which corresponds to the non-signing condition of the second voltage, namely the SSHV condition.

[0101] It should be noted that in the original STA environment under SSLV conditions, each Vth device already has a derating factor derate that takes into account on-chip variation (OCV), i.e., SSLV device delay = library delay × SSLV derate. When converting to SSHV, the original derate cannot be ignored. Therefore, it is not directly set as the voltage conversion factor, but rather the SSHV derate is set as SSLV derate × voltage conversion factor. That is, the non-signature condition derating factor corresponding to the second voltage is equal to the product of the signature condition derating factor corresponding to the first voltage and the voltage conversion factor.

[0102] For example, in a 22nm design, the derate of an H33 type device under SSLV conditions is 1.128, and its voltage conversion factor is calculated to be 0.715 in S1. Therefore, the SSHV derate is 1.128 × 0.715 = 0.806.

[0103] Step S3: Based on the voltage conversion coefficient and the delay deviation under the verification condition, determine the violation path under the non-verification condition derating factor corresponding to the second voltage; the delay deviation is the difference between the receive clock delay and the transmit clock delay on the clock path.

[0104] A violation path refers to a timing path in chip STA verification that fails to meet the core verification requirements of setup time or hold time. Essentially, it is a timing violation state in which the signal transmission path between flip-flops has a timing slack ≤ 0 due to delay, clock skew, or other issues.

[0105] The determination of the violation path can be as follows: compare the delay deviation of each clock path under the approval condition with the preset constraint value; for clock paths that maintain time violations under non-approval conditions, if the delay deviation of the clock path is greater than the constraint value, then the clock path is a violation path.

[0106] The constraint value is determined based on the product of the voltage conversion coefficient and a predetermined delay deviation threshold. In this embodiment, the predetermined delay deviation threshold can be 1 ns.

[0107] Specifically, when the STA verification condition is converted from SSLV to SSHV, the voltage is simulated to increase, and the device delay tends to decrease. This is beneficial for setup timing but detrimental to hold timing. Therefore, we need to perform timing correction on hold timing. However, according to observation and statistics, not all hold violations of SSHV conditions in STA will cause problems in the actual production chip, because the devices on the timing path are not extremely concentrated at the location of the highest voltage. Those that are prone to causing problems are usually paths with a delay deviation (clockskew) exceeding 1ns under SSLV conditions. Therefore, it is necessary to further screen these hold violation paths, find paths with clock skew greater than the constraint value (Max_Skew), and then perform timing adjustments.

[0108] like Figure 4As shown, in one specific implementation, the steps of step S2 (STA condition conversion) and step S3 (violation path detection) can be as follows: The STA database of the executed SSLT conditions (signature conditions) is retrieved from the verification tool, which includes the timing results of the SSLV conditions and the SSLV derate; the SSLV derate is multiplied by the voltage conversion factor to obtain the SSHV derate, and the derate in the STA database of the SSLT conditions is reset to the SSHV derate; under the SSHV derate, the STA performs a timing update, saving each timing path under the SSHV conditions. In step S3, the hold violation paths in the saved timing paths are traversed, and it is determined whether the delay deviation of each hold violation path is greater than the constraint value. If so, the clock path is recorded as a violation path in the violation report; otherwise, after traversing all hold violation paths, the judgment is received, and the violation report is output.

[0109] Step S4: Reduce the receive clock delay by replacing the device and / or removing redundant buffers on the receive clock path; and increase the transmit clock delay by inserting a buffer on the transmit clock path; perform clock path adjustment on the violation path, replacing the device with a device with a smaller delay than the original device, and the original device is connected to the clock pin of at least one signal receiver on the violation path.

[0110] Based on the criteria for determining the violation path, namely, for an existing hold violation path, the clock path delay deviation must also be greater than the aforementioned constraint value; since the delay deviation is equal to the difference between the receive clock delay and the transmit clock delay, two approaches can be used to repair the timing:

[0111] 1. Increase the transmit clock delay or decrease the receive clock delay to adjust the delay deviation clock skew below the constraint value;

[0112] 2. Increase the latency of the data path to meet the Hold time verification.

[0113] Currently, when using EDA tools for timing repair, only approach 2 is generally used, which involves inserting a buffer on the data path of the violation path to increase latency and meet the hold time requirement.

[0114] If we consider chip area and power consumption, the following is true: Figure 5 Adjusting the path using approach 1 is more optimal. For example... Figure 5Groups 1 and 3 correspond to one-to-many and many-to-many clock paths, respectively. The transmitting FFs are connected to the same buffer. Directly adjusting them using EDA tools would insert multiple buffers into the data path. Adjusting the clock path only requires inserting one or more buffers after the common buffer (shown by gray triangles in Groups 1 and 3). Similarly, the receiving FFs in Groups 2 and 3 have multiple identical buffer segments in their clock paths. Removing redundant buffers (shown by gray triangles marked with an "X" in Groups 2 and 3) can reduce the receiving clock delay, making the clock skew less than the constraint value. This reduces both area and power consumption. While using approach 1 alone cannot reduce the clock skew below the constraint value for paths with particularly large clock skews to ensure setup time and hold time for preceding and following timing paths, it can increase the hold slack value and reduce the number of buffers inserted into the data path.

[0115] Therefore, this step adds clock path adjustment before the EDA tool performs timing adjustment, prioritizing the adjustment of the clock path to its optimal state.

[0116] like Figure 6 As shown, the specific implementation process of this step includes steps S41-S45:

[0117] Step S41: Based on the STA data from SSHV and the violation path report determined in step S3, filter out the violation paths with sufficiently large Setup slack to ensure that clock adjustments will not cause setup time violations. Sufficiently large Setup slack means that the original Setup slack of the current path is greater than the reduction in Setupslack caused by clock path adjustments.

[0118] Step S42: Traverse all signal receivers on the violation path, i.e., receivers FF, obtain the devices connected to the clock pin CK pin of the receiver FF, and group the receivers FF connected to the same device (c_cell) into a group to determine at least one signal receiver group.

[0119] For any signal receiver packet in the packet, perform the following steps S431-S433:

[0120] Step S431: Determine whether c_cell can be replaced with a faster device. Specifically, if the hold time margin of the corresponding clock path of each signal receiver in the group exceeds the set value when acting as a signal transmitter, it is initially determined to replace the device corresponding to the current group with a faster (lower latency) device to reduce latency deviation.

[0121] Considering that replacing with a faster device would increase both chip area and power consumption, the area occupied by the buffer that needs to be inserted when adjusting the data path of the violation path is first calculated, and then compared with the area increase required to replace with a faster device: if the area increase from replacing the device is less than the area occupied by the inserted buffer, then the device corresponding to the current group is replaced to reduce the receive clock delay; otherwise, the receive clock delay is reduced through step S432, that is, by removing redundant buffers on the receive clock path.

[0122] The area occupied by the buffers that need to be inserted when adjusting the data path can be calculated as: the sum of the hold time margins of all adjusted data paths divided by the delay of the buffer to be inserted multiplied by the area of ​​the buffer to be inserted. The buffer to be inserted is typically H_Buf, the high-threshold buffer, which has a larger delay and is used to adjust the hold time.

[0123] Step S432: Calculate the number of adjustable buffers on the receive clock path. Specifically, this involves calculating and comparing the following data Buf1, Buf2, and Buf3, and selecting the smallest value as the number N of adjustable buffers for the clock. L_Buf is the low-threshold buffer, and typically the clock path will uniformly use a low-threshold buffer.

[0124] Where Buf1 represents the number of buffers that can be removed if the hold time of the subsequent clock path of each signal receiver in the current group does not violate the rules; the subsequent clock path refers to the timing path when the FF in this group is used as the transmit FF. Specifically, Buf1 is the ratio of the minimum value of each subsequent clock path corresponding to each signal receiver to the delay of the buffer that can be inserted, which can be expressed as: Buf1 = MIN(Subsequent Hold slack) ÷ L_Buf delay.

[0125] Buf2 represents the number of buffers that need to be inserted to ensure that the hold time of the local clock path of each signal receiver in the current group does not violate the rules; the local clock path refers to the timing path when the FF in this group is used as the receiving FF. Specifically, Buf2 is the ratio of the minimum value of each local clock path corresponding to each signal receiver to the delay of the buffer that needs to be inserted, which can be expressed as: Buf2 = MIN(local hold slack) ÷ L_Buf delay.

[0126] Buf3 represents the number of buffers that need to be removed to make the delay deviation less than the constraint value. Specifically, Buf3 is the difference between the delay deviation and the constraint value, divided by the delay of the buffers to be removed, which can be expressed as: Buf3 = (clock skew – Max_Skew) ÷ L_Buf delay.

[0127] Step S433: Connect the device to bufferN to complete the specific buffer removal operation. Specifically, this includes: starting from the CK pin of the receiving FF and searching towards the clock source, find the (N+1)th device, denoted as bufferN, and obtain the physical locations of all devices between the CK pin of the receiving FF and bufferN. If all these devices are buffers or multiples of 2 inverters, and the location of bufferN is less than a value that will not cause a design rule violation, then connect them, i.e., remove N buffers; otherwise, continue to determine whether the Nth device meets the connection conditions.

[0128] Step S44: Traverse all paths that are still invalid after adjusting the receive clock path, traverse the signal transmitters on the invalid paths, set each signal transmitter whose clock pin is connected to the same device as a group, in order to determine at least one group, and temporarily store each group in a temporary array.

[0129] Step S45: Iterate through each array in S44 and increase the transmit clock delay by inserting a buffer on the clock path of the violation path. This is specifically implemented through steps S451-S452:

[0130] Step S451: Calculate the number of buffers that can be inserted for the transmit clock.

[0131] By calculating and comparing the following data Buf4, Buf5, and Buf6, the smallest value is selected as the number of buffers M that can be inserted for the transmit clock.

[0132] Buf4 represents the number of buffers that need to be inserted to ensure the hold time of the local clock path for each signal transmitter in the current group. The local clock path refers to the timing path when the FF in this group is used as the transmit FF. Specifically, Buf4 is the ratio of the minimum value of each local clock path for each signal transmitter in the group to the delay of the buffer that needs to be inserted, which can be expressed as: Buf4 = MIN(local hold slack) ÷ L_Buf delay.

[0133] Buf5 represents the number of buffers that can be inserted if the hold time of the previous stage clock path for each signal receiver in the current group does not violate the rules. The previous stage clock path refers to the timing path when the FF in this group is used as the receiving FF. Specifically, Buf5 is the ratio of the minimum value of each previous stage clock path for each signal transmitter to the delay of the buffer that can be inserted, which can be expressed as: Buf5 = MIN(previous stage hold slack) ÷ L_Buf delay.

[0134] Buf6 represents the number of buffers required to make the delay deviation less than the constraint value. Specifically, Buf6 is the difference between the delay deviation and the constraint value, divided by the delay for which buffers need to be inserted, which can be expressed as: Buf6 = (clock skew – Max_Skew) ÷ L_Buf delay.

[0135] Step S452: Determine whether to insert the number of buffers calculated in step S451 into the transmit clock.

[0136] When chip design prioritizes area, or when chip design prioritizes power and the number of buffers required to adjust the data path is greater than the product of the number calculated in step S451 (the number of buffers to be inserted into the transmit clock path) and P, the number of buffers calculated in step S451 is inserted into the transmit clock path. Here, P is the ratio of the power of the low-threshold buffer to the power of the high-threshold buffer; the low-threshold buffer has a higher power consumption.

[0137] Calculate the number of buffers, Buf7, needed when adjusting the data path. Buf7 is the sum of the delay margins of each violation path, divided by the delay of the inserted buffer; it can be expressed as: Buf7 = total hold slack ÷ H_Bufdelay. If the design prioritizes area (i.e., minimizing area as much as possible), insert the required buffer on the clock path shared by the group of FFs; if it prioritizes power, compare Buf7 with M×P. When Buf7 is larger, it indicates that the power increase caused by adjusting the data path is greater than that caused by adjusting the clock path, so insert a buffer on the clock path.

[0138] In one feasible implementation, this embodiment further includes: for the violation paths that still exist after clock path adjustment, the following operations are performed: violation paths belonging to the same signal transmitter are grouped together to determine at least one violation path group; for one group, based on the ratio of the minimum setup time margin of each violation path in the group to the maximum delay of the buffer, the number of buffers to be inserted after the data output pin of the signal transmitter is determined; the number of buffers is inserted after the data output pin of the signal transmitter to perform data path adjustment.

[0139] In step S4 above, when clocking the violation path, timing is repaired in a way that minimizes the increase in components and power consumption, thereby improving chip yield while also considering chip area and power consumption, and reducing design costs.

[0140] Specifically, this embodiment also includes step S5: adjusting the data path.

[0141] After clock path adjustment in step S4, reducing clock skew can eliminate some timing violations, and larger timing violations can also be reduced to some extent. In this implementation, step S5 will further adjust the remaining violation paths. In existing EDA tools, a buffer is preferentially inserted before the D pin (data receive pin) of the receiving FF, but if... Figure 7 The path clearly shows that inserting a buffer after the Q pin (data transmit pin) that emits the FF can resolve more violations with less area increase. Therefore, as... Figure 8 Before using EDA tools to perform ECO, a data path adjustment process was added for the same transmitting FF to multiple receiving FFs (one-to-many data).

[0142] The specific implementation steps of step S5 are as follows: steps S51-S54:

[0143] Step S51: Group paths that transmit the same signal into a group and record them in the respective arrays. That is, group the violation paths belonging to the same signal transmitter to determine at least one violation path group.

[0144] Step S52: Calculate the number of buffers that can be inserted after the Q pin of the transmit FF. For any violation path group, calculate the number of setup time violations that will not occur in other timing paths that trigger the transmit FF after inserting the buffer. Specifically, the ratio of the minimum setup time margin of each violation path in the group to the maximum delay of the buffer is used as the number of buffers to be inserted; it can be expressed as: MIN(Setup slack) ÷ H_Buf max delay.

[0145] Step S53: Insert a buffer after the Q pin of FF.

[0146] Step S54: After the above data path adjustment, for any remaining violation paths, use the ECO command of the Electronic Design Automation (EDA) tool to adjust the data path of the remaining violation paths by inserting a buffer before the data pin of the signal receiver.

[0147] In step S5 of this embodiment, when adjusting the data path of the violation path, a priority repair step for the data one-to-many violation path is added on the basis of the original function of the EDA tool, so as to efficiently complete the timing repair work with the least amount of additional components.

[0148] In this embodiment, the timing characteristics of typical devices on the chip clock line under different voltages are verified to determine the voltage conversion coefficient between the non-signature condition SSHV (corresponding to the second voltage) and the signature condition SSLV (corresponding to the first voltage). Based on the signature condition derating factor and this voltage conversion coefficient, the corresponding non-signature condition derating factor is determined, thus generating the non-signature condition. Timing adjustments are then performed under this non-signature condition. Since this voltage conversion coefficient accurately quantifies the delay change ratio (delay ratio) of typical devices at high voltage (HV) and low voltage (LV) under slow process corner (SS), and this ratio can be directly mapped to the core parameter (derating factor) of STA verification, this embodiment enables timing adjustments for non-signature violation paths of the chip without increasing the signature condition in the process library. This avoids chip functional abnormalities caused by non-signature condition violations in actual chip applications, improving chip yield.

[0149] Example 2:

[0150] To address the problem of low chip yield caused by incomplete coverage of verification conditions in the process library in the prior art, and based on the same inventive concept as Embodiment 1, this application also provides a timing adjustment system for expanding chip verification conditions.

[0151] The specific structural diagram of the system is as follows: Figure 9 As shown, it includes the following functional units 91-94:

[0152] The delay ratio determination unit 91 determines the delay ratio of a typical device at a first voltage and a second voltage based on the delay limit of a typical device on the chip clock line at different voltages; the delay limit is determined by verifying the timing characteristics of the typical device at different voltages.

[0153] The condition conversion unit 92 is used to use the delay ratio as the voltage conversion coefficient between the first voltage and the second voltage, and to determine the non-approval condition derating factor for the second voltage based on the approval condition derating factor corresponding to the first voltage and the voltage conversion coefficient; the approval condition is a timing verification condition existing in a preset process library, and the non-approval condition is a timing verification condition not existing in the process library.

[0154] The violation path determination unit 93 determines the violation path under the non-signature condition derating factor corresponding to the second voltage based on the voltage conversion coefficient and the delay deviation under the signature condition; the delay deviation is the difference between the receive clock delay and the transmit clock delay on the timing path.

[0155] The violation path determination unit is specifically used to: compare the delay deviation of each clock path under the approval condition with a preset constraint value; for clock paths that maintain time violations under non-approval conditions, if the delay deviation of the clock path is greater than the constraint value, then the clock path is a violation path. The constraint value is determined based on the product of the voltage conversion coefficient and a preset delay deviation threshold.

[0156] The clock adjustment unit 94 reduces the receive clock delay by replacing devices and / or removing redundant buffers on the receive clock path; and increases the transmit clock delay by inserting buffers on the transmit clock path; and adjusts the clock path of the violation path by replacing the device with a device with a smaller delay than the original device, wherein the original device is connected to the clock pin of at least one signal receiver on the violation path.

[0157] The clock adjustment unit includes a receive clock adjustment subunit and a transmit clock adjustment subunit.

[0158] The receive clock adjustment subunit is specifically used for: traversing the signal receivers on the violation path, grouping each signal receiver whose clock pin is connected to the same device into a group to determine at least one signal receiver group; for any signal receiver group, performing the following: if the hold time margin of the corresponding clock path exceeds a set value when each signal receiver in the group acts as a signal transmitter, then it is initially determined to replace the device corresponding to the current group; calculating the area occupied by the buffer to be inserted when adjusting the data path of the violation path; if the area increased by replacing the device is less than the area occupied by the inserted buffer, then the device corresponding to the current group is replaced to reduce the receive clock delay; otherwise, the receive clock delay is reduced by removing redundant buffers on the receive clock path.

[0159] Reducing receive clock delay by removing redundant buffers on the receive clock path includes: calculating the number of buffers that can be removed when the hold time of the next-level clock path of each signal receiver in the current group is not violated, the number of buffers that need to be inserted when the hold time of the current-level clock path of each signal receiver in the current group is not violated, and the number of buffers that need to be removed to make the delay deviation less than the constraint value, and selecting the minimum value from each number of buffers as the number of redundant buffers to be removed.

[0160] The transmit clock adjustment subunit is specifically used to: traverse the signal transmitters on the violation path, group the signal transmitters whose clock pins are connected to the same device into a group to determine at least one group; for any group, perform the following: calculate the number of buffers that can be inserted when the hold time of the previous level clock path of each signal transmitter in the current group is not violated, the number of buffers that need to be inserted when the hold time of the current level clock path of each signal transmitter in the current group is not violated, and the number of buffers that need to be inserted to make the delay deviation less than the constraint value, and select the minimum value from each buffer number as the number of buffers that need to be inserted on the transmit clock path.

[0161] In one feasible implementation, the system of this embodiment further includes a data path adjustment unit, which is specifically used for: when there are still non-compliant paths after clock path adjustment of the non-compliant paths, setting non-compliant paths belonging to the same signal transmitter as a group to determine at least one non-compliant path group; for one group, determining the number of buffers to be inserted after the data output pin of the signal transmitter based on the ratio of the minimum establishment time margin of each non-compliant path in the group to the maximum delay of the buffer; and inserting the number of buffers after the data output pin of the signal transmitter to perform data path adjustment.

[0162] In one feasible implementation, the system of this embodiment further includes a tool adjustment unit, specifically used to: insert a buffer before the data pin of the signal receiver by means of electronic design automation tools when there is still an illegal path after the data path adjustment.

[0163] This embodiment verifies the timing characteristics of typical devices on the chip clock line under different voltages to determine the voltage conversion coefficient between the non-signature condition SSHV (corresponding to the second voltage) and the signature condition SSLV (corresponding to the first voltage). Based on the signature condition derating factor and this voltage conversion coefficient, the corresponding non-signature condition derating factor is determined, thus generating the non-signature condition. Timing adjustments are then performed under this non-signature condition. Since this voltage conversion coefficient accurately quantifies the delay change ratio (delay ratio) of typical devices at high voltage (HV) and low voltage (LV) under slow process corner (SS), and this ratio can be directly mapped to the core parameter (derating factor derate) of STA verification, this embodiment enables timing adjustments for non-signature violation paths on the chip without increasing the signature condition in the process library. This avoids chip functional abnormalities caused by non-signature conditions in actual chip applications, improving chip yield.

[0164] Based on the same inventive concept as the foregoing embodiments of this application, this application also provides a computing device.

[0165] like Figure 10As shown, the computing device includes a memory 1001 and a processor 1002. The memory 1001 can be configured to store various other data to support operation on the electronic device. Examples of such data include instructions for any application or method used to operate on the electronic device. The memory 1001 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0166] The processor 1002, coupled to the memory 1001, is used to execute the computer program stored in the memory 1001 to perform a timing adjustment method for expanding chip signature conditions as described in the foregoing embodiments.

[0167] When the processor 1002 executes the computer program to perform a timing adjustment method for expanding chip signature conditions, it verifies the timing characteristics of typical devices on the chip clock line under different voltages to determine the voltage conversion coefficient between the non-signature condition SSHV (corresponding to the second voltage) and the signature condition SSLV (corresponding to the first voltage). Based on the signature condition derating factor and the voltage conversion coefficient, the corresponding non-signature condition derating factor is determined, thus generating the non-signature condition, and timing adjustment is then performed under this non-signature condition. Since the voltage conversion coefficient accurately quantifies the delay change ratio (delay ratio) of typical devices under high voltage (HV) and low voltage (LV) at slow process corners (SS), and this ratio can be directly mapped to the core parameter (derating factor) of STA verification, this embodiment achieves timing adjustment of the chip for non-signature violation paths without increasing the signature conditions in the process library. This avoids chip functional abnormalities caused by non-signature conditions in actual chip applications, improving chip yield.

[0168] When the processor 1002 executes the computer program in the memory 1001, in addition to the functions described above, it can also perform other functions, as detailed in the descriptions of the preceding embodiments.

[0169] Furthermore, such as Figure 10 As shown, the computing device also includes other components such as a display 1004, a communication component 1003, a power supply component 1005, and an audio component 1006. Figure 10 The diagram only shows some components and does not mean that the computing device includes only these components. Figure 10 The components shown.

[0170] Accordingly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a computer, can implement the methods provided in the above embodiments.

[0171] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0172] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments.

[0173] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A timing adjustment method for expanding chip signature conditions, characterized in that, include: Based on the delay limits of typical devices on the chip clock line at different voltages, the delay ratio of typical devices at the first voltage and the second voltage is determined; the delay limits are determined by verifying the timing characteristics of the typical devices at different voltages. The delay ratio is used as the voltage conversion coefficient between the first voltage and the second voltage. Based on the derating factor of the approval condition corresponding to the first voltage and the voltage conversion coefficient, the derating factor of the non-approval condition corresponding to the second voltage is determined. The approval condition is a timing verification condition that exists in the preset process library, and the non-approval condition is a timing verification condition that does not exist in the process library. Based on the voltage conversion coefficient and the delay deviation under the verification conditions, the violation path under the non-verification condition derating factor corresponding to the second voltage is determined; the delay deviation is the difference between the receive clock delay and the transmit clock delay on the clock path; Reduce receive clock delay by replacing devices and / or removing redundant buffers in the receive clock path; In addition, the transmit clock delay is increased by inserting a buffer into the transmit clock path; the clock path of the violation path is adjusted by replacing the device with a device with a smaller delay than the original device, and the original device is connected to the clock pin of at least one signal receiver on the violation path.

2. The timing adjustment method for extended chip verification conditions according to claim 1, characterized in that, The method further includes: for violation paths that still exist after clock path adjustment, performing the following operations: Grouping violation paths belonging to the same signal transmitter into at least one violation path group; For one group, the number of buffers to be inserted after the data output pin of the signal transmitter is determined based on the ratio of the minimum establishment time margin of each violation path in the group to the maximum delay of the buffer; the number of buffers is inserted after the data output pin of the signal transmitter to perform data path adjustment.

3. The timing adjustment method for extended chip verification conditions according to claim 2, characterized in that, The method further includes: if, after the data path adjustment, there are still illegal paths, then: Using electronic design automation tools, a buffer is inserted before the data pin of the signal receiver.

4. The timing adjustment method for extended chip verification conditions according to claim 1, characterized in that, Based on the voltage conversion coefficient and the delay deviation under the approval conditions, the violation path under the non-approval condition derating factor corresponding to the second voltage is determined, including: Compare the delay deviation of each clock path under the verification conditions with the preset constraint value; For clock paths that maintain time violations under non-approval conditions, if the delay deviation of the clock path is greater than the constraint value, then the clock path is a violation path. The constraint value is determined based on the product of the voltage conversion coefficient and a predetermined delay deviation threshold.

5. The timing adjustment method for extended chip verification conditions according to claim 1, characterized in that, The method of reducing receive clock delay by replacing devices and / or removing redundant buffers on the receive clock path includes: Traverse the signal receivers on the violation path and group the signal receivers whose clock pins are connected to the same device to determine at least one group of signal receivers. For any signal receiver group, the following steps are performed: If the hold time margin of the corresponding clock path for each signal receiver in the group as a signal transmitter exceeds the set value, then it is initially determined that the device corresponding to the current group should be replaced; the area occupied by the buffer to be inserted when adjusting the data path of the violation path is calculated; if the area increased by replacing the device is less than the area occupied by the inserted buffer, then the device corresponding to the current group is replaced to reduce the receive clock delay; otherwise, the receive clock delay is reduced by removing redundant buffers on the receive clock path.

6. The timing adjustment method for extended chip verification conditions according to claim 5, characterized in that, The method of reducing receive clock latency by removing redundant buffers on the receive clock path includes: Calculate the number of buffers that can be removed when the hold time of the next-level clock path of each signal receiver in the current group is not violated, the number of buffers that need to be inserted when the hold time of the current-level clock path of each signal receiver in the current group is not violated, and the number of buffers that need to be removed to make the delay deviation less than the constraint value. Select the minimum value from each number of buffers as the number of redundant buffers to be removed.

7. The timing adjustment method for extended chip verification conditions according to claim 1, characterized in that, The method of increasing the transmit clock delay by inserting a buffer on the transmit clock path includes: Traverse the signal transmitters on the violation path and group the signal transmitters whose clock pins are connected to the same device to determine at least one group; For any group, perform the following: calculate the number of buffers that can be inserted when the hold time of the previous stage clock path of each signal transmitter in the current group is not violated, the number of buffers that need to be inserted when the hold time of the current stage clock path of each signal transmitter in the current group is not violated, and the number of buffers that need to be inserted to make the delay deviation less than the constraint value. Select the minimum value from each number of buffers as the number of buffers that need to be inserted on the transmit clock path.

8. A timing adjustment system for expanding chip verification conditions, characterized in that, include: The delay ratio determination unit determines the delay ratio of a typical device at a first voltage and a second voltage based on the delay limit of a typical device on the chip clock line at different voltages; the delay limit is determined by verifying the timing characteristics of the typical device at different voltages. The condition conversion unit is used to use the delay ratio as a voltage conversion coefficient between the first voltage and the second voltage, and to determine the non-approval condition derating factor for the second voltage based on the approval condition derating factor corresponding to the first voltage and the voltage conversion coefficient; the approval condition is a timing verification condition existing in a preset process library, and the non-approval condition is a timing verification condition not existing in the process library. The violation path determination unit determines the violation path under the non-signature condition derating factor corresponding to the second voltage based on the voltage conversion coefficient and the delay deviation under the signature condition; the delay deviation is the difference between the receive clock delay and the transmit clock delay on the timing path; The clock path adjustment unit reduces the received clock delay by replacing components and / or removing redundant buffers on the received clock path. In addition, the transmit clock delay is increased by inserting a buffer into the transmit clock path; the clock path of the violation path is adjusted by replacing the device with a device with a smaller delay than the original device, and the original device is connected to the clock pin of at least one signal receiver on the violation path.

9. An electronic device, characterized in that, include: A processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method as claimed in any one of claims 1-7.

10. A storage medium, characterized in that, include: The storage medium stores a program or instructions that, when executed by a processor, implement the steps of the method as described in any one of claims 1-7.

Images