A high-efficiency transmission USB link layer design

Abstract

The application relates to a USB transmission mode, in the data transmission process, a large number of air bubbles are usually generated due to waiting for handshaking, so as to cause the transmission speed to be reduced, a special synchronous FIFO buffer module is added between the upstream and downstream handshaking signals of the USB link layer, the ready signal is pulled high in advance when the FIFO is empty, so that the waiting time is reduced, the working clock frequency is improved, and in the example, the transmission speed can be increased by 20%.

Description

[0001] This invention relates to a USB transmission mode, and more particularly to transmission at the USB link layer. Background Technology

[0002] USB is a widely used universal serial bus protocol. It provides a high-speed, stable, and universal connection standard between computers and external devices. USB supports hot-swapping, allowing users to easily connect or disconnect devices at any time. It can connect various types of external devices, such as mice, keyboards, printers, and external hard drives, greatly enhancing the expandability and usability of computers. By using a unified interface standard, the USB protocol simplifies the process of device connection and data transfer, becoming an indispensable part of modern computer systems. However, this design has the following problems and drawbacks: during data transmission at the link layer, the handshake between upstream and downstream devices creates gaps, or "bubbles" of no data, which significantly reduces the data transmission rate. Summary of the Invention

[0003] To address the aforementioned problems, this invention provides an efficient link layer design aimed at eliminating bubbles generated during handshakes and improving transmission rates.

[0004] When transferring data via USB, a single transaction typically includes the transmission of a token packet, a data packet, and a handshake packet. To ensure that no data is lost during the transmission of each packet, a valid and ready signal handshake is usually used. However, this results in an excessively long combinational logic path, which reduces the clock frequency and thus slows down the transmission speed.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] S1. To address the clock frequency limitation issue caused by direct connection of traditional combinational logic to upstream and downstream devices, a dedicated synchronous FIFO buffer module is added between the upstream and downstream handshake signals of the USB link layer. This module performs a timing process on the upstream and downstream handshake signals, which not only segments the combinational logic path but also eliminates signal jitter caused by combinational logic transmission delay by sampling the edge of the synchronous signal through registers.

[0007] S2. Monitor the storage status of the FIFO in real time. When the FIFO is empty, pull the upstream ready signal high in advance to allow data to be cached in the FIFO and eliminate the bubbles caused by waiting for the ready signal to go high during the handshake.

[0008] S3. To ensure transmission stability, a FIFO full-state protection unit and a data verification mechanism are added. When the FIFO storage reaches the full threshold, the ready signal is automatically pulled low to suspend upstream data writing and avoid data overflow. At the same time, the upstream device is notified to suspend transmission through a feedback signal. After the FIFO data is read by the downstream, the ready signal is pulled high again to resume transmission.

[0009] S4. Protocol compatibility design: This design does not change the original protocol architecture and data format of the USB physical layer and transport layer, but only optimizes the handshake interaction logic and buffering mechanism of the link layer, which has good compatibility and portability. Attached Figure Description

[0010] The present invention will be further described in detail below with reference to the accompanying drawings.

[0011] Appendix Figure 1 This is the location of the design of this invention within the USB.

[0012] Appendix Figure 2 This is the design architecture of the present invention.

[0013] Appendix Figure 3 This indicates that the upstream ready signal has been raised in advance.

[0014] Appendix Figure 4 It is the handshake position in bubble-free transmission.

[0015] Appendix Figure 5 This is the upstream ready signal when bubble-free transmission is not used.

[0016] Appendix Figure 6 This is the handshake position when bubble-free transmission is not used. Detailed Implementation

[0017] This application discloses a solution for improving the data transmission rate of the USB link layer, which can eliminate bubbles caused by handshake during transmission and improve data transmission efficiency.

[0018] Example: The characteristic of this method is the elimination of air bubbles, specifically including the following steps:

[0019] S1. To ensure data stability when sending packets, a handshake mechanism needs to be established. When upstream data arrives, data will only be received when the ready signal goes high.

[0020] S2. To improve transmission speed, a FIFO is added between the upstream and downstream handshake signals for buffering.

[0021] S3. When the FIFO is empty, the upstream ready signal is pulled high in advance to allow data to be stored early, thereby eliminating bubbles. For example... Figure 4 As shown, in this example, eliminating bubbles can advance the handshake by 2 cycles and increase the transmission speed by 20%.

[0022] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. This application discloses a high-efficiency USB link layer design, which can improve the data transmission speed in USB. Its features include: Specifically, it includes the following: S1. In a first aspect, this disclosure provides a design to address clock frequency constraints. By adding a dedicated synchronous FIFO buffer module between the upstream and downstream handshake signals of the USB link layer, the upstream and downstream handshake signals are processed by timing, which not only segments the combinational logic path, but also eliminates signal jitter caused by combinational logic transmission delay by sampling the edge of the synchronization signal through registers; S2. In a second aspect, this disclosure provides a timing design to reduce handshake waiting time. By monitoring the FIFO's storage status in real time through a control module, when the FIFO is empty, the upstream ready signal is pulled high in advance, thereby allowing data to be cached in the FIFO and eliminating bubbles caused by waiting for the ready signal to go high during the handshake process; S3. Thirdly, this disclosure provides a design to ensure transmission stability. By adding a FIFO full-state protection unit and a data verification mechanism, when the FIFO storage reaches the full threshold, the ready signal is automatically pulled low to suspend upstream data writing and avoid data overflow; at the same time, a feedback signal is used to inform the upstream device to suspend transmission, and the ready signal is pulled high again to resume transmission after the FIFO data is read by the downstream.

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