A chip electrostatic discharge violation verification repair method and device, electronic equipment and storage medium

Abstract

The present disclosure provides a chip electrostatic discharge violation verification repair method and device, electronic equipment and storage medium, which simplifies the full-chip netlist data selectively, retains only the logic circuits with ESD risks, extracts the module layout information, imports the power domain area, and performs top-level power / ground network routing based on the simplified layout data, to construct simplified full-chip layout data that can be used for ESD protection verification in advance, so that the ESD protection verification work can be carried out in parallel with the module layout and routing work, ESD violation problems can be found and fed back in advance, the iteration and repair time window of ESD protection design is increased, the time and computing resources required for single verification are reduced, and the overall efficiency of full-chip ESD protection verification and violation repair is improved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit chip design technology, and more specifically, to a method, apparatus, electronic device, and storage medium for verifying and repairing chip electrostatic discharge violations. Background Technology

[0002] As integrated circuit manufacturing processes continue to evolve, the integration density of large-scale digital circuit chips continues to increase, leading to increasingly complex transistor counts, module counts, and power domain partitioning within the chips. During the chip physical design phase, electrostatic discharge (ESD) protection design and verification are crucial for ensuring chip reliability. Current ESD protection design and verification processes for large-scale digital circuit chips typically require the completion of basic chip layout and routing, and successful layout connectivity verification, before obtaining full-chip layout data directly usable for ESD protection verification. In other words, ESD protection verification largely depends on relatively complete and correctly connected full-chip layout data as input. Because top-level / bottom-level module layout and routing, and layout connectivity verification processes often require multiple rounds of iterative optimization, ESD protection verification can only be implemented in the later stages of the project.

[0003] However, with advanced process nodes, chip device density is increasing, the coupling relationships between power supply networks and logic modules are becoming more complex, and ESD inspection rules are becoming more cumbersome. In this situation, directly performing ESD protection verification using complete full-chip data not only consumes significant computing resources but also requires a long time for each verification, resulting in a slow feedback cycle for ESD protection issues. Consequently, although the overall chip project cycle may be long, the effective time allocated for iterative optimization and violation repair of ESD protection design is actually shorter, making it difficult to support multiple rounds of rapid verification and repair. Summary of the Invention

[0004] This disclosure provides at least one method, apparatus, electronic device, and storage medium for verifying and repairing chip electrostatic discharge violations. By selectively simplifying the full chip netlist data, only logic circuits with ESD risks are retained. Combined with module layout information extraction, power domain area import, and top-level power / ground network routing based on simplified layout data, simplified full chip layout data that can be used in advance for ESD protection verification is constructed. This allows ESD protection verification to be carried out in parallel with module layout and routing, enabling early detection and feedback of ESD violations, increasing the iteration and repair time window for ESD protection design, reducing the time and computing resources required for a single verification, and improving the overall efficiency of full chip ESD protection verification and violation repair.

[0005] This disclosure provides a method for verifying and repairing chip electrostatic discharge violations, including:

[0006] The full chip netlist data is acquired and parsed, logic circuits without electrostatic discharge risk are removed, and logic circuits with electrostatic discharge risk are retained to obtain simplified netlist data.

[0007] Perform full chip module layout and partitioning data generation, extract the physical location information of the remaining logic circuits in the simplified netlist data from the full chip module layout and partitioning data, and generate simplified full chip layout data based on the simplified netlist data and the physical location information;

[0008] Extract digital logic power domain area information from the full chip module layout and the partitioning data, and import the digital logic power domain area information into the simplified full chip layout data;

[0009] The simplified full-chip layout data and the complete full-chip layout data are set to correspond consistently in the preset electrostatic discharge protection design, and then the version is executed. Figure 1 Consistency verification was performed to determine simplified full-chip layout data;

[0010] Based on the simplified full-chip layout data and the digital logic power domain area information, top-level network routing is performed to generate routing data. Based on the simplified full-chip layout data and the routing data, full-chip electrostatic discharge protection verification is performed to determine electrostatic discharge violation results. Based on the electrostatic discharge violation results, the preset electrostatic discharge protection design is iteratively repaired.

[0011] In one optional implementation, the full-chip netlist data is acquired and parsed, logic circuits without electrostatic discharge risk are removed, and logic circuits with electrostatic discharge risk are retained to obtain simplified netlist data, specifically including:

[0012] Identify each logic circuit in the full-chip netlist data;

[0013] Based on the preset electrostatic discharge risk assessment rules, logic circuits associated with electrostatic discharge conduction paths, sensitive device distribution, power supply network coupling relationships, or electrostatic discharge protection structures are selected.

[0014] Delete logic circuits that do not meet the preset electrostatic discharge risk conditions, retain logic circuits that meet the preset electrostatic discharge risk conditions, and form the simplified full-chip netlist data as the simplified netlist data;

[0015] The simplified netlist data serves as the initial input data for the preset electrostatic discharge protection design and electrostatic discharge protection verification.

[0016] In one optional implementation, simplified full-chip layout data is generated based on the simplified netlist data and the physical location information, specifically including:

[0017] The physical location information is associated with the remaining logic circuits in the simplified netlist data.

[0018] Based on the association results, the simplified full-chip layout data, which includes logical connection relationships and physical location relationships, is constructed.

[0019] In one optional implementation, the physical location information includes at least one of module location, boundary range, and layout coordinate information;

[0020] The digital logic power domain area information includes at least one of the following: area range, area boundary, area coordinates, and area identifier corresponding to each digital logic power domain.

[0021] The winding data is the winding data of the top-level power or ground network simulated based on the simplified full-chip layout data and the digital logic power domain area information.

[0022] In one optional implementation, the version Figure 1 The consistency verification is a layout connectivity verification, used to confirm that the connection relationships in the simplified full-chip layout data meet the preset electrostatic discharge protection verification requirements.

[0023] The electrostatic discharge violation results include at least one of the following: violation location, violation path, violation type, and violation risk level.

[0024] In one optional implementation, the simplified full-chip layout data and the complete full-chip layout data are configured to correspond consistently in a preset electrostatic discharge protection design, specifically including:

[0025] The preset electrostatic discharge protection design is simultaneously imported into both the original complete full-chip layout data and the simplified full-chip layout data to ensure that the electrostatic discharge protection verification performed based on the simplified full-chip layout data has a consistent basis with the electrostatic discharge protection verification performed based on the complete full-chip layout data.

[0026] In one optional implementation, the preset electrostatic discharge protection design is iteratively repaired based on the electrostatic discharge violation result, specifically including:

[0027] The areas to be repaired are determined based on the results of the electrostatic discharge violations.

[0028] Adjust the electrostatic discharge protection structure or connection relationship corresponding to the area to be repaired;

[0029] The adjusted preset electrostatic discharge protection design is re-imported into the simplified full-chip layout data, and the version is executed again. Figure 1 The process continues from consistency verification to the full-chip electrostatic discharge protection verification until the preset electrostatic discharge protection verification requirements are met.

[0030] This disclosure also provides a verification and repair apparatus for chip electrostatic discharge violations, including:

[0031] The netlist stripping and simplification module is used to acquire and parse the full-chip netlist data, strip logic circuits without electrostatic discharge risk, and retain logic circuits with electrostatic discharge risk to obtain simplified netlist data.

[0032] The layout data simplification module is used to perform full chip module layout and partitioning data generation, extract the physical location information of the remaining logic circuits in the simplified netlist data from the full chip module layout and the partitioning data, and generate simplified full chip layout data based on the simplified netlist data and the physical location information.

[0033] The digital logic import module is used to extract digital logic power domain area information from the full chip module layout and the partitioning data, and import the digital logic power domain area information into the simplified full chip layout data.

[0034] The layout data simplification module is used to set the simplified full-chip layout data and the complete full-chip layout data to correspond consistently in the preset electrostatic discharge protection design, and then execute the layout data simplification module. Figure 1 Consistency verification was performed to determine simplified full-chip layout data;

[0035] The iterative repair module is used to perform top-level network routing based on the simplified full-chip layout data and the digital logic power domain area information, generate routing data, perform full-chip electrostatic discharge protection verification based on the simplified full-chip layout data and the routing data, determine electrostatic discharge violation results, and iteratively repair the preset electrostatic discharge protection design based on the electrostatic discharge violation results.

[0036] This disclosure also provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the above-described chip electrostatic discharge violation verification and repair method, or any possible implementation of the above-described chip electrostatic discharge violation verification and repair method, are performed.

[0037] This disclosure also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the above-described chip electrostatic discharge violation verification and repair method, or any possible implementation of the above-described chip electrostatic discharge violation verification and repair method.

[0038] This disclosure also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implements the above-described verification and repair method for chip electrostatic discharge violations, or the steps in any possible implementation of the above-described verification and repair method for chip electrostatic discharge violations.

[0039] This disclosure provides at least one method, apparatus, electronic device, and storage medium for verifying and repairing chip electrostatic discharge violations. By selectively simplifying the full chip netlist data, only logic circuits with ESD risks are retained. Combined with module layout information extraction, power domain area import, and top-level power / ground network routing based on simplified layout data, simplified full chip layout data that can be used in advance for ESD protection verification is constructed. This allows ESD protection verification to be carried out in parallel with module layout and routing, enabling early detection and feedback of ESD violations, increasing the iteration and repair time window for ESD protection design, reducing the time and computing resources required for a single verification, and improving the overall efficiency of full chip ESD protection verification and violation repair.

[0040] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. These drawings are incorporated in and constitute a part of this specification. They illustrate embodiments conforming to this disclosure and, together with the specification, serve to explain the technical solutions of this disclosure. It should be understood that the following drawings only show some embodiments of this disclosure and should not be considered as limiting the scope. Those skilled in the art can obtain other related drawings based on these drawings without creative effort.

[0042] Figure 1 One of the flowcharts of a verification and repair method for a chip electrostatic discharge violation provided in this disclosure is shown.

[0043] Figure 2 A second flowchart of a verification and repair method for a chip electrostatic discharge violation provided in an embodiment of this disclosure is shown;

[0044] Figure 3 A schematic diagram of a chip electrostatic discharge violation verification and repair apparatus provided in an embodiment of this disclosure is shown;

[0045] Figure 4 A schematic diagram of an electronic device provided in an embodiment of the present disclosure is shown. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0047] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0048] In this document, the term "and / or" merely describes a relationship, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0049] Research has revealed that at advanced process nodes, chip device density is increasing, the coupling relationships between power supply networks and logic modules are becoming more complex, and ESD inspection rules are becoming more cumbersome. In this context, directly performing ESD protection verification using complete, full-chip data not only consumes significant computing resources but also requires a long time for each verification, resulting in a slow feedback cycle for ESD protection issues. Consequently, while the overall chip project cycle may be lengthy, the effective time allocated for iterative optimization and violation repair of ESD protection design is actually limited, making it difficult to support multiple rounds of rapid verification and remediation.

[0050] Based on the above research, this disclosure provides a method, apparatus, electronic device, and storage medium for verifying and repairing chip electrostatic discharge violations. By selectively simplifying the full chip netlist data, only logic circuits with ESD risks are retained. Combined with module layout information extraction, power domain area import, and top-level power / ground network routing based on simplified layout data, simplified full chip layout data that can be used in advance for ESD protection verification is constructed. This allows ESD protection verification to be carried out in parallel with module layout and routing, enabling early detection and feedback of ESD violations, increasing the iteration and repair time window for ESD protection design, reducing the time and computing resources required for a single verification, and improving the overall efficiency of full chip ESD protection verification and violation repair.

[0051] To facilitate understanding of this embodiment, a detailed description of the chip electrostatic discharge violation verification and repair method disclosed in this disclosure embodiment will be provided first. The execution subject of the chip electrostatic discharge violation verification and repair method provided in this disclosure embodiment is generally a computer device with a certain computing capability. This computer device may include, for example, a terminal device, a server, or other processing device. The terminal device may be a user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, vehicle-mounted device, wearable device, etc. In some possible implementations, the chip electrostatic discharge violation verification and repair method can be implemented by the processor calling computer-readable instructions stored in memory.

[0052] See Figures 1-2 The diagram shows a flowchart of a chip electrostatic discharge violation verification and repair method provided in this embodiment of the present disclosure. The method includes steps S101 to S105, wherein:

[0053] S101. Obtain and parse the full chip netlist data, remove logic circuits without electrostatic discharge risk, retain logic circuits with electrostatic discharge risk, and obtain simplified netlist data.

[0054] In practice, the first step is to acquire the full-chip netlist data released during the front-end design phase. Full-chip netlist data can be digital circuit description data that characterizes the internal circuit connections, module hierarchy, and device instance information of the chip, such as gate-level netlists, synthesized netlists, or standard cell-level netlists used in the physical implementation phase.

[0055] Here, the full-chip netlist data typically includes top-level modules, multiple bottom-level functional modules, interconnections between modules, various logic unit instances, memory unit instances, interface unit instances, and network information related to power supply connections. By using the full-chip netlist data as input, basic circuit connection information can be provided for subsequent electrostatic discharge protection design and verification for the entire chip.

[0056] Specifically, after acquiring the full-chip netlist data, the data is parsed. A netlist reading program can be called to perform syntax parsing and hierarchical expansion of the netlist file, identifying module definitions, instance names, port connections, network names, power supply networks, grounding networks, and cross-module connections, and constructing the corresponding netlist data structure. The netlist data structure can be organized using a hierarchical tree, connection graph, instance table, netlist, or a combination thereof to facilitate subsequent filtering, marking, and stripping of different types of logic circuits.

[0057] Furthermore, after parsing, an electrostatic discharge (ESD) risk analysis is performed on the logic circuits in the full chip netlist data. This ESD risk analysis does not treat all logic circuits in the entire chip equally; rather, it assesses the correlation between each logic circuit and the ESD conduction path, the location of sensitive devices, the power supply network coupling, and the ESD protection structure, based on the requirements of ESD protection design and verification.

[0058] In other words, this step is not simply about deleting parts of the logic. Instead, it involves identifying which logic circuits might be involved in electrostatic discharge current conduction, affect the ESD path impedance distribution, be related to power domain boundaries, or have electrical coupling relationships with input / output interfaces and protection devices, focusing on the critical circuit range required for ESD protection verification. Logic circuits exhibiting these correlations are identified as having an electrostatic discharge risk; those not significantly related to electrostatic discharge conduction and protection verification are identified as having no electrostatic discharge risk.

[0059] In some implementations, logic circuits with electrostatic discharge risk may include: logic circuits that are directly or indirectly electrically connected to chip input / output ports; logic circuits associated with electrostatic discharge protection devices, clamping structures, or discharge paths; logic circuits coupled to power supply networks, grounding networks, or digital logic power domain boundaries; and sensitive logic units that may be subjected to abnormal voltage or current stress in the event of an electrostatic discharge.

[0060] Accordingly, logic circuits without electrostatic discharge risk may include: functional logic circuits that are used only to implement internal conventional logic functions and do not participate in critical electrostatic discharge conduction paths, are not directly related to ESD protection structures, and do not have a substantial impact on ESD verification results.

[0061] It should be noted that the absence of electrostatic discharge risk here is relative to the full-chip electrostatic discharge protection verification task to be performed by this invention. It means that this part of the circuit does not have a critical impact on the current ESD protection analysis and violation identification, but does not mean that it has no electrical effect in an absolute sense.

[0062] Furthermore, based on the above analysis results, selective stripping is performed on the full-chip netlist data. Specifically, logic circuits determined to have no electrostatic discharge risk can be deleted, bypassed, folded, or replaced with simplified connections according to preset screening rules, thereby removing them from the dataset for subsequent ESD protection design and verification; at the same time, logic circuits determined to have electrostatic discharge risk retain their module instances, network connections, and necessary hierarchical information.

[0063] Here, in order to ensure the effectiveness of subsequent ESD protection verification, it is preferable to retain the connection relationships related to the power supply network, grounding network, interface unit, ESD protection unit and key interconnection path when performing stripping, so as to avoid destroying the path continuity required for electrostatic discharge analysis due to oversimplification.

[0064] In a specific implementation process, the module instances in the parsed full-chip netlist data can be traversed first to extract the network connection, power supply terminal, grounding terminal, upstream and downstream connection relationship, and whether it is connected to the input / output interface or protection unit corresponding to each module instance. Then, each module instance is classified and marked according to the preset risk judgment conditions. Subsequently, the module instances marked as having no electrostatic discharge risk and their internal logic are stripped, while the module instances marked as having electrostatic discharge risk are retained, and the module connection relationship after stripping is reconstructed, thereby generating a simplified netlist data file or internal netlist database.

[0065] As one possible implementation, each logic circuit in the full-chip netlist data is identified; based on preset electrostatic discharge risk judgment rules, logic circuits associated with electrostatic discharge conduction paths, sensitive device distribution, power supply network coupling relationships, or electrostatic discharge protection structures are screened; logic circuits that do not meet the preset electrostatic discharge risk conditions are deleted, and logic circuits that meet the preset electrostatic discharge risk conditions are retained, forming simplified full-chip netlist data as simplified netlist data; wherein, the simplified netlist data serves as the initial input data for preset electrostatic discharge protection design and electrostatic discharge protection verification.

[0066] In this embodiment, the logic circuits in the full-chip netlist data are first identified. Specifically, the full-chip netlist file released during the front-end design stage can be obtained, and the full-chip netlist file can be parsed, its hierarchy expanded, and its connection relationships extracted to identify the top-level modules, bottom-level modules, functional unit instances, network nodes, and the connection relationships between the power supply and ground terminals in the netlist.

[0067] Here, the logic circuit may include interface logic connected to the input / output interface, functional logic coupled to the power supply network or grounding network, cross-module connection logic, timing logic, combinational logic, and connection branches associated with the electrostatic discharge protection unit, etc.

[0068] Furthermore, after identifying each logic circuit in the full chip netlist data, each logic circuit is screened according to a preset electrostatic discharge risk assessment rule. This preset electrostatic discharge risk assessment rule does not apply the same processing to all logic circuits on the chip, but rather focuses on assessing key factors relevant to the design and verification of electrostatic discharge protection.

[0069] Specifically, it can be determined whether the corresponding logic circuit is associated with the electrostatic discharge conduction path and whether it is located on a conduction path through which the electrostatic discharge current may pass; whether the corresponding logic circuit is associated with the distribution of sensitive devices and whether it may be subjected to overvoltage, overcurrent, or electrical stress due to local charge accumulation under electrostatic discharge events; whether the corresponding logic circuit is associated with the coupling relationship of the power supply network and whether it is coupled with the power domain boundary, power supply trunk, ground loop, or cross-power domain connection path; and whether the corresponding logic circuit is associated with the electrostatic discharge protection structure and whether it is connected to clamping devices, discharge channels, protection units, or their associated connection networks. Any logic circuit that meets any one or more of the above association conditions can be determined as a logic circuit that meets the preset electrostatic discharge risk conditions.

[0070] In some implementations, the logic circuit associated with the electrostatic discharge conduction path can be connection logic located near the chip's input, output, bidirectional port, or test port, or it can be an internal logic path that has a direct or indirect conductive relationship with the aforementioned ports. The logic circuit associated with the distribution of sensitive devices can be a logic path connected to thin-gate oxide devices, low-voltage devices, high-density interconnect regions, or surge-sensitive local functional units. The logic circuit associated with the power supply network coupling can be a logic circuit connected to the digital logic power domain boundary, main power trunk, ground network bus path, or cross-domain power supply interface. The logic circuit associated with the electrostatic discharge protection structure can be a logic portion that has a direct or indirect connection with the ESD clamping structure, protection diode, discharge branch, return path, or protection trigger unit.

[0071] S102. Execute full chip module layout and partitioning data generation, extract the physical location information of the remaining logic circuits in the simplified netlist data from the full chip module layout and partitioning data, and generate simplified full chip layout data based on the simplified netlist data and the physical location information.

[0072] In practical implementation, after selectively simplifying the aforementioned full-chip netlist data, the next step is to generate full-chip module layout and partitioning data. Specifically, based on the chip physical implementation process, layout planning and region partitioning can be performed on each functional module, sub-module, and its corresponding physical region in the full chip, forming full-chip module layout data that reflects the physical distribution of each module, as well as partitioning data that reflects the boundary attribution, region partitioning relationship, and hierarchical mapping relationship of each module.

[0073] Here, the full chip module layout data can include the placement position, occupied area, boundary outline, relative adjacency relationship, and layout information of each module in the chip layout; the partitioning data can include module partition identifier, area boundary definition, hierarchical mapping relationship, functional block affiliation relationship, and logical module index information corresponding to the physical area.

[0074] Furthermore, after obtaining the full-chip module layout data and partitioning data, the physical location information of the remaining logic circuits in the simplified netlist data is extracted from the full-chip module layout and partitioning data. Specifically, the remaining logic circuits in the simplified netlist data can first be identified as instances and located hierarchically to determine the module name, instance name, hierarchical path, or logical group identifier corresponding to each remaining logic circuit; then, the module name, instance name, hierarchical path, or logical group identifier is matched with the module layout information, region affiliation information, and hierarchical mapping information in the full-chip module layout and partitioning data to determine the physical location of each remaining logic circuit in the full chip.

[0075] Here, physical location information may include at least one of the following: the regional location, boundary range, coordinate location, relative adjacency, partition to which the corresponding logic circuit is located, and spatial relationship with other modules or power domains.

[0076] In some implementations, for any remaining logic circuit in the simplified netlist data, the corresponding functional module can be located first according to its netlist level, and then the physical region corresponding to the logic circuit can be determined according to the placement result of the functional module in the full chip module layout data. For logic circuits located near the module boundary, connected across regions, or with a strong interconnection relationship with the top layer, the specific distribution location or boundary relationship in the corresponding region can be determined by further combining the region boundary information, partition identification information, and connection mapping information in the partition data.

[0077] Furthermore, simplified full-chip layout data is generated based on simplified netlist data and physical location information. Specifically, the remaining logic circuits and their interconnections in the simplified netlist data can be used as the logical basis, and the extracted physical location information can be loaded onto the corresponding logic circuit instances, module nodes, or connection areas to construct a set of simplified full-chip layout data that combines logical connection attributes and physical layout attributes.

[0078] Here, the simplified full-chip layout data, compared to the original complete full-chip layout data, does not need to retain all logic circuits and their layout details that are irrelevant to ESD protection verification. Instead, it only retains the logic circuits that are relevant to ESD risk after screening and their physical distribution throughout the chip. Therefore, this simplified full-chip layout data can reflect the key logic paths and spatial relationships that are of concern in ESD protection verification, while effectively reducing the data scale involved in subsequent processing.

[0079] In a specific implementation, the simplified full-chip layout data can be generated in the following way: For each remaining logic circuit in the simplified netlist data, establish a mapping relationship between it and the corresponding module region in the full-chip module layout data; on this basis, associate the connection endpoints, network relationships, module affiliation, and hierarchical paths of the remaining logic circuit with the corresponding region coordinates, boundary ranges, and partition attributes; then, output the simplified full-chip layout file, internal database records, or intermediate layout description data according to a preset data organization format.

[0080] It's important to note that simplifying the full-chip layout data is not simply cutting down the complete full-chip layout data. Instead, it involves first performing ESD risk-oriented logic stripping at the netlist level, and then combining the full-chip module layout data and partitioning data to remap the remaining critical logic circuits into the full-chip physical space, resulting in dedicated layout data for ESD protection verification. In other words, this simplified full-chip layout data still maintains the physical authenticity corresponding to the actual chip module layout, while avoiding bringing a large amount of logic unrelated to ESD protection verification into the subsequent verification process, thus balancing the requirements of verification effectiveness and data lightweightness.

[0081] In this way, by extracting only the physical location information of the remaining logic circuits from the simplified netlist data in the full chip module layout and partitioning data, and constructing simplified full chip layout data accordingly, the data complexity of subsequent layout verification and ESD protection verification can be significantly reduced while retaining the key spatial distribution relationships required for electrostatic discharge protection verification. This provides favorable conditions for shortening the verification cycle, improving iteration efficiency, and reducing the consumption of computing resources.

[0082] S103. Extract digital logic power domain area information from the full chip module layout and the partitioning data, and import the digital logic power domain area information into the simplified full chip layout data.

[0083] In practice, after generating simplified full-chip layout data, digital logic power domain information is further extracted from the full-chip module layout and partitioning data. Specifically, the full-chip module layout data reflects the spatial distribution of each functional module, sub-module, and related physical area in the chip, while the partitioning data reflects the area boundaries, area affiliation, hierarchical mapping, and logical and physical correspondence between different partitions for each module.

[0084] Specifically, the process begins by traversing the physical regions within the full chip module layout data to identify the module affiliation, power supply attributes, and logic type of each region. Then, by combining the region identifiers, boundary definitions, hierarchical mapping relationships, and power supply affiliation information from the partitioned data, the power domain regions belonging to the digital logic modules are selected. For any given digital logic power domain, its region range, boundaries, location coordinates, region identifier, and boundary relationships with adjacent module regions can be further extracted, and this information is then used to define the digital logic power domain region information.

[0085] In some implementations, the digital logic power domain area information may include at least one of the following: the outer boundary outline of each digital logic power domain, the area coordinate range, the area center location, the module identifier, the power supply network identifier, the ground network affiliation, and the relative adjacency relationship with other power domains.

[0086] Here, for digital logic power domains with multiple independent power supply islands or cross-regional distribution, the connection relationships, merging relationships and boundary extension relationships between each sub-region can be further extracted so that the actual spatial structure of each power domain can be accurately reflected when the top-level power / ground network is routed.

[0087] Furthermore, after obtaining the digital logic power domain area information, the digital logic power domain area information is imported into the simplified full-chip layout data. Specifically, power domain identifiers, area boundary descriptions, and power supply attribution attributes can be added to the corresponding module areas, logic circuit instances, or layout partitions in the simplified full-chip layout data, so that the simplified full-chip layout data, while retaining the physical location information of the remaining logic circuits, further possesses the ability to express the area information of the digital logic power domain.

[0088] In a specific implementation, the import can be performed as follows: match the information of each digital logic power domain region with the corresponding module region in the simplified full chip layout data; assign the corresponding power domain region attributes to the remaining logic circuits located in the digital logic power domain region; for logic circuits distributed across power domain boundaries or close to the boundary, additionally record their boundary association and cross-domain connection relationships; if necessary, a power domain region layer, region identification table, or region mapping index can also be formed in the simplified full chip layout data for subsequent top-level power / ground network routing process.

[0089] It should be noted that importing the digital logic power domain area information into the simplified full-chip layout data is not to restore all the power supply implementation details of the complete full-chip layout, but rather to supplement the digital logic power supply area constraints closely related to ESD protection verification within the simplified data framework. Since subsequent top-level power / ground network routing and electrostatic discharge protection verification both need to consider the boundaries, distribution, and coupling relationships of different power supply areas, the extraction and import of digital logic power domain area information can ensure the necessary regional accuracy and engineering usability for subsequent ESD protection analysis while maintaining the advantages of data simplification.

[0090] Therefore, it should be noted that importing the digital logic power domain area information into the simplified full-chip layout data is not to restore all the power supply implementation details of the complete full-chip layout, but rather to supplement the digital logic power supply area constraints closely related to ESD protection verification within the simplified data framework. Since subsequent top-level power / ground network routing and electrostatic discharge protection verification both need to consider the boundaries, distribution, and coupling relationships of different power supply areas, the extraction and import of digital logic power domain area information can ensure the necessary regional accuracy and engineering usability for subsequent ESD protection analysis while maintaining the advantages of data simplification.

[0091] S104. Set the simplified full-chip layout data and the complete full-chip layout data to correspond consistently in the preset electrostatic discharge protection design, and execute version [version number missing]. Figure 1 Consistency verification was performed to determine simplified full-chip layout data.

[0092] In practical implementation, after importing the digital logic power domain area information, the simplified full-chip layout data and the complete full-chip layout data are further configured to correspond consistently in the preset electrostatic discharge protection design. Specifically, the complete full-chip layout data can be the complete layout data formed for the chip physical implementation process, including the module layout, connection relationships, power supply network related information, and corresponding layout representation within the entire chip; the simplified full-chip layout data is the dedicated layout data formed after selectively stripping the full-chip netlist with electrostatic discharge risk guidance and reconstructing it by combining module layout information and power domain area information.

[0093] Here, consistency in the preset electrostatic discharge protection design means establishing a consistent design mapping relationship for the protection structure, protection device, discharge path, return current relationship, interface protection connection relationship and related constraint information related to electrostatic discharge protection verification, in both simplified full-chip layout data and complete full-chip layout data.

[0094] In other words, the simplified full-chip layout data is not required to be identical to the complete full-chip layout data in all functional logic aspects. Rather, it requires that all critical design elements related to ESD protection design and verification be configured in both sets of data according to the same design intent, the same connection relationships, and the same protection constraints. This ensures that the simplified data accurately reflects the ESD protection design status in the complete data. Importing the ESD protection design simultaneously into both the original and simplified full-chip layout data guarantees that there are no differences between the simplified and complete data, thus ensuring the consistency of ESD protection verification.

[0095] In practical implementation, a preset electrostatic discharge (ESD) protection design can be loaded into both the complete full-chip layout data and the simplified full-chip layout data. The preset ESD protection design can include: the setting relationship of ESD protection devices, the connection relationship between interface ports and protection structures, the discharge path relationship between protection units and power supply networks and ground networks, ESD constraint relationships across modules or power domains, and protection rule parameters related to ESD verification.

[0096] Here, during the loading process, protection device instance mapping, protection network mapping, port connection mapping, and region association mapping can be established for the two sets of layout data respectively, so that the logic circuits, module regions, and power domain regions related to electrostatic discharge in the simplified full chip layout data all have ESD protection design attributes corresponding to the complete full chip layout data.

[0097] In some implementations, to achieve consistency, a corresponding identifier can be established for each type of ESD protection design object in the complete full-chip layout data, and this identifier can be synchronously written into the corresponding object in the simplified full-chip layout data. For example, information such as protection device number, protection network name, power supply domain affiliation, discharge path type, port association identifier, and constraint rule number can be synchronously associated with the two sets of data. For non-critical logic parts that exist in the complete layout data but have been removed from the simplified layout data, they are not required to be restored in the simplified layout data, but the ESD critical protection structures connected to them and their necessary boundary relationships are still retained and mapped.

[0098] Furthermore, after completing the above consistency settings, execute the version. Figure 1 Consistency verification was performed to determine simplified full-chip layout data. Specifically, the layout... Figure 1 Consistency verification is preferably layout connectivity verification, which is used to check whether the connection relationships between logic circuits, protection structures, power supply networks, ground networks and related area boundaries in the simplified full chip layout data meet the input requirements of subsequent electrostatic discharge protection verification.

[0099] Here, since the simplified full-chip layout data has already undergone ESD-free logic circuit stripping, the number of devices and connection scale involved in the verification is significantly reduced compared to the complete full-chip layout data. Therefore, the complexity of the consistency check can be significantly reduced when performing layout connectivity verification.

[0100] Specifically, the executable version Figure 1 During consistency verification, at least one or more of the following can be checked: whether the connection between the simplified retained logic circuit and its corresponding ESD protection structure is continuous; whether the connection between the protection device and the power supply network and ground network is correct; whether the digital logic power domain area attributes and the affiliation relationship of the related logic circuit are consistent; whether the critical ESD connection paths across modules, regions or power domains are complete; and whether the object mapping of the imported ESD protection design in the simplified full chip layout data is missing or conflicting.

[0101] When the above verification results meet the preset consistency requirements, the simplified full-chip layout data that has passed the verification can be determined as the simplified full-chip layout data, which can be used for subsequent top-level power / ground network routing and electrostatic discharge protection verification.

[0102] It's important to clarify that identifying simplified full-chip layout data doesn't mean the data has reached a state of completion suitable for final tape-out. Rather, it indicates that the data meets the input requirements for subsequent ESD protection verification in terms of ESD protection design consistency and layout connectivity. In other words, this simplified full-chip layout data is a dedicated intermediate layout data for electrostatic discharge protection verification. Its focus is on supporting subsequent rapid verification and iterative repair, not on replacing the complete full-chip layout in the final manufacturing output.

[0103] In this way, by setting the simplified full-chip layout data and the complete full-chip layout data to correspond consistently with the preset electrostatic discharge protection design, and then executing the version on the simplified layout data... Figure 1 Consistency verification can obtain simplified full-chip layout data suitable for subsequent rapid verification, while ensuring the accuracy of ESD protection design mapping. Compared with the method of directly conducting consistency checks and ESD verification based on complete full-chip layout data, this step can not only ensure the consistency and reference value of subsequent verification results, but also reduce the complexity of consistency checks, shorten the verification time, and accelerate the iteration pace.

[0104] S105. Perform top-level network routing based on the simplified full-chip layout data and the digital logic power domain area information to generate routing data. Perform full-chip electrostatic discharge protection verification based on the simplified full-chip layout data and the routing data to determine electrostatic discharge violation results. Iteratively repair the preset electrostatic discharge protection design based on the electrostatic discharge violation results.

[0105] In practice, after determining the simplified full-chip layout data, top-level network routing is performed based on the simplified full-chip layout data and digital logic power domain area information to generate routing data. Specifically, the simplified full-chip layout data has already been processed... Figure 1 Consistency verification can reflect the logical connection relationships, physical distribution relationships, and preset electrostatic discharge protection design information related to electrostatic discharge protection verification; digital logic power domain area information can characterize the spatial distribution, boundary constraints, and area affiliation of each digital logic power supply area in the whole chip.

[0106] Specifically, when performing the top-level network routing, the target direction, access relationship, and boundary crossing relationship of the top-level power trunk and ground network trunk corresponding to each power domain can be determined based on the regional range, regional boundary, regional adjacency relationship, and power supply affiliation relationship of each digital logic power domain. Then, combined with the location distribution of logic circuits, interface units, protection structures, and key connection paths retained in the simplified full-chip layout data, the top-level power / ground network connectivity relationship related to electrostatic discharge protection verification can be constructed.

[0107] Here, the top-level network routing does not require restoring all the metal wiring details in the complete chip layout, but focuses on generating a power supply network model that can support electrostatic discharge path analysis, protection path judgment, and violation identification.

[0108] In some implementations, the winding data may include at least one of the following: the top-level power backbone path corresponding to each digital logic power domain, the ground network return path, the boundary connection relationship between power domains, the connection relationship between the protection structure and the power supply network or ground network, and key network topology information related to the electrostatic discharge conduction path.

[0109] For protection paths distributed across power domains or critical logic circuits near regional boundaries, the cross-regional conduction relationship, return current direction, and boundary association attributes can be recorded in the winding data to accurately identify potential weaknesses during the subsequent full-chip electrostatic discharge protection verification.

[0110] It should be noted that the purpose of the wiring data is to provide input for ESD protection verification, and not to be used directly as the final layout tape-out data. In other words, the wiring data generated in this step is verification-type wiring data serving ESD protection analysis. Its focus is on reflecting the power supply and return network relationships related to ESD protection, rather than completely replacing the final wiring results of the physical implementation stage. The generated wiring data cannot be directly used for the final layout tape-out; it is only used for ESD protection verification. Furthermore, through actual project verification, its error compared to the verification results based on the full-chip layout can be controlled within 5%, and the verification results are relatively more pessimistic. This ensures that as long as the verification results of the simplified layout data are satisfactory, the verification results of the final complete full-chip layout will also meet the requirements.

[0111] Furthermore, after obtaining the wiring data, a full-chip electrostatic discharge (ESD) protection verification is performed based on the simplified full-chip layout data and the wiring data to determine the ESD violation result. Specifically, the logic circuits, interface units, protection structures, and region boundary relationships retained in the simplified full-chip layout data can be jointly analyzed with the top-level power / ground network topology in the wiring data to identify potential conduction paths, discharge paths, and protection coverage of the chip under ESD events. The relevant paths, connections, and structural configurations are then checked according to preset ESD protection verification rules to output the ESD violation result.

[0112] Here, the results of an electrostatic discharge violation may include at least one of the following: violation location, violation path, violation type, logic module or power domain associated with the violation, and violation severity.

[0113] Since this embodiment uses simplified full-chip layout data formed after selective simplification of the netlist, extraction of layout information and import of power domain information, rather than performing verification directly on the complete full-chip layout data, the number of devices and network size involved in the electrostatic discharge protection verification are significantly reduced.

[0114] Here, ESD protection verification is performed based on simplified full-chip layout data. Because circuit stripping has been performed, the time and computing resources required for running ESD protection verification are greatly reduced. According to comparisons with actual projects, the running time can be reduced by 70%, and the required computing resources can be reduced by 60%. Therefore, this embodiment can significantly improve verification efficiency and shorten the single-round feedback cycle while ensuring that the verification results have engineering reference value.

[0115] Furthermore, after determining the electrostatic discharge violation results, the preset electrostatic discharge protection design is iteratively repaired based on the results. Specifically, the target area, target protection path, target protection structure, or target connection relationship where the violation occurred can be located first based on the violation results; then, the corresponding violation can be analyzed to determine whether it is due to insufficient protection device configuration, discontinuous protection path, insufficient return current capability of power supply network or ground network, unreasonable cross-power domain boundary connection, or incomplete protection coverage in a local area; and then the preset electrostatic discharge protection design can be adjusted to address the corresponding problems.

[0116] Here, adjustments may include: adding or replacing protection devices, modifying the connection relationship between protection devices and the target network, adjusting the discharge path, optimizing the configuration of the protection structure near the power domain boundary, adjusting the connection relationship of the top-level power / ground network, or supplementing local protection units, etc.

[0117] After adjusting the preset electrostatic discharge (ESD) protection design, the updated design can be re-imported into the simplified full-chip layout data, and the top-level network routing and full-chip ESD protection verification can be performed again to verify the repair results. If ESD violations still exist after re-verification, the preset ESD protection design will be further adjusted based on the new violation results until the violations are eliminated or the preset ESD protection verification requirements are met.

[0118] It should be noted that the iterative repair in this embodiment is not limited to isolated processing of single violation points, but can combine the path characteristics, regional characteristics, and power domain boundary characteristics reflected by the violation results to optimize the relevant protection design as a whole. Especially for violations caused by top-level power / ground network distribution, cross-regional return paths, or the collaborative relationship of multiple protection units, iterative repair can be adjusted from the perspective of the entire path, the entire region, and the collaborative structure of the entire protection system to improve the repair effect and reduce rework.

[0119] In this way, by performing top-level network routing based on simplified full-chip layout data and digital logic power domain area information, and combining the generated routing data to carry out full-chip ESD protection verification and iterative repair, on the one hand, relatively pessimistic verification results can be obtained within an acceptable error range, thus providing a reliable reference for the final complete full-chip layout ESD protection design; on the other hand, it can significantly reduce the time and computing resources required for verification, shorten the violation feedback and repair iteration cycle, and improve the overall efficiency of full-chip ESD protection design and verification.

[0120] This disclosure provides a method for verifying and repairing chip electrostatic discharge violations. By selectively simplifying the full chip netlist data, only logic circuits with ESD risks are retained. Combined with module layout information extraction, power domain area import, and top-level power / ground network routing based on simplified layout data, simplified full chip layout data that can be used in advance for ESD protection verification is constructed. This allows ESD protection verification to be carried out in parallel with module layout and routing, enabling early detection and feedback of ESD violations. It also increases the iteration and repair time window for ESD protection design, reduces the time and computing resources required for a single verification, and improves the overall efficiency of full chip ESD protection verification and violation repair.

[0121] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0122] Based on the same inventive concept, this disclosure also provides a chip electrostatic discharge violation verification and repair device corresponding to the chip electrostatic discharge violation verification and repair method. Since the principle of the device in this disclosure for solving the problem is similar to the chip electrostatic discharge violation verification and repair method described above in this disclosure, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0123] Please see Figure 3 , Figure 3 This is a schematic diagram of a verification and repair device for chip electrostatic discharge violations provided in an embodiment of this disclosure. Figure 3 As shown in the figure, the chip electrostatic discharge violation verification and repair apparatus 300 provided in this embodiment includes:

[0124] The netlist stripping and simplification module 310 is used to acquire and parse the full-chip netlist data, strip logic circuits without electrostatic discharge risk, retain logic circuits with electrostatic discharge risk, and obtain simplified netlist data.

[0125] The layout data simplification module 320 is used to perform full chip module layout and partitioning data generation, extract the physical location information of the remaining logic circuits in the simplified netlist data from the full chip module layout and the partitioning data, and generate simplified full chip layout data based on the simplified netlist data and the physical location information.

[0126] The digital logic import module 330 is used to extract digital logic power domain area information from the full chip module layout and the partitioning data, and import the digital logic power domain area information into the simplified full chip layout data.

[0127] The layout data simplification module 340 is used to set the simplified full-chip layout data and the complete full-chip layout data to correspond and be consistent in the preset electrostatic discharge protection design, and to execute the layout data simplification module 340. Figure 1 Consistency verification was performed to determine simplified full-chip layout data.

[0128] The iterative repair module 350 is used to perform top-level network routing based on the simplified full-chip layout data and the digital logic power domain area information, generate routing data, perform full-chip electrostatic discharge protection verification based on the simplified full-chip layout data and the routing data, determine electrostatic discharge violation results, and iteratively repair the preset electrostatic discharge protection design based on the electrostatic discharge violation results.

[0129] The processing flow of each module in the device and the interaction flow between each module can be referred to the relevant descriptions in the above method embodiments, and will not be detailed here.

[0130] This disclosure provides a chip electrostatic discharge violation verification and repair device. By selectively simplifying the full chip netlist data, only logic circuits with ESD risks are retained. Combined with module layout information extraction, power domain area import, and top-level power / ground network routing based on simplified layout data, simplified full chip layout data that can be used in advance for ESD protection verification is constructed. This allows ESD protection verification to be carried out in parallel with module layout and routing, enabling early detection and feedback of ESD violations. This increases the iteration and repair time window for ESD protection design, while reducing the time and computing resources required for a single verification, thus improving the overall efficiency of full chip ESD protection verification and violation repair.

[0131] Corresponding to Figure 1 This disclosure also provides an electronic device 400, such as a method for verifying and repairing electrostatic discharge violations in chips. Figure 4 The diagram shown is a structural schematic of an electronic device 400 provided in an embodiment of this disclosure, including:

[0132] Processor 41, memory 42, and bus 43; memory 42 is used to store execution instructions, including main memory 421 and external memory 422; the main memory 421, also called internal memory, is used to temporarily store the computational data in processor 41, as well as the data exchanged with external memory 422 such as hard disk. Processor 41 exchanges data with external memory 422 through main memory 421. When the electronic device 400 is running, processor 41 and memory 42 communicate through bus 43, enabling processor 41 to execute... Figure 1 and Figure 2 The steps for verifying and repairing chip electrostatic discharge violations.

[0133] This disclosure also provides a computer-readable storage medium storing a computer program. When executed by a processor, the computer program performs the steps of the chip electrostatic discharge violation verification and repair method described in the above-described method embodiments. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0134] This disclosure also provides a computer program product, which includes computer instructions. When the computer instructions are executed by a processor, they can perform the steps of the chip electrostatic discharge violation verification and repair method described in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0135] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0136] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this disclosure, it should be understood that the disclosed device and method can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0137] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0138] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0139] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0140] Finally, it should be noted that the above-described embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A method for verifying and repairing electrostatic discharge violations in chips, characterized in that, include: The full chip netlist data is acquired and parsed, logic circuits without electrostatic discharge risk are removed, and logic circuits with electrostatic discharge risk are retained to obtain simplified netlist data. Perform full chip module layout and partitioning data generation, extract the physical location information of the remaining logic circuits in the simplified netlist data from the full chip module layout and partitioning data, and generate simplified full chip layout data based on the simplified netlist data and the physical location information; Extract digital logic power domain area information from the full chip module layout and the partitioning data, and import the digital logic power domain area information into the simplified full chip layout data; The simplified full-chip layout data and the complete full-chip layout data are set to correspond and be consistent in the preset electrostatic discharge protection design, and layout consistency verification is performed to determine the simplified full-chip layout data. Based on the simplified full-chip layout data and the digital logic power domain area information, top-level network routing is performed to generate routing data. Based on the simplified full-chip layout data and the routing data, full-chip electrostatic discharge protection verification is performed to determine electrostatic discharge violation results. Based on the electrostatic discharge violation results, the preset electrostatic discharge protection design is iteratively repaired.

2. The method according to claim 1, characterized in that, The full-chip netlist data is acquired and parsed, logic circuits without electrostatic discharge (ESD) risk are removed, and logic circuits with ESD risk are retained to obtain simplified netlist data, specifically including: Identify each logic circuit in the full-chip netlist data; Based on the preset electrostatic discharge risk assessment rules, logic circuits associated with electrostatic discharge conduction paths, sensitive device distribution, power supply network coupling relationships, or electrostatic discharge protection structures are selected. Delete logic circuits that do not meet the preset electrostatic discharge risk conditions, retain logic circuits that meet the preset electrostatic discharge risk conditions, and form the simplified full-chip netlist data as the simplified netlist data; The simplified netlist data serves as the initial input data for the preset electrostatic discharge protection design and electrostatic discharge protection verification.

3. The method according to claim 1, characterized in that, Simplified full-chip layout data is generated based on the simplified netlist data and the physical location information, specifically including: The physical location information is associated with the remaining logic circuits in the simplified netlist data. Based on the association results, the simplified full-chip layout data, which includes logical connection relationships and physical location relationships, is constructed.

4. The method according to claim 1, characterized in that: The physical location information includes at least one of module location, boundary range, and layout coordinate information; The digital logic power domain area information includes at least one of the following: area range, area boundary, area coordinates, and area identifier corresponding to each digital logic power domain. The winding data is the winding data of the top-level power or ground network simulated based on the simplified full-chip layout data and the digital logic power domain area information.

5. The method according to claim 1, characterized in that: The layout consistency verification is a layout connectivity verification, used to confirm that the connection relationship in the simplified full chip layout data meets the preset electrostatic discharge protection verification requirements. The electrostatic discharge violation results include at least one of the following: violation location, violation path, violation type, and violation risk level.

6. The method according to claim 1, characterized in that, Setting the simplified full-chip layout data and the complete full-chip layout data to correspond consistently in the preset electrostatic discharge protection design specifically includes: The preset electrostatic discharge protection design is simultaneously imported into the original complete full-chip layout data and the simplified full-chip layout data to ensure that the electrostatic discharge protection verification performed based on the simplified full-chip layout data has a consistent basis with the electrostatic discharge protection verification performed based on the complete full-chip layout data.

7. The method according to claim 1, characterized in that, Based on the electrostatic discharge violation results, the preset electrostatic discharge protection design is iteratively repaired, specifically including: The areas to be repaired are determined based on the results of the electrostatic discharge violations. Adjust the electrostatic discharge protection structure or connection relationship corresponding to the area to be repaired; The adjusted preset electrostatic discharge protection design is re-imported into the simplified full-chip layout data, and the layout consistency verification to the full-chip electrostatic discharge protection verification steps are performed again until the preset electrostatic discharge protection verification requirements are met.

8. A verification and repair device for chip electrostatic discharge violations, characterized in that, include: The netlist stripping and simplification module is used to acquire and parse the full-chip netlist data, strip logic circuits without electrostatic discharge risk, and retain logic circuits with electrostatic discharge risk to obtain simplified netlist data. The layout data simplification module is used to perform full chip module layout and partitioning data generation, extract the physical location information of the remaining logic circuits in the simplified netlist data from the full chip module layout and the partitioning data, and generate simplified full chip layout data based on the simplified netlist data and the physical location information. The digital logic import module is used to extract digital logic power domain area information from the full chip module layout and the partitioning data, and import the digital logic power domain area information into the simplified full chip layout data. The layout data simplification module is used to set the simplified full-chip layout data and the complete full-chip layout data to correspond and be consistent in the preset electrostatic discharge protection design, and to perform layout consistency verification to determine the simplified full-chip layout data. The iterative repair module is used to perform top-level network routing based on the simplified full-chip layout data and the digital logic power domain area information, generate routing data, perform full-chip electrostatic discharge protection verification based on the simplified full-chip layout data and the routing data, determine electrostatic discharge violation results, and iteratively repair the preset electrostatic discharge protection design based on the electrostatic discharge violation results.

9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, they perform the steps of the verification and repair method for chip electrostatic discharge violations as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the verification and repair method for chip electrostatic discharge violations as described in any one of claims 1 to 7.

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