Selection and subsystem design method, system and storage medium of SRAM

Abstract

The application belongs to the technical field of processors, and particularly relates to a selection and subsystem design method, system and storage medium for SRAM. The selection and subsystem design method comprises the following steps: obtaining system specification information of a target processor storage system, analyzing the system specification information to generate a corresponding access model and a hard constraint set; screening SRAM macros that meet the hard constraint set from a preset storage compiler or PDK macro library, and then simulating and rescreening the screened SRAM macros through the access model, and standardizing macro-level features of the rescreened SRAM macros; matching SRAM macros from an SRAM macro candidate set based on bandwidth requirements and concurrent access requirements in the system specification information, and automatically generating multiple groups of SRAM subsystem topology candidates. Compared with the prior art, the application can realize rapid landing, stable signing and production reuse of the SRAM subsystem.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to a method, system, and storage medium for selecting and designing an SRAM subsystem. Background Technology

[0002] The on-chip memory subsystem is a core component of the RISC-V processor. Its design quality directly determines the processor's memory bandwidth density, timing performance, power consumption control, and mass production reliability. The selection of SRAM macros is a crucial preliminary step in the memory subsystem design. At advanced process nodes, Process Design Kits (PDKs) and memory compilers provide a vast number of SRAM macro resources. These SRAM macros cover various combinations of capacities, bit widths, number of ports, threshold voltages (Vt), error correction code (ECC) support features, and read / write timing parameters, adapting to the diverse memory needs of RISC-V processors. However, this also presents a challenge to the accurate selection of SRAM macros.

[0003] Currently, the mainstream implementation schemes for SRAM selection and subsystem construction for RISC-V processors in the industry are mainly divided into three categories: The first is the experience-driven manual selection and EDA (Electronic Design Automation) trial process. Designers use tables, scripts, and other methods to manually select SRAM macros that meet basic requirements such as capacity and ports based on engineering experience. Then, they verify the selection through multiple rounds of automated place and route (APR), static timing analysis (STA), and power consumption analysis. The verification results drive repeated adjustments to the SRAM macro and subsystem structure. The second is the rule- or template-driven parameterized selection framework. Based on preset fixed rules (such as fixed bank size and fixed port reuse ratio), the SRAM subsystem topology is generated to achieve rapid matching of SRAM macros. The third is the recommended configuration scheme built into the storage compiler. Based on the single macro level parameters of the SRAM macro and typical process-voltage-temperature (PVT) data, the compiler provides macro-level recommended configurations, providing a basic reference for selection.

[0004] While the existing solutions mentioned above can complete basic SRAM selection and subsystem construction in practical engineering applications, they all have significant technical shortcomings and are no longer able to meet the efficiency, accuracy, and reliability requirements of RISC-V processors under advanced processes for memory subsystem design. First, the physical and timing awareness stages are generally postponed. Whether manual or rule-based selection, it is impossible to accurately predict risks such as timing margin and physical congestion in the early stages of design. Multiple rounds of Engineering Change Orders (ECOs) are required to achieve design convergence, resulting in high design iteration costs and long cycles. Second, multi-objective optimization capabilities are insufficient. There are complex interrelationships between timing, power consumption, area (PPA), reliability, and implementation cost in SRAM subsystem design. Experience-driven or fixed-rule-driven approaches are unlikely to consistently achieve near-Pareto fronts. While the optimal solution (Frontier) is available, the overall performance of the design results is limited. Furthermore, existing SRAM selection methods cannot consider physical implementation risks (such as routing congestion and voltage drop) in the early design stages, requiring several rounds or even weeks of placement and routing iterations to expose and fix them. Secondly, the lack of upfront assessment of physical reliability risks means that core reliability risks such as infrared voltage drop (IRDrop), electromigration (EM), and layout congestion often only surface in the later physical implementation stages, easily leading to large-scale design rework and significantly accumulating project development risks. In addition, the integration of Design for Testability (DFT) and ECC is weak. Testing and error correction interfaces are highly coupled with timing constraints and power domain configurations. Existing solutions require deep manual involvement in this integration work, easily leading to configuration inconsistencies and low approval rates. Finally, cross-process adaptability is weak. When process nodes or SRAM macro library versions change, existing solutions require rebuilding engineering experience and supporting scripts, hindering rapid technology migration and resulting in poor engineering reusability, further increasing development costs in multi-project, multi-process scenarios.

[0005] Therefore, there is an urgent need for a new SRAM selection and subsystem design method, system, and storage medium to solve the above-mentioned technical problems. Summary of the Invention

[0006] This invention provides a method, system, and storage medium for SRAM selection and subsystem design, aiming to solve technical problems in the prior art such as high iteration costs, poor optimization effects, insufficient reliability risk management, weak integration, and poor adaptability, and to meet the customized storage system design needs of complex chips such as RISC-V processors under advanced processes.

[0007] In a first aspect, the present invention provides a method for selecting SRAM and designing a subsystem, the method comprising the following steps:

[0008] S1. Obtain the system specification information of the target processor's storage system, parse the system specification information to generate the corresponding access model and hard constraint set, the system specification information includes the SRAM capacity, bit width, port characteristics and concurrent access requirements information.

[0009] S2. Select SRAM macros that meet the set of hard constraints from the preset storage compiler or PDK macro library, and then perform simulation screening on the selected SRAM macros through the access model. Standardize the macro-level features of the qualified SRAM macros to obtain a candidate set of SRAM macros.

[0010] S3. Based on the bandwidth requirements and concurrent access requirements in the system specification information, match SRAM macros from the SRAM macro candidate set and automatically generate multiple sets of SRAM subsystem topology candidates.

[0011] S4. Perform approximate static timing analysis, power consumption estimation, and area assessment on each group of SRAM subsystem topology candidates using a pre-trained evaluation model. Simultaneously, predict the physical reliability risk of each group of SRAM subsystem topology candidates to obtain a comprehensive evaluation result corresponding to each group of SRAM subsystem topology candidates. The input of the evaluation model includes the encoded representation of the interface control logic generated based on the access model.

[0012] S5. Based on the comprehensive evaluation results, the SRAM subsystem topology candidates are iteratively searched using a multi-objective optimization algorithm to obtain the optimal SRAM subsystem target scheme.

[0013] S6. Generate the corresponding constraint file, interface configuration script and functional logic configuration file according to the target scheme of the SRAM subsystem.

[0014] Preferably, step S4 includes the following sub-steps: S41. Encode the SRAM subsystem topology candidates to obtain encoded data; S42. The encoded data is used as input to the evaluation model for evaluation to obtain a feature vector; wherein the feature vector includes the estimated worst-case negative timing margin, the estimated total dynamic power consumption, the estimated total area, the physical congestion risk score, and the infrared voltage drop risk score. S43. The comprehensive evaluation result is obtained by calculating based on the feature vector using the weighted cost function; S44. When the physical congestion risk score or infrared voltage drop risk score exceeds a preset threshold, the corresponding SRAM subsystem topology candidate is removed.

[0015] Preferably, the SRAM subsystem topology candidates include a bank size partitioning strategy, a port mapping strategy, a time-division multiplexing strategy, and a logical replication strategy.

[0016] Preferably, the physical reliability risks include physical congestion risks, infrared voltage drop risks, and electromigration risks.

[0017] Secondly, the present invention also provides an SRAM selection and subsystem design system, the selection and subsystem design system comprising: The parsing module is used to obtain the system specification information of the target processor's storage system, and to parse the system specification information to generate a corresponding access model and hard constraint set. The system specification information includes the SRAM capacity, bit width, port characteristics, and concurrent access requirements.

[0018] The filtering module is used to filter out SRAM macros that meet the set of hard constraints from a preset storage compiler or PDK macro library, and then perform simulation re-screening on the filtered SRAM macros through the access model. The macro-level features of the SRAM macros that pass the re-screening are standardized to obtain a candidate set of SRAM macros.

[0019] The matching module is used to match SRAM macros from the SRAM macro candidate set based on the bandwidth requirements and concurrent access requirements in the system specification information, and automatically generate multiple sets of SRAM subsystem topology candidates.

[0020] The evaluation module is used to perform approximate static timing analysis, power consumption estimation, and area evaluation on each group of SRAM subsystem topology candidates using a pre-trained evaluation model. It also predicts the physical reliability risk of each group of SRAM subsystem topology candidates and obtains a comprehensive evaluation result for each group of SRAM subsystem topology candidates. The input of the evaluation model includes the encoded representation of the interface control logic generated based on the access model.

[0021] The optimization module is used to iteratively search the SRAM subsystem topology candidates based on the comprehensive evaluation results using a multi-objective optimization algorithm to obtain the optimal SRAM subsystem target scheme.

[0022] The generation module is used to generate corresponding constraint files, interface configuration scripts, and functional logic configuration files based on the target scheme of the SRAM subsystem.

[0023] Preferably, the evaluation module includes the following sub-units: An encoding unit is used to encode the SRAM subsystem topology candidates to obtain encoded data; An evaluation unit is used to evaluate the encoded data as input to the evaluation model to obtain a feature vector; wherein the feature vector includes the estimated worst-case negative timing margin, the estimated total dynamic power consumption, the estimated total area, the physical congestion risk score, and the infrared voltage drop risk score. The calculation unit is used to calculate the comprehensive evaluation result based on the feature vector according to the weighted cost function; The elimination unit is used to eliminate the corresponding SRAM subsystem topology candidate when the physical congestion risk score or infrared voltage drop risk score exceeds a preset threshold.

[0024] Preferably, the SRAM subsystem topology candidates include a bank size partitioning strategy, a port mapping strategy, a time-division multiplexing strategy, and a logical replication strategy.

[0025] Preferably, the physical reliability risks include physical congestion risks, infrared voltage drop risks, and electromigration risks.

[0026] Thirdly, the present invention also provides a computer device, including: a memory, a processor, and an SRAM selection and subsystem design program stored in the memory and executable on the processor, wherein when the processor executes the SRAM selection and subsystem design program, it implements the steps in the SRAM selection and subsystem design method as described in any of the above embodiments.

[0027] Fourthly, the present invention also provides a computer-readable storage medium storing an SRAM selection and subsystem design program, wherein when the SRAM selection and subsystem design program is executed by a processor, it implements the steps in the SRAM selection and subsystem design method as described in any of the above embodiments.

[0028] Compared to existing technologies, this invention, through pre-emptive physical and timing awareness, identifies physical reliability risks such as infrared voltage drop and electromigration in the early stages of SRAM subsystem design, improving the ability to manage reliability risks. Simultaneously, it significantly reduces the number of iterations for automated placement and routing (APR) and engineering change instructions, accelerating design convergence. Through a multi-objective optimization algorithm, it stably outputs solutions approaching the Pareto front, achieving optimal timing, power consumption, and area, resulting in superior optimization performance. Based on the target SRAM subsystem solution, it directly generates backend-usable constraint and interface files, effectively improving the integration efficiency of the SRAM subsystem, thereby enabling rapid deployment, stable approval, and mass production reuse of the SRAM subsystem. Furthermore, by introducing an evaluation model trained on physical approval data during the design architecture selection phase, this invention reduces the actual number of Auto Place and Route (APR) iterations required, thereby improving the overall efficiency of the computer system executing the design process. Attached Figure Description

[0029] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1 This is a flowchart of the SRAM selection and subsystem design method provided in the embodiments of the present invention; Figure 2 This is a schematic diagram of the SRAM selection and subsystem design system provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0031] Example 1 Please refer to Figure 1 This invention provides a method for selecting SRAM and designing a subsystem, the method comprising the following steps: S1. Obtain the system specification information of the target processor's storage system, parse the system specification information to generate the corresponding access model and hard constraint set, the system specification information includes the SRAM capacity, bit width, port characteristics and concurrent access requirements information.

[0032] In this embodiment of the invention, the invention transforms the unstructured storage requirements of the RISC-V processor system into a quantifiable, executable standardized access model and an inviolable set of hard constraints, providing a unified input benchmark for the entire process of selection, design and optimization.

[0033] In this embodiment of the invention, the access model is used to simulate system specification information. The generated precise timing access model provides a high-level functional description, simplifies memory interactions, and thus improves design verification and simulation efficiency. The access model manages core tasks such as data storage, read / write operations, and error checking, enabling engineers to verify controller logic without complex physical hardware. Simultaneously, the access model can accurately propagate latency and establish / hold constraints to precisely simulate actual hardware performance.

[0034] The system specifications include SRAM capacity, bit width, port characteristics, and concurrent access requirements. The set of hard constraints includes: Hard functional constraints: minimum capacity threshold, upper and lower limits of bit width, port type requirements, read / write concurrent access support requirements, and ECC / DFT function enable requirements.

[0035] Timing hard constraints: minimum operating frequency, input / output setup and hold time requirements relative to the system clock interface, number of clock domains and cross-clock domain requirements.

[0036] Physical hard constraints: maximum layout area, layout area boundary, minimum macrocell spacing requirement, power domain partitioning rules.

[0037] Hard constraints on power consumption: maximum dynamic power consumption, maximum leakage power consumption, and operating voltage range.

[0038] S2. Select SRAM macros that meet the set of hard constraints from the preset storage compiler or PDK macro library, and then perform simulation screening on the selected SRAM macros through the access model. Standardize the macro-level features of the qualified SRAM macros to obtain a candidate set of SRAM macros.

[0039] In this embodiment of the invention, by traversing all SRAM macros in the storage compiler or PDK macro library and matching the set of hard constraints one by one, macros that do not meet the requirements are filtered out: for example, if the hard constraint requires true dual-port, then all single-port and pseudo-dual-port macros are directly excluded; if the hard constraint requires the maximum area to not exceed 1mm², then all macros with an area exceeding the limit are directly excluded.

[0040] After the initial screening is completed, a secondary screening is performed based on the access model. The implicit hard constraints that meet the performance requirements are output through simulation as supplementary filtering conditions for the initial screening of SRAM macros. Invalid macros that cannot adapt to the real load are directly filtered out, narrowing the candidate range and reducing invalid calculations in subsequent stages.

[0041] In this embodiment of the invention, the macro-level features of the SRAM macro include: Basic specifications: capacity, bit width, number of ports, port type, address line bit width, data line bit width.

[0042] Timing characteristics: Address access time, data setup / hold time, minimum clock cycle, and maximum operating frequency under the process-voltage-temperature (PVT) angle.

[0043] Power consumption characteristics: dynamic power consumption during read / write operations under typical PVT angles, standby leakage power consumption, and power consumption leakage in shutdown mode.

[0044] Physical characteristics: layout width, height, total area, pin distribution, row height, layout proximity rules, minimum layout spacing.

[0045] Features: ECC support type, BIST built-in self-test support, scan chain compatibility, power gating support.

[0046] After the macro-level features of the qualified SRAM macros are standardized, each SRAM macro corresponds to an N-dimensional feature vector in a unified format (N is the total number of feature dimensions), thereby eliminating the impact of dimensional differences on subsequent evaluation and matching, and facilitating rapid retrieval, matching and calling in subsequent steps.

[0047] S3. Based on the bandwidth requirements and concurrent access requirements in the system specification information, match SRAM macros from the SRAM macro candidate set and automatically generate multiple sets of SRAM subsystem topology candidates.

[0048] In this embodiment of the invention, in this step, the invention provides precise transaction-level timing diagrams and protocol specifications required for generating time-division multiplexing (TDM), port mapping, and bank interleaving control logic through an access model. The access model ensures that the encapsulation logic corresponding to the generated SRAM subsystem topology candidates can meet the specific concurrent access patterns defined in the system specifications and strictly adhere to the setup / hold time constraints of the underlying SRAM macros.

[0049] Based on the bandwidth requirements and concurrent access requirements, SRAM macros are matched from the SRAM macro candidate set. The SRAM subsystem topology candidates include bank size partitioning strategies, port mapping strategies, time-division multiplexing strategies, and logical replication strategies. Furthermore, the insertion position of interface bridging logic (such as FIFO or CDC) is automatically suggested based on the physical layout environment. Wherein: Bank Size Partitioning Strategy: Based on total capacity requirements, this invention generates all compliant Bank partitioning schemes. The capacity of a single Bank must match the standard capacity of the SRAM macro in the S2 candidate set, conforming to conventional address decoding design rules. Each scheme corresponds to a different Bank size and concurrent access conflict avoidance capability. During the generation process, SRAM macros with corresponding capacities in the candidate set are matched synchronously, eliminating partitioning schemes without corresponding macro support, ensuring that all schemes are feasible for implementation.

[0050] Port mapping strategy: Map the access ports of the RISC-V system bus to the physical ports of the SRAM macro. For example, map the system's read and write ports to the independent read and write ports of the pseudo-dual-port SRAM, or map them to single-port SRAMs in different banks through address decoding logic to achieve conflict dispersion of concurrent access.

[0051] Time Division Multiplexing (TDM) Strategy: For high-frequency, low-concurrency scenarios, a time division multiplexing timing control strategy is generated to double the working clock of the SRAM macro, and complete the read and write operations in time division within one system clock cycle. The single-port SRAM is used to simulate the function of pseudo dual-port, reducing area and power consumption while meeting basic access requirements.

[0052] Logical copying strategy: For high-concurrency read access scenarios (such as the multi-issue instruction cache of RISC-V processors), an SRAM macro copying scheme is generated to copy the same storage content to multiple sets of SRAM macros. Each set of macros corresponds to an independent instruction fetch port, realizing conflict-free concurrent read access and significantly improving instruction fetch bandwidth.

[0053] S4. Perform approximate static timing analysis, power consumption estimation, and area assessment on each group of SRAM subsystem topology candidates using a pre-trained evaluation model. Simultaneously, predict the physical reliability risk of each group of SRAM subsystem topology candidates to obtain a comprehensive evaluation result corresponding to each group of SRAM subsystem topology candidates. The input of the evaluation model includes the encoded representation of the interface control logic generated based on the access model.

[0054] In this embodiment of the invention, the access model works in conjunction with a pre-trained evaluation model. While the evaluation model provides rapid predictions of path latency and physical risks, the access model is used to perform lightweight functional verification on the generated interface logic. The access model can detect protocol violations in complex scenarios that are not visible in static timing analysis, such as read-modify-write sequences or cross-clock domain (CDC) handshake logic in ECC integration.

[0055] In this embodiment of the invention, step S4 includes the following sub-steps: S41. Encode the SRAM subsystem topology candidates to obtain encoded data. By encoding the SRAM subsystem topology candidates, they are converted into a unified representation suitable for evaluation model inference. This representation can be changed as needed; for example, it can be a graph structure (nodes are SRAM macros, edges are routing channels) or a tokenized sequence describing netlist and layout constraints.

[0056] S42. The encoded data is used as input to the evaluation model for evaluation to obtain a feature vector; wherein the feature vector includes the estimated worst-case negative time margin (WNS), the estimated total dynamic power consumption (mW), the estimated total area (μm²), the physical congestion risk score, and the infrared voltage drop risk score. The architecture of the evaluation model can be selected according to the design scale and required accuracy. For example, the evaluation model architecture includes, but is not limited to: graph neural networks (GNNs) for learning physical proximity and congestion patterns; attention-based sequence models (such as Transformer or large language models) for modeling long-distance temporal dependencies; and state-space models (SSMs) or cyclic state-space hybrid models (such as Mamba or Jamba architectures) for efficient linear-time processing of lengthy netlist sequences.

[0057] In this embodiment of the invention, the pre-trained evaluation model employs a supervised learning method, trained based on historical physical implementation data of the target process node or its derived nodes. Specifically, for a given process design kit (PDK), multiple representative SRAM subsystem topologies are generated, and a complete automated placement and routing (APR) process is performed on each topology using industry-standard electronic design automation (EDA) tools. For each topology, its post-routing static timing analysis report, power analysis report, and IR / EM sign-off results are extracted and paired with the encoded representation of the topology (as described in step S41) to form labeled training samples. Subsequently, the evaluation model is trained to minimize the prediction error between its estimated feature vectors and actual sign-off metrics. Those skilled in the art should understand that this training process can be performed once per process node by the EDA methodology provider, and the trained model parameters can be distributed to end users without requiring end users to perform the training process themselves.

[0058] Unlike traditional methods that only predict the physical characteristics of isolated SRAM macros or already placed macros, the evaluation model of this invention receives coded representations that include functional interface logic generated by the access model—such as time-division multiplexing state machines and error-correcting code encapsulation logic. This enables the evaluation model to not only predict macro-level PPAs but also the impact of the synthesized encapsulation logic on timing and congestion, the latter being key factors causing design convergence problems in RISC-V SoC implementations.

[0059] S43. The comprehensive evaluation result is obtained by calculating based on the feature vector using a weighted cost function. A configurable weighted cost function integrates the feature vectors output by the evaluation model into a single comprehensive evaluation result. In an exemplary, non-limiting configuration, the function takes the form: ; Where f_i represents a normalization function for timing, power consumption, or area metrics, and w_i is a custom weight reflecting project priority (such as timing-critical or power-sensitive). It should be noted that the above functions are merely illustrative, and the specific mathematical relationships can be adjusted without departing from the scope of this invention.

[0060] S44. When the physical congestion risk score or infrared voltage drop risk score exceeds a preset threshold, the corresponding SRAM subsystem topology candidate is removed. For SRAM subsystem topologies with congestion risk scores or infrared voltage drop risk scores exceeding the predefined threshold, they are marked as high-risk schemes and excluded from the optimization search space or given a warning label. This step prevents downstream optimization algorithms from wasting iterations on physically unfeasible schemes.

[0061] The physical reliability risks include physical congestion risk, infrared voltage drop risk, and electromigration risk. Specifically, physical congestion risk involves predicting the cabling congestion rate and critical path congestion level after layout and wiring, and identifying high-congestion areas; infrared voltage drop risk involves predicting the worst-case voltage drop value and voltage drop percentage of the power network, and locating infrared hotspots; and electromigration risk involves predicting the current density of power lines and signal lines, and identifying EM violation risks.

[0062] This invention integrates indicators such as near-static timing analysis, power consumption estimation, and area assessment, along with risk levels, to generate standardized comprehensive evaluation results for each group of topology candidates. These results include basic topology information, quantitative indicators, risk levels for each dimension, and a comprehensive score. The comprehensive score is calculated based on preset basic weights and is used for initial ranking in subsequent searches. Simultaneously, high-risk topology candidates are directly marked as invalid solutions, excluding them from subsequent optimization and reducing computational load.

[0063] S5. Based on the comprehensive evaluation results, the SRAM subsystem topology candidates are iteratively searched using a multi-objective optimization algorithm to obtain the optimal SRAM subsystem target scheme.

[0064] In this embodiment of the invention, the multi-objective optimization algorithm is a Bayesian optimization algorithm or a reinforcement learning algorithm, and supports trade-off analysis on the Pareto front to adapt to the different application scenarios' emphasis on performance or cost. Based on the weight parameters configured by the user, the solution with the highest comprehensive score is selected from the Pareto front solution set as the optimal SRAM subsystem objective solution.

[0065] In this embodiment of the invention, step S5 specifically includes the following steps: The sequence model optimization framework is initialized based on a multi-objective optimization algorithm. Using the multiple sets of comprehensive evaluation results obtained in step S4, a probabilistic surrogate model (e.g., a Gaussian process) is fitted. This surrogate model serves as an approximation of the real PPA space.

[0066] Uncertainty in the surrogate model's predictions is analyzed through a data acquisition function (e.g., the expected improvement amount). The data acquisition function intelligently proposes the next candidate topology configuration to be evaluated—selecting design parameters such as the number of banks, the combination of SRAM macro threshold voltages (Vt), or the port replication factor to maximize the possibility of improving the current Pareto front estimate.

[0067] Repeat the above steps. Evaluate the proposed topology using the evaluation model, and use the results to update the surrogate model's understanding of the design space. Continue this feedback loop until convergence criteria are met, such as the expected improvement falling below a minimum threshold or reaching the maximum iteration budget.

[0068] Based on the system output non-dominated solution set (Pareto front) and user-configurable weight vectors, the system automatically selects the point on the front surface that represents the optimal trade-off between performance, power consumption and reliability for the target RISC-V application, as the optimal SRAM subsystem target scheme.

[0069] S6. Generate the corresponding constraint file, interface configuration script and functional logic configuration file according to the target scheme of the SRAM subsystem.

[0070] In this embodiment of the invention, before the final output constraint file, the model is run in a simulation environment to verify that the selected SRAM subsystem topology explicitly satisfies the set of hard constraints and the original system bandwidth requirements. This check ensures that the generated SDC timing constraints and RTL encapsulation function correctly before being delivered to the backend physical implementation.

[0071] In this embodiment of the invention, the constraint files include SDC timing constraint files (including clock definitions, setup / hold time constraints, and multi-cycle path / pseudo-path configurations); DEF format physical placement and routing constraint files (including SRAM macro placement locations, placement area restrictions, routing channel reservations, and affinity constraints); and UPF / CPF format low-power domain configuration files (including power domain partitioning, power gating configurations, and power state definitions), which can be directly imported into automated placement and routing (APR) tools.

[0072] The interface configuration scripts include DFT testable design scripts (such as scan chain insertion scripts and test mode constraints).

[0073] The functional logic configuration file includes ECC error correction code logic RTL code and configuration file (including error detection and correction logic, status reporting register configuration), thereby solving the problems of weak DFT / ECC integration, error-prone manual configuration, and inconsistent signatures in existing solutions.

[0074] When generating the corresponding constraint files, interface configuration scripts, and functional logic configuration files based on the target solution of the SRAM subsystem, all generated files undergo syntax compliance checks to ensure they conform to the syntax specifications of the corresponding EDA tools and are free of syntax errors. Simultaneously, a file list and usage instructions are generated, clearly defining the purpose of each file and the order and method for importing it into tools. The final complete output file package can be directly imported into mainstream APR tools to execute the backend physical implementation, enabling rapid deployment and approval of the SRAM subsystem.

[0075] Compared with existing technologies, this invention identifies physical reliability risks such as infrared voltage drop and electromigration in the early stages of SRAM subsystem design through pre-design physical and timing awareness, improving the ability to manage reliability risks. It also significantly reduces the number of iterations for automated placement and routing and engineering change instructions, accelerating design convergence. Through a multi-objective optimization algorithm, it stably outputs solutions close to the Pareto front, achieving optimal timing, power consumption, and area, resulting in superior optimization performance. Furthermore, it directly generates backend-usable constraint and interface files based on the SRAM subsystem's target solution, effectively improving the integration efficiency of the SRAM subsystem. This enables rapid deployment, stable approval, and mass production reuse of the SRAM subsystem.

[0076] Example 2 This invention also provides an SRAM selection and subsystem design system, please refer to... Figure 2 , Figure 2 This is a schematic diagram of the SRAM selection and subsystem design system 200 provided in an embodiment of the present invention, which includes: The parsing module 201 is used to obtain the system specification information of the target processor storage system, and parse the system specification information to generate the corresponding access model and hard constraint set.

[0077] In this embodiment of the invention, the invention transforms the unstructured storage requirements of the RISC-V processor system into a quantifiable, executable standardized access model and an inviolable set of hard constraints, providing a unified input benchmark for the entire process of selection, design and optimization.

[0078] In this embodiment of the invention, the access model is used to simulate system specification information. The generated precise timing access model provides a high-level functional description, simplifies memory interactions, and thus improves design verification and simulation efficiency. The access model manages core tasks such as data storage, read / write operations, and error checking, enabling engineers to verify controller logic without complex physical hardware. Simultaneously, the access model can accurately propagate latency and establish / hold constraints to precisely simulate actual hardware performance.

[0079] The system specifications include SRAM capacity, bit width, port characteristics, and concurrent access requirements. The set of hard constraints includes: Hard functional constraints: minimum capacity threshold, upper and lower limits of bit width, port type requirements, read / write concurrent access support requirements, and ECC / DFT function enable requirements.

[0080] Timing hard constraints: minimum operating frequency, input / output setup and hold time requirements relative to the system clock interface, number of clock domains and cross-clock domain requirements.

[0081] Physical hard constraints: maximum layout area, layout area boundary, minimum macrocell spacing requirement, power domain partitioning rules.

[0082] Hard constraints on power consumption: maximum dynamic power consumption, maximum leakage power consumption, and operating voltage range.

[0083] The filtering module 202 is used to filter out SRAM macros that meet the set of hard constraints from a preset storage compiler or PDK macro library, and then perform simulation re-screening on the filtered SRAM macros through the access model. The macro-level features of the SRAM macros that pass the re-screening are standardized to obtain a candidate set of SRAM macros.

[0084] In this embodiment of the invention, by traversing all SRAM macros in the storage compiler or PDK macro library and matching the set of hard constraints one by one, macros that do not meet the requirements are filtered out: for example, if the hard constraint requires true dual-port, then all single-port and pseudo-dual-port macros are directly excluded; if the hard constraint requires the maximum area to not exceed 1mm², then all macros with an area exceeding the limit are directly excluded.

[0085] After the initial screening is completed, a secondary screening is performed based on the access model. The implicit hard constraints that meet the performance requirements are output through simulation as supplementary filtering conditions for the initial screening of SRAM macros. Invalid macros that cannot adapt to the real load are directly filtered out, narrowing the candidate range and reducing invalid calculations in subsequent stages.

[0086] In this embodiment of the invention, the macro-level features of the SRAM macro include: Basic specifications: capacity, bit width, number of ports, port type, address line bit width, data line bit width.

[0087] Timing characteristics: Address access time, data setup / hold time, minimum clock cycle, and maximum operating frequency under the process-voltage-temperature (PVT) angle.

[0088] Power consumption characteristics: dynamic power consumption during read / write operations under typical PVT angles, standby leakage power consumption, and power consumption leakage in shutdown mode.

[0089] Physical characteristics: layout width, height, total area, pin distribution, row height, layout proximity rules, minimum layout spacing.

[0090] Features: ECC support type, BIST built-in self-test support, scan chain compatibility, power gating support.

[0091] After the macro-level features of the qualified SRAM macros are standardized, each SRAM macro corresponds to an N-dimensional feature vector in a unified format (N is the total number of feature dimensions), thereby eliminating the impact of dimensional differences on subsequent evaluation and matching, and facilitating rapid retrieval, matching and calling in subsequent steps.

[0092] The matching module 203 is used to match SRAM macros from the SRAM macro candidate set based on the bandwidth requirements and concurrent access requirements in the system specification information, and automatically generate multiple sets of SRAM subsystem topology candidates.

[0093] In this embodiment of the invention, the present invention provides precise transaction-level timing diagrams and protocol specifications required for generating Time Division Multiplexing (TDM), port mapping, and Bank interleaving control logic through an access model. The access model ensures that the encapsulation logic corresponding to the generated SRAM subsystem topology candidates can meet the specific concurrent access patterns defined in the system specification information and strictly adhere to the setup / hold time constraints of the underlying SRAM macros.

[0094] Based on the bandwidth requirements and concurrent access requirements, SRAM macros are matched from the SRAM macro candidate set. The SRAM subsystem topology candidates include bank size partitioning strategy, port mapping strategy, time-division multiplexing strategy, and logical replication strategy. Wherein: Bank Size Partitioning Strategy: Based on total capacity requirements, this invention generates all compliant Bank partitioning schemes. The capacity of a single Bank must match the standard capacity of the SRAM macro in the S2 candidate set, conforming to conventional address decoding design rules. Each scheme corresponds to a different Bank size and concurrent access conflict avoidance capability. During the generation process, SRAM macros with corresponding capacities in the candidate set are matched synchronously, eliminating partitioning schemes without corresponding macro support, ensuring that all schemes are feasible for implementation.

[0095] Port mapping strategy: Map the access ports of the RISC-V system bus to the physical ports of the SRAM macro. For example, map the system's read and write ports to the independent read and write ports of the pseudo-dual-port SRAM, or map them to single-port SRAMs in different banks through address decoding logic to achieve conflict dispersion of concurrent access.

[0096] Time Division Multiplexing (TDM) Strategy: For high-frequency, low-concurrency scenarios, a time division multiplexing timing control strategy is generated to double the working clock of the SRAM macro, and complete the read and write operations in time division within one system clock cycle. The single-port SRAM is used to simulate the function of pseudo dual-port, reducing area and power consumption while meeting basic access requirements.

[0097] Logical copying strategy: For high-concurrency read access scenarios (such as the multi-issue instruction cache of RISC-V processors), an SRAM macro copying scheme is generated to copy the same storage content to multiple sets of SRAM macros. Each set of macros corresponds to an independent instruction fetch port, realizing conflict-free concurrent read access and significantly improving instruction fetch bandwidth.

[0098] Evaluation module 204 is used to perform approximate static timing analysis, power consumption estimation, and area evaluation on each group of SRAM subsystem topology candidates using a pre-trained evaluation model, and simultaneously predict the physical reliability risk of each group of SRAM subsystem topology candidates to obtain a comprehensive evaluation result corresponding to each group of SRAM subsystem topology candidates. The input of the evaluation model includes the encoded representation of the interface control logic generated based on the access model.

[0099] In this embodiment of the invention, the access model works in conjunction with a pre-trained evaluation model. While the evaluation model provides rapid predictions of path latency and physical risks, the access model is used to perform lightweight functional verification on the generated interface logic. The access model enables the inspection of protocol violations in complex scenarios not visible in static timing analysis, such as read-modify-write sequences or cross-clock domain (CDC) handshake logic in ECC integration.

[0100] The evaluation module 204 includes the following sub-units: The encoding unit is used to encode the SRAM subsystem topology candidates to obtain encoded data. By encoding the SRAM subsystem topology candidates, they are converted into a unified representation suitable for evaluation model inference. This representation can be modified as needed; for example, it can be a graph structure (nodes are SRAM macros, edges are routing channels) or a tokenized sequence describing netlist and layout constraints.

[0101] An evaluation unit is used to evaluate the encoded data as input to the evaluation model, obtaining a feature vector. This feature vector includes the estimated worst-case negative time margin (WNS), estimated total dynamic power consumption (mW), estimated total area (μm²), physical congestion risk score, and infrared voltage drop risk score. The architecture of the evaluation model can be selected based on the design scale and required accuracy. For example, evaluation model architectures include, but are not limited to: graph neural networks (GNNs) for learning physical proximity and congestion patterns; attention-based sequence models (such as Transformer or large language models) for modeling long-distance temporal dependencies; and state-space models (SSMs) or cyclic state-space hybrid models (such as Mamba or Jamba architectures) for efficient linear-time processing of lengthy netlist sequences.

[0102] A computational unit is used to perform calculations based on the feature vectors using a weighted cost function to obtain the comprehensive evaluation result. A configurable weighted cost function integrates the feature vectors output by the evaluation model into a single comprehensive evaluation result. In an exemplary, non-limiting configuration, the function takes the form: ; Where f_i represents a normalization function for timing, power consumption, or area metrics, and w_i is a custom weight reflecting project priority (such as timing-critical or power-sensitive). It should be noted that the above functions are merely illustrative, and the specific mathematical relationships can be adjusted without departing from the scope of this invention.

[0103] The elimination unit is used to eliminate the corresponding SRAM subsystem topology candidate when the physical congestion risk score or infrared voltage drop risk score exceeds a preset threshold. For SRAM subsystem topologies with congestion or infrared voltage drop risk scores exceeding the predefined threshold, they are marked as high-risk schemes and excluded from the optimization search space or given a warning label. This step prevents downstream optimization algorithms from wasting iterations on physically unfeasible solutions.

[0104] In this embodiment of the invention, the pre-trained evaluation model includes, but is not limited to, dedicated architectures such as VeriGen and CodeV, as well as specially designed or optimized evaluation models such as Claude 3.5 Sonnet or DeepSeek, which can effectively handle the unique parallel logic and timing constraints of hardware description languages.

[0105] The physical reliability risks include physical congestion risk, infrared voltage drop risk, and electromigration risk. Specifically, physical congestion risk involves predicting the cabling congestion rate and critical path congestion level after layout and wiring, and identifying high-congestion areas; infrared voltage drop risk involves predicting the worst-case voltage drop value and voltage drop percentage of the power network, and locating infrared hotspots; and electromigration risk involves predicting the current density of power lines and signal lines, and identifying EM violation risks.

[0106] This invention integrates indicators such as near-static timing analysis, power consumption estimation, and area assessment, along with risk levels, to generate standardized comprehensive evaluation results for each group of topology candidates. These results include basic topology information, quantitative indicators, risk levels for each dimension, and a comprehensive score. The comprehensive score is calculated based on preset basic weights and is used for initial ranking in subsequent searches. Simultaneously, high-risk topology candidates are directly marked as invalid solutions, excluding them from subsequent optimization and reducing computational load.

[0107] The optimization module 205 is used to perform an iterative search on the SRAM subsystem topology candidates based on the comprehensive evaluation results using a multi-objective optimization algorithm to obtain the optimal SRAM subsystem target scheme.

[0108] In this embodiment of the invention, the multi-objective optimization algorithm is a Bayesian optimization algorithm or a reinforcement learning algorithm, which supports trade-off analysis on the Pareto front to adapt to the different application scenarios' emphasis on performance or cost, and selects the solution with the highest comprehensive score from the Pareto front solution set based on the user-configured weight parameters, as the optimal SRAM subsystem objective solution.

[0109] In this embodiment of the invention, a sequence model optimization framework is initialized based on a multi-objective optimization algorithm. Using the multiple sets of comprehensive evaluation results obtained in step S4, a probabilistic surrogate model (e.g., a Gaussian process) is fitted. This surrogate model serves as an approximate model of the real PPA space.

[0110] Uncertainty in the surrogate model's predictions is analyzed through a data acquisition function (e.g., the expected improvement amount). The data acquisition function intelligently proposes the next candidate topology configuration to be evaluated—selecting design parameters such as the number of banks, the combination of SRAM macro threshold voltages (Vt), or the port replication factor to maximize the possibility of improving the current Pareto front estimate.

[0111] Repeat the above steps. Evaluate the proposed topology using the evaluation model, and use the results to update the surrogate model's understanding of the design space. Continue this feedback loop until convergence criteria are met, such as the expected improvement falling below a minimum threshold or reaching the maximum iteration budget.

[0112] Based on the system output non-dominated solution set (Pareto front) and user-configurable weight vectors, the system automatically selects the point on the front surface that represents the optimal trade-off between performance, power consumption and reliability for the target RISC-V application, as the optimal SRAM subsystem target scheme.

[0113] The generation module 206 is used to generate corresponding constraint files, interface configuration scripts and functional logic configuration files according to the target scheme of the SRAM subsystem.

[0114] In this embodiment of the invention, before the final output constraint file, the model is run in a simulation environment to verify that the selected SRAM subsystem topology explicitly satisfies the set of hard constraints and the original system bandwidth requirements. This check ensures that the generated SDC timing constraints and RTL encapsulation function correctly before delivery to the backend physical implementation.

[0115] In this embodiment of the invention, the constraint files include SDC timing constraint files (including clock definitions, setup / hold time constraints, and multi-cycle path / pseudo-path configurations); DEF format physical placement and routing constraint files (including SRAM macro placement locations, placement area restrictions, routing channel reservations, and affinity constraints); and UPF / CPF format low-power domain configuration files (including power domain partitioning, power gating configurations, and power state definitions), which can be directly imported into automated placement and routing (APR) tools.

[0116] The interface configuration scripts include DFT testable design scripts (such as scan chain insertion scripts and test mode constraints).

[0117] The functional logic configuration file includes ECC error correction code logic RTL code and configuration file (including error detection and correction logic, status reporting register configuration), thereby solving the problems of weak DFT / ECC integration, error-prone manual configuration, and inconsistent signatures in existing solutions.

[0118] When generating the corresponding constraint files, interface configuration scripts, and functional logic configuration files based on the target solution of the SRAM subsystem, all generated files undergo syntax compliance checks to ensure they conform to the syntax specifications of the corresponding EDA tools and are free of syntax errors. Simultaneously, a file list and usage instructions are generated, clearly defining the purpose of each file and the order and method for importing it into tools. The final complete output file package can be directly imported into mainstream APR tools to execute the backend physical implementation, enabling rapid deployment and approval of the SRAM subsystem.

[0119] The SRAM selection and subsystem design system 200 can implement the steps in the SRAM selection and subsystem design method in the above embodiments and achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0120] Example 3 This invention also provides a computer device, please refer to... Figure 3 , Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and an SRAM selection and subsystem design program stored in the memory 302 and capable of running on the processor 301.

[0121] The processor 301 calls the SRAM selection and subsystem design program stored in the memory 302, and executes the steps in the SRAM selection and subsystem design method provided in this embodiment of the invention. Please refer to... Figure 1 Specifically, it includes the following steps: S1. Obtain the system specification information of the target processor's storage system, parse the system specification information to generate the corresponding access model and hard constraint set, the system specification information includes the SRAM capacity, bit width, port characteristics and concurrent access requirements information.

[0122] S2. Select SRAM macros that meet the set of hard constraints from the preset storage compiler or PDK macro library, and then perform simulation screening on the selected SRAM macros through the access model. Standardize the macro-level features of the qualified SRAM macros to obtain a candidate set of SRAM macros.

[0123] S3. Based on the bandwidth requirements and concurrent access requirements in the system specification information, match SRAM macros from the SRAM macro candidate set and automatically generate multiple sets of SRAM subsystem topology candidates.

[0124] S4. Perform approximate static timing analysis, power consumption estimation, and area assessment on each group of SRAM subsystem topology candidates using a pre-trained evaluation model. Simultaneously, predict the physical reliability risk of each group of SRAM subsystem topology candidates to obtain a comprehensive evaluation result corresponding to each group of SRAM subsystem topology candidates. The input of the evaluation model includes the encoded representation of the interface control logic generated based on the access model.

[0125] S5. Based on the comprehensive evaluation results, the SRAM subsystem topology candidates are iteratively searched using a multi-objective optimization algorithm to obtain the optimal SRAM subsystem target scheme.

[0126] S6. Generate the corresponding constraint file, interface configuration script and functional logic configuration file according to the target scheme of the SRAM subsystem.

[0127] The computer device 300 provided in this embodiment of the invention can implement the steps in the SRAM selection and subsystem design method as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0128] Example 4 This invention also provides a computer-readable storage medium storing an SRAM selection and subsystem design program. When the SRAM selection and subsystem design program is executed by a processor, it implements the various processes and steps in the SRAM selection and subsystem design method provided in this invention and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0129] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by hardware related to computer programs or instructions. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0130] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0131] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0132] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.

Claims

1. A method for selecting SRAM and designing a subsystem, characterized in that, The selection and subsystem design method includes the following steps: S1. Obtain the system specification information of the target processor's storage system, and parse the system specification information to generate a corresponding access model and hard constraint set; the system specification information includes the SRAM capacity, bit width, port characteristics, and concurrent access requirements information. S2. Select SRAM macros that meet the set of hard constraints from the preset storage compiler or PDK macro library, and then perform simulation screening on the selected SRAM macros through the access model. Standardize the macro-level features of the qualified SRAM macros to obtain a candidate set of SRAM macros. S3. Based on the bandwidth requirements and concurrent access requirements in the system specification information, match SRAM macros from the SRAM macro candidate set and automatically generate multiple sets of SRAM subsystem topology candidates. S4. Perform approximate static timing analysis, power consumption estimation, and area assessment on each group of SRAM subsystem topology candidates using a pre-trained evaluation model, and predict the physical reliability risk of each group of SRAM subsystem topology candidates to obtain a comprehensive evaluation result for each group of SRAM subsystem topology candidates; wherein, the input of the evaluation model includes the encoded representation of the interface control logic generated based on the access model; S5. Based on the comprehensive evaluation results, the SRAM subsystem topology candidates are iteratively searched using a multi-objective optimization algorithm to obtain the optimal SRAM subsystem target scheme. S6. Generate the corresponding constraint file, interface configuration script and functional logic configuration file according to the target scheme of the SRAM subsystem.

2. The SRAM selection and subsystem design method as described in claim 1, characterized in that, Step S4 includes the following sub-steps: S41. Encode the SRAM subsystem topology candidates to obtain encoded data; S42. The encoded data is used as input to the evaluation model for evaluation to obtain a feature vector; wherein the feature vector includes the estimated worst-case negative timing margin, the estimated total dynamic power consumption, the estimated total area, the physical congestion risk score, and the infrared voltage drop risk score. S43. The comprehensive evaluation result is obtained by calculating based on the feature vector using the weighted cost function; S44. When the physical congestion risk score or infrared voltage drop risk score exceeds a preset threshold, the corresponding SRAM subsystem topology candidate is removed.

3. The SRAM selection and subsystem design method as described in claim 1, characterized in that, The SRAM subsystem topology candidates include Bank size partitioning strategy, port mapping strategy, time-division multiplexing strategy, and logical replication strategy.

4. The SRAM selection and subsystem design method as described in claim 1, characterized in that, The physical reliability risks include physical congestion risk, infrared voltage drop risk, and electromigration risk.

5. A system for selecting SRAM and designing a subsystem, characterized in that, The selection and subsystem design system includes: The parsing module is used to obtain the system specification information of the target processor's storage system, and parse the system specification information to generate a corresponding access model and hard constraint set; the system specification information includes the SRAM capacity, bit width, port characteristics, and concurrent access requirements information. The filtering module is used to filter out SRAM macros that meet the set of hard constraints from the preset storage compiler or PDK macro library, and then perform simulation re-screening on the filtered SRAM macros through the access model. The macro-level features of the SRAM macros that pass the re-screening are standardized to obtain a set of SRAM macro candidates. The matching module is used to match SRAM macros from the SRAM macro candidate set based on the bandwidth requirements and concurrent access requirements in the system specification information, and automatically generate multiple sets of SRAM subsystem topology candidates. The evaluation module is used to perform approximate static timing analysis, power consumption estimation, and area evaluation on each group of SRAM subsystem topology candidates using a pre-trained evaluation model, while predicting the physical reliability risk of each group of SRAM subsystem topology candidates, and obtaining a comprehensive evaluation result for each group of SRAM subsystem topology candidates; wherein, the input of the evaluation model includes the encoded representation of the interface control logic generated based on the access model; The optimization module is used to iteratively search the SRAM subsystem topology candidates based on the comprehensive evaluation results using a multi-objective optimization algorithm to obtain the optimal SRAM subsystem target scheme. The generation module is used to generate corresponding constraint files, interface configuration scripts, and functional logic configuration files based on the target scheme of the SRAM subsystem.

6. The SRAM selection and subsystem design system as described in claim 5, characterized in that, The evaluation module includes the following sub-units: An encoding unit is used to encode the SRAM subsystem topology candidates to obtain encoded data; An evaluation unit is used to evaluate the encoded data as input to the evaluation model to obtain a feature vector; wherein the feature vector includes the estimated worst-case negative timing margin, the estimated total dynamic power consumption, the estimated total area, the physical congestion risk score, and the infrared voltage drop risk score. The calculation unit is used to calculate the comprehensive evaluation result based on the feature vector according to the weighted cost function; The elimination unit is used to eliminate the corresponding SRAM subsystem topology candidate when the physical congestion risk score or infrared voltage drop risk score exceeds a preset threshold.

7. The SRAM selection and subsystem design system as described in claim 5, characterized in that, The SRAM subsystem topology candidates include Bank size partitioning strategy, port mapping strategy, time-division multiplexing strategy, and logical replication strategy.

8. The SRAM selection and subsystem design system as described in claim 5, characterized in that, The physical reliability risks include physical congestion risk, infrared voltage drop risk, and electromigration risk.

9. A computer device, characterized in that, include: The selection and subsystem design program for SRAM, a memory, a processor, and an SRAM stored on the memory and executable on the processor, wherein when the processor executes the SRAM selection and subsystem design program, it implements the steps in the SRAM selection and subsystem design method as described in any one of claims 1-4.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores an SRAM selection and subsystem design program, which, when executed by a processor, implements the steps in the SRAM selection and subsystem design method as described in any one of claims 1-4.

Images