Method, apparatus, storage medium and qram for laying out qram on quantum processor

Abstract

The application discloses a method and device for laying out QRAM on a quantum processor, a storage medium and QRAM, comprising obtaining a topology graph of the quantum processor; traversing all nodes of the topology graph, determining a first list composed of optional nodes according to a selectable number; selecting a random optional node in the first list as a target node, obtaining a plurality of isosceles triangles satisfying a first condition to form a second list of the target node; selecting an isosceles triangle satisfying a second condition in the second list as a target isosceles triangle, laying out on the topology graph to form a Qrouter, and returning to traverse all nodes of the topology graph after reducing the selectable number of the three optional nodes and the one target node in the target isosceles triangle by one until the first list is empty. The above method makes the isosceles triangles on the quantum processor most densely laid out, that is, makes the Qrouter in the QRAM most to improve the connectivity of the QRAM.

Description

Technical Field

[0001] This application relates to the field of quantum computer technology, and in particular to a method, apparatus, storage medium, and QRAM for laying out QRAM on a quantum processor. Background Technology

[0002] Quantum computing is a computational paradigm that utilizes the fundamental properties of quantum mechanics to solve problems. By constructing precisely operable quantum physics hardware systems and running quantum computing software to implement quantum algorithms, computational problems can be solved, enabling the application of quantum computing in specific problems or fields.

[0003] Quantum random access memory (QRAM) plays a crucial role in quantum computing and makes significant contributions to the capabilities of quantum systems. The high efficiency of QRAM in storing and retrieving quantum information is the cornerstone for realizing large-scale quantum algorithms.

[0004] Building a QRAM prototype on a traditional QPU (quantum processor) requires the proper arrangement and connection of Qrouters—basic routing units—to achieve functionality.

[0005] How to deploy a sufficient number of Qrouters on a QPU with a limited number of bits is one of the hot research topics.

[0006] It should be noted that the information disclosed in the background section of this application is intended only to enhance the understanding of the general background of this application, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this application is to provide a method, apparatus, storage medium, and QRAM for laying out QRAM on a quantum processor, so that the QRAM contains the most Qrouters.

[0008] To achieve the above objectives, this application provides the following technical solution:

[0009] A first aspect of this application provides a method for laying out a QRAM on a quantum processor, the QRAM being constructed from a plurality of quantum routers (Qrouters), the method comprising:

[0010] Obtain a topology graph of the quantum processor, wherein each node in the topology graph represents a qubit;

[0011] Traverse all nodes of the topology graph and determine a first list of optional nodes based on the number of optional nodes; wherein, the optional nodes include qubits with an optional number of 2 that have not been used to form a Qrouter and qubits with an optional number of 1 that have formed a Qrouter;

[0012] Take one of the optional nodes randomly selected from the first list as the target node, and obtain several isosceles triangles that satisfy the first condition to form a second list of the target nodes; wherein, the first condition is that the isosceles triangle consists of only 4 nodes, the 4 nodes are the target node and 3 optional nodes, the target node and 2 optional nodes are located at the vertices of the isosceles triangle, and the other optional node is located at the midpoint of the base of the isosceles triangle;

[0013] Select an isosceles triangle from the second list that satisfies the second condition as the target isosceles triangle, and arrange it on the topology graph to form a Qrouter. Then, decrement the selectability of the three optional nodes and the target node in the target isosceles triangle by 1, and return to the step of traversing all nodes in the topology graph until the first list is an empty set. The second condition is that the target isosceles triangle is not connected to the isosceles triangles in the topology graph that form other Qrouters, or is connected to multiple isosceles triangles that form other Qrouters through vertices but does not form a closed region.

[0014] The method for laying out QRAM on a quantum processor as described above, further comprising the step of randomly selecting an optional node from the first list as a target node, and obtaining a plurality of isosceles triangles satisfying a first condition to form a second list of the target node, includes:

[0015] Randomly select an optional node from the first list as the target node;

[0016] Construct several standard isosceles triangles with the target node as the vertex; wherein the base of the standard isosceles triangle is 2a and the median is c; a and c are the distances between two adjacent nodes in different directions;

[0017] Based on the positions of the optional nodes in the first list in the topology graph, obtain the other two vertices and the midpoint of the bottom edge of the standard isosceles triangle, and determine it as an isosceles triangle that satisfies the first condition;

[0018] Collect all isosceles triangles that satisfy the first condition to form a second list of the target optional nodes.

[0019] In the method of laying out QRAM on a quantum processor as described above, when the topology is a square grid, a = c.

[0020] The method for deploying QRAM on a quantum processor as described above further includes, when there are adjacent nodes that are not connected in the topology graph, the second condition also includes that all sides of the target isosceles triangle exist in the topology graph.

[0021] The method for laying out QRAM on a quantum processor as described above, further comprising the step of selecting an isosceles triangle satisfying the second condition from the second list as the target isosceles triangle, laying it out in the topology graph to form a Qrouter, and decrementing the selectivity of the three selectable nodes and the target node in the target isosceles triangle by 1 before returning to the step of traversing all nodes in the topology graph until the first list is an empty set, includes:

[0022] Select one of the isosceles triangles randomly from the second list as the target isosceles triangle;

[0023] Determine whether all sides of the target isosceles triangle exist in the original topological graph;

[0024] If not, return to the step of randomly selecting an isosceles triangle from the second list as the target isosceles triangle;

[0025] If so, determine whether the target isosceles triangle has an overlapping edge with the isosceles triangles that form other Qrouters in the topology graph;

[0026] When there are overlapping sides, the current target isosceles triangle is removed from the second list, the second list is updated, and the process returns to execute the step of randomly selecting an isosceles triangle from the second list as the target isosceles triangle.

[0027] When there are no overlapping edges, it is determined whether the target isosceles triangle and multiple isosceles triangles forming other Qrouters in the topology graph form a closed interval.

[0028] When a closed interval is formed, the current target isosceles triangle is deleted from the second list, the second list is updated, and the process returns to the step of randomly selecting an isosceles triangle from the second list as the target isosceles triangle.

[0029] If no closed interval is formed, the target isosceles triangle is laid out on the topology graph to form a Qrouter. The selectivity of the three optional nodes and the target node in the target isosceles triangle is decremented by 1, and the process of traversing all nodes on the topology graph is returned until the first list is an empty set.

[0030] The method for laying out QRAM on a quantum processor as described above further includes, when the second list is an empty set:

[0031] Remove the target node from the first list, update the first list, and return to execute the steps of randomly selecting an optional node from the first list as the target node, and obtaining several isosceles triangles that satisfy the first condition to form a second list of the target node.

[0032] A second aspect of this application provides an apparatus for laying out a QRAM on a quantum processor, the QRAM being constructed from a plurality of quantum routers (Qrouters), the apparatus comprising:

[0033] The first acquisition module is used to acquire the topology graph of the quantum processor, wherein each node in the topology graph represents a qubit;

[0034] A determination module is used to traverse all nodes of the topology graph and determine a first list of optional nodes based on the number of optional nodes; wherein, the optional nodes include qubits with an optional node count of 2 that have not been used to form a Qrouter and qubits with an optional node count of 1 that have been used to form a Qrouter;

[0035] The second acquisition module is used to take a randomly selected optional node from the first list as the target node, and acquire a number of isosceles triangles that satisfy the first condition to form a second list of the target node; wherein, the first condition is that the isosceles triangle is composed of only 4 nodes, the 4 nodes are the target node and the other 3 optional nodes, the target node and 2 optional nodes are located at the vertices of the isosceles triangle, and the other optional node is located at the midpoint of the base of the isosceles triangle;

[0036] The layout module is used to select an isosceles triangle from the second list that satisfies the second condition as the target isosceles triangle, and lay it out on the topology graph to form a Qrouter. After decrementing the selectability counts of the three selectable nodes and the target node in the target isosceles triangle by 1, it returns to the step of traversing all nodes on the topology graph until the first list is an empty set. The second condition is that the target isosceles triangle is not connected to the isosceles triangles that form other Qrouters in the topology graph, or is connected to multiple isosceles triangles that form other Qrouters through vertices but does not form a closed region.

[0037] The apparatus for laying out QRAM on a quantum processor as described above, further comprising, when the second list is an empty set:

[0038] The update return module is used to remove the target node from the first list, update the first list, and trigger the second acquisition module.

[0039] A third aspect of this application provides a readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method described above for laying out QRAM on a quantum processor.

[0040] A fourth aspect of this application provides a QRAM obtained by the above-described method.

[0041] The beneficial effects of this application are as follows:

[0042] The method of this application lays out QRAM on the quantum processor. The number of optional nodes in the first list is 2 or 1, and the isosceles triangles in the second list satisfy the first condition. This ensures that the isosceles triangles in the second list are all composed of optional nodes and satisfy the Qrouter structure. Since the target isosceles triangles forming Qrouters satisfy the second condition, the isosceles triangles forming adjacent Qrouters are connected by as many vertices as possible, and the multiple isosceles triangles forming multiple Qrouters do not form closed regions. This achieves the densest distribution of isosceles triangles on the QPU, thus maximizing the number of Qrouters in the QRAM and improving the connectivity of the QRAM. Attached Figure Description

[0043] Figure 1 A schematic flowchart illustrating a first method for laying out QRAM on a quantum processor, as provided in an embodiment of this application.

[0044] Figure 2 This is a second flowchart illustrating a method for laying out QRAM on a quantum processor, as provided in an embodiment of this application.

[0045] Figure 3 This is a third flowchart illustrating a method for laying out QRAM on a quantum processor according to an embodiment of this application.

[0046] Figure 4 This is a fourth flowchart illustrating a method for laying out QRAM on a quantum processor, as provided in an embodiment of this application.

[0047] Figure 5 This is a schematic diagram of the Qrouter structure formed in the method provided in the embodiments of this application;

[0048] Figure 6 The diagram shows the structure of 12 standard isosceles triangles provided in the embodiments of this application. In the diagram, (A), (B), (C), (D), (E), (F), (G), (H), (I), (J), (K), and (L) each represent a standard isosceles triangle.

[0049] Figure 7 A topology diagram of a quantum processor provided in an embodiment of this application;

[0050] Figure 8 This is a schematic diagram of the structure of a quantum processor after QRAM is laid out, provided in an embodiment of this application;

[0051] Figure 9 A schematic diagram of a first structure of an apparatus for laying out QRAM on a quantum processor, provided in an embodiment of this application;

[0052] Figure 10 This is a second structural schematic diagram of a device for laying out QRAM on a quantum processor, provided in an embodiment of this application. Detailed Implementation

[0053] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of this application. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0054] In the description of this application, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0056] QRAM (Quantum Random Address Memory) is a quantum version of random address memory, capable of accessing or storing classical or quantum data under superimposed addresses. To build a QRAM prototype on a traditional QPU, Qrouters—basic routing units—need to be rationally arranged and connected to achieve functionality. A typical Qrouter structure requires 4 qubits, appearing as an isosceles triangle on the QPU. The more Qrouters in the QPU, the stronger the connectivity. Therefore, the optimal layout of QRAM (i.e., how to place a sufficient number of Qrouters on a QPU with a finite number of bits) is a pressing problem that needs to be solved. This can be abstracted as the problem of maximizing the density of isosceles triangles on the QPU.

[0057] The densest distribution of isosceles triangles follows these principles:

[0058] (1) Adjacent isosceles triangles are connected by their vertices.

[0059] (2) Multiple isosceles triangles do not form a closed region.

[0060] To solve the above problems, such as Figure 1 As shown, Figure 1 This is a first flowchart illustrating a method for laying out QRAM on a quantum processor according to an embodiment of this application. The embodiment of this application provides a method for laying out QRAM on a quantum processor, wherein the QRAM is constructed from multiple quantum routers (Qrouters), and the method includes the following steps:

[0061] Step S101: Obtain the topology of the quantum processor, wherein each node in the topology represents a qubit.

[0062] Step S102: Traverse all nodes of the topology graph and determine a first list of optional nodes based on the number of optional nodes; wherein, the optional nodes include qubits with an optional number of 2 that have not been used to form a Qrouter and qubits with an optional number of 1 that have formed a Qrouter.

[0063] Step S103: Randomly select an optional node from the first list as the target node, and obtain several isosceles triangles that satisfy the first condition to form a second list of the target node.

[0064] Step S104: Select an isosceles triangle from the second list that satisfies the second condition as the target isosceles triangle, place it on the topology graph to form Qrouter, and decrement the selectability counts of the three selectable nodes and the target node in the target isosceles triangle by 1, then return to the step of traversing all nodes of the topology graph until the first list is an empty set.

[0065] In this embodiment, the first condition in step S103 is that the isosceles triangle consists of only 4 nodes, which are the target node and 3 optional nodes. The target node and 2 optional nodes are located at the vertices of the isosceles triangle, and the other optional node is located at the midpoint of the base of the isosceles triangle.

[0066] In this embodiment, the second condition in step S104 is that the target isosceles triangle is not connected to the isosceles triangles that form other Qrouters in the topology graph, or is connected to multiple isosceles triangles that form other Qrouters through vertices but does not form a closed region.

[0067] By deploying QRAM on the quantum processor using the above method, the number of selectable nodes in the first list is 2 or 1, and the isosceles triangles in the second list satisfy the first condition. This ensures that the isosceles triangles in the second list are all composed of selectable nodes and satisfy the Qrouter structure. Since the target isosceles triangles forming Qrouters satisfy the second condition, the isosceles triangles forming adjacent Qrouters are connected by as many vertices as possible, and the isosceles triangles forming multiple Qrouters do not form closed regions, thereby achieving the densest distribution of isosceles triangles on the QPU, which means that the Qrouters in the QRAM are maximized, thus improving the connectivity of the QRAM.

[0068] Figure 5 This is a schematic diagram of the Qrouter structure formed in the method provided in the embodiments of this application; as shown below. Figure 5 As shown, the Qrouter formed by the method in this embodiment has only 4 nodes, namely four qubits: the first qubit 10, the second qubit 20, the third qubit 30, and the control qubit 40. The first qubit 10, the second qubit 20, and the third qubit 30 form the vertices of an isosceles triangle, and the control qubit 40 is located at the midpoint of the base of the isosceles triangle. The first qubit 10 is the parent node of the control qubit 40, and the second qubit 20 and the third qubit 30 are the two child nodes corresponding to the control qubit 40. The information to be stored is transmitted along the first qubit 10 to the second qubit 20 or the third qubit 30 by the control qubit 40, thereby realizing the transmission of stored information.

[0069] The information to be stored can be quantum information or encoded classical information. No specific limitations are imposed on the type of information to be stored.

[0070] The embodiments of this application will be described below through specific examples.

[0071] Regarding step S101 above, which involves obtaining the topology of the quantum processor, each node in the topology represents a qubit.

[0072] In this step, the topology of the quantum processor can be a square grid, a rectangular grid, or other grid shapes that can form isosceles triangles. When the topology of the quantum processor is a square grid, the isosceles triangles forming the Qrouter are right-angled isosceles triangles.

[0073] For step S102 above, that is, traversing all nodes of the topology graph and determining a first list of optional nodes based on the number of optional nodes; wherein, the optional nodes include qubits with an optional node count of 2 that have not been used to form a Qrouter and qubits with an optional node count of 1 that have formed a Qrouter;

[0074] In this step, the selectable node is a node that can be selected 1 or 2 times. This ensures that a node can form a maximum of 2 Qrouters. If a node forms 3 or more Qrouters, then multiple Qrouters will inevitably share edges, which will affect the stable operation of QRAM.

[0075] Regarding step S103 above, a selectable node is randomly selected from the first list as the target node, and several isosceles triangles that satisfy the first condition are obtained to form a second list of the target node.

[0076] In this step, by limiting the first condition to the isosceles triangle consisting of only 4 nodes—the target node and 3 optional nodes—the target node and 2 optional nodes are located at the vertices of the isosceles triangle, and the other optional node is located at the midpoint of the base of the isosceles triangle, the isosceles triangles in the second list are guaranteed to satisfy the condition. Figure 5 The Qrouter structure shown.

[0077] In an optional embodiment, according to the above... Figure 1 The method shown in this application embodiment also provides a method for laying out QRAM on a quantum processor. For example... Figure 2 As shown, Figure 2 This is a second flowchart illustrating a method for laying out QRAM on a quantum processor according to an embodiment of this application; Figure 2 The method shown above, step S103, can be further refined into the following steps, namely step S1031-step S1034.

[0078] Step S1031: Randomly select an optional node from the first list as the target node.

[0079] Step S1032: Construct several standard isosceles triangles with the target node as the vertex; wherein the base of the standard isosceles triangle is 2a and the median is c, where a and c are the distances between two adjacent nodes in different directions.

[0080] In this step, by restricting the lengths of the vertices, base, and median of a standard isosceles triangle, the triangle is ensured to contain only four nodes, with three nodes located at the vertices and the remaining node at the midpoint of the base, thus satisfying the following condition: Figure 5 The Qrouter structure requirements are shown.

[0081] To facilitate understanding, this step will be explained in detail below using a square grid quantum processor as an example. For instance, when the topology of the quantum processor is a square grid, there are 12 standard isosceles triangles with the target node as a vertex, such as... Figure 6 As shown, Figure 6 The diagram shows the structure of 12 standard isosceles triangles provided in the embodiments of this application. In the diagram, (A), (B), (C), (D), (E), (F), (G), (H), (I), (J), (K), and (L) each represent a standard isosceles triangle. Figure 6 The black dots represent the target node. Figure 6 As can be seen, all 12 standard isosceles triangles have the target node as their vertex and are all the same size, with a base length of 2a and a median length of c. Specifically, the base length 2a of a standard isosceles triangle is twice the distance between two adjacent qubits in the same row or column. Correspondingly, the median length c of a standard isosceles triangle can be the distance between two adjacent qubits in the same column or row. When the square grid is a square grid, a = c, and the standard isosceles triangles here are right-angled isosceles triangles.

[0082] Step S1033: Based on the position of the optional nodes in the first list in the topology graph, obtain the other two vertices and the midpoint of the bottom edge of a standard isosceles triangle, and determine it as an isosceles triangle that satisfies the first condition.

[0083] In this step, standard isosceles triangles that do not contain 4 optional nodes are excluded, thus obtaining isosceles triangles that satisfy the first condition.

[0084] Step S1034: Collect all isosceles triangles that satisfy the first condition to form a second list of the target optional nodes.

[0085] Through the above steps S1031-S1034, isosceles triangles that satisfy the first condition can be collected quickly and accurately to form a second list of target nodes. The isosceles triangles in the second list are all composed of optional nodes and satisfy the Qrouter structure.

[0086] For step S104 above, that is, selecting an isosceles triangle from the second list that satisfies the second condition as the target isosceles triangle, laying it on the topology graph to form Qrouter, and decrementing the selectability counts of the three selectable nodes and the target node in the target isosceles triangle by 1, then returning to the step of traversing all nodes of the topology graph until the first list is an empty set.

[0087] In this step, the second condition is that the target isosceles triangle is not connected to the isosceles triangles that form other Qrouters in the topology graph, or is connected to multiple isosceles triangles that form other Qrouters through vertices but does not form a closed region. This ensures that the isosceles triangles forming Qrouters follow the two principles mentioned above, thereby achieving the densest distribution of isosceles triangles on the QPU, which in turn maximizes the number of Qrouters in the QRAM to improve the connectivity of the QRAM.

[0088] In this step, when there are adjacent nodes that are not connected in the topology graph, the second condition also includes that all sides of the target isosceles triangle exist in the topology graph.

[0089] For example, Figure 7 A topology diagram of a quantum processor provided in an embodiment of this application; such as Figure 7 As shown in the figure, the two adjacent nodes with coordinates (3, 2) and (3, 3) are not connected. If the side of the isosceles triangle includes the connection between these two nodes, the isosceles triangle does not satisfy the second condition.

[0090] In an optional embodiment, according to the above... Figure 1 , 2 The method shown in this application embodiment also provides a method for laying out QRAM on a quantum processor. For example... Figure 3 As shown, Figure 3 This is a third flowchart illustrating a method for laying out QRAM on a quantum processor, provided as an embodiment of this application. Figure 3 The method shown above, step S104, can be further refined into the following steps, namely steps S1041-S1046.

[0091] Step S1041: Randomly select an isosceles triangle from the second list as the target isosceles triangle.

[0092] Step S1042: Determine whether all sides of the target isosceles triangle exist in the original topological graph.

[0093] If not, proceed to step S1046, delete the current target isosceles triangle from the second list, update the second list and return to step S1041, and randomly select an isosceles triangle from the second list as the target isosceles triangle.

[0094] If so, proceed to step S1043 to determine whether the target isosceles triangle has overlapping sides with the isosceles triangles that form other Qrouters in the topology graph.

[0095] When there are overlapping sides, proceed to step S1046, delete the current target isosceles triangle from the second list, update the second list and return to proceed to step S1041, and randomly select an isosceles triangle from the second list as the target isosceles triangle.

[0096] When there are no overlapping edges, step S1044 is executed to determine whether a closed interval is formed between the target isosceles triangle and multiple isosceles triangles forming other Qrouters in the topology graph.

[0097] When a closed interval is formed, step S1046 is executed to delete the current target isosceles triangle from the second list, update the second list, and return to execute step S1041 to select an isosceles triangle randomly selected from the second list as the target isosceles triangle.

[0098] If no closed interval is formed, then step S1045 is executed, the target isosceles triangle is laid out on the topology graph to form Qrouter, and the selectability counts of the 3 selectable nodes and 1 target node in the target isosceles triangle are all decremented by 1 before returning to the step of traversing all nodes of the topology graph until the first list is an empty set.

[0099] Through the above steps S1041-S1046, isosceles triangles that satisfy the second condition can be found quickly and accurately and arranged on the topology graph to form Qrouters. This ensures that isosceles triangles forming adjacent Qrouters are connected by as many vertices as possible, and that multiple isosceles triangles forming multiple Qrouters do not form closed regions. This achieves the densest distribution of isosceles triangles on the QPU, thus maximizing the number of Qrouters in the QRAM and improving the connectivity of the QRAM.

[0100] In this step, as the number of iterations increases during the loop execution, the number of selectable nodes in the first list decreases, potentially resulting in an empty second list. In one optional embodiment, based on the above... Figure 1-3 The method shown in this application embodiment also provides a method for laying out QRAM on a quantum processor. For example... Figure 4 As shown, Figure 4 This is a third flowchart illustrating a method for laying out QRAM on a quantum processor, as provided in an embodiment of this application.

[0101] When the second list is an empty set Figure 4 The method shown also includes the following steps:

[0102] Step S106: Remove the target node from the first list and update the first list.

[0103] Return to step S103, which is to randomly select an optional node from the first list as the target node and obtain several isosceles triangles that satisfy the first condition to form a second list of the target node.

[0104] Continue as Figure 4 As shown, in an optional embodiment, step S105 is further included after step S103, determining whether the second list is an empty set. If so, step S106 is executed to remove the target node from the first list and update the first list; if not, step S1041 is executed to randomly select an isosceles triangle from the second list as the target isosceles triangle.

[0105] Continue as Figure 4 As shown, in an optional embodiment, step S107 is further included after step S102, determining whether the first list is an empty set. If so, step S108 is executed to end the layout and output the layout result; if not, step S103 is executed to take an optional node randomly selected from the first list as the target node, and obtain several isosceles triangles that satisfy the first condition to form the second list of the target node.

[0106] For example, Figure 7 This application provides a topology diagram of a quantum processor according to an embodiment of the present application. Figure 8 This is a schematic diagram of the structure of a quantum processor after QRAM is laid out, provided in an embodiment of this application; as shown. Figure 7 and 8 As shown, when the topology of the quantum processor is Figure 7 As shown, after adopting the layout method of this implementation, the output layout result is as follows. Figure 8 As shown, Figure 8 A red isosceles triangle in the middle is a Qrouter. Figure 8 As can be seen, each Qrouter is an isosceles triangle composed of 4 optional nodes. While multiple isosceles triangles do not form a sealed region, it achieves as many connections as possible between adjacent isosceles triangles through vertices. At the same time, all edges of the isosceles triangles exist in the topology graph, thereby achieving the goal of arranging as many isosceles triangles as possible to improve the connectivity of QRAM.

[0107] It should be noted here that, Figure 7 and Figure 8 The qubits of each node are labeled according to their position in the topology graph; for example, the (0,1) node represents the second qubit in the first row. Furthermore, Figure 8 The legs of the first isosceles triangle in the first row exist in the topological graph because: since the four nodes (0,0), (0,1), (1,0), and (1,1) are all adjacent and connected, the nodes (1,0) and (0,1) are connected. Therefore, the left leg of the isosceles triangle is considered to exist in the topological graph. Similarly, the right leg is also considered to exist in the topological graph, and so are the legs of the other isosceles triangles.

[0108] Based on the same inventive concept, and according to the method for laying out QRAM on a quantum processor provided in the above embodiments of this application, this application also provides an apparatus for laying out QRAM on a quantum processor. For example... Figure 9 As shown, Figure 9 This application provides a first structural schematic diagram of an apparatus for laying out QRAM on a quantum processor; the apparatus includes:

[0109] The first acquisition module 1 is used to acquire the topology map of the quantum processor, wherein each node in the topology map represents a qubit.

[0110] Module 2 is used to traverse all nodes of the topology graph and determine a first list of optional nodes based on the number of optional nodes; wherein, the optional nodes include qubits with an optional number of 2 that have not been used to form a Qrouter and qubits with an optional number of 1 that have formed a Qrouter.

[0111] The second acquisition module 3 is used to take a randomly selected optional node from the first list as the target node, and acquire a number of isosceles triangles that satisfy the first condition to form a second list of the target node; wherein, the first condition is that the isosceles triangle is composed of only 4 nodes, the 4 nodes are the target node and the other 3 optional nodes, the target node and 2 optional nodes are located at the vertices of the isosceles triangle, and the other optional node is located at the midpoint of the base of the isosceles triangle.

[0112] The layout module 4 is used to select an isosceles triangle from the second list that satisfies the second condition as the target isosceles triangle, and lay it out on the topology graph to form a Qrouter. Then, it decrements the selectability counts of the three selectable nodes and the target node in the target isosceles triangle by 1 and returns to the step of traversing all nodes on the topology graph until the first list is an empty set. The second condition is that the target isosceles triangle is not connected to the isosceles triangles that form other Qrouters in the topology graph, or is connected to multiple isosceles triangles that form other Qrouters through vertices but does not form a closed region.

[0113] Optionally, the second acquisition module 3 mentioned above is specifically used for:

[0114] Randomly select an optional node from the first list as the target node.

[0115] Construct several standard isosceles triangles with the target node as the vertex; wherein the base of the standard isosceles triangle is 2a and the median is c; a and c are the distances between two adjacent nodes in different directions.

[0116] Based on the positions of the optional nodes in the first list in the topology graph, obtain the other two vertices and the midpoint of the base of a standard isosceles triangle, and determine it as an isosceles triangle that satisfies the first condition.

[0117] Collect all isosceles triangles that satisfy the first condition to form a second list of the target optional nodes.

[0118] Optionally, when there are adjacent nodes that are not connected in the topology graph, the second condition in the layout module 4 also includes that all sides of the target isosceles triangle exist in the topology graph.

[0119] Optionally, the above layout module 4 is specifically used for:

[0120] Select one of the isosceles triangles randomly from the second list as the target isosceles triangle.

[0121] Determine whether all sides of the target isosceles triangle exist in the original topological graph.

[0122] If not, return to the step of randomly selecting an isosceles triangle from the second list as the target isosceles triangle.

[0123] If so, determine whether the target isosceles triangle has an overlapping edge with the isosceles triangles that form other Qrouters in the topology graph.

[0124] If there are overlapping sides, the current target isosceles triangle is removed from the second list, the second list is updated, and the process returns to execute the step of randomly selecting an isosceles triangle from the second list as the target isosceles triangle.

[0125] When there are no overlapping edges, it is determined whether the target isosceles triangle and multiple isosceles triangles forming other Qrouters in the topology graph form a closed interval.

[0126] When a closed interval is formed, the current target isosceles triangle is deleted from the second list, the second list is updated, and the process returns to the step of randomly selecting an isosceles triangle from the second list as the target isosceles triangle.

[0127] If no closed interval is formed, the target isosceles triangle is laid out on the topology graph to form a Qrouter. The selectivity of the three optional nodes and the target node in the target isosceles triangle is decremented by 1, and the process of traversing all nodes on the topology graph is returned until the first list is an empty set.

[0128] Optionally, when the second list is an empty set, such as Figure 10 As shown, Figure 10 This is a first structural schematic diagram of a device for laying out QRAM on a quantum processor according to an embodiment of this application; the device further includes:

[0129] Update return module 5, which is used to remove the target node from the first list, update the first list and trigger the second acquisition module.

[0130] Based on the same application concept, this embodiment also provides a QRAM, which is obtained by the above method layout.

[0131] Based on the same concept, this embodiment also provides a readable storage medium storing a computer program thereon, which, when executed by a processor, can implement any of the above-mentioned methods for laying out QRAM on a quantum processor.

[0132] A readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device, such as, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer programs described herein can be downloaded from the readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. Networks can include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. Each computing / processing device's network adapter card or network interface receives the computer program from the network and forwards it for storage on a readable storage medium within the respective computing / processing device. The computer program used to perform the operations of this application can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as "C" or similar languages. The computer program can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information from a computer program. These electronic circuits can execute computer-readable program instructions to implement various aspects of this application.

[0133] Various aspects of this application are described herein with reference to flowchart illustrations and / or block diagrams of methods, systems, and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by a computer program. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer programs can also be stored in a readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the readable storage medium storing the computer program includes an article of manufacture comprising instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0134] A computer program may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the computer program executing on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0135] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0136] The above are merely preferred embodiments of this application and do not constitute any limitation on this application. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in this application without departing from the scope of the technical solutions of this application shall still fall within the protection scope of this application.

Claims

1. A method for deploying QRAM on a quantum processor, characterized in that, The QRAM is constructed from multiple quantum routers (Qrouter), and the method includes: Obtain a topology graph of the quantum processor, wherein each node in the topology graph represents a qubit; Traverse all nodes of the topology graph and determine a first list of optional nodes based on the number of optional nodes; wherein, the optional nodes include qubits with an optional number of 2 that have not been used to form a Qrouter and qubits with an optional number of 1 that have already formed a Qrouter; Take one of the optional nodes randomly selected from the first list as the target node, and obtain several isosceles triangles that satisfy the first condition to form a second list of the target nodes; wherein, the first condition is that the isosceles triangle consists of only 4 nodes, the 4 nodes are the target node and 3 optional nodes, the target node and 2 optional nodes are located at the vertices of the isosceles triangle, and the other optional node is located at the midpoint of the base of the isosceles triangle; Select an isosceles triangle from the second list that satisfies the second condition as the target isosceles triangle, and arrange it on the topology graph to form a Qrouter. Then, decrement the selectability of the three optional nodes and the target node in the target isosceles triangle by 1, and return to the step of traversing all nodes in the topology graph until the first list is an empty set. The second condition is that the target isosceles triangle is not connected to the isosceles triangles in the topology graph that form other Qrouters, or is connected to multiple isosceles triangles that form other Qrouters through vertices but does not form a closed region.

2. The method for laying out QRAM on a quantum processor according to claim 1, characterized in that, The step of randomly selecting an optional node from the first list as the target node and obtaining several isosceles triangles that satisfy the first condition to form a second list of the target node includes: Randomly select an optional node from the first list as the target node; Construct several standard isosceles triangles with the target node as the vertex; wherein the base of the standard isosceles triangle is 2a and the median is c; a and c are the distances between two adjacent nodes in different directions; Based on the positions of the optional nodes in the first list in the topology graph, obtain the other two vertices and the midpoint of the bottom edge of the standard isosceles triangle, and determine it as an isosceles triangle that satisfies the first condition; Collect all isosceles triangles that satisfy the first condition to form a second list of the target optional nodes.

3. The method for laying out QRAM on a quantum processor according to claim 2, characterized in that, When the topology is a square grid, a = c.

4. The method for laying out QRAM on a quantum processor according to claim 1, characterized in that, When there are adjacent nodes that are not connected in the topology graph, the second condition also includes that all sides of the target isosceles triangle exist in the topology graph.

5. The method for laying out QRAM on a quantum processor according to claim 4, characterized in that, The step of selecting an isosceles triangle from the second list that satisfies the second condition as the target isosceles triangle, arranging it in the topology graph to form a Qrouter, and decrementing the selectability counts of the three selectable nodes and the target node in the target isosceles triangle by 1 before returning to traverse all nodes in the topology graph until the first list is empty includes: Select one of the isosceles triangles randomly from the second list as the target isosceles triangle; Determine whether all sides of the target isosceles triangle exist in the original topological graph; If not, return to the step of randomly selecting an isosceles triangle from the second list as the target isosceles triangle; If so, determine whether the target isosceles triangle has an overlapping edge with the isosceles triangles that form other Qrouters in the topology graph; When there are overlapping sides, the current target isosceles triangle is removed from the second list, the second list is updated, and the process returns to execute the step of randomly selecting an isosceles triangle from the second list as the target isosceles triangle. When there are no overlapping edges, it is determined whether the target isosceles triangle and multiple isosceles triangles forming other Qrouters in the topology graph form a closed interval. When a closed interval is formed, the current target isosceles triangle is deleted from the second list, the second list is updated, and the process returns to the step of randomly selecting an isosceles triangle from the second list as the target isosceles triangle. If no closed interval is formed, the target isosceles triangle is laid out on the topology graph to form a Qrouter. The selectivity of the three optional nodes and the target node in the target isosceles triangle is decremented by 1, and the process of traversing all nodes of the topology graph is returned until the first list is an empty set.

6. The method for laying out QRAM on a quantum processor according to claim 1, characterized in that, When the second list is an empty set, the method further includes: Remove the target node from the first list, update the first list, and return to execute the steps of randomly selecting an optional node from the first list as the target node, and obtaining several isosceles triangles that satisfy the first condition to form a second list of the target node.

7. A device for deploying QRAM on a quantum processor, characterized in that, The QRAM is constructed from multiple quantum routers (Qrouters), and the device includes: The first acquisition module is used to acquire the topology graph of the quantum processor, wherein each node in the topology graph represents a qubit; A determination module is used to traverse all nodes of the topology graph and determine a first list of optional nodes based on the number of optional nodes; wherein, the optional nodes include qubits with an optional node count of 2 that have not been used to form a Qrouter and qubits with an optional node count of 1 that have already formed a Qrouter; The second acquisition module is used to take a randomly selected optional node from the first list as the target node, and acquire a number of isosceles triangles that satisfy the first condition to form a second list of the target node; wherein, the first condition is that the isosceles triangle is composed of only 4 nodes, the 4 nodes are the target node and the other 3 optional nodes, the target node and 2 optional nodes are located at the vertices of the isosceles triangle, and the other optional node is located at the midpoint of the base of the isosceles triangle; The layout module is used to select an isosceles triangle from the second list that satisfies the second condition as the target isosceles triangle, and lay it out on the topology graph to form a Qrouter. After decrementing the selectability counts of the three selectable nodes and the target node in the target isosceles triangle by 1, it returns to the step of traversing all nodes on the topology graph until the first list is an empty set. The second condition is that the target isosceles triangle is not connected to the isosceles triangles that form other Qrouters in the topology graph, or is connected to multiple isosceles triangles that form other Qrouters through vertices but does not form a closed region.

8. The apparatus for laying out QRAM on a quantum processor according to claim 7, characterized in that, When the second list is an empty set, the apparatus further includes: The update return module is used to remove the target node from the first list, update the first list, and trigger the second acquisition module.

9. A readable storage medium, characterized in that, The readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-6.

10. A QRAM, characterized in that, The layout is obtained by the method described in any one of claims 1-6.

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