An integrated chip with power monitoring and a method of manufacturing the same

Abstract

The application relates to an integrated chip with power monitoring and a preparation method thereof, and belongs to the field of optical communication device manufacturing. The integrated chip comprises a substrate layer and a multilayer semiconductor structure which is epitaxially grown on the substrate layer in sequence, and the multilayer semiconductor structure at least comprises a lower limiting layer, an active layer, an upper limiting layer and an upper contact layer; wherein the upper contact layer and part of the layer structure below the upper contact layer are etched to form a physically separated mesa structure on the integrated chip, and a semiconductor laser and a semiconductor light detector are physically separated in the width direction; the semiconductor laser is configured to generate laser when a first bias voltage is applied, and the semiconductor light detector is configured to convert a received optical signal into an electrical signal when a second bias voltage is applied. The integrated chip has the advantages of realizing power monitoring without external optical path, simplifying the packaging structure, reducing the cost and improving the system stability.

Description

Technical Field

[0001] This application relates to the field of optical communication device manufacturing, specifically to an integrated chip with power monitoring and its fabrication method. Background Technology

[0002] In recent years, with the rapid development of applications such as AI training, video streaming, 5G, and the Internet of Things, traffic within and between data centers has grown rapidly, creating an increasingly urgent need for higher bandwidth optical interconnects. In the field of optical communication, lasers have become the core signal source in optical communication systems due to their advantages such as small size, high efficiency, low power consumption, and ease of integration. In particular, distributed feedback (DFB) lasers, with their single-mode output and narrow output spectrum, are suitable for high-speed modulation and long-distance fiber optic communication, and are becoming the mainstream laser device for future development.

[0003] However, traditional DFB lasers typically require an external photodetector at the backlight end to monitor power during operation, a method with several drawbacks. First, to achieve high power output, the power-to-output ratio of the DFB laser after integrating an SOA (Semiconductor Optical Amplifier) ​​varies with the drive current, making power monitoring via the backlight impossible. Second, existing photodetectors usually require separate packaging, increasing packaging costs and hindering miniaturization. Furthermore, the traditional separation of the laser and photodetector introduces reliability issues and increases system complexity.

[0004] To address these issues, the industry has been seeking new technological solutions. Currently, common methods include monitoring optical power through beam splitting in an externally coupled optical path. However, this approach not only involves complex packaging structures but also increases the system's size and cost. Therefore, there is an urgent need for a solution that can integrate semiconductor lasers and semiconductor photodetectors on the same substrate, simultaneously achieving high power output and accurate power monitoring to meet the pressing needs of data centers for efficient optical interconnects.

[0005] Several invention applications have been filed to address the on-chip power monitoring problem of semiconductor optical amplifiers. For example: Chinese patent application CN13557936A discloses a laser power monitoring component and a laser emitting module and optical amplifier using the same. This application incorporates a nanowire grating to direct a predetermined proportion of incident laser light to a side offset from the incident direction, where a semiconductor photodetector placed on the side detects the laser power. In this structure, neither the metal nanowire grating nor the photodetector blocks the incident laser, facilitating photodetector placement. However, this application still has issues with the need for further optimization of the nanowire grating structure and photodetector placement to better handle incident laser offset and crosstalk.

[0006] Chinese patent application CN1104834A discloses an integrated DFB laser and its fabrication method. This application achieves integrated light emission and detection functions by forming an ion implantation region between a branched arc-shaped waveguide and a straight ridge waveguide at the laser's emission end face, thereby reducing device cost and increasing coupled emission power. However, this application still faces the challenge of further optimizing the distance between the branched and ridge waveguides to determine the optimal spacing value, aiming to achieve the same backlight monitoring function with a smaller spacing. Summary of the Invention

[0007] To address the problems of complex packaging, high cost, and poor reliability caused by the separate design of semiconductor lasers and semiconductor photodetectors in existing technologies, the purpose of this application is to provide an integrated chip with power monitoring and its fabrication method, which has the advantages of realizing power monitoring without external optical path, simplifying packaging structure, reducing cost, and improving system stability.

[0008] To achieve the above objectives, this application adopts the following technical solution: In a first aspect, this application provides an integrated chip with power monitoring capabilities. The integrated chip includes a substrate layer and a multilayer semiconductor structure epitaxially grown sequentially on the substrate layer. The multilayer semiconductor structure includes at least a lower confinement layer, an active layer, an upper confinement layer, and an upper contact layer. The upper contact layer and a portion of the underlying layer structure are etched to form physically separated mesa structures on the integrated chip, physically separating a semiconductor laser and a semiconductor photodetector in the width direction. The semiconductor laser is configured to generate laser light when a first bias voltage is applied, and the semiconductor photodetector is configured to convert a received optical signal into an electrical signal when a second bias voltage is applied.

[0009] The electrode corresponding to the semiconductor laser is configured to be subjected to a first voltage that causes it to generate stimulated emission, and the electrode corresponding to the semiconductor photodetector is configured to be subjected to a second voltage that causes it to generate a photoelectric response; wherein, the semiconductor photodetector is configured to receive a portion of the light signal reflected back from the light-emitting end face of the semiconductor laser.

[0010] As a further improvement of this application, the laser waveguide of the semiconductor laser is configured to guide the reflected light from its output end face to the semiconductor photodetector.

[0011] As a further improvement of this application, the total length of the laser waveguide of the semiconductor laser extending from the backlight end of the integrated chip to the light-emitting end along its optical transmission path is equal to the dimension of the integrated chip in the cavity length direction; the length of the optical detection waveguide of the semiconductor photodetector along its optical transmission path is less than the dimension of the integrated chip in the cavity length direction.

[0012] Furthermore, this application provides an integrated chip with power monitoring, wherein the integrated chip comprises, from bottom to top, an N-side metal layer, a substrate layer, a buffer layer, a lower confinement layer, a multiple quantum well layer, an upper confinement layer, a spacer layer, a grating layer, a capping layer, a cladding layer, a contact layer, a passivation layer, and a P-side metal layer; The integrated chip is physically separated into a semiconductor laser and a semiconductor photodetector in the width direction by etching the mesa structure formed by the cladding and the contact layer; When the semiconductor laser is in operation, it generates gain by applying a forward bias voltage to its corresponding P-side metal layer. When the semiconductor photodetector is in operation, it achieves photoelectric conversion by applying a reverse bias voltage to its corresponding P-side metal layer, thereby enabling on-chip monitoring of the output power of the semiconductor laser.

[0013] As a further improvement of this application, the projected length of the laser waveguide in the cavity length direction of the optical integrated chip is equal to the length of the integrated chip; the projected length of the optical probe waveguide in the cavity length direction of the optical integrated chip is less than the length of the optical integrated chip.

[0014] As a further improvement of this application, the laser waveguide of the semiconductor laser is tilted at the light-emitting end on either side of the integrated chip length direction, and the angle between the centerline of the laser waveguide and the cavity length direction of the integrated chip is 5 to 45°, so as to guide the reflected light from the light-emitting end face to deviate from the original transmission path and be captured by the semiconductor photodetector; the semiconductor photodetector is located on the side of the laser waveguide that is tilted, so as to directly receive the reflected light in the width direction of the integrated chip.

[0015] As a further improvement of this application, the laser waveguide of the semiconductor laser is a combination of a straight waveguide and a slanted waveguide, or a combination of a straight waveguide and a curved waveguide.

[0016] As a further improvement of this application, the semiconductor laser has a periodic grating etched on the grating layer of the straight waveguide to achieve single longitudinal mode lasing, and there is no periodic grating structure in the oblique waveguide or curved waveguide region. An anti-reflection dielectric film is deposited at the light-emitting end of the integrated chip to improve light emission efficiency and retain a preset proportion of reflected light for power monitoring; a high reflectivity dielectric film is deposited at the backlight end of the integrated chip to enhance the intensity of reflected light.

[0017] As a further improvement of this application, the cavity length of the integrated chip is 500μm to 5000μm; and the laser waveguide width of the semiconductor laser is 2μm to 50μm.

[0018] As a further improvement of this application, the mesa structure of the semiconductor photodetector has a projection shape of a circle, triangle, rectangle or polygon in the substrate direction to adapt to the spatial distribution of reflected light.

[0019] As a further improvement to this application, the N-side metal layer is an N-type nickel / gold alloy layer or an N-type gold-germanium-nickel alloy layer; the P-side metal layer is a P-type gold-germanium-nickel alloy layer. The substrate layer is N-type InP; the multiple quantum well layer is InGaAsP; and the grating layer is InP.

[0020] As a further improvement of this application, the mesa structure of the semiconductor photodetector has a length of 100μm-500μm, a width of 50μm-200μm, a quantum efficiency of not less than 30%, and a response speed of less than 100ps.

[0021] Secondly, this application provides a method for fabricating an integrated chip with power monitoring. The method includes forming a multilayer structure from bottom to top through the same epitaxial growth process. The multilayer structure includes an N-side metal layer, a substrate layer, a buffer layer, a lower confinement layer, a multiple quantum well layer, an upper confinement layer, a spacer layer, a grating layer, a capping layer, a cladding layer, a contact layer, a passivation layer, and a P-side metal layer. The method also includes forming the mesa structure through photolithography and etching processes to separate the semiconductor laser and the semiconductor photodetector in the width direction.

[0022] The beneficial effects of this application are as follows: This application integrates a semiconductor laser and a semiconductor photodetector onto a single integrated chip, employing a specific layer structure and electrical isolation design to achieve coordinated operation of the forward-biased semiconductor laser and the reverse-biased semiconductor photodetector. This solves the problems of complex structure and high cost associated with traditional external monitoring solutions, offering advantages such as power monitoring without an external optical path, simplified packaging structure, reduced cost, and improved system stability. The integrated design of the semiconductor laser and semiconductor photodetector avoids the complex structure required for beam splitting monitoring in an external coupling optical path, significantly reducing package size and cost while improving device reliability and stability. Utilizing the interface reflection principle, on-chip power monitoring of the semiconductor optical amplifier is achieved, eliminating the need for an additional backlight monitoring device, simplifying the device structure, and increasing integration. Furthermore, electrical isolation is achieved using a P-plane metal layer. The semiconductor optical amplifier and semiconductor photodetector are controlled by forward and reverse bias voltages, respectively, overcoming the shortcoming that the output power ratio of traditional DFB semiconductor lasers changes with the magnitude of the driving current, and realizing accurate power monitoring.

[0023] Furthermore, by optimizing the design of the laser waveguide (such as using a combination of straight waveguide + oblique waveguide or straight waveguide + curved waveguide) and combining it with a specific grating layer etching method (such as etching a periodic grating on a straight waveguide), the beam quality and output power of the device are further improved.

[0024] Furthermore, by rationally designing the cavity length (500μm~5000μm) of the integrated chip and the mesa structure (such as circular, triangular, rectangular or polygonal) of the semiconductor photodetector, miniaturization of the device and high integration of functions have been achieved, meeting the data center's demand for efficient optical interconnection. Attached Figure Description

[0025] Figure 1 This is a three-dimensional schematic diagram of an integrated chip with power monitoring according to an embodiment of this application. Figure 1 ; Figure 2 This is a three-dimensional schematic diagram of an integrated chip with power monitoring according to an embodiment of this application. Figure 2 ; Figure 3 This is a top view of an integrated chip with power monitoring according to an embodiment of this application; Figure 4 This is a cross-sectional view of an integrated chip with power monitoring according to an embodiment of this application; Figure 5 This is a cross-sectional view of an integrated chip with power monitoring according to an embodiment of this application.

[0026] Wherein: 100, semiconductor laser; 101, laser waveguide; 200, semiconductor photodetector; 201, photodetector waveguide; 1, N-plane metal layer; 2, substrate layer; 3, buffer layer; 4, lower confinement layer; 5, multiple quantum well layer; 6, upper confinement layer; 7, spacer layer; 8, grating layer; 9, capping layer; 10, cladding layer; 11, contact layer; 12, passivation layer; 13, P-plane metal layer; 81, periodic grating. Detailed Implementation

[0027] The technical solution of this application will now be clearly and completely described with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0028] The relevant terms in this application are explained as follows: Distributed feedback (DFB) is a semiconductor laser design that integrates a periodic grating to achieve stable single-mode output through Bragg reflection. Semiconductor lasers with this structure feature a narrow output spectrum and are suitable for high-speed modulation, making them widely used in optical communication. The semiconductor laser in this application employs a distributed feedback structure.

[0029] A semiconductor optical amplifier (SOA) is a device that amplifies optical signals using a semiconductor material gain medium. Its structure is similar to a semiconductor laser but lacks a resonant cavity feedback mechanism. When a forward current is applied, charge carriers are injected into the active region, generating stimulated emission and amplifying the incident optical signal. In this application, a semiconductor laser integrates the semiconductor optical amplifier function to improve output power.

[0030] On-chip power monitoring refers to a technology that integrates a semiconductor photodetector and a semiconductor laser within the same integrated chip, directly measuring the laser output power by utilizing the optical effects within the integrated chip (such as end-face reflection or interface reflection). This technology eliminates the need for external photodetectors or beam splitters, enabling device miniaturization and simplified packaging structures.

[0031] An epitaxial layer is a semiconductor material layer deposited layer by layer on a substrate through an epitaxial growth process. Epitaxial growth allows for precise control of the thickness, composition, and doping concentration of each layer, forming a layered structure with specific optoelectronic functions. The N-plane metal layer, substrate layer, buffer layer, confinement layer, multiple quantum well layer, grating layer, cladding layer, and contact layer in this application are all epitaxial layer structures.

[0032] A mesa structure is a raised platform structure formed on the surface of a semiconductor material through photolithography and etching processes. This structure provides physical isolation in the lateral direction, limiting the current injection path and enhancing the lateral optical field confinement capability of the optical waveguide. In this application, the mesa structure is used to achieve electrical isolation between the semiconductor laser and the semiconductor photodetector, preventing current crosstalk between the forward and reverse bias circuits.

[0033] A waveguide is a path structure used to guide the propagation of light waves. Its function is to limit the lateral diffusion of the light field, allowing light to propagate along a predetermined direction. In semiconductor lasers, waveguides are formed by the difference in refractive index of the dielectric materials, confining light propagation within the core layer region with the higher refractive index. In integrated circuits, waveguides are implemented using mesa structures—the raised platforms formed by the mesa structure act as the physical carrier of the waveguide, and light is laterally confined within the width of the raised platform and propagates along the cavity length. Specific waveguide forms include straight waveguides, angled waveguides, and curved waveguides, and their geometry determines the light propagation path.

[0034] The grating layer is a semiconductor material located between the upper confinement layer and the capping layer. In this application, InP (Indium Phosphide) is used. Periodic groove structures are etched on this layer using electron beam lithography or nanoimprint lithography to form a distributed feedback grating, which serves as a wavelength-selective element to achieve single-mode lasing.

[0035] A periodic grating is a groove array structure with a fixed period that coherently reflects light of a specific wavelength through the Bragg reflection effect. In distributed feedback semiconductor lasers, the periodic grating serves as a reflective element of the resonant cavity, enabling single-mode output. In this application, the periodic grating is only disposed in straight waveguides; it is absent in slanted or curved waveguide regions.

[0036] A passivation layer is an insulating dielectric layer covering the surface of a semiconductor device. In this application, SiO2 (silicon dioxide) or Si3N4 (silicon nitride) materials are used. The passivation layer is used to prevent surface leakage current, protect the device from the influence of the external environment (such as moisture and contaminants), and achieve electrical isolation between different electrodes.

[0037] An antireflective dielectric film is a multilayer dielectric thin film coated on the light-emitting end face, which reduces the Fresnel reflectivity of the end face through interference effect. In this application, the antireflective dielectric film increases the transmission ratio of the light-emitting end face to over 95%, while retaining approximately 5% of reflected light for power monitoring, thus achieving a balance between high-efficiency light emission and monitoring functions.

[0038] The high-reflectivity dielectric film is a multilayer dielectric thin film coated on the backlight end face, which achieves high reflectivity (not less than 90% in this application) within a specific wavelength range through interference effect. This film layer reflects the back-transmitted light back into the waveguide, reduces the light transmission loss at the backlight end, enhances the intensity of reflected light that can be captured by the semiconductor photodetector, and thus improves the stability of the monitoring signal.

[0039] Fresnel reflection refers to the reflection phenomenon that occurs when light passes through the interface of two media with different refractive indices due to the abrupt change in refractive index. The intensity of the reflected light is determined by the difference in refractive index between the media on both sides of the interface. In this application, Fresnel reflection at the light-emitting end face is used to generate reflected light for power monitoring, eliminating the need for additional beam splitting elements.

[0040] Bragg reflection is a coherent reflection phenomenon produced by a periodic structure (such as a grating) of light of a specific wavelength that satisfies the Bragg condition. When light propagates in a periodic structure, the reflected light from each periodic unit is phase-matched, forming constructive interference and producing a strong reflection peak. This effect is the physical basis for achieving single-mode output in distributed feedback semiconductor lasers.

[0041] InP (Indium Phosphide) is a group III-V compound semiconductor material with advantages such as direct bandgap, high electron mobility, and good thermal conductivity. In this application, it is used as a substrate and grating layer material. It is a commonly used substrate material for semiconductor lasers in the optical communication band (1.3 μm to 1.55 μm) and can form good lattice matching with materials such as InGaAsP.

[0042] InGaAsP (Indium Gallium Arsenide Phosphide) is a quaternary compound semiconductor material. Its bandgap width and lattice constant can be altered by adjusting the proportions of indium, gallium, arsenic, and phosphorus. In this application, it is used as a confinement layer, multiple quantum well layer, capping layer, cladding layer, etc., to achieve functions such as optical field confinement, carrier recombination luminescence, and refractive index modulation.

[0043] Multiple quantum wells (MQWs) are active region structures composed of multiple alternating thin layers (well layers and barrier layers). The well layers have narrow band gaps for carrier recombination and emission, while the barrier layers have wider band gaps for carrier confinement. This structure can improve the gain efficiency of semiconductor lasers, reduce the threshold current, and improve temperature stability.

[0044] The projected shape of the mesa structure refers to the geometric contour of the mesa structure on a plane perpendicular to the growth direction of the substrate layer. In this application, it can be designed as a circle, triangle, rectangle, or polygon. Different geometric shapes can adapt to the spatial distribution pattern of reflected light, optimize the matching degree between the photosensitive area of ​​the semiconductor photodetector and the energy density distribution of reflected light, thereby improving the photoelectric conversion efficiency.

[0045] In existing technologies, high-power semiconductor lasers in optical communication often employ external optoelectronic semiconductor photodetectors for power monitoring. However, with the increasing demand for miniaturization of optical modules in data centers, traditional discrete packaging solutions face problems of excessive size and cost. When a semiconductor laser is integrated with a semiconductor optical amplifier, the ratio of front-end to back-end output power changes with the drive current, leading to backlight monitoring failure. External beam splitting monitoring solutions require complex optical path designs, making it difficult to meet compact packaging requirements.

[0046] To address the aforementioned issues, the inventors discovered that interface reflection could be used for internal optical signal acquisition. Analysis of the optical waveguide transmission characteristics revealed a correlation between reflected light intensity and the waveguide end-face structure. Considering the integrability of semiconductor materials, they attempted to fabricate the semiconductor photodetector 200 and the semiconductor laser 100 on the same substrate. The key challenge lay in achieving electrical isolation between the two devices while maintaining optical coupling efficiency. Through numerous experimental verifications, they found that a specific mesa structure combined with a reverse bias operating mode could effectively separate photoelectric signals.

[0047] like Figure 1 and Figure 2 As shown, this application provides an integrated chip with power monitoring. The integrated chip includes a substrate layer 2 and a multilayer semiconductor structure epitaxially grown sequentially on the substrate layer 2. The multilayer semiconductor structure includes at least a lower confinement layer 4, an active layer, an upper confinement layer 6, and an upper contact layer. The upper contact layer and a portion of the underlying layer structure are etched to form a physically separated first mesa structure and a second mesa structure on the integrated chip. A semiconductor laser 100 and a semiconductor photodetector 200 are physically separated in the width direction. The semiconductor laser 100 is configured to generate laser light when a first bias voltage is applied, and the semiconductor photodetector 200 is configured to convert a received optical signal into an electrical signal when a second bias voltage is applied.

[0048] The electrode corresponding to the semiconductor laser 100 is configured to be subjected to a first voltage that causes it to generate stimulated emission, and the electrode corresponding to the semiconductor photodetector 200 is configured to be subjected to a second voltage that causes it to generate a photoelectric response; wherein, the semiconductor photodetector 200 is configured to receive a portion of the light signal reflected back from the light-emitting end face of the semiconductor laser 100.

[0049] More specifically, such as Figure 1 and Figure 2 As shown, this application proposes an integrated chip including a semiconductor laser 100 and a semiconductor photodetector 200. This integrated chip has a multi-layer stacked structure, specifically, as shown... Figure 4 and Figure 5 As shown, from bottom to top, the following layers are sequentially arranged: N-plane metal layer 1, substrate layer 2, buffer layer 3, lower confinement layer 4, multiple quantum well layer 5 (active layer), upper confinement layer 6, spacer layer 7, grating layer 8, capping layer 9, cladding layer 10, contact layer 11, passivation layer 12, and P-plane metal layer 13. The cavity length projection of the laser waveguide 101 is equal to the length of the integrated chip, while the projection of the photodetector waveguide 201 is smaller than the length of the integrated chip. The upper contact layer includes cladding layer 10, contact layer 11, and passivation layer 12. Electrical isolation is achieved through cladding layer 10, contact layer 11, and passivation layer 12. When the semiconductor laser 100 is operating, a forward bias voltage is applied, and when the semiconductor photodetector is operating, a reverse bias voltage is applied.

[0050] Furthermore, the electrodes corresponding to the semiconductor laser 100 are configured to be subjected to a first voltage that induces stimulated emission, and the electrodes corresponding to the semiconductor photodetector 200 are configured to be subjected to a second voltage that induces a photoelectric response; wherein, the semiconductor photodetector 200 is configured to receive a portion of the optical signal reflected from the emitting end face of the semiconductor laser 100. The waveguide of the semiconductor laser 100 is configured to guide the reflected light from its emitting end face to the semiconductor photodetector 200.

[0051] The semiconductor laser 100 refers to a light-emitting device based on a multi-quantum-well structure, specifically implemented using an InP material system, which generates stimulated emission through carrier injection. The semiconductor photodetector 200 refers to a PN junction device with photoelectric conversion function, specifically implemented using a PIN structure, which converts incident light into an electrical signal. The N-side metal layer 1 is used to form the cathode contact, for example, an ohmic contact can be achieved using an AuGeNi alloy material. The P-side metal layer 13 is used to form the anode contact, for example, a TiPtAu multilayer metal structure. Electrical isolation is achieved by etching the cladding layer 10 and the contact layer 11 to form a physical isolation region, preventing current crosstalk between the forward and reverse bias circuits.

[0052] Specifically, such as Figure 3As shown, the laser waveguide 101 extends along the length of the integrated chip to ensure effective feedback of the optical field within the resonant cavity. The shortened length design of the photodetector waveguide 201 avoids interference from full-cavity long reflections, collecting only the end-face reflection signal. When the semiconductor laser 100 operates, the forward bias causes population inversion in the multi-quantum well layer 5, and the grating layer 8 provides distributed feedback to form a single longitudinal mode output. Part of the output light is reflected at the end face and returns along the original path to the semiconductor photodetector region. The reverse-biased semiconductor photodetector converts the reflected light intensity into photocurrent, which is linearly related to the output light power. The etching depth control of the cladding layer 10 and the contact layer 11 can precisely adjust the electrical isolation effect, and the passivation layer 12 is used to prevent surface leakage current from affecting the detection accuracy.

[0053] Compared to existing technologies, current solutions require external beam splitters and independently packaged semiconductor photodetectors, leading to difficulties in optical path alignment and limitations in package size. This solution eliminates coupling losses between discrete components through monolithic integration and utilizes internal reflection within the integrated chip for in-situ monitoring. Electrical isolation design allows the semiconductor laser 100 and semiconductor photodetector to be independently controlled, avoiding signal crosstalk. Through these technical solutions, this application achieves on-chip real-time monitoring of laser output power, eliminating the packaging complexity caused by external optical path components. The integrated structure reduces the physical size of the device, making it suitable for high-density optical module applications. Electrical isolation design ensures the accuracy of the monitoring signal, and the reverse bias operating mode improves photoelectric conversion efficiency.

[0054] This application further proposes that the waveguides of the semiconductor laser 100 and the semiconductor photodetector 200 form mesa structures by etching the cladding layer 10 and the contact layer 11. The etching of the cladding layer 10 and the contact layer 11 refers to the selective removal of semiconductor material through photolithography and chemical etching processes, specifically dry etching or wet etching processes, with specific contours formed by controlling the etching depth and shape. The mesa structure refers to a raised platform formed by the unetched area, which can be achieved through mask patterning. This structure can limit the current path and enhance the lateral confinement capability of the optical waveguide.

[0055] Specifically, in the manufacturing process of the semiconductor laser 100 and the semiconductor photodetector 200, a photoresist mask is formed on the surface of the contact layer 11 using photolithography. Subsequently, plasma etching or an acidic solution is used to selectively remove the cladding layer 10 and the contact layer 11. Areas not covered by the mask are etched to form recessed regions, while the remaining areas constitute a mesa structure. This structure provides lateral physical isolation between the active region of the semiconductor laser 100 and the absorption region of the semiconductor photodetector 200. Simultaneously, the abrupt change in refractive index at the mesa edge enhances the waveguide mode confinement effect. This approach directly forms the mesa structure through etching, simplifying the manufacturing process and avoiding lattice mismatch problems associated with epitaxial growth. The unique geometry of the mesa structure also effectively reduces lateral carrier diffusion, improving device stability.

[0056] Through the above technical solution, this application achieves effective electrical isolation between the semiconductor laser 100 and the semiconductor photodetector 200 during monolithic integration, avoiding photocurrent crosstalk problems. The physical barrier formed by the mesa structure can precisely control the current injection area, while enhancing the transverse optical field confinement capability of the optical waveguide, providing a fundamental support condition for the subsequent realization of the tilted waveguide structure.

[0057] This application further proposes that the laser waveguide 101 of the semiconductor laser 100 is tilted at the light-emitting end to any side of the integrated chip length direction, and the angle between the centerline of the laser waveguide 101 and the cavity length direction of the integrated chip is 5 to 45°.

[0058] The centerline of the laser waveguide 101 refers to the geometric central axis of the waveguide structure on its cross-section. Specifically, it can be formed into a waveguide morphology with a specific tilt direction through photolithography and etching processes. The included angle range of 5–45° is set based on the balance between optical transmission efficiency and reflected light collection efficiency. For example, if the angle is too small, the reflected light may not be effectively transmitted to the semiconductor photodetector 200; if the angle is too large, it may cause a significant increase in waveguide transmission loss.

[0059] Specifically, a tilted waveguide is provided at the output end of the semiconductor laser 100, allowing part of the laser light to undergo interface reflection during transmission and return to the integrated chip along a specific path. The geometry of the tilted waveguide guides the reflected light away from its original transmission direction, allowing it to be captured by the reverse-biased semiconductor photodetector 200. For example, the angle between the centerline of the laser waveguide 101 and the cavity length direction can be achieved by adjusting the photomask pattern or etching process parameters, thereby controlling the spatial matching relationship between the propagation angle of the reflected light and the receiving area of ​​the semiconductor photodetector 200. The tilted waveguide structure achieves directional transmission of the reflected light through optical path control within the integrated chip, eliminating the need for external optical components. This reduces the complexity of the packaging structure and avoids the additional insertion loss caused by the beam splitter. Through the above technical solution, this application achieves effective collection and conversion of reflected light within the integrated chip, enabling the semiconductor photodetector 200 to directly monitor changes in the output power of the semiconductor laser 100. The tilted waveguide angle design optimizes the coupling efficiency between the reflected light and the semiconductor photodetector 200 while ensuring laser output efficiency, thus providing a reliable physical basis for on-chip power monitoring.

[0060] This application further proposes that the laser waveguide 101 of the semiconductor laser 100 can be a combination of a straight waveguide and an angled waveguide, or a straight waveguide and a curved waveguide. A straight waveguide refers to a waveguide structure extending linearly along the length of the integrated chip cavity. Specifically, it can be formed using photolithography and etching processes to create a straight mesa structure, used to support a periodic grating 81 on the grating layer 8 to achieve single-mode lasing. An angled waveguide refers to a waveguide structure where the centerline of the laser waveguide 101 forms an angle with the length of the integrated chip cavity. Specifically, it can be formed using an angled etching process, used to change the light transmission direction to reduce the impact of reflected light from the output end face on the stability of the semiconductor laser 100. A curved waveguide refers to a waveguide structure with continuously changing curvature, specifically formed using a curved etching process, used to adjust the light transmission path to achieve spatial separation of the optical signal.

[0061] Specifically, the straight waveguide achieves single-mode laser emission through the periodic structure of the grating layer 8, while the oblique or curved waveguide regions enhance output power through optical amplification without a grating structure. At the connection between the straight and oblique or curved waveguides, the optical signal transitions from the grating-modulated region to the grating-free amplification region, thereby avoiding interference from grating reflection on the reflected light at the output end face. For example, the straight waveguide length can account for 30% to 70% of the cavity length, while the oblique or curved waveguide extends to the output end face, changing the light transmission direction to deviate the reflected light from its original path, thus allowing it to be captured by the semiconductor photodetector 200 located on one side of the integrated chip's width direction. This scheme separates the grating reflection region and the amplified output region by combining waveguide structures, enabling the reflected light to be directionally transmitted to the semiconductor photodetector 200 while maintaining the stability of the semiconductor laser 100's output power.

[0062] Through the above technical solution, this application can realize on-chip monitoring of the output power of semiconductor laser 100 without increasing packaging complexity. At the same time, by optimizing the waveguide structure, the interference of reflected light on the working state of semiconductor laser 100 is reduced, thereby improving the accuracy of power monitoring and the reliability of the device.

[0063] This application further proposes that the semiconductor laser 100 has a periodic grating 81 etched on the grating layer 8 of the straight waveguide, while the oblique waveguide or curved waveguide region has no periodic grating structure.

[0064] The straight waveguide refers to a straight waveguide segment in which the centerline of the laser waveguide 101 is parallel to the length direction of the integrated chip cavity. Specifically, it can be formed using photolithography and etching processes to maintain the stability of the optical field distribution. The periodic grating 81 refers to a groove structure with a fixed periodic arrangement. Specifically, it can be formed on the surface of the grating layer 8 using electron beam lithography or nanoimprint lithography to achieve single-mode lasing in the straight waveguide. The oblique or curved waveguide region refers to a waveguide segment in the laser waveguide 101 where the centerline deviates from the length direction of the integrated chip cavity. Specifically, it can be formed using oblique etching or curved waveguide design to change the light transmission path and suppress reflected light interference.

[0065] Specifically, the periodic grating 81 set in the straight waveguide forms a resonant cavity through Bragg reflection, enabling the semiconductor laser 100 to generate a stable single longitudinal mode output. When the optical signal enters the oblique or curved waveguide region, since no periodic grating structure is set in this region, the optical field will not generate additional reflection loss during transmission, thus maintaining high amplification efficiency. This partitioned grating layout ensures the single-mode characteristic of the semiconductor laser 100 while avoiding mode interference caused by grating reflection in the oblique or curved waveguide regions. This scheme effectively eliminates the grating reflection effect in non-straight waveguide sections by limiting the grating to exist only in the straight waveguide.

[0066] Through the above technical solutions, this application achieves high-efficiency power amplification of the semiconductor laser 100 in single longitudinal mode lasing state. At the same time, by suppressing grating reflection interference in the non-linear waveguide section, the detection accuracy of the semiconductor photodetector 200 for reflected light signals is improved, thus providing a reliable optical basis for on-chip power monitoring of integrated chips.

[0067] This application further proposes an integrated chip with power monitoring, whose cavity length can be from 500 micrometers to 5000 micrometers. Here, the cavity length refers to the physical length of the waveguide of the semiconductor laser 100 in the integrated chip in the optical transmission direction. Specifically, it can be achieved by controlling the waveguide etching depth and epitaxial layer thickness using photolithography. This range can balance optical amplification efficiency and mode stability.

[0068] Specifically, in the integrated structure of semiconductor laser 100 and semiconductor photodetector 200, the cavity length directly affects the light transmission path and reflected light intensity within the waveguide. When the cavity length is between 500 micrometers and 5000 micrometers, effective amplification of light transmission within the waveguide is achieved, while the efficiency of the reflected light being captured by the semiconductor photodetector 200 at the backlight end is optimized. For example, when the cavity length is too short, the light amplification effect is insufficient and the reflected light intensity is too low; when the cavity length is too long, light transmission loss increases and mode stability decreases. By limiting this range, it can be ensured that the reflected light signal captured by the semiconductor photodetector 200 maintains a linear relationship with the transmitted light power at the output end, thereby achieving accurate power monitoring. This solution optimizes the light transmission path and reflected light distribution by limiting the cavity length range, enabling the semiconductor photodetector 200 to accurately capture the reflected light signal and avoiding complex packaging structures.

[0069] Through the above technical solution, this application solves the problem of insufficient or distorted intensity of reflected light monitoring signal while ensuring optical amplification efficiency, significantly improving the power monitoring accuracy of the integrated chip, and eliminating the need to rely on external optical beam splitting structures.

[0070] This application further proposes that the projected shape of the mesa structure of the semiconductor photodetector 200 in the substrate direction can be circular, triangular, rectangular, or polygonal. The mesa structure refers to the raised region formed by etching the cladding layer 10 and the contact layer 11, which can be achieved using dry or wet etching processes. This structure is used to define the effective photosensitive area of ​​the semiconductor photodetector 200 and control the carrier transport path. The projected shape refers to the geometric contour of the mesa structure in a plane perpendicular to the substrate growth direction, which can be achieved by adjusting the photolithographic mask pattern design. Different geometric shapes can adapt to different reflected light distribution patterns and optimize light absorption efficiency and current response characteristics.

[0071] Specifically, during the operation of the semiconductor photodetector 200, the reflected light exhibits a non-uniform spatial distribution characteristic when propagating within the integrated chip. By designing the projection shape of the mesa structure as a circle, triangle, rectangle, or polygon, the corresponding photosensitive area geometric parameters can be matched according to the energy density distribution characteristics of the reflected light field. For example, when the reflected light exhibits a Gaussian distribution laterally, a circular mesa can maximize the coverage of high energy density areas; when the reflected light exhibits multipath interference effects, a polygonal mesa can suppress the formation of standing waves in the light field through its angular structure. This design enables the semiconductor photodetector 200 to effectively capture reflected light energy under different operating conditions, while avoiding excessive increases in the lateral dimensions of the device. This solution, through a configurable projection shape design, achieves geometric matching between the mesa structure and the spatial pattern of the reflected light field, significantly improving photocurrent conversion efficiency.

[0072] Through the above technical solution, this application can flexibly select the optimal mesa shape according to the actual optical path characteristics, maintaining the compactness of the device structure while ensuring power monitoring accuracy. This geometric adaptation mechanism effectively solves the contradiction between the sensitivity and space occupation of the semiconductor photodetector 200 in the integrated environment, avoiding the technical dilemma of being forced to increase the size of the integrated chip in order to improve monitoring accuracy.

[0073] like Figures 1 to 3 As shown, this application further proposes that the semiconductor photodetector 200 is located on the side where the waveguide of the semiconductor laser 100 is tilted, in the width direction of the integrated chip. The width direction of the integrated chip refers to the lateral dimension perpendicular to the cavity length direction of the integrated chip, which can be achieved using the lateral cutting direction defined in photolithography. This direction forms a spatial orthogonal relationship with the optical signal transmission path. The side where the waveguide is tilted refers to the spatial region formed after the centerline of the laser waveguide 101 at the light-emitting end of the semiconductor laser 100 deviates from the central axis of the cavity length of the integrated chip. This can be achieved by forming a waveguide sidewall structure with a preset angle through ion beam etching or chemical etching. This tilted structure can change the propagation path of the reflected light.

[0074] Specifically, when the laser waveguide 101 of the semiconductor laser 100 is tilted at its output end, the light signal reflected from the output end face diffuses along the tilt direction towards the width of the integrated chip. The semiconductor photodetector 200 is arranged on the same width side of the tilted waveguide, allowing the reflected light to be directly captured by the semiconductor photodetector's mesa structure during lateral diffusion. Since the tilted waveguide and the semiconductor photodetector 200 are on the same width side, the reflected light can be effectively received without complex spatial coupling, reducing optical path transmission loss. This solution optimizes the spatial layout, allowing the reflected light to be directly captured by the semiconductor photodetector 200 integrated on the same side in the natural diffusion path, avoiding the intervention of external optical components.

[0075] Through the above technical solution, this application solves the problem of complex reflected light monitoring paths. By coordinating the tilted waveguide and the semiconductor photodetector on the same side, efficient capture and conversion of reflected light is achieved. This structure reduces optical signal transmission loss, simplifies the internal optical path design of the integrated chip, and avoids the packaging complexity introduced by an external beam splitter.

[0076] This application further proposes depositing an antireflection dielectric film at the light-emitting end of the integrated chip. The antireflection dielectric film refers to a multilayer dielectric thin film formed by a vacuum deposition process, specifically composed of silicon dioxide, silicon nitride, or aluminum oxide, and its total thickness can be an integer multiple of one-quarter of the incident light wavelength. This film layer reduces Fresnel reflection at the light-emitting end face through interference effects, thereby increasing the transmitted light ratio to over 95%, while retaining approximately 5% of reflected light for monitoring by the semiconductor photodetector 200.

[0077] Specifically, an antireflection dielectric film is deposited on the light-emitting end face of the semiconductor optical amplifier waveguide. By precisely controlling the combination of the film's refractive index and thickness, destructive interference occurs between the incident light and the film interface. This design allows most of the light energy to penetrate through the end face and be output, while the residual reflected light returns along its original path and is captured by the semiconductor photodetector 200. The refractive index gradient of the film can be designed as a gradual transition structure from the waveguide core to the air medium, further suppressing higher-order reflection modes.

[0078] In some specific embodiments, the antireflective dielectric film can employ a distribution structure of alternating stacks of high-refractive-index and low-refractive-index materials, such as a five-layer Bragg mirror structure formed by alternating deposition of titanium dioxide and silicon dioxide. The film deposition process can utilize plasma-enhanced chemical vapor deposition, completing the deposition at a process temperature below 300°C to avoid damaging the waveguide structure. This solution controls reflection loss to below 5% through the antireflective dielectric film, while simultaneously confining the reflected light path within the waveguide of the integrated chip, enabling optical power monitoring without the need for an external beam splitter.

[0079] Through the above technical solution, this application effectively solves the problem of output power reduction caused by excessive reflection loss at the light-emitting end face, and at the same time utilizes the residual reflected light to construct a built-in power monitoring channel. This design enables the optical amplifier and semiconductor photodetector to maintain stable power monitoring function in a monolithic integrated state, avoiding the packaging complexity introduced by the beam splitter element in traditional solutions.

[0080] This application further proposes depositing a high-reflectivity dielectric film on the backlight end of an integrated chip. The high-reflectivity dielectric film refers to a thin film structure composed of multiple dielectric materials, specifically formed by alternating deposition of silicon dioxide and silicon nitride, etc., achieving high reflectivity within a specific wavelength range by adjusting the thickness and refractive index matching of each layer. This film layer enhances the reflectivity of the backlight end interface, reduces light transmission loss at the backlight end, and thus improves the efficiency of the semiconductor photodetector 200 in capturing reflected light.

[0081] Specifically, after depositing a high-reflectivity dielectric film on the backlight end of the integrated chip, when the light generated by the semiconductor laser 100 is transmitted to the backlight end in the waveguide, most of the light is reflected back into the waveguide, with only a very small portion transmitting out of the integrated chip. The reflected light is transmitted in the reverse direction in the waveguide to the semiconductor photodetector 200, where it is converted into photocurrent by the reverse-biased semiconductor photodetector 200. The high-reflectivity dielectric film, by suppressing light transmission at the backlight end, ensures a stable proportional relationship between the intensity of reflected light and the intensity of transmitted light at the output end, thereby enabling the electrical signal output by the semiconductor photodetector 200 to accurately reflect the actual output power of the semiconductor laser 100. This solution, by introducing a high-reflectivity dielectric film, effectively reduces the light loss at the backlight end and improves the usable intensity of reflected light, thereby optimizing the stability of the monitoring signal.

[0082] Through the above technical solution, this application can enhance the intensity of reflected light through the high reflectivity film layer at the backlight end without adding external optical path or beam splitting element, ensuring that the semiconductor photodetector 200 obtains sufficient signal strength to achieve accurate power monitoring, while maintaining the compactness of the integrated chip structure and the simplification of the packaging process.

[0083] An antireflective dielectric film is applied to the light-emitting end of the integrated chip, with the light-emitting end face having a conical structure and a cone angle of 15-30°, to improve beam quality. A high-reflectivity dielectric film with a reflectivity of not less than 90% is applied to the backlight end of the integrated chip. The cavity length of the integrated chip is 500μm-5000μm.

[0084] As an optional solution, the specific structures of the semiconductor laser 100 and the semiconductor photodetector 200 are as follows: The semiconductor laser 100 has a length of 500μm, a center wavelength frequency difference of 10-15GHz, an output power deviation of less than 70%, and an anti-reflection coating with a reflectivity of 0.1% at the output port.

[0085] In the semiconductor photodetector 200, the length of the doped passive optical waveguide is 300 μm; the length of the mesa structure of the semiconductor photodetector 200 is 100 μm-500 μm; the width of the mesa structure of the semiconductor photodetector 200 is 50 μm-200 μm; the quantum efficiency of the semiconductor photodetector 200 is not less than 30%; and the response speed of the semiconductor photodetector 200 is less than 100 ps. Therefore, this application can be applied in the field of optical communication, specifically as a DFB laser integrated chip based on the InP / InGaAsP material system, for use in scenarios such as data center optical interconnects.

[0086] Example 1: like Figures 1-3 As shown, this application provides an integrated chip with power monitoring capabilities, such as... Figure 4 and Figure 5 As shown, it includes, from bottom to top, an N-side metal layer 1, a substrate layer 2, a buffer layer 3, a lower confinement layer 4, a multiple quantum well layer 5, an upper confinement layer 6, a spacer layer 7, a grating layer 8, a capping layer 9, a cladding layer 10, a contact layer 11, a passivation layer 12, and a P-side metal layer 13.

[0087] The N-side metal layer 1 is an N-type nickel / gold alloy layer with a thickness of 500 nm; the substrate layer 2 is an N-type InP with a thickness of 2 μm; the buffer layer 3 is an undoped In0.53Ga0.47As with a thickness of 100 nm; the lower confinement layer 4 is InGaAsP with a thickness of 150 nm; the multiple quantum well layer 5 is InGaAsP with a thickness of 100 nm; the upper confinement layer 6 is InGaAsP with a thickness of 150 nm; the spacer layer 7 is undoped InGaAsP with a thickness of 100 nm; the grating layer 8 is InP with a thickness of 80 nm; the capping layer 9 is InGaAsP with a thickness of 500 nm; the cladding layer 10 is InGaAsP with a thickness of 2 μm; the contact layer 11 is P-type InGaAs with a thickness of 100 nm; the passivation layer 12 is SiO2 with a thickness of 1 μm; and the P-side metal layer 13 is a P-type gold-germanium-nickel alloy layer with a thickness of 300 nm.

[0088] The projected length of the laser waveguide 101 of the semiconductor laser 100 along the cavity length direction of the optical integrated chip is 5000 μm, such as... Figure 3 As shown, a combination of straight waveguide and inclined waveguide design is adopted. The inclined waveguide has a length of 2000μm and is inclined at 5° towards the length of the integrated chip at the light-emitting end. The angle between the centerline of the laser waveguide 101 and the length direction of the integrated chip cavity is 25°. In the straight waveguide, a periodic grating 81 with a period of 290nm is etched on the grating layer 8 to realize single-mode lasing.

[0089] The semiconductor photodetector 200 has a rectangular mesa structure with a length of 300 μm and a width of 100 μm, a quantum efficiency of 40%, and a response speed of 50 ps. The semiconductor photodetector 200 operates by applying a -5V reverse bias voltage through the P-side metal layer 13 on the right side.

[0090] An antireflective coating with a thickness of 50 nm is set at the light-emitting end of the integrated chip, and the light-emitting end face has a conical structure with a conical angle of 20°; a high reflectivity dielectric film with a thickness of 100 nm and a reflectivity of 92% is set at the backlight end of the integrated chip.

[0091] Example 2: like Figures 1-3 As shown, this application also provides another integrated chip with power monitoring, such as... Figure 4 and Figure 5 As shown, it includes, from bottom to top, an N-side metal layer 1, a substrate layer 2, a buffer layer 3, a lower confinement layer 4, a multiple quantum well layer 5, an upper confinement layer 6, a spacer layer 7, a grating layer 8, a capping layer 9, a cladding layer 10, a contact layer 11, a passivation layer 12, and a P-side metal layer 13.

[0092] The N-side metal layer 1 is an N-type gold-germanium-nickel alloy layer with a thickness of 300 nm; the substrate layer 2 is an N-type InP with a thickness of 3 μm; the buffer layer 3 is undoped In0.52Ga0.48As with a thickness of 150 nm; the lower confinement layer 4 is InGaAsP with a thickness of 120 nm; the multiple quantum well layer 5 is InGaAsP with a thickness of 120 nm; the upper confinement layer 6 is InGaAsP with a thickness of 180 nm; the spacer layer 7 is undoped InGaAsP with a thickness of 150 nm; the grating layer 8 is InP with a thickness of 100 nm; the capping layer 9 is InGaAsP with a thickness of 600 nm; the cladding layer 10 is InGaAsP with a thickness of 2.5 μm; the contact layer 11 is P-type InGaAs with a thickness of 150 nm; the passivation layer 12 is Si3N4 with a thickness of 1.5 μm; and the P-side metal layer 13 is a P-type gold-germanium-nickel alloy layer with a thickness of 400 nm.

[0093] The laser waveguide 101 of the semiconductor laser 100 has a projected length of 4000 μm along the cavity length of the integrated chip. It adopts a combination design of straight waveguide and curved waveguide, with the curved waveguide having a length of 1500 μm. The waveguide is tilted at 15° towards the length of the integrated chip at the light-emitting end, and the angle between the centerline of the laser waveguide 101 and the cavity length of the integrated chip is 35°. A periodic grating 81 with a period of 300 nm is etched on the grating layer 8 of the straight waveguide to achieve single-mode lasing.

[0094] The semiconductor photodetector 200 has a circular mesa structure with a diameter of 200 μm, a quantum efficiency of 35%, and a response speed of 70 ps. The semiconductor photodetector 200 operates by applying a reverse bias of -8V through the P-side metal layer 13 on the right side.

[0095] An antireflective coating with a thickness of 70 nm is set at the light-emitting end of the integrated chip, and the light-emitting end face has a conical structure with a conical angle of 25°; a high reflectivity dielectric film with a thickness of 120 nm and a reflectivity of 95% is set at the backlight end of the integrated chip.

[0096] Example 3: Combination Figures 1-3 This embodiment provides a method for fabricating the integrated chip with power monitoring, specifically including the following steps: Step 1: Epitaxial layer growth Using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), the following epitaxial layer structures are deposited sequentially from bottom to top on substrate 2 during the same epitaxial growth process: On an N-type InP substrate, a buffer layer 3, a lower confinement layer 4, a multiple quantum well layer 5, an upper confinement layer 6, a spacer layer 7, a grating layer 8, a capping layer 9, a cladding layer 10, and a contact layer 11 are grown sequentially.

[0097] The substrate layer 2 is made of N-type InP material with a thickness of 2 μm to 3 μm; the buffer layer 3 is made of undoped InGaAsP material with a thickness of 100 nm to 150 nm; the lower confinement layer 4 is made of InGaAsP material with a thickness of 120 nm to 150 nm; the multiple quantum well layer 5 is made of InGaAsP material and consists of 5 to 8 alternating well and barrier layers with a total thickness of 100 nm to 120 nm; the upper confinement layer 6 is made of InGaAsP material with a thickness of 150 nm to 180 nm; the spacer layer 7 is made of undoped InGaAsP material with a thickness of 100 nm to 150 nm; the grating layer 8 is made of InP material with a thickness of 80 nm to 100 nm; the capping layer 9 is made of InGaAsP material with a thickness of 500 nm to 600 nm; the cladding layer 10 is made of InGaAsP material with a thickness of 2 μm to 2.5 μm; and the contact layer 11 is made of P-type InGaAs material with a thickness of 100 nm to 150 nm.

[0098] Step 2: Grating fabrication Periodic gratings 81 are formed on the surface of the grating layer 8 corresponding to the straight waveguide using electron beam lithography (EBL) or nanoimprint lithography (NIL). The grating period is determined according to the target lasing wavelength, specifically 290 nm to 300 nm, the grating duty cycle is 0.4 to 0.6, and the etching depth is 40 nm to 60 nm. Periodic grating structures are not placed in the inclined or curved waveguide regions.

[0099] Step 3: Mesa Structure and Waveguide Fabrication Using photolithography and etching processes, physically separated mesa structures are formed along the width direction of the integrated chip, specifically including: First, photoresist is coated on the surface of contact layer 11, and the patterns of semiconductor laser 100 and semiconductor photodetector 200 are defined by photolithography. The projected length of the waveguide of semiconductor laser 100 along the cavity length direction of the integrated optical chip is equal to the length of the integrated chip, while the projected length of the waveguide of semiconductor photodetector 200 along the cavity length direction is less than the length of the integrated optical chip. That is, the total length of the laser waveguide of the semiconductor laser extending along its light transmission path from the backlight end to the light-emitting end of the integrated chip is equal to the dimension of the integrated chip in the cavity length direction; the length of the photodetector waveguide 201 of the semiconductor photodetector along its light transmission path is less than the dimension of the integrated chip in the cavity length direction.

[0100] Then, using inductively coupled plasma reactive ion etching (ICP-RIE) or wet etching processes, the cladding layer 10 and contact layer 11 are etched to form a mesa structure. The etching depth is 2 μm to 2.5 μm, until it penetrates the contact layer 11 and enters the interior of the cladding layer 10, forming a physical isolation region in the width direction, thereby separating the semiconductor laser 100 and the semiconductor photodetector 200 in the width direction of the integrated chip.

[0101] The laser waveguide 101 of the semiconductor laser 100 adopts a combination of straight waveguide and oblique waveguide, or a combination of straight waveguide and curved waveguide. The straight waveguide extends along the length of the integrated chip, and the oblique or curved waveguide is disposed at the light-emitting end. The angle between the centerline of the laser waveguide 101 and the length direction of the integrated chip cavity is 5° to 45°. The waveguide width is 2μm to 50μm.

[0102] The mesa structure of the semiconductor photodetector 200 has a circular, triangular, rectangular or polygonal projection shape in the substrate direction, with a mesa structure length of 100μm to 500μm and a width of 50μm to 200μm.

[0103] Step 4: Passivation layer preparation A passivation layer 12 is deposited on the entire surface of the integrated chip using plasma-enhanced chemical vapor deposition (PECVD). The passivation layer material is SiO2 or Si3N4, and the thickness is 1 μm to 1.5 μm. Electrode windows are then created on the passivation layer 12 using photolithography and etching processes to expose the electrode areas on the surface of the contact layer 11.

[0104] Step 5: Electrode Preparation A P-plane metal layer 13 is deposited in the electrode window region of the passivation layer 12 using electron beam evaporation or magnetron sputtering. The P-plane metal layer 13 is a TiPtAu multilayer metal structure or a P-type gold-germanium-nickel alloy layer with a thickness of 300 nm to 400 nm. An N-plane metal layer 1 is deposited on the back side of the substrate layer 2. The N-plane metal layer is an AuGeNi alloy layer or an N-type nickel / gold alloy layer with a thickness of 300 nm to 500 nm.

[0105] The P-side metal layer 13 forms independent electrode structures in the semiconductor laser 100 and the semiconductor photodetector 200, which are used to apply forward bias and reverse bias, respectively.

[0106] Step Six: End Face Coating An antireflective dielectric film is deposited on the light-emitting end of the integrated chip using electron beam evaporation or ion-assisted deposition processes. The antireflective dielectric film is formed by alternating stacking of SiO2 and Si3N4 to form a multilayer structure with a total thickness of 50nm to 70nm, which reduces the reflectivity of the light-emitting end face to below 5%.

[0107] A high-reflectivity dielectric film is deposited on the backlight end of the integrated chip. The high-reflectivity dielectric film is formed by alternating stacking of SiO2 and Si3N4 to form a multilayer structure with a total thickness of 100nm to 120nm, so that the reflectivity of the backlight end face is not less than 90%.

[0108] Step 7: Integrated Chip Cleavage and Testing The wafer is diced into individual integrated chips using laser dicing or diamond dicing processes. The fabricated integrated chips are then tested. A semiconductor laser 100 is forward biased through a P-side metal layer to generate gain and output laser light; a semiconductor photodetector 200 is reverse biased through a P-side metal layer to convert reflected light from the output end face into photocurrent, enabling on-chip power monitoring.

[0109] The integrated chip prepared by the above method has a cavity length of 500μm to 5000μm, which enables on-chip power monitoring without the need for an external optical path, simplifies the packaging structure, reduces costs and improves system stability.

[0110] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this application. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this application. Furthermore, the shapes and sizes of the components in the drawings do not reflect actual size and proportion, but only illustrate the content of the embodiments of this application. Moreover, the word "comprising" does not exclude the presence of elements or steps not listed. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0111] Similarly, it should be understood that, in order to simplify this application and aid in understanding one or more of the various aspects of the invention, in the description of exemplary embodiments of this application above, various features of this application are sometimes grouped together into a single embodiment, figure, or description thereof.

[0112] The above specific embodiments further illustrate the purpose, technical solution and beneficial effects of this application. It should be understood that the above are only specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An integrated chip with power monitoring capabilities, characterized in that, The integrated chip includes a substrate layer and a multilayer semiconductor structure epitaxially grown sequentially on the substrate layer. The multilayer semiconductor structure includes at least a lower confinement layer, an active layer, an upper confinement layer, and an upper contact layer. The upper contact layer and a portion of the underlying layer structure are etched to form physically separated mesa structures on the integrated chip, physically separating a semiconductor laser and a semiconductor photodetector in the width direction. The semiconductor laser is configured to generate laser light when a first bias voltage is applied, and the semiconductor photodetector is configured to convert a received optical signal into an electrical signal when a second bias voltage is applied. The electrode corresponding to the semiconductor laser is configured to be subjected to a first voltage that causes it to generate stimulated emission, and the electrode corresponding to the semiconductor photodetector is configured to be subjected to a second voltage that causes it to generate a photoelectric response; wherein, the semiconductor photodetector is configured to receive a portion of the light signal reflected back from the light-emitting end face of the semiconductor laser.

2. The integrated chip with power monitoring according to claim 1, characterized in that, The laser waveguide of the semiconductor laser is configured to guide the reflected light from its output end face to the semiconductor photodetector.

3. An integrated chip with power monitoring according to claim 1, characterized in that, The total length of the laser waveguide of the semiconductor laser extending from the backlight end of the integrated chip to the light-emitting end along its optical transmission path is equal to the dimension of the integrated chip in the cavity length direction; the length of the optical detection waveguide of the semiconductor photodetector along its optical transmission path is less than the dimension of the integrated chip in the cavity length direction.

4. An integrated chip with power monitoring according to any one of claims 1 to 3, characterized in that, The laser waveguide of the semiconductor laser is tilted at the output end on either side of the integrated chip length direction, and the angle between the centerline of the laser waveguide and the cavity length direction of the integrated chip is 5 to 45°, so as to guide the reflected light from the output end face to deviate from the original transmission path and be captured by the semiconductor photodetector; the semiconductor photodetector is located on the side of the laser waveguide that is tilted, so as to directly receive the reflected light in the width direction of the integrated chip.

5. An integrated chip with power monitoring according to any one of claims 1 to 3, characterized in that, The laser waveguide of the semiconductor laser is a combination of a straight waveguide and a slanted waveguide, or a combination of a straight waveguide and a curved waveguide.

6. An integrated chip with power monitoring according to claim 5, characterized in that, The semiconductor laser has a periodic grating etched on the corresponding grating layer of the straight waveguide to achieve single-mode lasing, and no periodic grating structure in the oblique waveguide or curved waveguide region. An anti-reflection dielectric film is deposited at the light-emitting end of the integrated chip; a high-reflectivity dielectric film is deposited at the backlight end of the integrated chip.

7. An integrated chip with power monitoring according to any one of claims 1 to 3, characterized in that, The cavity length of the integrated chip is 500μm to 5000μm; the laser waveguide width of the semiconductor laser is 2μm to 50μm.

8. An integrated chip with power monitoring according to any one of claims 1 to 3, characterized in that, The mesa structure of the semiconductor photodetector has a projection shape of a circle, triangle, rectangle, or polygon in the direction of the substrate layer to adapt to the spatial distribution of reflected light.

9. An integrated chip with power monitoring according to any one of claims 1 to 3, characterized in that, The mesa structure of the semiconductor photodetector has a length of 100μm-500μm, a width of 50μm-200μm, a quantum efficiency of not less than 30%, and a response speed of less than 100ps.

10. A method for fabricating an integrated chip with power monitoring, used to fabricate an integrated chip with power monitoring as described in any one of claims 1 to 9, characterized in that, include: A multi-layer structure is formed from bottom to top through the same epitaxial growth process. The multi-layer structure includes at least a lower confinement layer, an active layer, an upper confinement layer, and an upper contact layer. The mesa structure is formed by photolithography and etching processes to separate the semiconductor laser and the semiconductor photodetector in the width direction.

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