FPGA-based composite video signal generation and acquisition system

Abstract

The application relates to an FPGA-based composite video signal generation and acquisition system and relates to the technical field of video signal processing.The system comprises an FPGA chip and an external supporting circuit, the FPGA chip is integrated with a video signal input sub-module, a video signal receiving sub-module and a video data comparison and verification sub-module; the video signal input sub-module supports LVDS and DVI format signal generation and input, the video signal receiving sub-module supports LVDS, eDP and mini-LVDS format signal receiving and analysis, and the video data comparison and verification sub-module compares the time sequence and pixel difference of input and feedback video data; the FPGA chip adopts a modular architecture to realize multi-format compatibility, multi-channel parallel processing and accurate verification; and the external supporting circuit comprises a signal driving circuit, an interface protection circuit and a clock auxiliary circuit.The application has the advantages of multi-format compatibility, stable multi-channel processing, accurate verification, flexible configuration, strong anti-interference capability, integration of signal generation, receiving and comparison and verification, and is suitable for PCBA video processing function testing.

Description

Technical Field

[0001] This invention relates to the field of video signal processing technology, and more specifically to an FPGA-based composite video signal generation and acquisition system. Background Technology

[0002] With the rapid development of electronic devices, PCBAs (Printed Circuit Board Assemblies) are widely used in various electronic products, and the reliability of their video signal processing function directly affects product performance. Currently, PCBA video signal testing needs to be compatible with multiple video formats (such as LVDS, DVI, eDP, mini-LVDS) and support parallel processing of multiple signals, as well as accurate signal generation and reception verification.

[0003] Existing video signal generation and acquisition solutions have the following shortcomings: 1) Poor multi-format compatibility: most solutions only support one or a few video formats, making it difficult to meet the testing requirements of multiple interfaces in PCBA; 2) Insufficient multi-channel parallel processing capability: resource competition between different modules leads to unstable signal transmission timing and high data error rate; 3) Low signal comparison and verification accuracy: lack of accurate detection of timing differences and pixel detail differences makes it difficult to locate faults; 4) Weak anti-interference capability: external noise, static electricity, etc., can easily cause signal distortion or chip damage; 5) Insufficient parameter configuration flexibility: the program needs to be re-programmed to adjust signal parameters, resulting in poor adaptability.

[0004] Therefore, a composite video signal generation and acquisition scheme that is compatible with multiple formats, stable in multi-channel parallel operation, accurate in verification, strong in anti-interference capability, and flexible in configuration is needed to overcome the shortcomings of existing technologies. Summary of the Invention

[0005] A primary objective of this invention is to overcome at least one of the aforementioned deficiencies and to provide an FPGA-based composite video signal generation and acquisition system that can comprehensively adapt to the generation and acquisition of multiple video signal formats, has stable processing timing, and offers high verification accuracy and strong anti-interference capabilities.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: This invention provides an FPGA-based composite video signal generation and acquisition system, comprising an FPGA chip and peripheral circuitry. The FPGA chip integrates a multi-format video signal processing module, which includes a video signal input submodule, a video signal receiving submodule, and a video data comparison and verification submodule, wherein: The video signal input submodule supports the generation and input of LVDS and DVI format video signals, the video signal receiving submodule supports the reception and parsing of LVDS, eDP and mini-LVDS format video signals, and the video data comparison and verification submodule is used to compare the differences between the input video data input by the video signal input submodule and the feedback video data received by the video signal receiving submodule. The FPGA chip achieves multi-format signal compatibility and adaptation, multi-channel parallel processing and accurate verification through a modular architecture. The peripheral circuits include signal driving circuits, interface protection circuits and clock auxiliary circuits.

[0007] According to one embodiment of the present invention, the video signal input submodule is provided with corresponding input submodules for LVDS and DVI format video signals, and each input submodule supports independent input of video data of the corresponding format.

[0008] According to one embodiment of the present invention, the architecture of each input submodule is the same, including a video source generation module, an encoding and standard switching module, a clock management module and a multi-output control module integrated within the FPGA; The video source generation module supports real-time generation of built-in test patterns such as color bars, grayscale levels, and checkerboard patterns. It configures redundant data such as the number of effective pixels per row, the number of effective rows per frame, and the number of extra rows through registers, and uses an 8-bit parallel data bus to transmit R, G, and B channel data. The encoding and standard switching module is used to realize JEIDA / VESA standard switching and differential signal encoding. The clock management module is used to generate and allocate clocks and control refresh rates. The multi-output control module is used to switch channel modes and independently control each LVDS channel.

[0009] According to one embodiment of the present invention, the clock management module uses an internal PLL of the FPGA to generate a 20MHz~90MHz odd pixel clock, supports 1MHz adjustable step size, distributes clock signals through a global clock network, and achieves an adjustable refresh rate of 60Hz~120Hz by adjusting the period of the horizontal synchronization signal.

[0010] According to one embodiment of the present invention, the video signal receiving submodule is provided with corresponding receiving submodules for LVDS, eDP and mini-LVDS format video signals, and each input submodule supports independent input of video data of the corresponding format.

[0011] According to one embodiment of the present invention, the receiving submodules have the same architecture, including a clock recovery and synchronization module, a decoding and standard adaptation module, and a data buffer and format adaptation module integrated within the FPGA. The clock recovery and synchronization module extracts the clock through CDR logic and achieves synchronization locking; the decoding and standard adaptation module realizes differential signal decoding and standard switching; the data buffer and format adaptation module uses BRAM to build a frame buffer and achieves resolution adaptation.

[0012] According to one embodiment of the present invention, the video data comparison and verification submodule includes a data acquisition module, a timing comparison module, a pixel comparison module, and a result processing and output module integrated within the FPGA, wherein... The data acquisition module collects pixel data and timing parameters of the input video data and feedback video data and achieves frame alignment; the timing comparison module compares the differences in clock cycle, refresh rate and synchronization signal delay; the pixel comparison module compares the RGB values ​​pixel by pixel in "row → column" order and records the difference coordinates; the result processing and output module integrates the difference information and uploads it to the host computer, while triggering an alarm mechanism.

[0013] According to one embodiment of the present invention, the pixel comparison module adopts a pipeline architecture to process multi-line pixel comparison in parallel, the result processing and output module uploads the difference report through a UART interface or an Ethernet interface, supports storage to an external SD card, and the alarm mechanism includes an LED alarm.

[0014] According to one embodiment of the present invention, the FPGA chip receives configuration parameters from the host computer via the SPI interface and uploads status information via the IIC interface. The configuration parameters include channel mode, standard type, clock frequency, resolution, refresh rate, and channel enable status.

[0015] According to one embodiment of the present invention, the FPGA chip adopts a resource partitioning design, allocating video signal processing related modules to independent logic resource areas, and achieving signal timing alignment through a global clock network and a synchronization register chain.

[0016] Compared with existing technologies, the advantages and beneficial effects of the FPGA-based composite video signal generation and acquisition system proposed in this patent application are as follows: This application supports four mainstream video formats: LVDS, DVI, eDP, and mini-LVDS, covering common PCBA video interfaces. It eliminates the need to change test equipment, offering wide adaptability and strong compatibility. Furthermore, it integrates signal generation, reception, and comparison verification, simplifying the test system architecture, reducing testing costs, improving testing efficiency, and achieving high functional integration. It employs FPGA resource partitioning design and a global clock synchronization mechanism to avoid resource contention between modules, ensuring timing stability when processing multiple signals simultaneously. This achieves stable parallel processing and effectively reduces data error rates. In terms of verification, it implements dual comparison of timing differences (clock cycle, refresh rate, synchronization delay) and pixel RGB value differences, accurately recording difference parameters and pixel coordinates to provide precise evidence for fault diagnosis.

[0017] In addition, the system provided in this application adjusts signal parameters in real time through the configuration register of the host computer, without the need to reprogram the FPGA, adapting to different test requirements such as resolution and refresh rate, and is flexible and convenient to configure. Detailed Implementation

[0018] The technical solution of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0020] This embodiment describes an FPGA-based composite video signal generation and acquisition system, including an FPGA chip (such as the Xilinx Kintex-7 series) and external supporting circuits. The FPGA chip integrates a multi-format video signal processing module. The external supporting circuits include a dedicated LVDS driver chip (TI's SN75LVDS83), a dedicated eDP receiver chip (TI's SN65DP159), a mini-LVDS receiver chip (ON Semiconductor's NCV7685), an ESD protection device (Littelfuse's SP0508), a TVS diode (Littelfuse's SMBJ6.5CA), an optocoupler isolation module (Toshiba's TLP181), DDR3 SDRAM (Micron's MT41J128M16HA-125), an SD card interface, a UART interface, an Ethernet interface, and an LED alarm device.

[0021] The composite video signal generation and acquisition system of this embodiment is used to test the product under test. The composite video signal generation and acquisition system includes an FPGA chip and peripheral circuitry. The FPGA chip integrates a multi-format video signal processing module, which includes a video signal input submodule, a video signal receiving submodule, and a video data comparison and verification submodule. The video signal input submodule is used to inject video signals into the product under test. The video signal input submodule supports the generation and input of LVDS and DVI format video signals. The video signal receiving submodule is used to receive signals output by the product under test, and supports the reception and parsing of LVDS, eDP and mini-LVDS format video signals; The video data comparison and verification submodule is used to compare the difference between the input video data input by the video signal input submodule and the feedback video data received by the video signal receiving submodule, thereby reflecting the yield of the tested product. The FPGA chip achieves multi-format signal compatibility and adaptation, multi-channel parallel processing and accurate verification through a modular architecture. The peripheral circuits include signal driving circuits, interface protection circuits and clock auxiliary circuits.

[0022] I. Specific Implementation of the Video Signal Input Submodule 1.1 LVDS Input Submodule (1) FPGA internal logic implementation Video source generation module: Generates color bars (RGB 8-bit fixed values ​​cycling), grayscale levels (0~255 gradient), and checkerboard (alternating black and white pixels) test patterns through hardware logic; Configures the number of effective pixels per row (e.g., 1920), the number of effective rows per frame (e.g., 1082), and two additional rows of redundant data (configured as synchronization signals) through registers, automatically adjusting the period and pulse width of the horizontal / vertical synchronization signals; Uses an 8-bit parallel bus to transmit R, G, and B three-channel data, with timing strictly synchronized with the LVDS clock.

[0023] LVDS Encoding and Standard Switching Module: Selects either JEIDA or VESA standard via configuration register. When JEIDA standard is selected, data is transmitted in the order of "odd pixel → big pixel", with the synchronization signal embedded in the data channel. When VESA standard is selected, data is transmitted in the order of "big pixel → odd pixel", with the synchronization signal transmitted separately. The parallel RGB data is converted into LVDS differential signals through internal differential drive logic.

[0024] Clock management module: It uses the FPGA's internal PLL to generate a 20MHz~90MHz odd-even pixel clock with an adjustable step size of 1MHz. The clock frequency is configured via the host computer's SPI interface. The clock is distributed to each module through a global clock network (BUFG) to ensure phase consistency. By adjusting the horizontal synchronization signal period, the refresh rate can be adjusted from 60Hz to 120Hz (e.g., a refresh rate of 60Hz when the horizontal synchronization period is 16.67ms, and a refresh rate of 120Hz when the horizontal synchronization period is 8.33ms).

[0025] Multi-output control module: The channel mode is controlled by the mode selection register (address 0x0001). When bit0=0, it is a 2-channel single-pixel mode, activating 2 LVDS encoded channels. Each channel is independently configured with resolution (register 0x0002~0x0005) and clock frequency (register 0x0006~0x0007). When bit0=1, it is a 1-channel dual-pixel mode, disabling 1 channel and merging data output. The enable state of each channel is controlled by registers 0x0008~0x0009 (bit0=1 enables).

[0026] (2) External hardware circuit The dedicated LVDS driver chip SN75LVDS83 amplifies the power of the LVDS differential signal output from the FPGA, and the output impedance is matched by an external 50Ω resistor. The interface is divided into Data Line (transmitting differential data), Gradient Line (transmitting pixel gradient compensation signal), and Visible Area (transmitting visible area control signal). The interface end is connected in series with ESD protection device SP0508 and TVS diode SMBJ6.5CA to prevent electrostatic discharge and transient high voltage.

[0027] (3) Parameter configuration process The host computer writes configuration parameters to the FPGA registers via the SPI interface: channel mode (0x0001), LVDS standard (0x000A, bit0=0 for JEIDA, bit0=1 for VESA), clock frequency (0x0006~0x0007), resolution (0x0002~0x0005), refresh rate (configured via the horizontal synchronization cycle, register 0x000B), and channel enable (0x0008~0x0009). After receiving the parameters, the FPGA sequentially completes PLL clock locking, video source generation, and LVDS encoding, and inputs the signal to the PCBA via SN75LVDS83. The FPGA uploads the PLL lock status (0x0010, bit0=1 locked) and channel enable status (0x0011~0x0012) via the IIC interface (address 0x40). When the clock is lost, LED1 alarm is triggered.

[0028] 1.2 DVI Input Submodule (1) FPGA internal logic implementation Video source generation module: Supports built-in test pattern generation and external data import. It reads BMP images through the SD card interface and converts them into 8-bit RGB data through the decoding module. It configures the number of effective pixels per line, the number of effective lines per frame, and the data type of the additional 2 lines through registers 0x0100~0x0103, and automatically calculates the line / field blanking duration.

[0029] TMDS Encoding Module: Following the DVI 1.0 standard, it uses the "minimize transition" algorithm to convert 8-bit RGB data into 10-bit TMDS data, while encoding Hsync, Vsync, and DE control signals; it allocates independent encoding logic units for the two DVI channels (addresses 0x0104~0x0107 configure encoding parameters).

[0030] Clock management module: adopts a dual PLL architecture. PLL1 generates CLK_DVI1 (configured by registers 0x0108~0x0109) at 100MHz~180MHz, and PLL2 generates CLK_DVI2 (configured by registers 0x010A~0x010B), with jitter ≤50ps. The phase difference between the two clocks is adjusted to ≤10ns through the phase calibration register 0x010C. The clock is distributed to each module through BUFG.

[0031] Multi-output control module: 2 independent configuration register groups for each channel (Channel 1: 0x0110~0x011F, Channel 2: 0x0120~0x012F), supporting individual configuration of resolution, refresh rate, and video source type; Status registers 0x0130~0x0131 store the channel working status, and trigger the corresponding channel alarm when the PLL loses lock (LED2 corresponds to Channel 1, LED3 corresponds to Channel 2).

[0032] (2) External hardware circuit A TMDS differential driver chip (TI's SN75LVDS86) is used to convert the TMDS encoded data output by the FPGA into a differential signal and output it to the DVI interface of the PCBA; ESD protection devices and TVS diodes are set at the interface end, and an optocoupler isolation module isolates external interference.

[0033] (3) Parameter configuration process The host computer writes configuration instructions via the SPI interface: channel enable (0x0110 bit0, 0x0120 bit0), resolution (0x0100~0x0103), clock frequency (0x0108~0x010B), video source type (0x0111 bit0=0 built-in pattern, bit0=1 external import), and synchronization mode (0x010C). The FPGA completes PLL initialization, video source generation, and TMDS encoding, and outputs signals through SN75LVDS86. The status register is read every 10ms, and the corresponding channel is stopped and reported to the host computer when an abnormality occurs.

[0034] II. Detailed Implementation of the Video Signal Receiving Submodule 2.1 LVDS Receiver Submodule (1) FPGA internal logic implementation Clock recovery and synchronization module: Extracts 20MHz~90MHz clock from LVDS differential data through CDR logic, eliminates metastability through multi-sampling (3 times); monitors the rising edge of the horizontal / vertical synchronization signal to achieve frame synchronization locking, and stores the synchronization status in register 0x0200 (bit0=1 for locking).

[0035] LVDS Decoding and Standard Adaptation Module: Converts differential signals into single-ended parallel data and adjusts the parsing order according to configuration register 0x0201 (bit0=0 JEIDA, bit0=1 VESA); in dual-pixel mode, splits 24-bit data into two 12-bit single-pixel data streams and converts them into RGB 8-bit data.

[0036] Data caching and format adaptation module: The frame buffer is built using BRAM (the maximum resolution supported is 1920×1082). The resolution is automatically identified by monitoring the line / field synchronization cycle and stored in registers 0x0202~0x0203. The bit width of the RGB data is detected, and an error signal is triggered when there is an abnormality (register 0x0204 bit0=1).

[0037] (2) External hardware circuit An LVDS receiver chip (TI's SN75LVDS87) is used to filter and condition the LVDS signal output from the PCBA before outputting it to the FPGA. ESD protection and TVS diodes are set at the interface, and an optocoupler isolation module isolates interference.

[0038] (3) Status monitoring process The FPGA monitors the clock lock status (0x0200), frame synchronization status (0x0205), and data error status (0x0204) in real time. When the clock is lost, the CDR logic is automatically restarted. If the clock fails three times in a row, LED4 alarm is triggered and reported to the host computer.

[0039] 2.2 eDP Receiver Submodule (1) FPGA internal logic implementation CDR module: Extracts high-frequency clock (accuracy ±10ppm) from eDP serial differential data, samples serial data at high speed, and achieves complete data frame reception through bit synchronization and frame synchronization logic. The synchronization status is stored in register 0x0300.

[0040] eDP protocol parsing module: During the initialization phase, it performs link training with the PCBA eDP transmitter, negotiating the number of lanes, rate, and equalization parameters (configuration registers 0x0301~0x0303); it performs 8b / 10b decoding on serial data, recovers 8-bit parallel data, and extracts RGB pixel data and control signals; it calculates the refresh rate by counting the Vsync signal cycles and stores it in register 0x0304.

[0041] Data caching and format conversion module: BRAM stores the current row data, and DDR3 SDRAM stores the complete frame data to avoid data loss; converts RGB data into a unified parallel format and outputs it to the video comparison module, synchronizing the timing with the recovery clock.

[0042] (2) External hardware circuit The dedicated eDP receiver chip SN65DP159 conditions and equalizes the eDP signal output from the PCBA and outputs it to the FPGA; the interface is equipped with ESD protection, TVS diode and optocoupler isolation module.

[0043] 2.3 mini-LVDS Receiver Submodule (1) FPGA internal logic implementation Mode switching and configuration module: The receive mode is selected through register 0x0400 (bit0=0 for 1CLK+3DATA, bit0=1 for 2CLK+12DATA); in 1CLK+3DATA mode, 1 clock channel and 3 data channels (12 bits each) are configured; in 2CLK+12DATA mode, 2 clock channels and 12 data channels (8 bits each) are configured.

[0044] Clock recovery and synchronization module: In 1CLK+3DATA mode, the clock is extracted from the differential clock pair of 1 channel and the sampling clock is generated by PLL frequency multiplication / division; in 2CLK+12DATA mode, the odd / even element clock is extracted and the phase difference is ≤5ns through synchronization logic; multi-sampling (3-sampling) eliminates metastability and the frame synchronization status is stored in register 0x0401.

[0045] The mini-LVDS data decoding module converts differential signals into single-ended parallel data. In 1CLK+3DATA mode, it reassembles 36-bit data into 3-pixel RGB data, and in 2CLK+12DATA mode, it reassembles 96-bit data into 12-pixel RGB data. It performs parity checking, and stores the error status in register 0x0402 (bit0=1 error).

[0046] (2) External hardware circuit The NCV7685 mini-LVDS receiver chip receives and conditions the mini-LVDS signal output from the PCBA and outputs it to the FPGA; the interface is equipped with ESD protection, TVS diode and optocoupler isolation module.

[0047] III. Specific Implementation of the Video Data Comparison and Verification Submodule 3.1 FPGA Internal Logic Implementation Data acquisition module: Acquires 8-bit RGB data of input video from LVDS input and DVI input modules via internal data bus (stored in BRAM input frame buffer, address 0x100000~0x17FFFF) and timing parameters (clock cycle, refresh rate, synchronization signal parameters, stored in input timing register 0x0500~0x050F); acquires 8-bit RGB data of feedback video from LVDS receiver, eDP receiver, and mini-LVDS receiver modules (stored in BRAM receive frame buffer, address 0x180000~0x1FFFFF) and timing parameters (stored in receive timing register 0x0510~0x051F); triggers acquisition through frame synchronization signal (register 0x0520 bit0=1) to ensure frame alignment.

[0048] Timing Comparison Module: Reads the clock cycle value from the input and timing register, calculates the difference (accuracy 0.1ns), stores the threshold in register 0x0521 (default 0.5ns), and records values ​​exceeding the threshold in timing difference register 0x0522; calculates the refresh rate difference, with a threshold of 0.2Hz, and records values ​​exceeding the threshold in 0x0523; measures the Hsync / Vsync signal delay, with a threshold of 20ns, and records values ​​exceeding the threshold in 0x0524.

[0049] Pixel comparison module: Adopts a pipelined architecture to process 4 rows of pixel comparisons in parallel; Based on the input data, it compares RGB values ​​pixel by pixel in the order of row number (0~1081) and column number (0~1919). The comparison accuracy is configured through register 0x0525 (bit0=0 for exact comparison, bit0=1 for ±1 error); When a difference is detected, the row number and column number are written to the difference coordinate FIFO (depth 1024), and the FIFO state is stored in 0x0526.

[0050] The results processing and output module reads the timing difference register and the difference coordinate FIFO, integrates them into a difference report (format: timing difference [clock cycle difference: X ns, refresh rate difference: Y Hz, synchronization delay: Z ns]; difference pixel coordinates [(row 1, column 1), (row 2, column 2),...]); uploads the report to the host computer via UART interface (baud rate 115200) or Ethernet interface (TCP / IP protocol), and simultaneously stores it on the SD card (path / SD / DIFF_REPORT_YYYYMMDDHHMMSS.txt); when the number of difference pixels exceeds the threshold (configured by register 0x0527, default 100) or the timing difference is severe, triggers LED5 alarm.

[0051] 3.2 Host Computer Software Interaction The host computer software is developed using LabVIEW. After receiving the difference report, it graphically displays the timing difference curve and shows the difference parameters in a table. The video preview window marks the difference pixels in red and displays the difference coordinates in a list. It supports exporting the difference report to Excel / TXT format and storing historical data. It provides a parameter configuration interface, and the configuration commands are sent to the FPGA via the SPI interface.

[0052] IV. Overall System Control Flow System initialization: After the FPGA is powered on, the internal registers are initialized to their default values, the PLL, BRAM, and DDR3 SDRAM are initialized, and the initialization status is reported to the host computer via IIC; Parameter configuration: The host computer sends configuration parameters, and the FPGA receives them and updates the corresponding registers to configure the working mode and parameters of each submodule; Signal generation and reception: The video signal input submodule generates and outputs LVDS / DVI signals to the PCBA, and the video signal receiving submodule receives and analyzes the LVDS / eDP / mini-LVDS signals fed back from the PCBA. Data comparison and verification: The video data comparison and verification submodule collects input and feedback data, performs time-series and pixel comparisons, and generates a difference report; Results output and alarms: The difference report is uploaded to the host computer and stored. An LED alarm is triggered when an anomaly occurs. Status monitoring and anomaly handling: The FPGA monitors the status of each module in real time. When anomalies such as clock loss or data error occur, it automatically attempts to recover (restarting the CDR, relocking the PLL, etc.). If the recovery fails, the corresponding module is stopped and the host computer is notified.

[0053] In this embodiment, the FPGA chip, through modular design and cooperation with external supporting circuits, realizes the generation, reception, and accurate comparison and verification of multi-format video signals, meets the testing requirements of PCBA video processing functions, and has good compatibility, stability and practicality.

[0054] The above embodiments are only for illustrating the technical concept and features of the present invention. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be used to limit the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention. This invention relates to an FPGA-based composite video signal generation and acquisition system, belonging to the field of video signal processing technology. The system includes an FPGA chip and external supporting circuitry. The FPGA chip integrates a video signal input submodule, a video signal receiving submodule, and a video data comparison and verification submodule. The video signal input submodule supports LVDS and DVI format signal generation and input; the video signal receiving submodule supports LVDS, eDP, and mini-LVDS format signal reception and parsing; and the video data comparison and verification submodule compares the timing and pixel differences between input and feedback video data. The FPGA chip adopts a modular architecture to achieve multi-format compatibility, multi-channel parallel processing, and accurate verification. The external supporting circuitry includes signal driving, interface protection, and clock auxiliary circuitry. This invention features multi-format compatibility, stable multi-channel processing, accurate verification, flexible configuration, and strong anti-interference capabilities, integrating signal generation, reception, and comparison verification into one system, suitable for PCBA video processing function testing.

Claims

1. A composite video signal generation and acquisition system based on FPGA, characterized in that, The system includes an FPGA chip and peripheral circuitry. The FPGA chip integrates a multi-format video signal processing module, which comprises a video signal input submodule, a video signal receiving submodule, and a video data comparison and verification submodule. The video signal input submodule supports the generation and input of LVDS and DVI format video signals, the video signal receiving submodule supports the reception and parsing of LVDS, eDP and mini-LVDS format video signals, and the video data comparison and verification submodule is used to compare the differences between the input video data input by the video signal input submodule and the feedback video data received by the video signal receiving submodule. The FPGA chip achieves multi-format signal compatibility and adaptation, multi-channel parallel processing and accurate verification through a modular architecture. The peripheral circuits include signal driving circuits, interface protection circuits and clock auxiliary circuits.

2. The FPGA-based composite video signal generation and acquisition system according to claim 1, characterized in that, The video signal input submodule is configured with corresponding input submodules for LVDS and DVI format video signals, and each input submodule supports independent input of video data of the corresponding format.

3. The FPGA-based composite video signal generation and acquisition system according to claim 2, characterized in that, The architecture of each input submodule is the same, including the video source generation module, encoding and standard switching module, clock management module and multi-output control module integrated inside the FPGA; The video source generation module supports real-time generation of built-in test patterns such as color bars, grayscale levels, and checkerboard patterns. It configures redundant data such as the number of effective pixels per row, the number of effective rows per frame, and the number of extra rows through registers, and uses an 8-bit parallel data bus to transmit R, G, and B channel data. The encoding and standard switching module is used to realize JEIDA / VESA standard switching and differential signal encoding. The clock management module is used to generate and allocate clocks and control refresh rates. The multi-output control module is used to switch channel modes and independently control each LVDS channel.

4. The FPGA-based composite video signal generation and acquisition system according to claim 3, characterized in that, The clock management module uses the FPGA's internal PLL to generate a 20MHz~90MHz odd pixel clock, supports 1MHz adjustable step size, distributes clock signals through a global clock network, and achieves an adjustable refresh rate of 60Hz~120Hz by adjusting the period of the horizontal synchronization signal.

5. The FPGA-based composite video signal generation and acquisition system according to claim 1, characterized in that, The video signal receiving submodule is configured with corresponding receiving submodules for LVDS, eDP and mini-LVDS format video signals, and each input submodule supports independent input of video data of the corresponding format.

6. The FPGA-based composite video signal generation and acquisition system according to claim 5, characterized in that, The architecture of each receiving submodule is the same, including a clock recovery and synchronization module, a decoding and standard adaptation module, and a data buffer and format adaptation module integrated within the FPGA. The clock recovery and synchronization module extracts the clock through CDR logic and achieves synchronization locking; the decoding and standard adaptation module realizes differential signal decoding and standard switching; the data buffer and format adaptation module uses BRAM to build a frame buffer and achieves resolution adaptation.

7. The FPGA-based composite video signal generation and acquisition system according to claim 1, characterized in that, The video data comparison and verification submodule includes a data acquisition module, a timing comparison module, a pixel comparison module, and a result processing and output module integrated within the FPGA. The data acquisition module collects pixel data and timing parameters of the input video data and the feedback video data and achieves frame alignment; the timing comparison module compares the differences in clock cycle, refresh rate and synchronization signal delay; the pixel comparison module compares the RGB values ​​pixel by pixel in "row → column" order and records the difference coordinates; the result processing and output module integrates the difference information and uploads it to the host computer, while triggering an alarm mechanism.

8. The FPGA-based composite video signal generation and acquisition system according to claim 7, characterized in that, The pixel comparison module adopts a pipeline architecture to process multi-line pixel comparisons in parallel. The result processing and output module uploads difference reports through a UART interface or an Ethernet interface and supports storage to an external SD card. The alarm mechanism includes LED alarms.

9. The FPGA-based composite video signal generation and acquisition system according to claim 1, characterized in that, The FPGA chip receives configuration parameters from the host computer via the SPI interface and uploads status information via the IIC interface. The configuration parameters include channel mode, standard type, clock frequency, resolution, refresh rate, and channel enable status.

10. The FPGA-based composite video signal generation and acquisition system according to claim 1, characterized in that, The FPGA chip adopts a resource partitioning design, allocating video signal processing modules to independent logical resource areas, and achieving signal timing alignment through a global clock network and a synchronization register chain.