Md5 value calculation method and device of video postprocessor and video decoder

Abstract

The application discloses a video decoder, which comprises a video postprocessor, an internal external memory and an MD5 computing device of the video postprocessor, and the computing device is used for executing the following computing method: reading video decoding data stored in a non-linear data block TILE format from the external memory and loading the video decoding data into an internal cache of the video postprocessor through address mapping; converting the video decoding data stored in the non-linear data block TILE format into a linear format, and generating one or more 512-bit data units according to the size N of an internal basic data unit of the TILE format; sequentially executing MD5 computation on each 512-bit data unit to generate a final 128-bit MD5 value. The technical scheme of the application is realized based on the working mode of an existing video decoding result processing module in a hardware system, the basic MD5 algorithm is added in the existing processing logic, the hardware resource sharing is maximally realized, the complexity of the hardware design is simplified, the hardware MD5 verification time is shortened, and the performance of the hardware MD5 computation is ensured.

Description

Technical Field

[0001] This invention relates to the field of video image processing technology, and in particular to a method for calculating the MD5 value of a video post-processor, a computing device, and a video decoder. Background Technology

[0002] As the resolution of video decoded images increases, the verification time for video decoder designs also gradually increases. Improving the verification efficiency of video hardware decoders is a pressing issue that needs to be addressed during the design process. Increasing the verification efficiency of video hardware decoders can significantly shorten the verification cycle, thereby greatly reducing the overall hardware design cycle. It also allows for the early detection of potential design problems and the identification of possible solutions, which is crucial in the design of video hardware decoders.

[0003] The main function of a video post-processor (VPP) is to move decoded video image data and perform specific data format conversions, enabling the display hardware module to acquire the data for normal playback. The video post-processor can be embedded as a hardware sub-module within the video decoder chip, a design common in standalone video decoder IPs. Alternatively, the VPP can exist as a separate hardware module from the video hardware decoder, a design more common in integrated chip designs. For the video hardware decoder, the VPP hardware module is essential; in both designs, the VPP hardware module performs video decoding data movement and some basic data conversion functions.

[0004] Because the basic calculation algorithm of MD5 (Message Digest Algorithm) is simple and has been implemented in the latest generations of official video standard decoders, it is used to calculate the MD5 hash of the decoded video result, which can then be used as verification data for the correctness of the decoding result. Therefore, it is feasible to use the hardware module of the Video Post-Processor (VPP) to perform MD5 calculation.

[0005] Currently, using the MD5 value calculated from video decoded data for video decoder verification is a common method. Official software decoders used by newer video codec standards such as HEVC (High Efficiency Video Coding), VVC (Versatile Video Coding), AVS2 (Advanced Video Coding Standard 2), AVS3 (Advanced Video Coding Standard 3), and AV1 (AOMedia Video1, an open-source video coding format developed by AOM (Alliance for Open Media)) all support MD5 calculation. Furthermore, the corresponding video decoding standard in the FFMPEG (Fast Forward Moving Pictures Experts Group) open-source library also supports MD5 calculation. Similarly, some chip manufacturers also use MD5 to verify their self-developed video decoders; however, most MD5 calculations are implemented in the upper-layer applications of the chip manufacturer's video decoder verification system.

[0006] The computational performance of MD5 at the software level is limited by the CPU configuration. From the perspective of video decoding data verification, it can be seen that calculating MD5 at the software level will face the problem that the calculation time of MD5 value increases exponentially as the resolution of video decoding frames increases. If MD5 is calculated at the software level for the verification of video decoding frames, it will not save the verification time of high-resolution video decoding frames.

[0007] The general architecture for MD5 value calculation at the video decoder software level is shown in the figure below. After the video decoder completes the decoding of a frame, the upper-layer application calculates the MD5 value of the current frame's decoding result and compares it with the corresponding MD5 baseline data value. The algorithm used to calculate the MD5 baseline data value must be consistent with that used by the upper-layer application to calculate the video decoder's decoding result; only then can the MD5 values ​​calculated by the two parties be compared. Summary of the Invention

[0008] One of the objectives of this invention is to overcome the shortcomings of the prior art and, in view of the above-mentioned technical problems existing in the prior art, to provide a method, computing device and video decoder for calculating the MD5 value of a video post-processor.

[0009] To achieve the above objectives, the present invention is implemented through the following technical solution: In a first aspect, this application provides a method for calculating the MD5 value of a video post-processor, comprising the following steps: S100: Read video decoding data stored in non-linear data block TILE format from external memory and load it into the internal cache of the video post-processor through address mapping; S200: Convert the video decoding data stored in the non-linear data block TILE format into a linear format, and generate one or more 512-bit data units according to the size N of the basic data unit inside the TILE format. S300: Performs MD5 value calculation sequentially on each 512-bit data unit to generate the final 128-bit MD5 value.

[0010] In a preferred embodiment of the calculation method of this application, S100 specifically includes: S101: Locate the starting address of the external memory for the video decoding data stored in the non-linear data block TILE format in the external memory; S102: Locate the starting address of the video decoding data stored in the non-linear data block TILE format within the basic data unit of the TILE format; S103: Locate the address of the basic data unit within the TILE format of the currently accessed pixel.

[0011] In a preferred embodiment of the calculation method of this application, S200 specifically includes: S201: Read N-bit video luminance or chrominance data stored in TILE format from the internal cache of the video post-processor; S202: Determine the size and scanning method of the luminance data block or chrominance data block contained in the 512-bit data block based on the data block size N being read; S203: Process the luminance data block or chrominance data block corresponding to each 512-bit data unit in the data block in sequence, and convert the pixel data corresponding to the luminance data block or chrominance data block from TILE format to linear format; S204: Use the converted 512-bit data unit as input data for calculating the MD5 value of the video post-processor.

[0012] In a preferred embodiment of the calculation method of this application, in S202, when N is greater than 512 bits, the data block needs to be divided into multiple 512-bit data units according to the size of N, and the MD5 value of each 512-bit data unit is calculated sequentially according to the pre-designed scanning order of pixels in the data block N; when N is less than 512 bits, the data of multiple N-sized data blocks need to be concatenated into a 512-bit block, and then the MD5 value of the 512-bit data unit is calculated.

[0013] In a preferred embodiment of the calculation method of this application, the data block size N corresponds to a luminance data block of M×M pixels or a chrominance data block of (M / 2)×(M / 2) pixels.

[0014] In a preferred embodiment of the calculation method of this application, S300 specifically includes: S301: Initialize the 128-bit initial link variable to obtain a 128-bit initial data sequence; S302: Split the input 512-bit data unit into multiple 512-bit blocks of data and arrange them sequentially; S303: Starting from the first 512-bit block of data, perform an MD5 update operation on the first 512-bit block of data in combination with the initial sequence of 128-bit data to generate the corresponding first 128-bit intermediate MD5 value. Then, combine the first 128-bit intermediate MD5 value with the MD5 update operation on the second 512-bit block of data to generate the corresponding second 128-bit intermediate MD5 value. And so on. By combining the 128-bit intermediate MD5 value generated by the previous 512-bit block of data with the MD5 update operation on the MD5 value of the next 512-bit block of data, the MD5 update operation is performed sequentially on each 512-bit block of data. Finally, the last 128-bit intermediate MD5 value corresponding to the last 512-bit block of data is obtained. S304: Perform the final MD5 operation on the last 128-bit intermediate MD5 value to generate the final 128-bit MD5 value corresponding to the input data.

[0015] In a preferred embodiment of the calculation method of this application, in the video decoding data stored in the nonlinear data block TILE format, multiple TILE format data are linearly arranged in external memory, and the basic data units inside the TILE format are stored in Zig-Zag scanning order.

[0016] In a preferred embodiment of the calculation method of this application, the TILE format is NV12T or P010T format.

[0017] In a preferred embodiment of the calculation method of this application, the process of the video post-processor performing MD5 value calculation is executed in parallel with the decoding process of the video hardware decoder.

[0018] Secondly, this application provides an MD5 value calculation device for a video post-processor, characterized in that it includes: a data loading module, a format conversion module, and a calculation core module; The data loading module is used to read video decoding data stored in non-linear data block TILE format from external storage and load it into the internal cache of the video post-processor through address mapping; The format conversion module is used to convert the video decoding data stored in the non-linear data block TILE format into a linear format, and generate one or more 512-bit data units according to the size N of the basic data unit inside the TILE format. The computational core module is used to sequentially perform MD5 value calculation on each 512-bit data unit to generate the final 128-bit MD5 value.

[0019] In a preferred embodiment of the computing device of this application, the data loading module is configured to read the TILE format data from the external memory by calculating a three-level mapping of the external memory start address, the TILE internal basic data unit start address, and the pixel address.

[0020] In a preferred embodiment of the computing device of this application, the format conversion module is configured to: split the data block into multiple 512-bit data units when N is greater than 512 bits; and concatenate the multiple data blocks into a single 512-bit data unit when N is less than 512 bits.

[0021] In a preferred embodiment of the computing device of this application, the data loading module, the format conversion module, and the computing core module are integrated into the video post-processor (VPP) hardware.

[0022] In a preferred embodiment of the computing device of this application, the intermediate MD5 value calculated by the computing core module is stored in a register inside the video post-processor (VPP) for calculating the MD5 value of the next 512-bit data unit.

[0023] Thirdly, the present invention provides a video decoding verification system, comprising: A video hardware decoder is used to decode video streams and output decoded data stored in external memory in TILE format. The computing device as described in any one of claims 10 to 14 is configured to read the decoded data from the external storage and calculate its MD5 value; The upper-layer application compares the MD5 value obtained by the computing device with a pre-stored reference MD5 value to verify the correctness of the video hardware decoder's decoding result; The video hardware decoder works in parallel with the computing device.

[0024] Fourthly, the present invention provides a video post-processor, including external storage and a computing device as described in any one of claims 10 to 14.

[0025] Fifthly, the present invention provides a video decoder, including the video post-processor as described in claim 16.

[0026] In a sixth aspect, the present invention provides a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform the MD5 value calculation method of the video post-processor as described in the first aspect.

[0027] In a seventh aspect, the present invention provides a computer program product comprising a computer program that, when run on a computer, causes the computer to execute the MD5 value calculation method of the video post-processor as described in the first aspect.

[0028] The MD5 value calculation method, calculation device, and video decoder for video post-processors disclosed in this invention are based on the working mode of the existing video decoding result processing module in the hardware system. The basic MD5 algorithm is added to the existing processing logic, which maximizes hardware resource sharing, simplifies the complexity of hardware design, shortens the time of hardware MD5 verification, and ensures the performance of hardware MD5 value calculation. Attached Figure Description

[0029] The present invention is described with reference to the following figures: Figure 1a This is a schematic diagram of a video decoder according to an embodiment of the present invention; Figure 1b This is a schematic diagram of another structure of a video decoder according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the MD5 value calculation device of the video post-processor in a video decoder according to an embodiment of the present invention; Figure 3 This is a flowchart illustrating the steps of the MD5 value calculation device of the video post-processor executing the MD5 value calculation method in a video decoder according to an embodiment of the present invention. Figure 4 This is a schematic diagram illustrating the working principle of the data loading module of the MD5 value calculation device of the video post-processor in a video decoder according to an embodiment of the present invention. Figure 5 This is a schematic diagram illustrating the working principle of the format conversion module of the MD5 value calculation device of the video post-processor in a video decoder according to an embodiment of the present invention. Figure 6 This is an example diagram of how the format conversion module of the MD5 value calculation device of the video post-processor in a video decoder according to an embodiment of the present invention divides a 2048-bit basic data block into 512-bit data blocks. Figure 7 This is an example diagram of how the format conversion module of the MD5 value calculation device of the video post-processor in a video decoder according to an embodiment of the present invention assembles 128-bit basic data blocks into 512-bit data blocks. Figure 8 This is a schematic diagram illustrating the working principle of a video decoder performing MD5 value calculation according to an embodiment of the present invention; Figure 9 This is a schematic diagram illustrating the working principle of the calculation core module of the MD5 value calculation device of the video post-processor in a video decoder according to an embodiment of the present invention for calculating the MD5 value. Figure 10 This is a schematic diagram illustrating the working principle of the calculation core module of the MD5 value calculation device of the video post-processor in a video decoder according to an embodiment of the present invention, which calculates the MD5 value of a single 512-bit block data. Figure 11 This is a schematic diagram of the structure of a video decoding verification system according to another embodiment of the present invention.

[0030] Figure label: VIDEO - Video hardware decoder; VPP - Video post-processor; 100 - Computing device; 110 - Data loading module; 120 - Format conversion module; 130 - Computing core module; 200 - External storage. Detailed Implementation

[0031] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0032] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0033] This invention discloses a video decoder. Based on the existing working mode of processing video decoding data in the hardware module of the video post-processor (VPP), namely, reading data through mapping using a non-linear data block TILE format scanning method, and combined with the basic MD5 calculation algorithm, it realizes a method for quickly calculating the MD5 of video decoding data using the hardware module of the video post-processor (VPP), thereby accelerating the verification speed of the video decoding results of the video hardware decoder.

[0034] like Figure 1a and Figure 1b As shown, one embodiment of the present invention provides a video decoder, including a video hardware decoder (VIDEO) and a video post-processor (VPP) located at the hardware layer, and an upper-layer application located at the upper application layer. The video hardware decoder (VIDEO) and the video post-processor (VPP) can be independent hardware design architectures (such as...). Figure 1a As shown), it can also be used for integrated hardware design architectures (such as...). Figure 1b(As shown). Data transmission and communication occur between the video hardware decoder (VIDEO) and the video post-processor (VPP), while the video post-processor (VPP) transmits and communicates with the upper-layer application.

[0035] The video post-processor (VPP) includes external storage 200 and an MD5 value calculation device 100 for the video post-processor. The calculation device 100 is embedded in the video post-processor (VPP) as a sub-module and implemented at the hardware level. A video decoding verification system comprises a video hardware decoder (VIDEO), a video post-processor MD5 value calculation device (100), and an upper-layer application. The video hardware decoder (VIDEO) decodes the video stream and outputs decoded data in TILE format stored in external storage (200). The MD5 value calculation device (100) reads the decoded data from external storage (200) and calculates its MD5 value. The upper-layer application pre-calculates the baseline MD5 value of the decoded data from the video hardware decoder (VIDEO) and saves the calculated baseline MD5 value locally as a sub-file of the decoding test instance. Since the baseline MD5 value is fixed and the pre-stored baseline MD5 value is also fixed, during video decoding verification, the upper-layer application compares the MD5 value obtained by the calculation device (100) with the pre-stored baseline MD5 value to verify the correctness of the video hardware decoder (VIDEO) decoding result. The video hardware decoder (VIDEO) and the calculation device (100) work in parallel.

[0036] like Figure 2 As shown, in one embodiment of the present invention, the MD5 value calculation device 100 of the video post-processor includes: a data loading module 110, a format conversion module 120, and a calculation core module 130. Each module executes the MD5 value calculation method according to the following steps, such as... Figure 3 As shown: S100: Reads video decoding data stored in non-linear data block TILE format from external memory 200 and loads it into the internal cache of the video post-processor through address mapping; S200: Converts video decoded data stored in non-linear data block TILE format into linear format, and generates one or more 512-bit data units according to the size N of the basic data unit inside the TILE format. S300: Performs MD5 value calculation sequentially on each 512-bit data unit to generate the final 128-bit MD5 value.

[0037] Among them, the data loading module 110 is used to execute step S100, the format conversion module 120 is used to execute step S200, and the calculation kernel module 130 is used to execute step S300.

[0038] Specifically, the overall architecture of the MD5 value calculation device 100 of the video post-processor includes a format conversion module 120 for hardware video data after the data loading module 110 of the video hardware post-processor (VPP). This module converts non-linear data block TILE format video decoding data to linear format data and divides the input data basic units of the VPP MD5 value calculation core module 130 of the video post-processor. The calculation of the VPP MD5 value of the video post-processor is then completed in the MD5 hardware calculation core module 130.

[0039] The data loading module 110 is used to read video decoding data stored in non-linear data block TILE format from external storage 200 and load it into the internal cache of the video post-processor VPP through address mapping; the format conversion module 120 is used to convert the video decoding data stored in non-linear data block TILE format into a linear format and generate one or more 512-bit data units according to the size N of the basic data unit inside the TILE format; the calculation core module 130 is used to sequentially perform MD5 value calculation on each 512-bit data unit to generate the final 128-bit MD5 value.

[0040] like Figure 4 As shown, in the MD5 value calculation device 100 of the video post-processor, the data loading module 110 is configured to read TILE format data from the external memory 200 by calculating a three-level mapping of the starting address of the external memory 200, the starting address of the TILE internal basic data unit, and the pixel address. It mainly completes the function of reading video decoding data from the external memory 200 into the internal buffer (Line-Buffer) of the video post-processor VPP. The most important function is the mapping of the external memory 200 address. The address mapping calculation is bound to the storage method of the video decoding data in the external memory 200.

[0041] Video decoding data is generally stored in a non-linear format in external storage 200, which can be called TILE format data storage. The TILE format data storage method in external storage 200 is related to block-based video decoding. By setting the TILE format, the size of the basic data units within the TILE format, and the data scanning order, the read / write efficiency of external storage 200 can be maximized, saving bandwidth.

[0042] In a preferred embodiment of the present invention, in the video decoding data stored in the non-linear data block TILE format, multiple TILE format data are linearly arranged in the external storage 200, and the basic data units inside the TILE format are stored in Zig-Zag scanning order.

[0043] In a preferred embodiment of the present invention, the TILE format can be NV12T or P010T format.

[0044] In the video post-processor (VPP), the external memory address 200 of the data loading module 110 is fully bound to the data size of the TILE format, the size of the basic data unit within the TILE format, and the data scanning method. When performing step S100 to map the external memory address 200, the data loading module 110 executes the following steps: S101: Locates the starting address of external memory 200 for video decoding data stored in non-linear data block TILE format in external memory 200; S102: Locate the starting address of the video decoding data stored in the TILE format (a non-linear data block format) within the basic data unit of the TILE format. S103: Locate the address of the basic data unit within the TILE format of the currently accessed pixel.

[0045] The above steps S101, S102, and S103 are actually the process of the data loading module 110 implementing three-level mapping. Step S101 completes the mapping of the address of external memory 200, step S102 completes the mapping of TILE format and basic data units within TILE format, and step S103 completes the mapping of the currently accessed pixel within the basic data units of TILE format. The mapping of each step needs to be calculated according to the storage method of the data mapped in that step in external memory 200.

[0046] Currently, the video decoding data of mainstream video decoders is mainly stored in external memory in NV12T (8BPE TILE format data) and P010T (16BPE TILE format data) formats, which is a non-linear (T, TILE) storage method, where BPE (Bit Per Element) is the element data bit.

[0047] The distribution of commonly used non-linear data blocks (TILE) follows these patterns: 1) Different TILE format data are stored linearly in external storage 200; 2) The basic data units within the TILE format are stored in a ZIG-ZAG manner; 3) Individual pixels are stored in the basic data unit within the TILE format in a ZIG-ZAG or linear manner; It should be noted that the distribution pattern of non-linear data blocks in TILE format is not limited to the three patterns mentioned above. In practical applications, adjustments need to be made based on different types of video decoder hardware and external storage access control hardware.

[0048] like Figure 5 As shown, in the MD5 value calculation device 100 of the video post-processor, the format conversion module 120 mainly performs the conversion of non-linear data block TILE format data to linear data, thereby obtaining the input data required by the VPP MD5 value calculation core module 130 of the video post-processor. When the format conversion module 120 executes step S200, it specifically follows these steps: S201: Read N-bit video luminance or chrominance data stored in TILE format from the internal cache of the video post-processor; S202: Determine the size and scanning method of the luminance data block or chrominance data block contained in the 512-bit data block based on the data block size N being read; S203: Process the luminance data block or chrominance data block corresponding to each 512-bit data unit in the data block in sequence, and convert the pixel data corresponding to the luminance data block or chrominance data block from TILE format to linear format; S204: Use the converted 512-bit data unit as input data for calculating the MD5 value of the video post-processor.

[0049] The data block size N corresponds to either an M×M pixel luminance data block or an (M / 2)×(M / 2) pixel chrominance data block. The format conversion module 120 reads the luminance data block Y, chrominance data block Cb, and chrominance data block Cr from the internal cache of the video post-processor VPP via step S201, and processes them sequentially. Step S202 determines the size and scanning method of the luminance data block Y, chrominance data block Cb, and chrominance data block Cr respectively. Step S203 then sequentially converts the pixel data corresponding to the luminance data block Y, chrominance data block Cb, and chrominance data block Cr from TILE format to the current format. Step S204 generates a converted 512-bit data unit, which serves as input data for the calculation core module 130 for MD5 value calculation.

[0050] The format conversion module 120 is configured to split the data block into multiple 512-bit data units when N is greater than 512 bits, and to concatenate the multiple data blocks into a single 512-bit data unit when N is less than 512 bits.

[0051] Specifically, when executing step S202, the format conversion module 120 determines whether to split or concatenate the 512-bit data block based on the size N of the read data block: 1) When N is greater than 512 bits, the format conversion module 120 needs to split the data block into multiple 512-bit data units according to the size of N, and calculate the MD5 value of each 512-bit data unit in turn according to the scanning order of the pixels in the designed data block N. 2) When N is less than 512 bits, the format conversion module 120 needs to concatenate the data of multiple N-sized data blocks into a 512-bit data unit, and then calculate the MD5 value of the 512-bit data unit.

[0052] Two examples are given for each of the two possible values ​​of N, as follows: 1. When the data block size N is greater than 512 bits, if the basic data unit inside the TILE format is a 2048-bit data block, then N is 2048. For 8BPE format data, the size of the luminance data block Y may be 16×16, and the sizes of the chrominance data blocks Cb and Cr may be 8×8 Cb and 8×8 Cr. A 2048-bit data block contains two such chrominance data blocks Cb and Cr.

[0053] The data processing method for the basic data block N read is as follows: Figure 6 As shown, for a 16×16 luminance data block Y, it is divided into four vertically arranged 16×4 luminance sub-data blocks {16×4_0, 16×4_1, 16×4_2, 16×4_3} according to the size of each horizontal row of 16×4. The scanning method is to scan each 16×4 luminance sub-data block in order from left to right, starting from the 16×4_0 luminance sub-data block and scanning vertically downwards to the 16×4_3 luminance sub-data block.

[0054] For an 8×8 chroma data block Cb, it is divided into two horizontally arranged 8×4 chroma sub-data blocks Cb{8×4_0_Cb, 8×4_1_Cb} according to the size of each column of 8×4. The scanning method is to scan each 8×4 chroma sub-data block Cb in a left-to-right order, from the 8×4_0Cb chroma sub-data block to the 8×4_1 chroma sub-data block Cb.

[0055] For an 8×8 chromaticity data block Cr, it is divided into two horizontally arranged 8×4 chromaticity sub-data blocks Cr{8×4_0_Cr, 8×4_1_Cr} according to the size of each column of 8×4. The scanning method is to scan each 8×4 chromaticity sub-data block Cr in a left-to-right order, from the 8×4_0Cr chromaticity sub-data block to the 8×4_1 chromaticity sub-data block Cr.

[0056] 2. When the data block size N is less than 512 bits, if the basic data unit of TILE format is 128 bits, then the value of N is 128. For 8BPE format data, the size of the luma data block may be 4×4, and the size of the chroma data block may be 2×2 Cb and 2×2 Cr. A 128-bit data block contains two such chroma data blocks.

[0057] The data processing method for reading multiple basic data blocks N is as follows: Figure 7 As shown, four 4×4 luminance data blocks Y{4×4_0, 4×4_1, 4×4_2, 4×4_3} are sequentially stitched together from left to right to form a large 16×4 luminance data block. The scanning method is to scan each 4×4 luminance data block Y in a left-to-right order, starting from the 4×4_0 luminance data block and scanning horizontally to the right to the 4×4_3 luminance data block.

[0058] Sixteen 2×2 chroma data blocks Cb{2×2_0_Cb, 2×2_1_Cb, 2×2_2_Cb, 2×2_3_Cb, 2×2_4_Cb, 2×2_5_Cb, 2×2_6_Cb, 2×2_7_Cb, 2×2_8_Cb, 2×2_9_Cb, 2×2_10_Cb, 2×2_11_Cb, 2×2_12_Cb, 2×2_13_Cb, 2×2_14_Cb, ... The 2×2_15_Cb blocks are sequentially concatenated from left to right to form a 16×4 large chroma data block Cb. The scanning method is to scan each 2×2 chroma data block Cb in a left-to-right order, starting from the 2×2_0_Cb chroma data block Cb and scanning horizontally to the right to the 2×2_7_Cb chroma data block Cb, then moving to the next line and scanning horizontally to the right from the 2×2_8_Cb chroma data block Cb to the 2×2_15_Cb chroma data block Cb.

[0059] Convert 16 2×2 chroma data blocks Cr{2×2_0_Cr, 2×2_1_Cr, 2×2_2_Cr, 2×2_3_Cr, 2×2_4_Cr, 2×2_5_Cr, 2×2_6_Cr, 2×2_7_Cr, 2×2_8_Cr, 2×2_9_Cr, 2×2_10_Cr, 2×2_11_Cr, 2×2_12_Cr, 2×2_13_Cr, 2×2_14_Cr, The 2×2_15_Cr blocks are sequentially concatenated from left to right to form a 16×4 large chromaticity data block Cr. The scanning method is to scan each 2×2 chromaticity data block Cr in a left-to-right order, starting from the 2×2_0_Cr chromaticity data block Cr and scanning horizontally to the right to the 2×2_7_Cr chromaticity data block Cr, then moving to the next line and scanning horizontally to the right from the 2×2_8_Cr chromaticity data block Cr to the 2×2_15_Cr chromaticity data block Cr.

[0060] The above two examples are only for illustrating the technical solution of the present invention and do not represent a limitation on the scope of protection of the present invention. In fact, the processing method of the format conversion module 120 for the read basic data block N is not limited to the above two examples.

[0061] In the MD5 value calculation device 100 of the video post-processor, the calculation kernel module 130 calculates the MD5 value using the basic MD5 algorithm, such as... Figure 8 As shown, the computational architecture of a video decoder according to an embodiment of the present invention includes the following three processes: 1) The video decoding data is stored in external memory 200 in a YUV linear manner. Assuming the format of the video decoding data is 420, the video decoding data is stored in external memory 200 as follows: first, the luminance data (Y) of the video frame width Wx and the video frame height H is stored; then, the chrominance data (Cb) of the video frame width W / 2x and the video frame height H / 2 is stored; finally, the chrominance data (Cr) of the video frame width W / 2x and the video frame height H / 2 is stored. 2) Divide the luminance data (Y), chrominance data (Cb), and chrominance data (Cr) of the video decoding data into multiple 512-bit data units respectively; 3) Calculate the MD5 value sequentially for each 512-bit data unit to obtain the MD5 value of the luminance data (Y), chrominance data (Cb), and chrominance data (Cr) of the video decoded data.

[0062] When the computing core module 130 executes step S300, it specifically follows these steps: S301: Initialize the 128-bit initial link variable to obtain a 128-bit initial data sequence; S302: Split the input 512-bit data unit into multiple 512-bit blocks of data and arrange them sequentially; S303: Starting from the first 512-bit block of data, perform an MD5 update operation on the first 512-bit block of data in combination with the initial sequence of 128-bit data to generate the corresponding first 128-bit intermediate MD5 value. Then, combine the first 128-bit intermediate MD5 value with the MD5 update operation on the second 512-bit block of data to generate the corresponding second 128-bit intermediate MD5 value. And so on. By combining the 128-bit intermediate MD5 value generated by the previous 512-bit block of data with the MD5 update operation on the MD5 value of the next 512-bit block of data, the MD5 update operation is performed sequentially on each 512-bit block of data. Finally, the last 128-bit intermediate MD5 value corresponding to the last 512-bit block of data is obtained. S304: Perform the final MD5 operation on the last 128-bit intermediate MD5 value to generate the final 128-bit MD5 value corresponding to the input data.

[0063] like Figure 9 and Figure 10 As shown, the computation core module 130 receives 512-bit data units of input data transmitted by the format conversion module 120. The computation core module 130 first executes step S301 to initialize its pre-stored 128-bit initial link variable, obtaining a 128-bit initial data sequence. Then, it executes step S302 to split the input data into M groups of 512-bit data. If, after splitting the input data into (M-1) groups, the remaining m bits are less than 512 bits, the remaining (512-m) bits are padded with 0s, and each group of 512-bit data is arranged sequentially. Next, it executes step S303 to sequentially perform MD5 value update operations on each group of 512-bit data, finally obtaining the last 128-bit intermediate MD5 value (MD5 Final) corresponding to the last group of 512-bit data. Finally, step S304 is executed to perform the final calculation on the last 128-bit intermediate MD5 value to obtain the final 128-bit MD5 value corresponding to the input data.

[0064] In the MD5 value calculation device 100 of the video post-processor according to an embodiment of the present invention, the MD5 algorithm used by the calculation core module 130 is based on the working mode of the existing video decoding result processing module in the hardware system—the video post-processor VPP (which can be an internal module embedded in the video hardware decoder VIDEO, or a separate hardware processor). Its main function is to calculate the MD5 value of the current input data's 512-bit data unit and store the final 128-bit MD5 value obtained from the current calculation in a register inside the video post-processor VPP for use in the calculation of the MD5 value of the next 512-bit data unit. In other words, the input data of the next 512-bit data unit includes its own 512-bit linear data and the final 128-bit MD5 value obtained from the MD5 value calculation of the previous 512-bit data unit stored in the register.

[0065] The MD5 value calculation device 100 and calculation method of the video post-processor of this invention incorporates the basic MD5 algorithm into the existing processing logic, maximizes hardware resource sharing, simplifies the complexity of hardware design, shortens the time of hardware MD5 verification, and ensures the performance of hardware MD5 calculation.

[0066] In a preferred embodiment of the present invention, the process of calculating the MD5 value by the video post-processor (VPP) is executed in parallel with the decoding process of the video hardware decoder (VIDEO).

[0067] In a preferred embodiment of the present invention, in the MD5 value calculation device 100 of the video post-processor, the data loading module 110, the format conversion module 120, and the calculation core module 130 are all integrated into the video post-processor VPP hardware.

[0068] In a preferred embodiment of the present invention, in the MD5 value calculation device 100 of the video post-processor, the intermediate MD5 value calculated by the calculation core module 130 is stored in the register inside the video post-processor VPP for MD5 value calculation of the next 512-bit data unit.

[0069] The MD5 value calculation method for a video post-processor disclosed in one embodiment of the present invention, and the performance achievable by implementing the hardware calculation of the MD5 value of the video post-processor (VPP) in a hardware system are shown in Tables 1 and 2 below. It should be noted that the video hardware decoder (VIDEO) and the video hardware post-processor (VPP) operate in parallel in the hardware system; therefore, implementing the MD5 value calculation of the video post-processor (VPP) in the video hardware decoder (VIDEO) does not affect the decoding performance of the video hardware decoder (VIDEO).

[0070]

[0071] Table 1: Frame Rate Calculation Based on Video Post-Processor (VPP) MD5 Values ​​Achieved with 8BPE Format Data

[0072] Table 2: Frame Rate Calculation Based on Video Post-Processor (VPP) MD5 Values ​​of 16BPE P010T Format Data Another embodiment of the present invention discloses a video decoding verification system, including: a video hardware decoder VIDEO, an MD5 value calculation device 100 for a video post-processor, and an upper-layer application.

[0073] like Figure 11 As shown, the video hardware decoder VIDEO is used to decode the video bitstream and outputs decoded data stored in external memory 200 in TILE format; the MD5 value calculation device 100 of the video post-processor is used to read the decoded data from external memory 200 and calculate its MD5 value; the upper-layer application is used to compare the MD5 value obtained by the calculation device 100 with the pre-stored reference MD5 value to verify the correctness of the decoding result of the video hardware decoder VIDEO; wherein, the video hardware decoder VIDEO and the calculation device 100 work in parallel.

[0074] The comparison results of video verification time using software to calculate the MD5 value and hardware to calculate the VPPMD5 value in the VIDEO hardware decoder system are shown in Tables 3 and 4 below. The test time comparison data shows that using hardware to calculate the VPPMD5 value for video decoding verification can save approximately ten to several hundred times the test time. Moreover, the higher the resolution of the test bitstream for video decoding, the greater the time saving. It should be noted that in Tables 3 and 4, the time for calculating and comparing the VPPMD5 value using hardware is set to 1 second. This is because this part of the test data is less than 1 second; to allow for comparison between software and hardware-based MD5 value calculation, this time was set to 1 second.

[0075]

[0076] Table 3: Comparison of Test Times for 8BPE NV12T Format Data

[0077] Table 4: Comparison of Test Times for 16BPE P010T Format Data The test data tested in the video decoding verification system above is based on a test platform configuration with a CPU (Central Processing Unit) with 4GB of memory and a 1GHz operating frequency, and a GPU (Graphics Processing Unit) with 4GB of video memory, a 452MHz video output frequency, and a 452MHz video post-processor (VPP) operating frequency.

[0078] Another embodiment of the present invention discloses a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to execute an MD5 value calculation method for a video post-processor.

[0079] Another embodiment of the present invention discloses a computer program product comprising a computer program that, when run on a computer, causes the computer to execute an MD5 value calculation method for a video post-processor.

[0080] The MD5 value calculation method, calculation device, and video decoder for video post-processors disclosed in this invention are implemented based on the working mode of existing video decoding result processing modules in the hardware system. A basic MD5 algorithm is added to the existing processing logic, maximizing hardware resource sharing, simplifying hardware design complexity, shortening hardware MD5 verification time, and ensuring hardware MD5 calculation performance. The advantages of this invention's technical solution for hardware design, utilizing the existing processing logic of the video post-processing hardware module, are as follows: 1. Achieve hardware resource sharing: By utilizing the existing working mode of the video post-processor (VPP) module in the hardware system, data loading and format conversion of MD5 input data are performed, realizing hardware resource sharing and reducing the area of ​​hardware design. 2. It simplifies the complexity of hardware design: In the hardware system, only the basic algorithm of MD5 value needs to be implemented. During the MD5 value calculation process, there is no need to consider input data processing and data format conversion, which greatly reduces the complexity of hardware design. 3. Reduced the time required for MD5 value verification of video decoding data in the hardware system: By utilizing the processing logic of the existing video post-processor (VPP) module in the hardware system, it is only necessary to verify the correctness of the basic MD5 algorithm to ensure the accuracy of video decoding data processing. 4. Ensure the performance of MD5 value calculation in the hardware system: The basic algorithm for MD5 values ​​is essentially a simple AND or OR operation on the data. The performance bottleneck for MD5 value calculation in hardware systems is the data loading and format conversion steps. The video decoder disclosed in this invention can utilize the existing processing logic of the video post-processor (VPP) module to ensure the performance of MD5 value calculation for video decoding data in hardware systems.

[0081] It should be understood that the above description of specific embodiments of the present invention is only for illustrating the technical approach and features of the present invention, and is intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. However, the present invention is not limited to the specific embodiments described above. All changes or modifications made within the scope of the claims of the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for calculating the MD5 value of a video post-processor, characterized in that, Includes the following steps: S100: Read video decoding data stored in non-linear data block TILE format from external memory and load it into the internal cache of the video post-processor through address mapping; S200: Convert the video decoding data stored in the non-linear data block TILE format into a linear format, and generate one or more 512-bit data units according to the size N of the basic data unit inside the TILE format. S300: Performs MD5 value calculation sequentially on each 512-bit data unit to generate the final 128-bit MD5 value.

2. The method for calculating the MD5 value of a video post-processor according to claim 1, characterized in that, S100 specifically includes: S101: Locate the starting address of the external memory for the video decoding data stored in the non-linear data block TILE format in the external memory; S102: Locate the starting address of the video decoding data stored in the non-linear data block TILE format within the basic data unit of the TILE format; S103: Locate the address of the basic data unit within the TILE format of the currently accessed pixel.

3. The method for calculating the MD5 value of a video post-processor according to claim 1, characterized in that, S200 specifically includes: S201: Read N-bit video luminance or chrominance data stored in TILE format from the internal cache of the video post-processor; S202: Determine the size and scanning method of the luminance data block or chrominance data block contained in the 512-bit data block based on the data block size N being read; S203: Process the luminance data block or chrominance data block corresponding to each 512-bit data unit in the data block in sequence, and convert the pixel data corresponding to the luminance data block or chrominance data block from TILE format to linear format; S204: Use the converted 512-bit data unit as input data for calculating the MD5 value of the video post-processor.

4. The method for calculating the MD5 value of a video post-processor according to claim 3, characterized in that, In S202, when N is greater than 512 bits, the data block needs to be split into multiple 512-bit data units according to the size of N. The MD5 value of each 512-bit data unit is calculated sequentially according to the pre-designed scanning order of pixels in the data block N. When N is less than 512 bits, the data of multiple N-sized data blocks need to be concatenated into a 512-bit block, and then the MD5 value of the 512-bit data unit is calculated.

5. The method for calculating the MD5 value of a video post-processor according to claim 3 or 4, characterized in that, The data block size N corresponds to a luminance data block of M×M pixels or a chrominance data block of (M / 2)×(M / 2) pixels.

6. The method for calculating the MD5 value of a video post-processor according to claim 1, characterized in that, The S300 specifically includes: S301: Initialize the 128-bit initial link variable to obtain a 128-bit initial data sequence; S302: Split the input 512-bit data unit into multiple 512-bit blocks of data and arrange them sequentially; S303: Starting from the first 512-bit block of data, perform an MD5 update operation on the first 512-bit block of data in combination with the initial sequence of 128-bit data to generate the corresponding first 128-bit intermediate MD5 value. Then, combine the first 128-bit intermediate MD5 value with the MD5 update operation on the second 512-bit block of data to generate the corresponding second 128-bit intermediate MD5 value. And so on. By combining the 128-bit intermediate MD5 value generated by the previous 512-bit block of data with the MD5 update operation on the MD5 value of the next 512-bit block of data, the MD5 update operation is performed sequentially on each 512-bit block of data. Finally, the last 128-bit intermediate MD5 value corresponding to the last 512-bit block of data is obtained. S304: Perform the final MD5 operation on the last 128-bit intermediate MD5 value to generate the final 128-bit MD5 value corresponding to the input data.

7. The method for calculating the MD5 value of a video post-processor according to claim 1, characterized in that, In the video decoding data stored in the non-linear data block TILE format, multiple TILE format data are linearly arranged in external storage, and the basic data units within the TILE format are stored in Zig-Zag scanning order.

8. The method for calculating the MD5 value of a video post-processor according to claim 1, characterized in that, The TILE format is NV12T or P010T.

9. The method for calculating the MD5 value of a video post-processor according to claim 1, characterized in that, The process of calculating the MD5 value by the video post-processor is executed in parallel with the decoding process of the video hardware decoder.

10. An MD5 value calculation device for a video post-processor, characterized in that, include: Data loading module, format conversion module, and calculation kernel module; The data loading module is used to read video decoding data stored in non-linear data block TILE format from external storage and load it into the internal cache of the video post-processor through address mapping; The format conversion module is used to convert the video decoding data stored in the non-linear data block TILE format into a linear format, and generate one or more 512-bit data units according to the size N of the basic data unit inside the TILE format. The computational core module is used to sequentially perform MD5 value calculation on each 512-bit data unit to generate the final 128-bit MD5 value.

11. The computing device according to claim 10, characterized in that, The data loading module is configured to read the TILE format data from the external storage by calculating a three-level mapping of the external storage start address, the TILE internal basic data unit start address, and the pixel address.

12. The computing device according to claim 10, characterized in that, The format conversion module is configured to: split the data block into multiple 512-bit data units when N is greater than 512 bits; and concatenate multiple data blocks into a single 512-bit data unit when N is less than 512 bits.

13. The computing device according to claim 10, characterized in that, The data loading module, format conversion module, and computing core module are integrated into the video post-processor (VPP) hardware.

14. The computing device according to claim 10, characterized in that, The intermediate MD5 value calculated by the computing core module is stored in a register inside the video post-processor (VPP) and used for calculating the MD5 value of the next 512-bit data unit.

15. A video decoding verification system, characterized in that, include: A video hardware decoder is used to decode video streams and output decoded data stored in external memory in TILE format. The computing device as described in any one of claims 10 to 14 is configured to read the decoded data from the external storage and calculate its MD5 value; The upper-layer application compares the MD5 value obtained by the computing device with a pre-stored reference MD5 value to verify the correctness of the video hardware decoder's decoding result; The video hardware decoder works in parallel with the computing device.

16. A video post-processor, characterized in that, Includes external storage and a computing device as described in any one of claims 10 to 14.

17. A video decoder, characterized in that, Includes the video post-processor as described in claim 16.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when run on a computer, causes the computer to perform the MD5 value calculation method of the video post-processor as described in any one of claims 1 to 9.

19. A computer program product, characterized in that, The computer program product includes a computer program that, when run on a computer, causes the computer to perform the MD5 value calculation method of the video post-processor as described in any one of claims 1 to 9.

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