Semiconductor structure, method of manufacturing the same, and semiconductor device

Abstract

Some embodiments of the present application provide a semiconductor structure, a method of manufacturing the semiconductor structure, and a semiconductor device. The semiconductor structure includes a semiconductor substrate, a second transistor structure, and a first transistor structure. The first transistor structure is disposed on a side of the second transistor structure distal to the semiconductor substrate and is coupled to the second transistor structure by a first contact structure. A first word line structure is coupled to the first transistor structure. A first bit line structure is coupled to a first semiconductor layer within the first transistor structure. A second word line structure is coupled to one electrode region of a second semiconductor layer of the second transistor structure. A second bit line structure is coupled to another electrode region of the second semiconductor layer. The first contact structure is coupled to the first semiconductor layer and a second conductive layer of the second transistor structure, respectively; the first semiconductor layer covers a side surface of the first contact structure distal to the second transistor structure, and the second conductive layer covers a side surface of the first contact structure distal to the first transistor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, its fabrication method, and a semiconductor device. Background Technology

[0002] With the development of integrated circuit technology, the size of semiconductor devices is shrinking, and the integration density requirements of electronic components such as transistors are increasing, posing a significant challenge to the data read and write performance of semiconductor devices. Especially in the application of Dynamic Random Access Memory (DRAM), the structure and relative arrangement of different electronic components within DRAM are one of the important factors affecting the performance of semiconductor devices. Summary of the Invention

[0003] In view of this, the present disclosure provides a semiconductor structure and its fabrication method, as well as a semiconductor device, which can reduce the size of the semiconductor structure and improve its stability and reliability.

[0004] On one hand, some embodiments of this application provide a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a second transistor structure, a first transistor structure, a first word line structure, a first bit line structure, a second word line structure, and a second bit line structure. The second transistor structure is disposed on one side of the semiconductor substrate. The first transistor structure is disposed on the side of the second transistor structure away from the semiconductor substrate and is coupled to the second transistor structure via a first contact structure. The first word line structure is disposed within the layer structure of the second transistor structure and is coupled to a first conductive layer within the first transistor structure. The first bit line structure is disposed on the side of the first transistor structure away from the second transistor structure and is coupled to a first semiconductor layer within the first transistor structure. The second word line structure is disposed within the layer structure of the second transistor structure and is coupled to one electrode region of the second semiconductor layer of the second transistor structure. The second bit line structure is disposed within the layer structure of the second transistor structure and is coupled to another electrode region of the second semiconductor layer. The first contact structure is coupled to the first semiconductor layer and the second conductive layer of the second transistor structure at opposite ends along the stacking direction of the first transistor structure; the first semiconductor layer covers the surface of the first contact structure away from the second transistor structure, and the second conductive layer covers the surface of the first contact structure away from the first transistor structure.

[0005] In some examples, the first semiconductor layer is made of an oxide semiconductor material; the cross-sectional area of ​​the first contact structure along the stacking direction of the first transistor structure and the second transistor structure decreases along the direction from the first transistor structure to the second transistor structure.

[0006] In some examples, the material used for the second semiconductor layer includes an oxide semiconductor material; the cross-sectional area of ​​the first contact structure along the stacking direction of the first transistor structure and the second transistor structure decreases along the direction from the second transistor structure to the first transistor structure.

[0007] In some examples, the material of the first semiconductor layer includes indium gallium zinc oxide; and / or, the material of the second semiconductor layer includes indium gallium zinc oxide.

[0008] In some examples, the first transistor structure further includes a first transition structure, one end of which is coupled to the first semiconductor layer and the other end of which is coupled to the first bit line structure. The first transition structure and the first contact structure are respectively coupled to opposite sides of the first semiconductor layer along a direction perpendicular to the stacking direction of the first transistor structure and the second transistor structure.

[0009] In some examples, the first transistor structure further includes a first conductive layer. The first conductive layer is disposed on the side of the first semiconductor layer away from the second transistor structure, and is spaced apart from the first transition structure along a stacking direction perpendicular to the first transistor structure and the second transistor structure.

[0010] In some examples, the first transistor structure further includes: a first dielectric layer, a first conductive layer, and a second dielectric layer. The first dielectric layer is disposed on the side of the first semiconductor layer away from the second transistor structure. The first conductive layer is disposed on the side of the first dielectric layer away from the first semiconductor layer. The second dielectric layer is disposed on the side of the first conductive layer away from the first dielectric layer. The first semiconductor layer includes a first electrode region and a second electrode region spaced apart. The first electrode region is coupled to the second transistor structure via the first contact structure, and the second electrode region is coupled to the first bit line structure via the first transition structure.

[0011] In some examples, the second semiconductor layer is disposed on the side of the second conductive layer away from the first transistor structure.

[0012] In some examples, the second transistor structure includes: a second semiconductor layer, a third dielectric layer, a second conductive layer, and a fourth dielectric layer. The second semiconductor layer includes a third electrode region and a fourth electrode region spaced apart. The third dielectric layer is disposed on one side of the second semiconductor layer. The second conductive layer is disposed on the side of the third dielectric layer away from the second semiconductor layer; the second conductive layer is coupled to the first transistor structure via a second contact structure. The fourth dielectric layer is disposed on the side of the second conductive layer away from the third dielectric layer. The third electrode region is coupled to the second word line structure; the fourth electrode region is coupled to the second bit line structure.

[0013] In some examples, the first transistor structure includes a second dielectric layer and a first pillar-shaped conductive structure disposed in the second dielectric layer. The first pillar-shaped conductive structure extends along the stacking direction of the first transistor structure and the second transistor structure, with one end coupled to the second transistor structure and the other end coupled to the first word line structure.

[0014] The first columnar conductive structure includes: a columnar first semiconductor layer, a first dielectric layer, and a first conductive layer. The columnar first semiconductor layer includes a first electrode region and a second electrode region spaced apart at both ends of the columnar first semiconductor layer; the second electrode region is coupled to a second transistor structure via a first contact structure; the first electrode region is coupled to a first bit line structure. The first dielectric layer is disposed on one side of the columnar first semiconductor layer. The first conductive layer is disposed on the side of the first dielectric layer away from the columnar first semiconductor layer; the first conductive layer is coupled to the first word line structure.

[0015] In some examples, the first transistor structure includes a second dielectric layer and a first pillar-shaped conductive structure. The first pillar-shaped conductive structure is disposed in the second dielectric layer; the first pillar-shaped conductive structure extends along the stacking direction of the first transistor structure and the second transistor structure, with one end coupled to the second transistor structure and the other end coupled to the first word line structure.

[0016] The first columnar conductive structure includes: a columnar first conductive layer, a first dielectric layer, and a first semiconductor layer. The columnar first conductive layer is coupled to the first word line structure. The first dielectric layer surrounds the columnar first conductive layer. The first semiconductor layer surrounds the first dielectric layer; the first semiconductor layer includes a first electrode region and a second electrode region spaced apart along the stacking direction of the first transistor structure and the second transistor structure; the second electrode region is coupled to the second transistor structure through a first contact structure; the first electrode region is coupled to the first bit line structure.

[0017] In some examples, the second transistor structure includes a fourth dielectric layer and a second pillar-shaped conductive structure disposed in the fourth dielectric layer. The second pillar-shaped conductive structure extends along the stacking direction of the second transistor structure and the first transistor structure, with one end coupled to the first transistor structure and the other end coupled to the second word line structure or the second bit line structure.

[0018] The second columnar conductive structure includes: a columnar second conductive layer, a third dielectric layer, and a second semiconductor layer. One end of the columnar second conductive layer is coupled to the first semiconductor layer of the first transistor structure via a first contact structure. The third dielectric layer surrounds the columnar second conductive layer. The second semiconductor layer surrounds the third dielectric layer; the second semiconductor layer includes a third electrode region and a fourth electrode region spaced apart along the stacking direction of the second transistor structure and the first transistor structure; the third electrode region is coupled to the second word line structure; the fourth electrode region is coupled to the second bit line structure.

[0019] In some examples, the layer structure of the first transistor structure is the same as that of the second transistor structure.

[0020] In some examples, the first transistor structure includes a planar transistor structure or a vertical transistor structure; and / or, the second transistor structure includes a planar transistor structure or a vertical transistor structure.

[0021] In the aforementioned semiconductor structure, the second transistor structure and the first transistor structure are stacked on the semiconductor substrate, which helps to reduce the size of the semiconductor structure and increase its integration density. Furthermore, the functional layers (e.g., semiconductor layers) in the second and first transistor structures are not fabricated along the same layer parallel to the semiconductor substrate, but rather layer by layer perpendicular to the semiconductor substrate. This reduces the impact of the fabrication process conditions of one transistor structure on the performance stability of the material layers of the subsequently fabricated transistor structure. Additionally, a first contact structure is provided between the first and second transistor structures, further increasing the distance between them (which, from a process step perspective, increases the time interval between their processes), further reducing the impact of the fabrication process conditions of one transistor structure on the performance stability of the material layers of the subsequently fabricated transistor structure. Specifically, the first semiconductor layer covers the surface of the first contact structure away from the second transistor structure, and the second conductive layer covers the surface of the first contact structure away from the first transistor structure. This reduces the leakage probability of the first contact structure, also helps to reduce the overall space occupied by the two stacked transistor structures, decreases the planar dimensions of the semiconductor structure, and improves its stability and reliability.

[0022] On the other hand, embodiments of this application provide a method for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming a second transistor structure on one side of the semiconductor substrate; forming a first transistor structure on the side of the second transistor structure away from the semiconductor substrate; the first transistor structure and the second transistor structure being coupled through a first contact structure; wherein the first contact structure is coupled to a first semiconductor layer and a second conductive layer of the second transistor structure at opposite ends along the stacking direction of the first transistor structure and the second transistor structure, respectively; the first semiconductor layer covers the surface of the first contact structure away from the second transistor structure, and the second conductive layer covers the surface of the first contact structure away from the first transistor structure; forming a first word line structure; the first word line structure is coupled to the first conductive layer of the first transistor structure; forming a first bit line structure; the first bit line structure is coupled to a first electrode region of the first semiconductor layer of the first transistor structure; forming a second word line structure; the second word line structure is coupled to a third electrode region of the second semiconductor layer of the second transistor structure; forming a second bit line structure, the second bit line structure being coupled to a fourth electrode region of the second semiconductor layer of the second transistor structure.

[0023] In some examples, after forming the second transistor structure, a first semiconductor layer of the first transistor structure is formed; the material of the first semiconductor layer includes an oxide semiconductor material. Wherein, before forming the second transistor structure, the fabrication method includes forming the first contact structure; the cross-sectional area of ​​the first contact structure along the stacking direction of the first and second transistor structures decreases along the direction from the first transistor structure to the second transistor structure.

[0024] In some examples, after the first transistor structure is formed, a second semiconductor layer of the second transistor structure is formed; the material of the second semiconductor layer includes an oxide semiconductor material.

[0025] Before forming the second transistor structure, the fabrication method includes forming the first contact structure; the cross-sectional area of ​​the first contact structure along the stacking direction of the first transistor structure and the second transistor structure decreases along the direction from the second transistor structure to the first transistor structure.

[0026] The beneficial effects of the above-described semiconductor structure fabrication method are the same as those of the semiconductor structures provided in any of the above examples, and will not be repeated here. Furthermore, in the above-described semiconductor structure fabrication method, one transistor structure can be formed first, followed by another. This fabrication sequence of electronic components can reduce the adverse effects of the process temperature of the first-formed transistor structure on the performance of the material layer of the subsequently formed transistor structure. The two transistor structures are coupled through a first contact structure. The process of fabricating the first contact structure can further increase the time interval between the process steps of the two transistor structures, further reducing the adverse effects of the process temperature of the first-formed second transistor structure on the performance of the material layer of the subsequently formed first transistor structure, thereby improving the product performance of the semiconductor structure.

[0027] In another aspect, embodiments of this application provide a semiconductor device. The semiconductor device includes at least one semiconductor structure as provided in any of the examples above, and a peripheral circuit structure coupled to said at least one semiconductor structure.

[0028] The beneficial effects of the semiconductor device described above are the same as those of the semiconductor structure provided in any of the above examples, and will not be repeated here. Attached Figure Description

[0029] In the accompanying drawings, similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0030] Figure 1 This is a schematic diagram of a circuit diagram corresponding to a semiconductor structure provided in an embodiment of this application;

[0031] Figure 2 A schematic diagram of a semiconductor structure provided in an embodiment of this application. Figure 1 ;

[0032] Figure 3 A schematic diagram illustrating the structural relationship between the first contact structure, the first semiconductor layer, and the second conductive layer provided in an embodiment of this application;

[0033] Figure 4 A schematic diagram of a semiconductor structure provided in an embodiment of this application. Figure 2 ;

[0034] Figure 5 A schematic diagram of a semiconductor structure provided in an embodiment of this application. Figure 3 ;

[0035] Figure 6 A schematic diagram of a semiconductor structure provided in an embodiment of this application. Figure 4;

[0036] Figure 7 A schematic diagram of the first transistor structure of a semiconductor structure provided in an embodiment of this application. Figure 1 ;

[0037] Figure 8 A schematic diagram of the first transistor structure of a semiconductor structure provided in an embodiment of this application. Figure 2 ;

[0038] Figure 9 A schematic diagram of the first transistor structure of a semiconductor structure provided in an embodiment of this application. Figure 3 ;

[0039] Figure 10 A schematic diagram of the second transistor structure of a semiconductor structure provided in an embodiment of this application. Figure 1 ;

[0040] Figure 11 A schematic diagram of the second transistor structure of a semiconductor structure provided in an embodiment of this application. Figure 2 ;

[0041] Figure 12 A schematic diagram of the second transistor structure of a semiconductor structure provided in an embodiment of this application. Figure 3 ;

[0042] Figure 13 A schematic diagram of the second transistor structure of a semiconductor structure provided in an embodiment of this application. Figure 4 ;

[0043] Figure 14 Schematic diagram of the first transistor structure and the second transistor structure of the semiconductor structure provided in an embodiment of this application Figure 1 ;

[0044] Figure 15 Schematic diagram of the first transistor structure and the second transistor structure of the semiconductor structure provided in another embodiment of this application Figure 2 ;

[0045] Figure 16 Schematic diagram of the first transistor structure and the second transistor structure of the semiconductor structure provided in another embodiment of this application Figure 3 ;

[0046] Figure 17 Schematic diagram of the first transistor structure and the second transistor structure of the semiconductor structure provided in another embodiment of this application Figure 4 ;

[0047] Figure 18 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application. Figure 1 ;

[0048] Figure 19 A schematic diagram of the process flow for fabricating a semiconductor structure according to an embodiment of this application;

[0049] Figure 20 A schematic diagram of the process flow for a method of fabricating a semiconductor structure according to another embodiment of this application;

[0050] Figure 21 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application. Figure 2 ;

[0051] Figure 22 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application. Figure 3 ;

[0052] Figure 23 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0053] Figure 24 A schematic diagram of the peripheral circuit structure of a semiconductor device provided in an embodiment of this application;

[0054] Figure 25 This is a schematic diagram of the structure of a memory system provided in an embodiment of this application;

[0055] Figure 26 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0056] The technical solution of this disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0057] In this disclosure, the terms "first," "second," etc., are used to distinguish similar objects, and not to describe a specific order or sequence.

[0058] In this embodiment of the disclosure, the term "A in contact with B" includes the case where A and B are in direct contact, or the case where there are other components between A and B and A is indirectly in contact with B.

[0059] It should be understood that the phrases "some embodiments" or "some examples" mentioned throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "some embodiments" or "some examples" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0060] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0061] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0062] It should be noted that although this specification describes the embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0063] With the development of integrated circuit technology, the size of semiconductor devices is shrinking, and the integration density requirements of electronic components such as transistors are increasing, posing a significant challenge to the data read and write performance of semiconductor devices. Especially in the application of Dynamic Random Access Memory (DRAM), the structure and relative arrangement of different electronic components within DRAM are one of the important factors affecting the performance of semiconductor devices.

[0064] For example, in DRAM devices of related technologies, a single memory cell can have a 1T1C structure. The capacitor has a planar structure, occupying a large area, which is not conducive to reducing the area occupied by the semiconductor structure.

[0065] For example, in DRAM devices of the related art, a memory cell can be a 2T0C or 2T1C structure. However, if the two transistors are arranged side by side along a horizontal plane, they occupy a large area; or if they are stacked along a plane perpendicular to the horizontal plane, the process temperature of the transistor structure fabricated first can easily affect the electrical performance of the transistor structure fabricated later, reducing the reliability of the semiconductor structure.

[0066] To address the aforementioned issues, this application provides a semiconductor structure, its fabrication method, and a semiconductor device, which can reduce the size of the semiconductor structure and improve its stability and reliability.

[0067] In some embodiments, such as Figure 1 and Figure 2 As shown, this application provides a semiconductor structure 100.

[0068] For example, semiconductor structure 100 may include a stacked structure of functional layers corresponding to multiple memory cells arranged in an array within a memory device. For instance, if the memory device is DRAM, semiconductor structure 100 may include, for example, Figure 1 The diagram shows the layer structure of a 2T0C memory cell. The control electrode (e.g., gate) of the first transistor T1 is coupled to the first word line WWL, the first electrode (e.g., source) of the first transistor T1 is coupled to the first bit line WBL, and the second electrode (e.g., drain) of the first transistor T1 is coupled to the memory node SN. The control electrode (e.g., gate) of the second transistor T2 is coupled to the memory node SN, the first electrode (e.g., source) of the second transistor T2 is coupled to the second bit line RBL, and the second electrode (e.g., drain) of the second transistor T2 is coupled to the second word line RWL.

[0069] The following examples are based on Figure 1 Taking the connection relationship of electronic components in the circuit schematic shown as an example, an exemplary description of the layer structure of semiconductor structure 100 is given.

[0070] In some examples, such as Figure 2 As shown, the semiconductor structure 100 includes: a semiconductor substrate 110, a second transistor structure 120, a first transistor structure 130, a first bit line structure 151, a first word line structure 161, a second bit line structure 152, and a second word line structure 162.

[0071] The semiconductor substrate 110 can be a composite layer of one or more stacked materials, providing support and fabrication space for the subsequent fabrication of the first transistor structure 130 and the second transistor structure 120; alternatively, it can be removed or thinned after the subsequent structures are formed. The specific structure and arrangement of the semiconductor substrate 110 can be set according to actual needs and are not limited here. For example, the materials used in the semiconductor substrate 110 include one or more inorganic materials such as glass, quartz, silicon carbide, and silicon oxide, or organic materials such as epoxy resin or polyurethane.

[0072] The second transistor structure 120 is disposed on one side of the semiconductor substrate 110. For example, the second transistor structure 120 may be a layer structure forming a transistor. For instance, as... Figure 1 As shown, the second transistor structure 120 can be a layer structure of the second transistor T2 within a memory cell in the circuit structure.

[0073] The first transistor structure 130 is disposed on the side of the second transistor structure 120 away from the semiconductor substrate 110, and is coupled to the second transistor structure 120 through the first contact structure 141. For example, the first transistor structure 130 may be a layer structure forming a transistor. Figure 1 As shown, the first transistor structure 130 can be a layer structure of the first transistor T1 within a memory cell in the circuit structure.

[0074] Continue reading Figure 2 The first word line structure 161 is disposed within the layer structure of the first transistor structure 130 and coupled to the first conductive layer 132 within the first transistor structure 130. For example, the first word line structure 161 may be formed as follows: Figure 1 The layer structure of the first word line WWL is shown. The example provided in this application does not impose specific limitations on the specific pattern of the first word line structure 161.

[0075] The first line structure 151 is disposed on the side of the first transistor structure 130 away from the second transistor structure 120, and is coupled to the first semiconductor layer 131 within the first transistor structure 130. For example, the first line structure 151 may be formed as follows: Figure 1 The first line WBL layer structure is shown. The example provided in this application does not impose specific limitations on the specific pattern of the first line structure 151.

[0076] The second word line structure 162 is disposed within the layer structure of the second transistor structure 120 and coupled to an electrode region of the second semiconductor layer 122 of the second transistor structure 120. For example, the second word line structure 162 may be formed as follows: Figure 1The layer structure of the second word line RWL is shown. The example provided in this application does not specifically limit the specific pattern of the second word line structure 162.

[0077] The second bit line structure 152 is disposed within the layer structure of the second transistor structure 120 and coupled to another electrode region of the second semiconductor layer 122. For example, the second bit line structure 152 may be formed as follows: Figure 1 The layer structure of the second bit line RBL is shown. The example provided in this application does not impose specific limitations on the specific pattern of the second bit line structure 152.

[0078] The first contact structure 141 is coupled to the first semiconductor layer 131 and the second conductive layer 121 of the second transistor structure 120 at opposite ends along the stacking direction Y of the first transistor structure 130 and the second transistor structure 120, respectively. The first semiconductor layer 131 covers the side of the first contact structure 141 away from the second transistor structure 120, and the second conductive layer 121 covers the side of the first contact structure 141 away from the first transistor structure 130.

[0079] In the aforementioned semiconductor structure 100, the second transistor structure 120 and the first transistor structure 130 are stacked on the semiconductor substrate 110, which helps to reduce the size of the semiconductor structure 100 and increase its integration density. Furthermore, since the functional layers (e.g., semiconductor layers) in the second transistor structure 120 and the first transistor structure 130 are not fabricated along the same layer parallel to the semiconductor substrate 110, but rather layer by layer along a direction perpendicular to the semiconductor substrate 110, this reduces the impact of the fabrication process conditions of one transistor structure on the performance stability of the material layers of the subsequently fabricated transistor structure. Moreover, the first contact structure 141 provided between the first transistor structure 130 and the second transistor structure 120 further increases the distance between them (which, from a process step perspective, increases the time interval between their processes), improving the precise control of the coupling between the first semiconductor layer 131 and the second conductive layer 121, and further reducing the impact of the fabrication process conditions of one transistor structure on the performance stability of the material layers of the subsequently fabricated transistor structure. The first semiconductor layer 131 covers the side surface of the first contact structure 141 away from the second transistor structure 120, and the second conductive layer 121 covers the side surface of the first contact structure 141 away from the first transistor structure 130. This can reduce the leakage probability of the first contact structure 141, and also help to reduce the overall space occupied by the two stacked transistor structures, reduce the planar size of the semiconductor structure 100, and improve the stability and reliability of the semiconductor structure 100.

[0080] For example, the materials used in the first bit line structure 151, the first word line structure 161, the second bit line structure 152, or the second word line structure 162 include conductive materials, such as one or more of the following metallic elements or metallic compounds: copper, aluminum, tungsten, tantalum, titanium, nickel, platinum, tungsten nitride, tantalum nitride, or titanium nitride.

[0081] For example, at least two of the first bit line structure 151, the first character line structure 161, the second bit line structure 152, and the second character line structure 162 may use the same or different materials. The examples provided in this application do not limit this.

[0082] For example, the first contact structure 141 may be made of a conductive material, such as one or more of the following metallic elements or compounds: copper, aluminum, tungsten, tantalum, titanium, nickel, platinum, tungsten nitride, tantalum nitride, or titanium nitride.

[0083] In some examples, the first semiconductor layer 131 is made of an oxide semiconductor material. And, as... Figure 2 and Figure 4 As shown, the cross-sectional area of ​​the first contact structure 141 along the stacking direction of the first transistor structure 130 and the second transistor structure 120 decreases along the direction from the first transistor structure 130 to the second transistor structure 120.

[0084] For example, using an oxide semiconductor material (e.g., indium gallium zinc oxide) to fabricate the first semiconductor layer 131 can improve the performance of the first transistor structure 130. Furthermore, based on the cross-sectional area of ​​the first contact structure 141 along the stacking direction of the first transistor structure 130 and the second transistor structure 120, decreasing in the direction from the first transistor structure 130 to the second transistor structure 120, it indicates the fabrication sequence of fabricating the second transistor structure 120 first, followed by the first transistor structure 130. Thus, considering the materials, process conditions, and fabrication sequence of different functional layers, the fabrication sequence of the first transistor structure 130 and the second transistor structure 120 can be adjusted, reducing the adverse effects of the process temperature of the second transistor structure 120 on the material properties of the first semiconductor layer 131, and improving the stability and reliability of the first transistor structure 130.

[0085] It should be noted that this application Figure 2 and Figure 4 The provided semiconductor structure 100 takes into account the material properties of the first semiconductor layer 131, and the fabrication sequence of the first transistor structure 130 and the second transistor structure 120 is reflected through the first contact structure 141. Among these, in... Figure 2 and Figure 4The first transistor structure 130 and the second transistor structure 120 can be exemplarily represented as either planar transistors or vertical transistors. The relative positions of the layers within the first transistor structure 130 and the second transistor structure 120 are not limited here and can be set according to requirements. The specific fabrication order of each layer will be illustrated in the subsequent example of the semiconductor structure 100 fabrication method.

[0086] Similarly, in the future Figure 5 and Figure 6 The semiconductor structure 100 shown also takes into account the material properties of the second semiconductor layer 122. The fabrication sequence of the first transistor structure 130 and the second transistor structure 120 can be reflected by the change in the cross-sectional area of ​​the first contact structure 141 along the stacking direction Y of the first transistor structure 130 and the second transistor structure 120. The relative positional relationship of each layer within the first transistor structure 130 and the second transistor structure 120 is not limited here and can be set according to requirements. The specific fabrication sequence of each layer will be shown in the subsequent examples of the semiconductor structure 100 fabrication method.

[0087] In other examples, the second semiconductor layer 122 is made of an oxide semiconductor material. And, as... Figure 5 and Figure 6 As shown, the cross-sectional area of ​​the first contact structure 141 along the stacking direction Y of the first transistor structure 130 and the second transistor structure 120 decreases along the direction from the second transistor structure 120 to the first transistor structure 130.

[0088] For example, using an oxide semiconductor material (e.g., indium gallium zinc oxide) to fabricate the second semiconductor layer 122 can improve the performance of the second transistor structure 120. Furthermore, based on the cross-sectional area of ​​the first contact structure 141 along the stacking direction Y of the first transistor structure 130 and the second transistor structure 120, which decreases in the direction from the second transistor structure 120 to the first transistor structure 130, this indicates a fabrication sequence where the first transistor structure 130 is fabricated first, followed by the second transistor structure 120. Thus, considering the materials, process conditions, and fabrication sequence of different functional layers, the fabrication sequence of the first transistor structure 130 and the second transistor structure 120 can be adjusted, reducing the adverse effects of the process temperature of the first transistor structure 130 on the material properties of the second semiconductor layer 122 and improving the stability and reliability of the second transistor structure 120.

[0089] In some examples, the material of the first semiconductor layer 131 includes indium gallium zinc oxide; and / or, the material of the second semiconductor layer includes indium gallium zinc oxide.

[0090] Understandably, the high electron mobility and stability of indium gallium zinc oxide (IGZO) materials are beneficial for improving the conductivity stability and reliability of electronic components. However, IGZO has a relatively low processing temperature and is susceptible to degradation in conductivity due to high temperatures. Therefore, for a semiconductor structure 100 using an IGZO transistor structure, the processing conditions of other electronic components within the semiconductor structure 100 and their relative positions to the IGZO transistor structure are key factors affecting the performance of the IGZO transistor structure. Especially when the IGZO transistor structure is used as a critical component for data readout from a memory, improving the performance stability of the IGZO transistor structure is crucial for improving memory performance.

[0091] Furthermore, the materials of the first semiconductor layer 131 and the second semiconductor layer 122 can be the same or different. For example, the semiconductor material used in the second semiconductor layer 122 may include one or more of silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and gallium nitride (GaN); it may also include oxide semiconductor materials, such as indium gallium zinc oxide. The material used in the first semiconductor layer 131 may include indium gallium zinc oxide.

[0092] For example, the material of the second semiconductor layer 122 and the first semiconductor layer 131 are both indium gallium zinc oxide (IGNOO). Based on the conductivity of IGNOO, the conductivity of the semiconductor structure 100 can be improved. It is understood that, in this example, the fabrication order of the first transistor structure 130 and the second transistor structure 120 is not limited and can be adjusted according to requirements.

[0093] For example, the second semiconductor layer 122 can be made of ion-doped silicon, and the first semiconductor layer 131 can be made of indium gallium zinc oxide. Thus, considering material properties and process conditions, such as... Figure 2 and Figure 4 As shown, the second transistor structure 120 can be fabricated first, followed by the first transistor structure 130.

[0094] For example, the second semiconductor layer 122 can be made of indium gallium zinc oxide, and the first semiconductor layer 131 can be made of ion-doped silicon. Considering the application scenarios of the semiconductor structure 100, based on the different roles of the first transistor structure 130 and the second transistor structure 120 in the data reading process of the memory cell, for example, combining... Figure 1 The circuit schematic shown shows the first transistor structure 130 (fabrication). Figure 1 The first transistor T1 shown serves to maintain data in the storage node during the data writing process. The second transistor structure 120 (fabricated) Figure 1The second transistor T2 shown is used to enable a fast response and reduce charge loss during the data reading process.

[0095] Thus, as Figure 5 and Figure 6 As shown, the first transistor structure 130 can be fabricated first, followed by the second transistor structure 120. This reduces the adverse effects of the process temperature of the first semiconductor layer 131 (e.g., doping with ions and annealing) on ​​the electrical properties of the second semiconductor layer 122, which uses indium gallium zinc oxide material, thereby improving the reading accuracy and reliability of the second transistor structure 120 during the data reading process.

[0096] Based on the influence of the performance, interconnection, and positional relationships of each functional layer in the first transistor structure 130 and each functional layer in the second transistor structure 120 on the performance and integration density of the semiconductor structure 100, as mentioned in the above examples, in some examples, such as Figures 7-9 As shown, the first transistor structure 130 in the semiconductor structure 100 includes a planar transistor structure or a vertical transistor structure; and / or, as Figure 10 and Figure 13 As shown, the second transistor structure 120 includes a planar transistor structure or a vertical transistor structure.

[0097] For example, such as Figure 11 and Figure 14 As shown, the first transistor structure 130 includes a planar transistor structure, and the second transistor structure 120 includes a planar transistor structure.

[0098] Or, such as Figure 15 and Figure 16 As shown, the first transistor structure 130 includes a vertical transistor structure, and the second transistor structure 120 includes a vertical transistor structure.

[0099] Alternatively, the first transistor structure 130 may include a planar transistor structure, and the second transistor structure 120 may include a vertical transistor structure.

[0100] Or, as Figure 17 As shown, the first transistor structure 130 includes a vertical transistor structure, and the second transistor structure 120 includes a planar transistor structure.

[0101] The following examples illustrate the layer structure of the first transistor structure 130 and the second transistor structure 120 by combining different types of first transistor structures 130 and second transistor structures 120.

[0102] In some embodiments, such as Figure 7 and Figure 14As shown, in a semiconductor structure 100, the first transistor structure 130 is a planar transistor structure, and the second transistor structure 120 is a planar transistor structure.

[0103] like Figure 7 As shown, the first transistor structure 130 includes: a first adapter structure 132, one end of which is coupled to the first semiconductor layer 131, and the other end of which is coupled to the first bit line structure 151.

[0104] Specifically, the first transition structure 132 and the first contact structure 141 are respectively coupled to opposite sides of the first semiconductor layer 131 along the stacking direction X perpendicular to the first transistor structure 130 and the second transistor structure 120. Thus, the configuration is as follows: Figure 7 The first transition structure 132 and the first contact structure 141 shown are located on the upper and lower sides of the first semiconductor layer 131 along the stacking direction Y of the first transistor structure 130 and the second transistor structure 120, and are coupled to the first semiconductor layer 131. This helps to reduce the size of the first transistor structure 130 along the direction Y perpendicular to the semiconductor substrate 110 and reduce the size of the semiconductor structure 100.

[0105] Continue reading Figure 7 The first transistor structure 130 includes a first conductive layer 133. The first conductive layer 133 is coupled to a first word line structure 161. For example, the first conductive layer 133 is made of a conductive material, such as one or more of elemental metals or metal compounds such as copper, aluminum, tungsten, tantalum, titanium, nickel, platinum, tungsten nitride, tantalum nitride, or titanium nitride.

[0106] It is understood that a portion of the first word line structure 161 serves as the first conductive layer 133 (e.g., gate) of the first transistor structure 130. To facilitate explanation of the connection relationship between the first word line structure 161 and the first transistor structure 130, as follows... Figure 7 In the cross-sectional structure of the semiconductor structure 100 shown, the first conductive layer (e.g., the gate) of the first transistor structure 130 is identified by the reference numeral "133 / 161". For example, combined with Figure 1 The circuit schematic shown indicates that the first conductive layer 133 can serve as the gate of transistor T1 and the first word line WWL. Similarly, Figure 8 In the cross-sectional structure of the semiconductor structure 100 shown, the first conductive layer (e.g., the gate) of the first transistor structure 130 is identified by the reference numeral "133 / 161".

[0107] In the examples provided later, such as Figure 9 In the cross-sectional structure of the semiconductor structure 100 shown, the first conductive layer (e.g., the gate) of the first transistor structure 130 is identified by the reference numeral "133", and the first word line structure is identified by the reference numeral "161". For example, combined with Figure 1The circuit schematic shown shows that the first conductive layer 133 can be used as the gate of transistor T1, and the first word line structure 161 can be used as the first word line WWL.

[0108] Continue reading Figure 7 The first conductive layer 133 is disposed on the side of the first semiconductor layer 131 away from the second transistor structure 120, and is spaced apart from the first transition structure 132 along the stacking direction X perpendicular to the first transistor structure 130 and the second transistor structure 120.

[0109] Based on the relative positional relationship between the first transition structure 132 and the first semiconductor layer 131 of the first transistor structure 130, and the relative positional relationship between the two and the first contact structure 141 and the first first line structure 151, the first conductive layer 133 is set in the layer between the first semiconductor layer 131 and the first transition structure 132 along the stacking direction X perpendicular to the first transistor structure 130 and the second transistor structure 120, without adding extra size to the first transistor structure 130 along the direction Y perpendicular to the semiconductor substrate 110, which is beneficial to reducing the size of the semiconductor structure 100.

[0110] In some examples, such as Figure 10 As shown, the second semiconductor layer 122 of the second transistor structure 120 is disposed on the side of the second conductive layer 121 away from the first transistor structure 130.

[0111] It is understandable that when the material of the second semiconductor layer 122 includes doped silicon, the process temperature for forming the second semiconductor layer 122 is relatively high. Therefore, placing the second semiconductor layer 122 further away from the first transistor structure 130 increases the time interval between fabricating the second semiconductor layer 122 and fabricating the first transistor structure 130 (especially the first semiconductor layer 131). This helps to reduce the adverse effects of the process temperature of the second semiconductor layer 122 on the performance of the first semiconductor layer 131 of the first transistor structure 130, improves the electrical stability and reliability of the first transistor structure 130, and ultimately improves the product performance of the semiconductor structure 100.

[0112] In some examples, such as Figure 7 As shown, the first transistor structure 130 includes: a first semiconductor layer 131, a first transition structure 132, a first dielectric layer 134, a first conductive layer 133 / 161, and a second dielectric layer 135.

[0113] The first dielectric layer 134 is disposed on the side of the first semiconductor layer 131 away from the second transistor structure 120. For example, the material used for the first dielectric layer 134 includes dielectric materials, such as one or more of silicon oxide, aluminum oxide, and hafnium oxide.

[0114] The first conductive layer 133 is disposed on the side of the first dielectric layer 134 away from the first semiconductor layer 131. For example, the material used for the first conductive layer 133 includes conductive materials, such as one or more of the following metallic elements or metallic compounds: copper, aluminum, tungsten, tantalum, titanium, nickel, platinum, tungsten nitride, tantalum nitride, or titanium nitride.

[0115] The second dielectric layer 135 is disposed on the side of the first conductive layer 133 away from the first dielectric layer 134. For example, the material used for the second dielectric layer 135 includes dielectric materials, such as one or more of silicon oxide, aluminum oxide, and hafnium oxide. The materials of the second dielectric layer 135 and the first dielectric layer 134 may be the same or different.

[0116] The first semiconductor layer 131 includes a first electrode region 1311 and a second electrode region 1312 spaced apart. The first electrode region 1311 is coupled to the second transistor structure 120 through a first contact structure 141, and the second electrode region 1312 is coupled to the first bit line structure 151 through a first transition structure 132.

[0117] Based on such Figure 7 The layer structure of the first transistor structure 130 shown can form a transistor T1 with a smaller size along the direction Y perpendicular to the semiconductor substrate 110, which is beneficial to reducing the size of the semiconductor structure 100.

[0118] In some examples, such as Figure 10 and Figure 14 As shown, the second transistor structure 120 includes: a second semiconductor layer 122, a third dielectric layer 123, a second conductive layer 121, and a fourth dielectric layer 124.

[0119] The second semiconductor layer 122 includes a third electrode region 1221 and a fourth electrode region 1222 spaced apart. The third electrode region 1221 is coupled to the second word line structure 162; the fourth electrode region 1222 is coupled to the second bit line structure 152.

[0120] The third dielectric layer 123 is disposed on one side of the second semiconductor layer 122.

[0121] The second conductive layer 121 is disposed on the side of the third dielectric layer 123 away from the second semiconductor layer 122. The second conductive layer 121 is coupled to the first transistor structure 130 through a second contact structure 142. For example, the second contact structure 142 is coupled to the first contact structure 141. As an example, the material used for the second conductive layer 121 includes conductive materials, such as one or more of elemental metals or metal compounds such as copper, aluminum, tungsten, tantalum, titanium, nickel, platinum, tungsten nitride, tantalum nitride, or titanium nitride.

[0122] The second contact structure 142 extends along the stacking direction Y of the first transistor structure 130 and the second transistor structure 120. For example, the material used for the second contact structure 142 includes conductive materials, such as one or more of the following: copper, aluminum, tungsten, tantalum, titanium, nickel, platinum, tungsten nitride, tantalum nitride, or titanium nitride, or other elemental metals or metal compounds.

[0123] The fourth dielectric layer 124 is disposed on the side of the second conductive layer 121 away from the third dielectric layer 123.

[0124] It should be noted that, since the patterns of the second word line structure 162 and the second bit line structure 152 intersect, they can be fabricated separately on different layers of the semiconductor structure 100. Combined with the second transistor structure 120, they form... Figure 1 The connection relationship of the control electrode (e.g., gate), first electrode (e.g., source), and second electrode (e.g., drain) of transistor T2 is shown as follows: Figure 10 As shown, the pattern of the second word line structure 162 (or the second bit line structure 152) can be disposed on the same layer as the pattern of the control electrode of the transistor T2 (i.e., the second conductive layer 121), which is beneficial to reduce the size of the semiconductor structure 100 along the direction Y perpendicular to the semiconductor substrate 110.

[0125] In this way, the 2T0C semiconductor structure 100, which stacks two electronic components along the Y direction, can reduce the size of the semiconductor structure 100 along the X direction, which is beneficial to improving the integration density. Moreover, reducing the impact of the process conditions for fabricating one transistor structure on the performance stability of the material layer of the subsequently fabricated transistor structure improves the product performance of the semiconductor structure 100.

[0126] In addition, such as Figure 11 As shown, the patterns of the second word line structure 162, the second bit line structure 152, and the control electrode pattern of transistor T2 (i.e., the second conductive layer 121) can be respectively disposed on different layers. Combined with the second contact structure 142, which couples the second conductive layer 121 of the second transistor structure 120 with the first transistor structure 130, it also provides space for fabricating the pattern of the second bit line structure 152 (or the pattern of the second word line structure 162). For example, as... Figure 11 As shown, the pattern of the second bit line structure 152 is located in the same layer as the second contact structure 142, and the pattern of the second word line structure 162 is located in the layer between the second conductive layer 121 and the second contact structure 142. In this way, without increasing the dimension of the semiconductor structure 100 along the Y direction perpendicular to the semiconductor substrate 110, it also improves the fabrication space for the patterns of the second word line structure 162 and the second bit line structure 152, thereby enhancing the fabrication flexibility and conductivity of the second word line structure 162 and the second bit line structure 152.

[0127] In other embodiments, such as Figure 15 and Figure 16 As shown in the example below, a semiconductor structure 100 has a first transistor structure 130 that is a vertical transistor structure and a second transistor structure 120 that is a vertical transistor structure, which can further reduce the size of the semiconductor structure 100, increase the integration density, and improve the conductivity stability and reliability of the semiconductor structure 100.

[0128] Example, combination Figure 1 The circuit schematic shown indicates that the first transistor structure 130 corresponds to transistor T1, and the second transistor structure 120 corresponds to transistor T2. In the layered structure of the semiconductor structure 100, the first transistor structure 130 and the second transistor structure 120 are stacked along the Y direction. The fabrication order of the first transistor structure 130 and the second transistor structure 120 is not limited; it can be arranged according to... Figure 11 and Figure 12 The two layer structures and corresponding processes of the first transistor structure 130 shown are adjusted.

[0129] In some examples, such as Figure 15 As shown, the first transistor structure 130 includes: a second dielectric layer 135, and a first columnar conductive structure 1301 disposed in the second dielectric layer 135.

[0130] The first columnar conductive structure 1301 extends along the stacking direction Y of the first transistor structure 130 and the second transistor structure 120, with one end coupled to the second transistor structure 120 and the other end coupled to the first line structure 151.

[0131] Continue reading Figure 15 The first columnar conductive structure 1301 includes: a columnar first semiconductor layer 131, a first dielectric layer 134, and a first conductive layer 133 / 151.

[0132] The columnar first semiconductor layer 131 includes a first electrode region 1311 and a second electrode region 1312 spaced apart at both ends of the columnar first semiconductor layer 131. The second electrode region 1312 is coupled to the second transistor structure 120 through a first contact structure 141; the first electrode region 1311 is coupled to the first bit line structure 151.

[0133] The first dielectric layer 134 is disposed on one side of the columnar first semiconductor layer 131.

[0134] The first conductive layer 133 is disposed on the side of the first dielectric layer 134 away from the columnar first semiconductor layer 131; the first conductive layer 133 is coupled to the first word line structure 161.

[0135] In other examples, such as Figure 16As shown, the first transistor structure 130 includes a second dielectric layer 135 and a first pillar-shaped conductive structure 1301. The first pillar-shaped conductive structure 1301 is disposed in the second dielectric layer 135; the first pillar-shaped conductive structure 1301 extends along the stacking direction Y of the first transistor structure 130 and the second transistor structure 120, with one end coupled to the second transistor structure 120 and the other end coupled to the first word line structure 161.

[0136] The first columnar conductive structure 1301 includes: a columnar first conductive layer 133, a first dielectric layer 134, and a first semiconductor layer 131.

[0137] The columnar first conductive layer 133 is coupled to the first word line structure 161.

[0138] The first dielectric layer 134 surrounds the columnar first conductive layer 133.

[0139] The first semiconductor layer 131 surrounds the first dielectric layer 134; the first semiconductor layer 131 includes a first electrode region 1311 and a second electrode region 1312 disposed at intervals along the stacking direction Y of the first transistor structure 130 and the second transistor structure 120; the second electrode region 1312 is coupled to the second transistor structure 120 through a first contact structure 141; the first electrode region 1311 is coupled to the first bit line structure 151.

[0140] The semiconductor structure 100 can be fabricated using either of the two layer structures of the first transistor structure 130 provided above, depending on the requirements, in order to improve the product performance of the semiconductor structure 100.

[0141] For the layered structure of the second transistor structure 120, in some examples, such as Figure 15 and Figure 16 As shown, the second transistor structure 120 includes a fourth dielectric layer 124 and a second pillar-shaped conductive structure 1201 disposed in the fourth dielectric layer 124. The second pillar-shaped conductive structure 1201 extends along the stacking direction Y of the second transistor structure 120 and the first transistor structure 130, with one end coupled to the first transistor structure 130 and the other end coupled to the second word line structure 152 or the second bit line structure 162.

[0142] Continue reading Figure 15 and Figure 16 The second columnar conductive structure 1201 includes: a columnar second conductive layer 121, a third dielectric layer 123, and a second semiconductor layer 122.

[0143] One end of the columnar second conductive layer 121 is coupled to the first semiconductor layer 131 of the first transistor structure 130 through the first contact structure 141.

[0144] The third dielectric layer 123 surrounds the columnar second conductive layer 121.

[0145] The second semiconductor layer 122 surrounds the third dielectric layer 123. The second semiconductor layer 122 includes a third electrode region 1221 and a fourth electrode region 1222 disposed at intervals along the stacking direction Y of the second transistor structure 120 and the first transistor structure 130. The third electrode region 1221 is coupled to the second word line structure 162; the fourth electrode region 1222 is coupled to the second bit line structure 152.

[0146] Based on the examples provided above, such as Figure 8 The first transistor structure 130 shown and as follows Figure 12 The second transistor structure 120 shown is a vertically oriented transistor, while the first transistor structure 130 is a vertically oriented transistor. Both the second transistor structure 120 and the first transistor structure 130 are vertically oriented transistors, and can be formed as shown in the diagram. Figure 15 The 2T0C semiconductor structure 100 stacked along the Y direction shown can further reduce the size of the semiconductor structure 100 along the X direction, which is beneficial to improving the integration density.

[0147] Alternatively, based on the examples provided above, such as Figure 9 The first transistor structure 130 shown and as follows Figure 13 The second transistor structure 120 shown is a vertically oriented transistor, while the first transistor structure 130 is a vertically oriented transistor. Both the second transistor structure 120 and the first transistor structure 130 are vertically oriented transistors, and can be formed as shown in the diagram. Figure 16 The 2T0C semiconductor structure 100 stacked along the Y direction shown can further reduce the size of the semiconductor structure 100 along the X direction, which is beneficial to improving the integration density. Moreover, because Figure 16 The first transistor structure 130 and the second transistor structure 120 shown have the same layer structure, which can simplify the process complexity from the perspective of process operation.

[0148] In addition, the examples provided above can be combined with such examples. Figures 7-9 The first transistor structure 130 or the second transistor structure 120 shown, and as... Figures 10-13 The first transistor structure 130 or the second transistor structure 120 shown are used to construct a semiconductor structure 100 with other transistor combinations to meet actual needs.

[0149] For example, such as Figure 17 As shown, a semiconductor structure 100 is provided in which the first transistor structure 130 is a vertical transistor structure and the second transistor structure 120 is a planar transistor structure. The specific layer structures of the first transistor structure 130 and the second transistor structure 120 can be found in the examples above, and will not be repeated here.

[0150] In some examples, the layer structure of the first transistor structure 130 is the same as that of the second transistor structure 120.

[0151] For example, such as Figure 16 As shown, the relative positional relationship (and number of layers) of each functional layer of the first transistor structure 130 is the same as that of each functional layer of the second transistor structure 120, which indicates that the layer structure of the first transistor structure 130 and the second transistor structure 120 is the same.

[0152] The patterns of each functional layer in the first transistor structure 130 may be the same as or different from the patterns of each functional layer in the second transistor structure 120. This can be set according to actual needs.

[0153] Furthermore, the specific materials of each functional layer of the first transistor structure 130 may be the same as or different from the specific materials of each functional layer of the second transistor structure 120. This can be set according to actual needs.

[0154] The semiconductor structure 100 obtained in this way can be fabricated using the same process to fabricate the first transistor structure 130 and the second transistor structure 120, which simplifies the operation of the semiconductor structure 100. The specific layer structures of the first transistor structure 130 and the second transistor structure 120 are not specifically limited in this application and can be set according to actual needs.

[0155] Furthermore, when the first semiconductor layer 131 is made of indium gallium zinc oxide, the process conditions of the second semiconductor layer 122 of the second transistor structure 120 will not affect the stability and reliability of the performance of the first semiconductor layer 131.

[0156] Based on the semiconductor structure 100 provided in the above example, and the corresponding semiconductor structure 100 Figure 1 The diagram shows a circuit schematic of a memory cell, wherein the first transistor structure 130 (corresponding to...) Figure 1 Transistor T1), and second transistor structure 120 (corresponding to) Figure 1 Transistor T2 in the first word line structure 161 (corresponding to) Figure 1 The first character line WWL), the first character line structure 151 (corresponding to) Figure 1 The first line (WBL) and the second line structure (162) correspond to Figure 1 The second word line (RWL) and the second bit line structure 152 (corresponding to) Figure 1 The second bit line (RBL) in the middle.

[0157] Under the control of the transmission signals of the first word line (WWL), the first bit line (WBL), the second word line (RWL), and the second bit line (RWL), data storage and retrieval in a 2T0C structure can be realized. This can be applied to DRAM memories that integrate in-memory computing, improving the reliability of DRAM memory data read and write operations.

[0158] On the other hand, such as Figures 18-22 As shown, this application provides a method for fabricating a semiconductor structure 100. The fabrication method includes steps S100, S200, S300, S400, S500, S600, and S700. It should be noted that, considering the different process conditions and fabrication processes of the first transistor structure 130 and the second transistor structure 120 with different layer structures, the order of steps S100, S200, S300, S400, S500, S600, and S700 can be adjusted according to requirements.

[0159] S100: As Figure 18 , Figure 19 (a) and Figure 20 As shown in (f), a semiconductor substrate 110 is provided.

[0160] For example, the semiconductor substrate 110 can be a composite layer of one or more stacked materials, providing support and fabrication space for the subsequent fabrication of the first transistor structure 130 and the second transistor structure 120; or, it can be removed or thinned after the subsequent structures are formed. The specific structure and arrangement of the semiconductor substrate 110 can be set according to actual needs and are not limited here. For example, the materials used in the semiconductor substrate 110 include one or more inorganic materials such as glass, quartz, silicon carbide, and silicon oxide, or organic materials such as epoxy resin or polyurethane.

[0161] S200: such as Figure 18 , Figure 19 (b) in the middle Figure 19 (d) in the middle, and Figure 20 (c)~ Figure 20 As shown in (e), a second transistor structure 120 is formed on one side of the semiconductor substrate 110.

[0162] For example, multiple dielectric layers and multiple conductive layers are formed respectively, and patterned to obtain a second transistor structure 120 of a transistor device. For example, as Figure 1 As shown, the second transistor structure 120 can be a layer structure of transistor T2 within a memory cell in the circuit structure.

[0163] S300: such as Figure 18 , Figure 19 (e) in Figure 19 (g) in, and Figure 20 (a) and Figure 20 As shown in (b), a first transistor structure 130 is formed on the side of the second transistor structure 120 away from the semiconductor substrate 110. The first transistor structure 130 and the second transistor structure 120 are coupled through a first contact structure 141. For example, as Figure 1 As shown, the drain of transistor T1 (i.e., the first transistor structure 130) is coupled to the control electrode of transistor T2 (i.e., the second transistor structure 120), and the equivalent circuit node of the two coupled is the storage node SN (i.e., the first contact structure 141).

[0164] For example, multiple alternating layers of dielectric and conductive material are formed, and the dielectric and conductive material layers are patterned respectively to obtain a first transistor structure 130 of a transistor device. For example, as Figure 1 As shown, the first transistor structure 130 can be a layer structure of transistor T1 within a memory cell in the circuit structure.

[0165] In this configuration, the first contact structure 141 is coupled to the first semiconductor layer 131 of the first transistor structure 130 and the second conductive layer 121 of the second transistor structure 120 at opposite ends along the stacking direction Y of the first transistor structure 130 and the second transistor structure 120, respectively. The first semiconductor layer 131 covers the side of the first contact structure 141 away from the second transistor structure 120, and the second conductive layer 121 covers the side of the first contact structure 141 away from the first transistor structure 130. This helps to reduce the leakage probability of the first contact structure 141, reduce the overall space occupied by the two stacked transistor structures, reduce the planar dimensions of the semiconductor structure 100, and improve the stability and reliability of the semiconductor structure 100.

[0166] S400: Forming a first word line structure 161. The first word line structure 161 is coupled to the first conductive layer 133 of the first transistor structure 130.

[0167] For example, such as Figure 19 (g) and Figure 20 As shown in (b), a first word line structure 161 is formed simultaneously with the formation of the first conductive layer 133 of the first transistor structure 130. The first conductive layer 133 and the first word line structure 161 can be different conductive structures formed in one step using the same material and synchronous process. Furthermore, the first word line structure 161 is coupled to the first conductive layer 133 of the first transistor structure 130.

[0168] S500: Forming the first bit line structure 151. The first bit line structure 151 is coupled to the first electrode region 1311 of the first semiconductor layer 131 of the first transistor structure 130.

[0169] For example, such as Figure 19 As shown in (g), after the first transistor structure 130 is formed, a first line structure 151 is formed on the side of the first transistor structure 130 away from the second transistor structure 120. The first line structure 151 is coupled to the first electrode region 1311 of the first semiconductor layer 131 of the first transistor structure 130 through a first transition structure 132.

[0170] For example, such as Figure 20 As shown in (f), after forming the second transistor structure 120, the first transistor structure 130 and the second transistor structure 120 are inverted on the semiconductor substrate 110, and the surface of the first transistor structure 130 away from the second transistor structure 120 is thinned. A first transition structure 132 is formed on the side of the first transistor structure 130 away from the second transistor structure 120, and the first transition structure 132 extends in a direction Y perpendicular to the semiconductor substrate 110. A conductive material layer is formed on the side of the first transition structure 132 away from the second transistor structure 120 to obtain the pattern of the first first line structure 151. Thus, one end of the first transition structure 132 is coupled to the first electrode region 1311 of the first semiconductor layer 131, and the other end is coupled to the first first line structure 151.

[0171] S600: Forming a second word line structure 162. The second word line structure 162 is coupled to the third electrode region 1221 of the second semiconductor layer 122 of the second transistor structure 120.

[0172] For example, such as Figure 19 As shown in (c), a second word line structure 162 is formed simultaneously with the formation of the second conductive layer 121 of the second transistor structure 120. The second conductive layer 121 and the second word line structure 162 can be different conductive structures formed in one step using the same material and synchronous process. Furthermore, the second word line structure 162 is coupled to the second conductive layer 121 of the first transistor structure 130.

[0173] Or, such as Figure 11 As shown, the second word line structure 162 is located on the side of the second conductive layer 121 away from the semiconductor substrate 110. The second word line structure 162 is coupled to the third electrode region 1221 of the second semiconductor layer 122 of the second transistor structure 120 through a transition structure.

[0174] For example, such as Figure 20 (c) and Figure 20As shown in (d), a second word line structure 162 is formed on one side of the first transistor structure 130 before the second transistor structure 120 is formed. Then, the second transistor structure 120 is formed on the side of the second word line structure 162 away from the first transistor structure 130. The second word line structure 162 is coupled to the third electrode region 1221 of the second semiconductor layer 122 of the second transistor structure 120.

[0175] S700: Forming a second bit line structure 152. The second bit line structure 152 is coupled to the fourth electrode region 1222 of the second semiconductor layer 122 of the second transistor structure 120.

[0176] For example, such as Figure 19 As shown in (d), after forming the second transistor structure 120, a second bit line structure 152 is formed on the side of the second transistor structure 120 away from the semiconductor substrate 110. The second bit line structure 152 and the second contact structure 142 can be different conductive structures formed in one step using the same layer material and synchronous process. The second bit line structure 152 is coupled to the fourth electrode region 1222 of the second semiconductor layer 122. The second contact structure 142 is coupled to the second conductive layer 121 of the second transistor structure 120.

[0177] For example, such as Figure 20 (c) and Figure 20 As shown in (d), before forming the second transistor structure 120, after forming a stacked second word line structure 162 and a fourth dielectric layer 124 on one side of the first transistor structure 130, a conductive material layer is formed on the side of the fourth dielectric layer 124 away from the second word line structure 162. Based on the stacked structure of the second word line structure 162, the fourth dielectric layer 124, and the conductive material layer, a groove extending in the direction Y perpendicular to the semiconductor substrate 110 is subsequently formed, resulting in the pattern of the second bit line structure 152. The second bit line structure 152, the fourth dielectric layer 124, and the second word line structure 162 together constitute the inner wall of the groove. Thus, the fourth electrode region 1222 of the second semiconductor layer 122 formed on the inner wall of the groove is coupled to the second bit line structure 152, and the third electrode region 1221 of the second semiconductor layer 122 is coupled to the second word line structure 162.

[0178] In some examples, the materials used for the first bit line structure 151, the second bit line structure 152, the first word line structure 161, and the second word line structure 162 include conductive materials, such as one or more of the following metallic elements or compounds: copper, aluminum, tungsten, tantalum, titanium, nickel, platinum, tungsten nitride, tantalum nitride, or titanium nitride. The materials used for the first bit line structure 151, the second bit line structure 152, the first word line structure 161, and the second word line structure 162 can be the same or different, depending on actual requirements.

[0179] The order of the fabrication steps S400, S500, S600 and S700 can be formed during the fabrication of each functional layer of the first transistor structure 130 and the second transistor structure 120. The example provided in this application does not limit the order of the fabrication steps S400, S500, S600 and S700, nor does it limit the order of the fabrication steps S400, S500, S600 and S700 with the fabrication steps of each functional layer of the first transistor structure 130 and the second transistor structure 120.

[0180] In some examples, such as Figure 21 As shown, between step S300: forming the second transistor structure 120 and step S400: forming the first transistor structure 130, the fabrication method further includes step S800.

[0181] S800: such as Figure 19 (e) and Figure 20 As shown in (b), a first contact structure 141 is formed. The first contact structure 141 is coupled to the first semiconductor layer 131 and the second conductive layer 121 at opposite ends along the stacking direction Y of the first transistor structure 130 and the second transistor structure 120, respectively.

[0182] In this way, one transistor structure can be formed first, and then another transistor structure can be formed. This manufacturing sequence of electronic components can reduce the adverse effects of the process temperature of the first transistor structure on the performance of the material layer of the subsequently formed transistor structure. The two transistor structures are coupled together through the first contact structure 141. The process of manufacturing the first contact structure 141 can further increase the time interval between the process steps of the two transistor structures, further reducing the adverse effects of the process temperature of the first transistor structure on the performance of the material layer of the subsequently formed transistor structure, and improving the product performance of the semiconductor structure 100.

[0183] For example, a photolithography process can be used to form a via on the side of the second transistor structure 120 near the first transistor structure 130, and fill it with conductive material to obtain a first contact structure 141. One first contact structure 141 corresponds to a first semiconductor layer 131 of the first transistor structure 130 and a second conductive layer 121 of the second transistor structure 120.

[0184] The order of steps S200 and S300 provided in the above example can be either S200 performed first and S300 performed later, or S200 performed after S300. The following example, in conjunction with the materials of the semiconductor layers of the first transistor structure 130 and the second transistor structure 120, and the first contact structure 141, exemplifies the order of steps S200 and S300.

[0185] In some examples, such as Figure 19 (e) and Figure 21 As shown, after step S200: forming the second transistor structure 120, step S300 includes S310: forming the first semiconductor layer 131 of the first transistor structure 130. The material of the first semiconductor layer 131 includes an oxide semiconductor material, such as indium gallium zinc oxide.

[0186] Before forming the first semiconductor layer 131, step 800 includes S810: forming a first contact structure 141. The cross-sectional area of ​​the first contact structure 141 along the stacking direction Y of the first transistor structure 130 and the second transistor structure 120 decreases along the direction from the first transistor structure 130 to the second transistor structure 120.

[0187] For example, such as Figure 19 As shown in (e), in the process of fabricating a planar transistor, the layer structure of the second transistor structure 120 is formed first, and then the layer structure of the first transistor structure 130 is formed. For example, based on... Figure 14 The diagram illustrates the first transistor structure 130 and the relative positions of its functional layers. The first transistor structure 130 includes: a first semiconductor layer 131, a first dielectric layer 134, a first conductive layer 133 / 161, and a second dielectric layer 135. The first dielectric layer 134 is disposed on the side of the first semiconductor layer 131 away from the second transistor structure 120. The first conductive layer 133 / 161 is disposed on the side of the first dielectric layer 134 away from the first semiconductor layer 131. The second dielectric layer 135 is disposed on the side of the first conductive layer 133 / 161 away from the first dielectric layer 134. The first semiconductor layer 131 includes a first electrode region 1311 and a second electrode region 1312 spaced apart. The first electrode region 1311 is coupled to the first electrode plate layer 141 via a first contact structure 141, and the second electrode region 1312 is coupled to the first bit line structure 151 via a first transition structure 132.

[0188] like Figure 19 As shown in (e), an oxide semiconductor material layer is formed on the side of the first contact structure 141 away from the second transistor structure 120, and a first semiconductor layer 131 is formed after patterning etching. For example, the first semiconductor layer 131 can be made of indium gallium zinc oxide.

[0189] Understandably, indium gallium zinc oxide (IGNOO) materials have relatively low processing temperatures and are easily affected by high temperatures, which can reduce their conductivity. Under the processing conditions of the second transistor structure 120, for example, the high processing temperature for ion doping and annealing of the second semiconductor layer 122 of the second transistor structure 120 can easily lead to a decrease in the electrical properties of the first semiconductor layer 131 using IGNOO material.

[0190] Thus, after the second semiconductor layer 122 of the second transistor structure 120 is fabricated, the fabricated multilayer functional layer and first contact structure 141 help to reduce the adverse effects of the process temperature of the second semiconductor layer 122 on the electrical properties of the first semiconductor layer 131, improve the conductivity of the first transistor structure 130, and improve the product performance of the semiconductor structure 100.

[0191] In other examples, such as Figure 20 (c)~ Figure 20 (e) and Figure 22 As shown, after step S300: forming the first transistor structure 130, step S200 includes S210: forming the second semiconductor layer 122 of the second transistor structure 120; the material of the second semiconductor layer 122 includes indium gallium zinc oxide.

[0192] Before forming the first semiconductor layer 131, the fabrication method includes S820: forming a first contact structure 141. The cross-sectional area of ​​the first contact structure 141 along the stacking direction Y of the first transistor structure 130 and the second transistor structure 120 decreases along the direction from the second transistor structure 120 to the first transistor structure 130.

[0193] For example, after forming the first transistor structure 130, a structure such as... is fabricated on the side of the first transistor structure 130 away from the semiconductor substrate 110. Figure 15 The first contact structure 141 and the second transistor structure 120 are shown. The cross-sectional area of ​​the first contact structure 141 along the direction perpendicular to the semiconductor substrate 110 decreases along the direction from the second transistor structure 120 to the first transistor structure 130.

[0194] For example, based on such Figure 15 The diagram illustrates the relative positions of the second transistor structure 120 and its functional layers. The second transistor structure 120 includes a fourth dielectric layer 124 and a second pillar-shaped conductive structure 1201 disposed within the fourth dielectric layer 124. The second pillar-shaped conductive structure 1201 extends along the stacking direction Y of the second transistor structure 120 and the first transistor structure 130, with one end coupled to the first transistor structure 130 and the other end coupled to the second word line structure 152 or the second bit line structure 162.

[0195] The second columnar conductive structure 1201 includes: a columnar second conductive layer 121, a third dielectric layer 123, and a second semiconductor layer 122.

[0196] One end of the columnar second conductive layer 121 is coupled to the first semiconductor layer 131 of the first transistor structure 130 through the first contact structure 141.

[0197] The third dielectric layer 123 surrounds the columnar second conductive layer 121.

[0198] The second semiconductor layer 122 surrounds the third dielectric layer 123. The second semiconductor layer 122 includes a third electrode region 1221 and a fourth electrode region 1222 disposed at intervals along the stacking direction Y of the second transistor structure 120 and the first transistor structure 130. The third electrode region 1221 is coupled to the second word line structure 162; the fourth electrode region 1222 is coupled to the second bit line structure 152.

[0199] The steps for fabricating the second transistor structure 120 are as follows: Figure 20 (c)~ Figure 20 As shown in (e), a fourth dielectric layer 124 and a second bit line structure 152 are formed on the side of the first contact structure 141 away from the first transistor structure 130, and a groove extends in a direction perpendicular to the semiconductor substrate 110.

[0200] Semiconductor material is deposited within the trench to form a second semiconductor layer 122 located on the inner wall of the trench. The third electrode region 1221 of the second semiconductor layer 122 is coupled to the second word line structure 162, and the fourth electrode region 1222 is coupled to the second bit line structure 152. For example, the second semiconductor layer 122 can be fabricated using indium gallium zinc oxide.

[0201] Then, a dielectric material is deposited in the groove to form a third dielectric layer 123 located on the side of the second semiconductor layer 122 away from the second bit line structure 15 coupled thereto. A conductive material is filled in the groove, filling the space within the third dielectric layer 123 to form a columnar second conductive layer 121, thus forming a first columnar conductive structure 1201.

[0202] It should be noted that, when the first transistor structure 130 includes a first semiconductor layer 131, based on, as Figure 20 (a) in Figure 20 The semiconductor structure 100 is fabricated in step (f) of the second transistor structure 120. The material used for the second semiconductor layer 122 in the second transistor structure 120 can be an oxide semiconductor material. For example, the material used for the second semiconductor layer 122 is the same as the material used for the first semiconductor layer 131, which is indium gallium zinc oxide. In this way, the adverse effects of the process temperature of the subsequently fabricated second transistor structure 120 on the electrical performance of the first semiconductor layer 131 can be avoided.

[0203] On the other hand, such as Figure 23As shown, this application provides a semiconductor device 200. For example, the semiconductor device 200 may include, but is not limited to, one or more of the following types of memory: NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), and Nano Random Access Memory (NRAM). For instance, this application uses DRAM semiconductor memory as an example for illustrative purposes.

[0204] In some examples, such as Figure 23 As shown, this application includes a semiconductor device 200 comprising at least one semiconductor structure 100 as provided in any of the examples above and a peripheral circuit structure 210 coupled to the at least one semiconductor structure 100. It should be noted that this application does not limit the specific layer structure of the peripheral circuit structure 210, nor does it limit the relative positional relationship between the peripheral circuit structure 210 and the semiconductor structure 100; the examples merely illustrate the coupling relationship between the two, and the specific configuration can be determined according to actual needs.

[0205] For example, a semiconductor structure 100 may include multiple arrays such as Figure 1 The 2T0C memory cell structure shown is a DRAM memory cell array (see...) Figure 24 Furthermore, the peripheral circuit structure 210 may include various types of circuit structures formed using metal-oxide-semiconductor (MOS) transistors, configured to transmit electrical signals to the memory cell array.

[0206] For example, such as Figures 14-16As shown, the semiconductor structure 100, under the functional action of the first word line structure 161, the first bit line structure 151, the second word line structure 162, and the second bit line structure 152, can store charge for the semiconductor device 1000 to realize data reading and writing; and based on the relative positional relationship of the first transistor structure 130 and the second transistor structure 120 and the characteristics of the semiconductor layer material, the reliability of reading and writing data can be improved.

[0207] Combination Figure 24 The DRAM memory cell array shown includes multiple memory cells arranged in an array. Multiple memory cells in the same row are coupled to a first word line (WWL) (e.g., first word line structure 161) and a second word line (RWL) (e.g., second word line structure 162). Multiple memory cells in the same column are coupled to a first bit line (WBL) (e.g., first bit line structure 151) and a second bit line (RBL) (e.g., second bit line structure 152). Each memory cell includes, as shown... Figure 1 Transistors T1 and T2 are shown in the diagram. The control electrode (e.g., gate) of transistor T1 is coupled to the first word line WWL, the first electrode (e.g., source) of transistor T1 is coupled to the first bit line WBL, and the second electrode (e.g., drain) of transistor T1 is coupled to the memory node SN. The control electrode (e.g., gate) of transistor T2 is coupled to the memory node SN, the first electrode (e.g., source) of transistor T2 is coupled to the second bit line RBL, and the second electrode (e.g., drain) of transistor T2 is coupled to the second word line RWL. The memory cell is configured to store 1 or 0 by using transistor T2 as a capacitor, storing more or less charge at the memory node SN. Individual memory cells in the DRAM array can be accessed independently by specifying row and column addresses, and read, write, or refresh operations can be performed on the data stored within them.

[0208] And, such as Figure 24 As shown, the peripheral circuit structure 210 may include various circuit structures such as a row decoder, a sense amplifier, a column decoder, and a data input / output buffer. The row decoder is coupled to the first word line WWL and the second word line RWL. The column decoder is coupled to the first bit line WBL and the second bit line RBL.

[0209] In some embodiments, such as Figure 25 As shown in the illustration, an embodiment of this application illustrates a memory system 300. The memory system 300 includes a memory controller 310 and one or more semiconductor devices 200, as well as other integrated circuit structures for signal transmission. The memory controller 310 is configured to control the semiconductor devices 200.

[0210] For example, the memory controller 310 and one or more semiconductor devices 200 can be integrated and packaged in the same memory device. This facilitates the application of the memory system 300 in different types of end electronic products.

[0211] In some embodiments, such as Figure 26 As shown in the illustration, an electronic device 400 is presented in this application embodiment. For example, the electronic device 400 may include, but is not limited to, a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a semiconductor device 1000 therein.

[0212] In some examples, such as Figure 26 As shown, electronic device 400 may include host 410 and memory system 300. Host 410 may be a processor of electronic device (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)). Host 410 may be configured to send data to memory system 300 or receive data from memory system 300.

[0213] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Semiconductor substrate; A second transistor structure is disposed on one side of the semiconductor substrate; A first transistor structure is disposed on the side of the second transistor structure away from the semiconductor substrate, and is coupled to the second transistor structure through a first contact structure; The first word line structure is disposed within the layer structure of the second transistor structure and coupled to the first conductive layer within the first transistor structure. The first line structure is disposed on the side of the first transistor structure away from the second transistor structure and is coupled to the first semiconductor layer within the first transistor structure; The second word line structure is disposed within the layer structure of the second transistor structure and coupled to an electrode region of the second semiconductor layer of the second transistor structure. The second bit line structure is disposed within the layer structure of the second transistor structure and coupled to another electrode region of the second semiconductor layer. Wherein, the first contact structure is coupled to the first semiconductor layer and the second conductive layer of the second transistor structure at opposite ends along the stacking direction of the first transistor structure and the second transistor structure, respectively; the first semiconductor layer covers the side surface of the first contact structure away from the second transistor structure, and the second conductive layer covers the side surface of the first contact structure away from the first transistor structure.

2. The semiconductor structure according to claim 1, characterized in that, The first semiconductor layer is made of an oxide semiconductor material; The cross-sectional area of ​​the first contact structure along the stacking direction of the first transistor structure and the second transistor structure decreases along the direction from the first transistor structure to the second transistor structure.

3. The semiconductor structure according to claim 1, characterized in that, The second semiconductor layer is made of an oxide semiconductor material; The cross-sectional area of ​​the first contact structure along the stacking direction of the first transistor structure and the second transistor structure decreases along the direction from the second transistor structure to the first transistor structure.

4. The semiconductor structure according to claim 1, characterized in that, The material of the first semiconductor layer includes indium gallium zinc oxide; And / or, the material of the second semiconductor layer includes indium gallium zinc oxide.

5. The semiconductor structure according to claim 1, characterized in that, The first transistor structure further includes: a first adapter structure, one end of which is coupled to the first semiconductor layer and the other end of which is coupled to the first bit line structure; The first adapter structure and the first contact structure are respectively coupled to the opposite sides of the first semiconductor layer along the stacking direction perpendicular to the first transistor structure and the second transistor structure.

6. The semiconductor structure according to claim 5, characterized in that, The first conductive layer is disposed on the side of the first semiconductor layer away from the second transistor structure, and is spaced apart from the first transition structure along a stacking direction perpendicular to the first transistor structure and the second transistor structure.

7. The semiconductor structure according to claim 5, characterized in that, The first transistor structure further includes: A first dielectric layer is disposed on the side of the first semiconductor layer away from the second transistor structure; The first conductive layer is disposed on the side of the first dielectric layer away from the first semiconductor layer; A second dielectric layer is disposed on the side of the first conductive layer away from the first dielectric layer; The first semiconductor layer includes a first electrode region and a second electrode region spaced apart. The first electrode region is coupled to the second transistor structure through the first contact structure, and the second electrode region is coupled to the first bit line structure through the first transition structure.

8. The semiconductor structure according to claim 1, characterized in that, The second semiconductor layer is disposed on the side of the second conductive layer away from the first transistor structure.

9. The semiconductor structure according to claim 1, characterized in that, The second transistor structure includes: The second semiconductor layer includes a third electrode region and a fourth electrode region disposed at intervals. A third dielectric layer is disposed on one side of the second semiconductor layer; A second conductive layer is disposed on the side of the third dielectric layer away from the second semiconductor layer; the second conductive layer is coupled to the first transistor structure through a second contact structure. A fourth dielectric layer is disposed on the side of the second conductive layer away from the third dielectric layer; The third electrode region is coupled to the second word line structure; the fourth electrode region is coupled to the second bit line structure.

10. The semiconductor structure according to claim 1, characterized in that, The first transistor structure includes: Second dielectric layer; A first columnar conductive structure is disposed in the second dielectric layer; the first columnar conductive structure extends along the stacking direction of the first transistor structure and the second transistor structure, one end of which is coupled to the second transistor structure and the other end of which is coupled to the first word line structure; The first columnar conductive structure includes: The columnar first semiconductor layer includes a first electrode region and a second electrode region spaced apart at both ends of the columnar first semiconductor layer; the second electrode region is coupled to the second transistor structure through a first contact structure; the first electrode region is coupled to the first bit line structure. A first dielectric layer is disposed on one side of the columnar first semiconductor layer; The first conductive layer is disposed on the side of the first dielectric layer away from the columnar first semiconductor layer.

11. The semiconductor structure according to claim 1, characterized in that, The first transistor structure includes: Second dielectric layer; A first columnar conductive structure is disposed in the second dielectric layer; the first columnar conductive structure extends along the stacking direction of the first transistor structure and the second transistor structure, one end of which is coupled to the second transistor structure and the other end of which is coupled to the first word line structure; The first columnar conductive structure includes: A columnar first conductive layer is coupled to the first word line structure; A first dielectric layer surrounding the columnar first conductive layer; The first semiconductor layer surrounds the first dielectric layer; the first semiconductor layer includes a first electrode region and a second electrode region disposed at intervals along the stacking direction of the first transistor structure and the second transistor structure; the second electrode region is coupled to the second transistor structure through a first contact structure; the first electrode region is coupled to the first bit line structure.

12. The semiconductor structure according to claim 1, characterized in that, The second transistor structure includes: Fourth dielectric layer; A second columnar conductive structure is disposed in the fourth dielectric layer; the second columnar conductive structure extends along the stacking direction of the second transistor structure and the first transistor structure, one end is coupled to the first transistor structure, and the other end is coupled to the second word line structure or the second bit line structure; The second columnar conductive structure includes: The columnar second conductive layer is coupled at one end to the first semiconductor layer of the first transistor structure through the first contact structure. A third dielectric layer surrounding the columnar second conductive layer; The second semiconductor layer surrounds the third dielectric layer; the second semiconductor layer includes a third electrode region and a fourth electrode region spaced apart along the stacking direction of the second transistor structure and the first transistor structure; the third electrode region is coupled to the second word line structure; the fourth electrode region is coupled to the second bit line structure.

13. The semiconductor structure according to claim 1, characterized in that, The layer structure of the first transistor structure is the same as that of the second transistor structure.

14. The semiconductor structure according to claim 1, characterized in that, The first transistor structure includes a planar transistor structure or a vertical transistor structure; And / or, the second transistor structure includes a planar transistor structure or a vertical transistor structure.

15. A method for fabricating a semiconductor structure, characterized in that, include: Provide a semiconductor substrate; A second transistor structure is formed on one side of the semiconductor substrate; A first transistor structure is formed on the side of the second transistor structure away from the semiconductor substrate; the first transistor structure and the second transistor structure are coupled through a first contact structure; The first contact structure is coupled to the first semiconductor layer of the first transistor structure and the second conductive layer of the second transistor structure at opposite ends along the stacking direction of the first transistor structure and the second transistor structure, respectively; the first semiconductor layer covers the side surface of the first contact structure away from the second transistor structure, and the second conductive layer covers the side surface of the first contact structure away from the first transistor structure. Forming the first character line structure; The first word line structure is coupled to the first conductive layer of the first transistor structure; A first bit line structure is formed; the first bit line structure is coupled to the first electrode region of the first semiconductor layer of the first transistor structure. Forming a second character line structure; The second word line structure is coupled to the third electrode region of the second semiconductor layer of the second transistor structure; A second bit line structure is formed, and the second bit line structure is coupled to the fourth electrode region of the second semiconductor layer of the second transistor structure.

16. The preparation method according to claim 15, characterized in that, After forming the second transistor structure, a first semiconductor layer of the first transistor structure is formed; the material of the first semiconductor layer includes an oxide semiconductor material. Before forming the first semiconductor layer, the fabrication method includes forming the first contact structure; the cross-sectional area of ​​the first contact structure along the stacking direction of the first transistor structure and the second transistor structure decreases along the direction from the first transistor structure to the second transistor structure.

17. The preparation method according to claim 15, characterized in that, After the first transistor structure is formed, a second semiconductor layer is formed to form the second transistor structure; the material of the second semiconductor layer includes an oxide semiconductor material. Before forming the second transistor structure, the fabrication method includes forming the first contact structure; the cross-sectional area of ​​the first contact structure along the stacking direction of the first transistor structure and the second transistor structure decreases along the direction from the second transistor structure to the first transistor structure.

18. A semiconductor device, characterized in that, It includes at least one semiconductor structure as described in any one of claims 1 to 14, and a peripheral circuit structure coupled to the at least one semiconductor structure.

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