High-low voltage dual-zone asymmetric TVS chip and manufacturing method

Abstract

The application provides a high-low voltage dual-zone asymmetric TVS chip and a manufacturing method, and the core idea is to design a high-low voltage dual-zone asymmetric doping structure, to realize graded protection of high-low voltage surges by precisely regulating and controlling dual-zone impurity concentration and interface transition layer parameters, to optimize chip longitudinal electric field distribution, to break through the limitation of single voltage grade protection of traditional TVS chips, and to improve the withstand voltage capacity of the high voltage zone while guaranteeing the rapid response performance of the low voltage zone and the low leakage current effect under high temperature conditions.

Description

Technical Field

[0001] This invention relates to the field of asymmetric TVS chip process development technology, specifically to a high- and low-voltage dual-zone asymmetric TVS chip and its manufacturing method. Background Technology

[0002] A transient voltage suppressor (TVS) diode is an overvoltage protection device with bidirectional voltage regulation and bidirectional negative resistance characteristics, similar to a varistor. It is used in various AC and DC power supply circuits to suppress instantaneous overvoltages. When a surge voltage pulse occurs in the protected circuit, the bidirectional breakdown diode quickly breaks down through the Zener diode, changing from a high-resistance state to a low-resistance state, thus shunting and clamping the surge voltage, protecting the components in the circuit from damage by the instantaneous surge voltage pulse.

[0003] To meet the asymmetric voltage protection requirements prevalent in modern electronic systems (such as +20V / -5V drive of automotive SiC MOSFETs or +12V / -7V operation scenarios of RS-485 interfaces), and to overcome the drawbacks of traditional symmetric TVS devices or dual discrete device solutions, such as low integration, poor matching of protection characteristics and circuits, and limited performance and reliability, this invention proposes the process development of a high- and low-voltage dual-zone asymmetric TVS chip.

[0004] Patent application CN101180709A discloses an epitaxial stacked asymmetric TVS, employing a double epitaxial layer and P+ diffusion layer design to achieve a breakdown voltage difference between high and low voltage regions. However, this patent requires high precision in controlling the thickness of the epitaxial layer, increasing the process cost by 20%, and the high and low voltage regions are isolated by a single passivation layer, making them prone to leakage at high temperatures. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this invention is to provide a high- and low-voltage dual-zone asymmetric TVS chip and its manufacturing method.

[0006] The method for manufacturing a high- and low-voltage dual-zone asymmetric TVS chip according to the present invention includes:

[0007] Step 1: Provide a P-type silicon substrate, clean and oxidize its surface to form a first oxide layer; Step 2: Boron doping is performed on the first surface of the P-type silicon substrate to form a P+ region, and the first main expansion is then performed; Step 3: Phosphorus doping is performed on the second side of the P-type silicon substrate opposite to the first side to form a first N-type region, and a second main expansion is performed. The second main expansion is wet oxygen main expansion, and a second oxide layer is grown simultaneously during the process. Step 4: Phosphorus doping is performed on the first surface of the P-type silicon substrate to form a second N-type region, and a third main expansion is performed. The third main expansion is dry oxide main expansion, and a third oxide layer is grown simultaneously during the process. Step 5: Isolation trenches are formed on the substrate having the first N-type region and the second N-type region by photolithography and chemical etching to define independent chip cells; Step 6: Prepare a multilayer passivation structure containing a glass layer on the surface of the chip unit; Step 7: Photolithography and etching are performed on the multilayer passivated structure to form contact windows; Step 8: Fabricate metal electrodes on the contact window and the back of the chip.

[0008] Preferably, the step of boron doping on the first side of the P-type silicon substrate includes: applying a boron source by spin coating, and introducing nitrogen gas at a flow rate of 3 L / min to 10 L / min and oxygen gas at a flow rate of 0.5 L / min to 1 L / min at a temperature of 1000℃ to 1180℃ for 3 to 7 hours for pre-diffusion.

[0009] Preferably, the step of phosphorus doping on the second side of the P-type silicon substrate includes: using phosphorus oxychloride as the phosphorus source, introducing nitrogen gas at a flow rate of 1.5 L / min to 4 L / min and oxygen gas at a flow rate of 0.5 L / min to 1 L / min at a temperature of 1000℃ to 1180℃ for 3 to 7 hours for pre-diffusion; and testing the sheet resistance after pre-diffusion, and performing subsequent wet oxygen main diffusion when the resistance value is 600 mΩ to 750 mΩ.

[0010] Preferably, the wet oxygen master expansion step includes: placing the substrate in an environment of 1100℃~1200℃, introducing oxygen at a flow rate of 2L / min~6L / min for 8±1 hours to generate wet oxygen, and then performing master expansion at 1200℃~1250℃ with a nitrogen flow rate of 6L / min~10L / min and an oxygen flow rate of 3L / min~5L / min until the breakdown voltage corresponding to the second surface reaches a predetermined value and a second oxide layer with a thickness of 16000Å~24000Å is formed.

[0011] Preferably, the step of phosphorus doping on the first side of the P-type silicon substrate includes: using phosphorus oxychloride as the phosphorus source, introducing nitrogen gas at a flow rate of 1.5 L / min to 4 L / min and oxygen gas at a flow rate of 0.5 L / min to 1 L / min at a temperature of 1000℃ to 1180℃ for 3 to 7 hours for pre-diffusion; and testing the sheet resistance after pre-diffusion, and performing subsequent dry oxygen main diffusion when the resistance value is 600 mΩ to 750 mΩ.

[0012] Preferably, the dry oxygen primary expansion step includes: carrying out primary expansion at 1100℃~1280℃ with a nitrogen flow rate of 2L / min~3L / min and an oxygen flow rate of 3L / min until the breakdown voltage corresponding to the first surface reaches a predetermined value, and the third oxide layer with a thickness of 4000Å~6000Å is grown.

[0013] Preferably, the step of forming the isolation trench includes: after the trench pattern is photolithographically etched on both sides of the substrate, the exposed silicon area is etched using a mixed acid solution prepared in a mass ratio of nitric acid: hydrofluoric acid: glacial acetic acid = 5:4:4 for 0.5 to 10 minutes to form the isolation trench.

[0014] Preferably, the step of preparing the multilayer passivation structure comprising a glass layer includes: A fourth oxide layer with a thickness of 5000Å~8000Å is grown on the surface of the chip unit; A photoresist, consisting of a mixture of negative photoresist and glass powder with a particle size of 5μm~14μm in a mass ratio of 10:9.5, is coated onto the fourth oxide layer, and a pattern is formed by photolithography. At 570℃~830℃, nitrogen gas is first introduced to burn off the organic components in the photoresist, and then oxygen is introduced to vitrify it, forming the glass layer. A silicon dioxide film with a thickness of 500 Å to 2500 Å is deposited on the glass layer at a temperature of 360°C to 500°C to form the multilayer passivation structure.

[0015] Preferably, the steps for preparing the metal electrode include: forming a nickel layer with a thickness of 0.3 μm to 0.8 μm using a nickel plating process; performing an alloying treatment at 520°C to 560°C under a nitrogen atmosphere for 25 to 35 minutes; repeating the above nickel plating and alloying process at least once; and finally forming a gold layer with a thickness of 0.3 μm to 0.5 μm on the back side of the chip by chemical plating.

[0016] The high- and low-voltage dual-zone asymmetric TVS chip provided by the present invention is prepared by the manufacturing method of the high- and low-voltage dual-zone asymmetric TVS chip described above.

[0017] Compared with the prior art, the present invention has the following beneficial effects: (1) The present invention designs a dual-region asymmetric doping structure for high and low voltage. By precisely controlling the impurity concentration in the dual regions and the parameters of the interface transition layer, a single chip can achieve graded protection against high and low voltage surges. At the same time, the longitudinal electric field distribution of the chip is optimized, breaking through the limitations of single voltage level protection of traditional TVS chips. While improving the withstand voltage capability of the high voltage region, it ensures the fast response performance of the low voltage region and the low leakage current effect under high temperature conditions. (2) This invention adopts dual-region independent doping to solve the problems of electric field crosstalk and voltage leakage drift, and ensures accurate clamping in the positive and negative voltage domains; relying on differential junction depth optimization, it solves the pain points of slow response in the low voltage region and inaccurate clamping in the high voltage region, and achieves the effect of full voltage domain protection without dead angles; at the same time, this asymmetric TVS chip is protected by three layers of passivation layer, enabling the chip to operate in more extreme environments. Attached Figure Description

[0018] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the cross-section and planar structure of a high- and low-voltage dual-zone asymmetric TVS chip in step 1 state; Figure 2 This is a schematic diagram of the cross-section and planar structure of the high- and low-voltage dual-zone asymmetric TVS chip in step 16. Figure 3 This is a schematic diagram of the cross-section and planar structure of the high- and low-voltage dual-zone asymmetric TVS chip in step 18. Figure 4 This is a schematic diagram of the cross-section and planar structure of the high- and low-voltage dual-zone asymmetric TVS chip in step 22. Figure 5 This is a schematic diagram of the cross-section and planar structure of the high- and low-voltage dual-zone asymmetric TVS chip in step 27. Figure 6 This is a schematic diagram of the cross-section and planar structure of the high- and low-voltage dual-zone asymmetric TVS chip in step 47. Detailed Implementation

[0019] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0020] Example This invention provides a method for manufacturing a high- and low-voltage dual-zone asymmetric TVS chip, comprising the following steps: Step 1: Silicon wafer inspection and marking; A 5-inch P-type silicon substrate was used, with a thickness of 280±40 μm (300 μm in this example), and a resistivity range of 0.010 Ω. cm~0.60Ω cm (in this example, it is 0.050Ω) cm~0.051Ω cm), and a unique mark is engraved on the edge of any one side of the silicon surface (the side with the mark is called the front side).

[0021] like Figure 1 The diagram shows a high- and low-voltage dual-zone asymmetric TVS chip. The cross-sectional view (labeled area P) shows the longitudinal structural outline of the chip, reflecting its internal partitioning characteristics. The planar view shows the overall planar layout of the chip, intuitively reflecting the shape of step 1.

[0022] Step 2: Surface acid corrosion; Using equipment (mixed acid tank, hydrofluoric acid tank) and materials (mixed acid solution ratio of nitric acid: hydrofluoric acid: glacial acetic acid = 18:1:1, hydrofluoric acid ratio of hydrofluoric acid: pure water = 1:1), first immerse the substrate in room temperature mixed acid solution for 30±5s (30s in this embodiment) to remove the surface damage layer, and then immerse it in hydrofluoric acid solution for 3±1min (3min in this embodiment) to remove the surface silicon powder and oxide layer.

[0023] Step 3: RCA cleaning; Using the following equipment (RCA cleaning equipment) and materials (SC1 solution ratio: ammonium hydroxide: hydrogen peroxide: deionized water = 1:2:1, SC2 solution ratio: hydrochloric acid: hydrogen peroxide: deionized water = 1:2:1): First, immerse the substrate in SC1 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove organic contaminants and impurities from the substrate surface. Then, immerse the substrate in SC2 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove metal ions from the substrate surface.

[0024] Step 4: Wet oxygen oxidation; The equipment (high-temperature furnace, quartz tube) and materials used include oxygen, nitrogen and hydrochloric acid solution (the hydrochloric acid solution is a mixture of hydrochloric acid and water in a volume ratio of 1:5). The substrate was placed in a quartz tube constant temperature zone at 1100~1200℃ (1150℃ in this embodiment). The hydrochloric acid mixture was heated to 90℃~99℃ (99℃ in this embodiment) using a water bath. Then, the water bath was connected to the quartz tube with a gas pipe, and oxygen was introduced at a rate of 2L~6L / min (5L / min in this embodiment) to produce a wet oxygen oxide layer. The wet oxygen generation process took 8±1h (8h in this embodiment). Finally, nitrogen was introduced at a rate of 2L~6L / min (5L / min in this embodiment) to form a dense oxide layer of 16000Å-24000Å (21000±500Å in this embodiment).

[0025] Step 5: Apply adhesive to the front side; Using a photoresist coating device and a negative photoresist material, a photoresist with a thickness of 8±3um (8um in this embodiment) is coated on the front side of the substrate.

[0026] Step 6: Wet etching; The substrate back oxide layer is removed by immersing it in a 1:6 ratio of hydrofluoric acid to ammonium fluoride etching solution at 36-40°C (38°C in this example) for 3-7 minutes (5 minutes in this example).

[0027] Step 7: Remove the photoresist; The substrate was immersed in 98% sulfuric acid at 70-120°C (120°C in this example) for 45 minutes to remove the photoresist on the chip surface; then it was ultrasonically cleaned with deionized water for 30 minutes.

[0028] Step 8: RCA cleaning; Using the following equipment (RCA cleaning equipment) and materials (SC1 solution ratio: ammonium hydroxide: hydrogen peroxide: deionized water = 1:2:1; SC2 solution ratio: hydrochloric acid: hydrogen peroxide: deionized water = 1:2:1): First, immerse the substrate in SC1 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove organic contaminants and impurities from the substrate surface; then immerse the substrate in SC2 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove metal ions from the substrate surface.

[0029] Step 9: Boron pre-expansion treatment; Boron doping was performed on the back side of the substrate; the diffusion equipment consisted of a high-temperature furnace and a quartz tube, and the materials were oxygen, nitrogen, and a boron source (a layer of boron latex source was first spin-coated onto the back side of the substrate using a spin-coating method); the process conditions were: diffusion temperature 1000~1180℃ (1180℃ in this embodiment), time 3~7h (5h in this embodiment), nitrogen 3~10L / min (4L / min in this embodiment), and oxygen 0.5~1L / min (0.5L / min in this embodiment).

[0030] Step 10: Pre-expansion post-processing; Hydrofluoric acid solution is prepared by mixing hydrofluoric acid and water in a mass ratio of 1:1. The substrate after boron pre-diffusion treatment is cleaned with hydrofluoric acid for 8-12 minutes (10 minutes in this example) to remove surface diffusion source impurities and diffusion reaction byproducts.

[0031] Step 11: Pre-expansion post-inspection; The resistivity of the back side of the pre-expanded silicon wafer was tested.

[0032] When the resistivity of the tested P-type substrate is 0.010Ω cm~0.60Ω When the value reaches cm, proceed to the next step.

[0033] In this embodiment, the sheet resistance of the substrate after pre-expansion treatment is 0.040Ω. cm~0.041Ω cm.

[0034] Step 12: RCA cleaning; Equipment (RCA cleaning equipment) and materials (SC1 solution ratio: ammonium hydroxide: hydrogen peroxide: deionized water = 1:2:1; SC2 solution ratio: hydrochloric acid: hydrogen peroxide: deionized water = 1:2:1): First, immerse the substrate in SC1 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove organic contaminants and impurities from the substrate surface. Then, immerse the substrate in SC2 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove metal ions from the substrate surface.

[0035] Step 13: Wet oxygen oxidation; The equipment (high-temperature furnace, quartz tube) and materials used include oxygen, nitrogen and hydrochloric acid solution (the hydrochloric acid solution is a mixture of hydrochloric acid and water in a volume ratio of 1:5). The substrate was placed in a quartz tube constant temperature zone at 1100~1200℃ (1150℃ in this embodiment). The hydrochloric acid mixture was heated to 90℃~99℃ (99℃ in this embodiment) using a water bath. Then, the water bath was connected to the quartz tube with a gas pipe, and oxygen was introduced at a rate of 2L~6L / min (5L / min in this embodiment) to produce a wet oxygen oxide layer. The wet oxygen generation process took 8±1h (8h in this embodiment). Finally, nitrogen was introduced at a rate of 2L~6L / min (5L / min in this embodiment) to form a dense oxide layer of 16000Å-24000Å (21000±500Å in this embodiment).

[0036] Step 14: Apply adhesive to the back; Using a photoresist coating device and negative photoresist material, a photoresist with a thickness of 8±3um (8um in this embodiment) is coated on the back side of the substrate.

[0037] Step 15: Wet etching; The substrate's front oxide layer is removed by immersing it in a 1:6 ratio of hydrofluoric acid to ammonium fluoride etching solution at 36-40°C (38°C in this example) for 3-7 minutes (5 minutes in this example).

[0038] Step 16: Remove the photoresist; The substrate was immersed in 98% sulfuric acid at 70-120°C (120°C in this example) for 45 minutes to remove the photoresist on the chip surface; then it was ultrasonically cleaned with deionized water for 30 minutes.

[0039] like Figure 2 The diagram shows the cross-sectional and planar structures of the high- and low-voltage dual-zone asymmetric TVS chip in state 16. The cross-sectional view shows the vertical layered structure of the chip substrate, from top to bottom: oxide layer, P-type silicon substrate (P-region), and highly doped P+ layer (back-compensated boron region) formed by the boron enrichment process. The planar view shows the two-dimensional outline of the chip substrate, intuitively reflecting its overall planar layout, which corresponds to the cross-sectional view.

[0040] Step 17: RCA cleaning; Equipment (RCA cleaning equipment) and materials (SC1 solution ratio: ammonium hydroxide: hydrogen peroxide: deionized water = 1:2:1; SC2 solution ratio: hydrochloric acid: hydrogen peroxide: deionized water = 1:2:1): First, immerse the substrate in SC1 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove organic contaminants and impurities from the substrate surface. Then, immerse the substrate in SC2 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove metal ions from the substrate surface.

[0041] Step 18: Phosphorus pre-expansion treatment; The front side of the substrate is doped with phosphorus; the diffusion equipment is a high-temperature furnace and a quartz tube, and the materials are oxygen, nitrogen and phosphorus oxychloride; the process conditions are: diffusion temperature 1000~1180℃ (1150℃ in this example), time 3~7h (5h in this example), nitrogen 1.5~4L / min (4L / min in this example), oxygen 0.5~1L / min (0.7L / min in this example).

[0042] like Figure 3 The diagram shows the cross-sectional and planar structures of the high-low voltage dual-zone asymmetric TVS chip in step 18. The cross-sectional view shows the vertical layered structure of the substrate, from top to bottom: an N-type layer formed by positive phosphorus doping, a P-type silicon substrate layer (P-region), and a highly doped P+ layer (back-boron-rich region) formed by the back-boron-rich process. This reflects the vertical doping design of the substrate at this stage, which is the basis for the subsequent high-low voltage dual-zone formation. The planar view shows the two-dimensional outline of the chip substrate at this stage, which intuitively reflects its overall planar layout and corresponds to the cross-sectional view.

[0043] Step 19: Pre-expansion post-processing; Hydrofluoric acid solution is prepared by mixing hydrofluoric acid and water in a mass ratio of 1:1. The substrate after phosphorus pre-diffusion treatment is cleaned with hydrofluoric acid for 8-12 minutes (10 minutes in this example) to remove surface diffusion source impurities and diffusion reaction byproducts.

[0044] Step 20: Post-pre-expansion inspection; Test the sheet resistance of the pre-expanded silicon wafer.

[0045] When the tested P-type substrate resistance is 600mΩ~750mΩ, proceed to the next step.

[0046] In this embodiment, the sheet resistance of the substrate after pre-expansion treatment is 650±30mΩ.

[0047] Step 21: RCA cleaning; Equipment (RCA cleaning equipment) and materials (SC1 solution ratio: ammonium hydroxide: hydrogen peroxide: deionized water = 1:2:1; SC2 solution ratio: hydrochloric acid: hydrogen peroxide: deionized water = 1:2:1): First, immerse the substrate in SC1 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove organic contaminants and impurities from the substrate surface. Then, immerse the substrate in SC2 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove metal ions from the substrate surface.

[0048] Step 22: Wet oxygen main expansion; The RCA-treated substrate surface is subjected to primary diffusion treatment using diffusion equipment and materials; The diffusion equipment consists of a high-temperature furnace and a silicon carbide tube, and the materials are oxygen, nitrogen, and hydrochloric acid solution (the hydrochloric acid solution is a mixture of hydrochloric acid and water in a volume ratio of 1:5). Process conditions: First, the substrate is placed in a silicon carbide tube constant temperature zone at 1100℃~1200℃ (1150℃ in this embodiment). The hydrochloric acid mixture is heated to 90℃~99℃ (99℃ in this embodiment) using a water bath. Then, the water bath is connected to a quartz tube via a gas pipe, and oxygen is introduced at a rate of 2L / min~6L / min (5L / min in this embodiment) to produce a wet oxide layer. The wet oxide generation process takes 8±1h (7h in this embodiment). Finally, in a furnace tube at 1200℃~1250℃ (1250℃ in this embodiment), nitrogen is introduced at a rate of 6L / min~10L / min, and oxygen at a rate of 3~5L / min. The substrate is expanded to the corresponding cutoff voltage on the front side (22.8±0.5V in this embodiment). Simultaneously, the density of the wet oxide layer on the silicon surface of the substrate is increased at high temperature to form a dense oxide layer of 16000Å—24000Å (20000±500Å in this embodiment).

[0049] like Figure 4The diagram shows the cross-sectional and planar structures of the high- and low-voltage dual-zone asymmetric TVS chip in step 22. The cross-sectional view shows the vertical layered structure of the substrate, from top to bottom: a top wet oxide layer, an N-type layer (containing N-region) formed by phosphorus main expansion, a P-type silicon substrate layer (P-region), a highly doped P+ layer (P+ region) formed by boron main expansion, and a bottom wet oxide layer. This clearly demonstrates the vertical doping and insulation protection design of the substrate after the main expansion process, which is the key structural basis for the subsequent high- and low-voltage dual-zone formation. The planar view shows the two-dimensional outline of the chip substrate at this stage, intuitively reflecting its overall planar layout, which corresponds to the cross-sectional view.

[0050] Step 23: Apply adhesive to the front side; Using a photoresist coating device and a negative photoresist material, a photoresist with a thickness of 8±3um (8um in this embodiment) is coated on the front side of the substrate.

[0051] Step 24: Wet etching; The substrate back oxide layer is removed by immersing it in a 1:6 ratio of hydrofluoric acid to ammonium fluoride etching solution at 36-40°C (38°C in this example) for 3-7 minutes (5 minutes in this example).

[0052] Step 25: Remove the photoresist; The substrate was immersed in 98% sulfuric acid at 70-120°C (120°C in this example) for 45 minutes to remove the photoresist on the chip surface; then it was ultrasonically cleaned with deionized water for 30 minutes.

[0053] Step 26: RCA cleaning; Equipment (RCA cleaning equipment) and materials (SC1 solution ratio: ammonium hydroxide: hydrogen peroxide: deionized water = 1:2:1; SC2 solution ratio: hydrochloric acid: hydrogen peroxide: deionized water = 1:2:1): First, immerse the substrate in SC1 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove organic contaminants and impurities from the substrate surface. Then, immerse the substrate in SC2 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove metal ions from the substrate surface.

[0054] Step 27: Phosphorus pre-expansion treatment; The back side of the substrate is doped with phosphorus; the diffusion equipment is a high-temperature furnace and a quartz tube, and the materials are oxygen, nitrogen and phosphorus oxychloride; The process conditions are as follows: diffusion temperature 1000~1180℃ (1150℃ in this example), time 3~7h (5h in this example), nitrogen 1.5~4L / min (4L / min in this example), oxygen 0.5~1L / min (0.7L / min in this example).

[0055] like Figure 5 The diagram shows the cross-sectional and planar structures of the high- and low-voltage dual-zone asymmetric TVS chip in step 27. The cross-sectional view shows the vertical layered structure of the substrate, from top to bottom: a top wet oxide layer, an N-type phosphorus region formed by phosphorus doping, a P-type silicon substrate layer, a P-type boron region formed by boron doping, and an N-type back layer formed by back phosphorus doping. It clearly shows the vertical doping and forming structure of the high- and low-voltage dual zones (phosphorus region and boron region), which is a key process node to achieve asymmetric breakdown characteristics. The planar view shows the two-dimensional outline of the chip substrate at this stage, which intuitively reflects its overall planar layout and corresponds to the cross-sectional view.

[0056] Step 28: Pre-expansion post-processing; Hydrofluoric acid solution is prepared by mixing hydrofluoric acid and water in a mass ratio of 1:1. The substrate after phosphorus pre-diffusion treatment is cleaned with hydrofluoric acid for 8-12 minutes (10 minutes in this example) to remove surface diffusion source impurities and diffusion reaction byproducts.

[0057] Step 29: Post-pre-expansion inspection; Test the sheet resistance of the pre-expanded silicon wafer.

[0058] When the tested P-type substrate resistance is 600mΩ~750mΩ, proceed to the next step.

[0059] In this embodiment, the sheet resistance of the substrate after pre-expansion treatment is 650±30mΩ.

[0060] Step 30: RCA cleaning; Equipment (RCA cleaning equipment) and materials (SC1 solution ratio: ammonium hydroxide: hydrogen peroxide: deionized water = 1:2:1; SC2 solution ratio: hydrochloric acid: hydrogen peroxide: deionized water = 1:2:1): First, immerse the substrate in SC1 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove organic contaminants and impurities from the substrate surface. Then, immerse the substrate in SC2 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove metal ions from the substrate surface.

[0061] Step 31: Dry oxygen main expansion; The RCA-treated substrate surface is subjected to primary diffusion treatment using diffusion equipment and materials; The diffusion equipment consists of a high-temperature furnace and silicon carbide tubes, and the materials are oxygen and nitrogen. Process conditions: In a furnace tube at 1100~1280℃ (1150℃ in this embodiment), nitrogen gas is supplied at a rate of 2~3L / min and oxygen gas at a rate of 3L / min. The main expansion is carried out to the corresponding cutoff voltage (7.15±0.1V in this embodiment), and a dense dry oxide layer of 4000Å-6000Å is grown on the silicon substrate surface.

[0062] Step 32: One photolithography step; Trench channels were photolithographically formed on both sides of the substrate after dry oxygen main expansion treatment, and the oxide layer on the trench channels was removed. Process parameters: photoresist thickness 8±3um, exposure light intensity 12mw~20mw, development time 9min, rinsing time 6min, ammonium fluoride etching solution (reagent grade in this example) temperature 40±2℃, etching time 6min; The equipment involved includes a photoresist coater, a double-sided exposure machine, a developing and rinsing machine, and an oxide etching machine. The materials involved include photoresist, developing solution, rinsing solution, and ammonium fluoride etching solution.

[0063] Step 33: The chip is cut out through the corrosion trench; Prepare the second mixed acid solution according to the mass ratio of nitric acid: hydrofluoric acid: glacial acetic acid = 5:4:4; The substrate after the first photolithography step is immersed in the second mixed acid solution for 0.5~10 min (265 s in this embodiment) to etch the silicon surface without photoresist protection, thereby creating trenches and forming a chip prototype.

[0064] Step 34: Remove the photoresist; First, immerse the chip after the edge removal step in sulfuric acid (98% concentration) at 70~120℃ (120℃ in this example) for 45 minutes to remove the photoresist on the chip surface; then immerse it in hydrogen peroxide for 0.8~1.2 minutes (1 minute in this example); then ultrasonically clean it with deionized water for 30 minutes; finally immerse it in ammonium fluoride etching solution (reagent grade in this example) for 20 seconds.

[0065] Step 35: Acidification trench; Using equipment (deoxidation tank, mixed acid tank) and materials (mixed acid tank ratio of nitric acid: hydrofluoric acid: glacial acetic acid = 18:1:1, deoxidation tank uses hydrofluoric acid and water = 1:1), the surface damage layer is removed by soaking in mixed acid at room temperature for 30s-1min (45s in this example); then the chip is soaked in hydrofluoric acid solution at room temperature for 6min to remove the surface oxide layer and silicon powder.

[0066] Step 36: RCA cleaning; Equipment (RCA cleaning equipment) and materials (SC1 solution ratio: ammonium hydroxide: hydrogen peroxide: deionized water = 1:2:1; SC2 solution ratio: hydrochloric acid: hydrogen peroxide: deionized water = 1:2:1): First, immerse the substrate in SC1 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove organic contaminants and impurities from the substrate surface. Then, immerse the substrate in SC2 solution at 55±5℃ (55℃ in this embodiment) for 10±1 min (10 min in this embodiment) to remove metal ions from the substrate surface.

[0067] Step 37: Oxidation; The chip that has undergone the RCA cleaning step is then subjected to oxidation treatment. The equipment involved includes a high-temperature furnace and a quartz tube, and the materials involved include oxygen, nitrogen, and hydrochloric acid solution (the hydrochloric acid solution is a mixture of hydrochloric acid and water in a volume ratio of 1:5). The chip is placed in a quartz tube constant temperature zone of 600~1200℃ (1150℃ in this embodiment). The hydrochloric acid mixture is heated to 90℃~99℃ using a water bath. Then, the water bath is connected to the quartz tube with a gas pipe, and oxygen is introduced at a rate of 2L~6L / min to produce a wet oxygen oxide layer. Finally, nitrogen is introduced at a rate of 2L~6L / min to form a dense oxide layer of 5000Å~8000Å.

[0068] Step 38: Secondary photolithography; The photoresist was prepared according to the mass ratio of negative photoresist to glass powder = 10:9.5. The negative photoresist used was RFJ-210-450 photoresist, and the glass powder had a particle size of 5~14μm. The two materials were stirred for 24 hours to mix evenly before use. Using photoresist, scribe lines, bottom glass edge area, and mesa glass edge area are photolithographically formed on the chip after step S14. The photolithography equipment involved includes a coating machine, a single-sided exposure machine, and a spray developing and rinsing machine. The materials involved include photoresist, developer, and rinsing solution. The process conditions are: photoresist thickness 12±5μm (14μm in this embodiment), exposure light intensity 12~20mW (12mW in this embodiment), spray developing time 30±5s, and spray rinsing time 15±5s.

[0069] Step 39: Firing; After the second photolithography step, the chip is first burned off with nitrogen gas at 10L / min for 2min at 570~830℃ (820℃ in this embodiment), and then glass passivation is performed with oxygen gas at 3~7L / min (5L / min in this embodiment) for 90min to form a uniform and dense glass layer.

[0070] Step 40: Low-temperature oxidation treatment; The chip after the firing process is oxidized at 360~500℃ (430℃ in this embodiment) to form a silicon dioxide film (LTO) with a thickness of 500~2500 Å (2000 Å in this embodiment) to resist tin from flowing into the glass edge area and external physical collisions.

[0071] Step 41: Three-stage photolithography; After the low-temperature oxidation process, lead hole areas are photolithographically etched on both the front and back surfaces of the chip. Process parameters: photoresist thickness 12±3μm (12 in this example), exposure light intensity 12~20mW (15 in this example), development time 9min, rinsing time 6min; The equipment involved includes a photoresist coater, a single-sided exposure machine, a developing and rinsing machine, and an oxide etching machine. The materials involved include photoresist, developing solution, and rinsing solution.

[0072] Step 42: Wet etching; Use ammonium fluoride etching solution (reagent grade) at 38~42℃ (40℃ in this example) to soak for 5~7 minutes (7 minutes in this example) to remove the unwanted oxide layer on the chip mesa.

[0073] Step 43: Remove the photoresist; First, the chip after wet etching is immersed in sulfuric acid (98% concentration) at 70~120℃ (120℃ in this example) for 45 minutes to remove the photoresist on the chip surface; then it is ultrasonically cleaned with deionized water for 30 minutes.

[0074] Step 44: Metallization; After the photoresist removal process, the chip is subjected to nickel plating at a temperature of 87~97℃ (92℃ in this embodiment) and a plating thickness of 0.3~0.8μm (0.4μm in this embodiment).

[0075] Step 45: Alloying; The chip after the metallization step is placed in an atmospheric pressure furnace at a process temperature of 520~560℃ (540℃ in this example) for 25~35min (30min in this example) with nitrogen gas at a flow rate of 20~30L / min (25L / min in this example) to ensure good ohmic contact between silicon and metal.

[0076] Step 46: Repeat metallization and alloying; Repeat the metallization and alloying steps once, and then repeat the metallization step once more.

[0077] Step 47: Back Gold; After repeated metallization and alloying steps, the chip is placed in a gold chloride solution for back gold treatment at a process temperature of 90~100℃ (95℃ in this example) to obtain a gold layer with a thickness of 0.3~0.5μm (0.4μm in this example).

[0078] like Figure 6 The diagram shows the cross-sectional and planar structures of the high- and low-voltage dual-zone asymmetric TVS chip in step 47. The cross-sectional view shows the chip's vertical layered functional structure, from the outside to the inside: glass layer, passivation layer, LTO layer (insulating layer), and inside: N-type layer, P-type silicon substrate, P+ layer. The trench isolation structure at the edge is also visible, clearly demonstrating the chip's vertical insulation protection and the bonding relationship between the electrode layer and the substrate. The planar view shows the chip's two-dimensional planar layout, from the inside to the outside: nickel-gold electrode area, LTO insulating layer, glass layer protective ring, and the outermost trench isolation structure. This visually reflects the functional partitioning and insulation protection design on the chip plane, corresponding to the cross-sectional view and fully presenting the final three-dimensional structural form of the chip.

[0079] Step 48: Test the cut; The chip performance is inspected, the chips are cut and divided, defective products are picked out, and then they are packaged and shipped.

[0080] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0081] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A method for manufacturing a high- and low-voltage dual-zone asymmetric TVS chip, characterized in that, include: Step 1: Provide a P-type silicon substrate and oxidize its surface to form a first oxide layer; Step 2: Boron doping is performed on the first surface of the P-type silicon substrate to form a P+ region, and the first main expansion is then performed; Step 3: Phosphorus doping is performed on the second side of the P-type silicon substrate opposite to the first side to form a first N-type region, and a second main expansion is performed. The second main expansion is wet oxygen main expansion, and a second oxide layer is grown simultaneously during the process. Step 4: Phosphorus doping is performed on the first surface of the P-type silicon substrate to form a second N-type region, and a third main expansion is performed. The third main expansion is dry oxide main expansion, and a third oxide layer is grown simultaneously during the process. Step 5: Isolation trenches are formed on the substrate having the first N-type region and the second N-type region by photolithography and chemical etching to define independent chip cells; Step 6: Prepare a multilayer passivation structure containing a glass layer on the surface of the chip unit; Step 7: Photolithography and etching are performed on the multilayer passivated structure to form contact windows; Step 8: Fabricate metal electrodes on the contact window and the back of the chip.

2. The manufacturing method of the high- and low-voltage dual-zone asymmetric TVS chip according to claim 1, characterized in that, The step of boron doping on the first side of the P-type silicon substrate includes: applying a boron source by spin coating, and introducing nitrogen gas at a flow rate of 3 L / min to 10 L / min and oxygen gas at a flow rate of 0.5 L / min to 1 L / min at a temperature of 1000℃ to 1180℃ for 3 to 7 hours for pre-diffusion.

3. The manufacturing method of the high- and low-voltage dual-zone asymmetric TVS chip according to claim 2, characterized in that, The step of phosphorus doping on the second side of the P-type silicon substrate includes: using phosphorus oxychloride as the phosphorus source, introducing nitrogen gas at a flow rate of 1.5 L / min to 4 L / min and oxygen gas at a flow rate of 0.5 L / min to 1 L / min at a temperature of 1000℃ to 1180℃ for 3 to 7 hours for pre-diffusion; and testing the sheet resistance after pre-diffusion. When the resistance value is 600 mΩ to 750 mΩ, the subsequent wet oxygen main diffusion is performed.

4. The manufacturing method of the high- and low-voltage dual-zone asymmetric TVS chip according to claim 3, characterized in that, The wet oxygen master expansion step includes: placing the substrate in an environment of 1100℃~1200℃, introducing oxygen at a flow rate of 2L / min~6L / min for 8±1 hours to generate wet oxygen, and then carrying out master expansion at 1200℃~1250℃ with a nitrogen flow rate of 6L / min~10L / min and an oxygen flow rate of 3L / min~5L / min until the breakdown voltage corresponding to the second surface reaches a predetermined value and a second oxide layer with a thickness of 16000Å~24000Å is formed.

5. The method for manufacturing a high- and low-voltage dual-zone asymmetric TVS chip according to claim 4, characterized in that, The step of phosphorus doping on the first side of the P-type silicon substrate includes: using phosphorus oxychloride as the phosphorus source, introducing nitrogen gas at a flow rate of 1.5 L / min to 4 L / min and oxygen gas at a flow rate of 0.5 L / min to 1 L / min at a temperature of 1000℃ to 1180℃ for 3 to 7 hours for pre-diffusion; and testing the sheet resistance after pre-diffusion. When the resistance value is 600 mΩ to 750 mΩ, the subsequent dry oxygen main diffusion is performed.

6. The method for manufacturing a high- and low-voltage dual-zone asymmetric TVS chip according to claim 5, characterized in that, The dry oxygen primary expansion step includes: at 1100℃~1280℃, primary expansion is carried out at a nitrogen flow rate of 2L / min~3L / min and an oxygen flow rate of 3L / min until the breakdown voltage corresponding to the first surface reaches a predetermined value and the third oxide layer with a thickness of 4000Å~6000Å is grown.

7. The method for manufacturing a high- and low-voltage dual-zone asymmetric TVS chip according to claim 1, characterized in that, The step of forming the isolation trench includes: after the trench pattern is photolithographically etched on both sides of the substrate, the exposed silicon area is etched with a mixed acid solution prepared in a mass ratio of nitric acid: hydrofluoric acid: glacial acetic acid = 5:4:4 for 0.5 to 10 minutes to form the isolation trench.

8. The method for manufacturing a high- and low-voltage dual-zone asymmetric TVS chip according to claim 1, characterized in that, The step of preparing the multilayer passivation structure comprising a glass layer includes: A fourth oxide layer with a thickness of 5000Å~8000Å is grown on the surface of the chip unit; A photoresist, consisting of a mixture of negative photoresist and glass powder with a particle size of 5μm~14μm in a mass ratio of 10:9.5, is coated onto the fourth oxide layer, and a pattern is formed by photolithography. At 570℃~830℃, nitrogen gas is first introduced to burn off the organic components in the photoresist, and then oxygen is introduced to vitrify it, forming the glass layer. A silicon dioxide film with a thickness of 500 Å to 2500 Å is deposited on the glass layer at a temperature of 360°C to 500°C to form the multilayer passivation structure.

9. The method for manufacturing a high- and low-voltage dual-zone asymmetric TVS chip according to claim 1, characterized in that, The steps for preparing the metal electrode include: forming a nickel layer with a thickness of 0.3 μm to 0.8 μm using a nickel plating process; performing an alloying treatment at 520°C to 560°C under a nitrogen atmosphere for 25 to 35 minutes; repeating the above nickel plating and alloying process at least once; and finally forming a gold layer with a thickness of 0.3 μm to 0.5 μm on the back of the chip by chemical plating.

10. A high- and low-voltage dual-zone asymmetric TVS chip, characterized in that, It is prepared using the manufacturing method of the high- and low-voltage dual-zone asymmetric TVS chip according to any one of claims 1 to 9.

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