Package structure and method of manufacturing the same

Abstract

A package structure can be formed by providing a composite package including at least one semiconductor die and a die frame; attaching the composite package to a package substrate to form a bonded assembly; providing a lid structure including a floor portion, a ceiling portion, a sidewall frame portion laterally surrounding a cavity between the floor portion and the ceiling portion, and a solid block portion extending vertically between the floor portion and the ceiling portion; and attaching the lid structure to the bonded assembly such that a thermal interface material (TIM) layer is interposed between the at least one semiconductor die and the floor portion. The solid block portion does not overlap any area of the at least one semiconductor die in a plan view along a vertical direction.

Description

Technical Field

[0001] This invention relates to a packaging structure and its manufacturing method. Background Technology

[0002] Semiconductor devices generate heat during operation, requiring efficient heat dissipation to ensure performance and reliability. A thermal interface material (TIM) layer needs to be appropriately applied between the semiconductor die and the cover structure to ensure that the heat generated by the semiconductor die is effectively transferred to the cover structure, allowing the cover structure to function as a heat sink. X-ray inspection is typically used to determine whether the TIM layer has been properly applied and covers the necessary areas without gaps or defects. Summary of the Invention

[0003] This invention provides a method for manufacturing a package structure, comprising: providing a composite package including at least one semiconductor die and a die frame; attaching the composite package to a package substrate to form a bonding assembly; providing a cover structure including a bottom plate portion, a top plate portion, a sidewall frame portion, and a solid cube portion, wherein the top plate portion is perpendicularly spaced from the bottom plate portion, the sidewall frame portion laterally surrounds a cavity located between the bottom plate portion and the top plate portion, and the solid cube portion is located within the sidewall frame portion and extends perpendicularly from a first horizontal plane including the bottom surface of the bottom plate portion to a second horizontal plane including the top surface of the top plate portion, and is located in a corner region of the cover structure; and attaching the cover structure to the bonding assembly such that a thermal interface material (TIM) layer is inserted between at least one semiconductor die and the bottom plate portion, wherein the solid cube portion is completely outside the region of at least one semiconductor die in a plan view along the vertical direction.

[0004] This invention provides a method for manufacturing a package structure, comprising: providing a composite package including at least one semiconductor die and a die frame; attaching the composite package to a package substrate to form a bonding assembly; providing a cover structure including a bottom plate portion, a top plate portion, a sidewall frame portion, and a solid cube portion, wherein the bottom surface of the bottom plate portion is located in a first horizontal plane, the top plate portion is perpendicularly spaced from the bottom plate portion and its top surface is located in a second horizontal plane, the sidewall frame portion laterally surrounds a cavity located between the bottom plate portion and the top plate portion, and the solid cube portion is located within the sidewall frame portion and extends vertically from the first horizontal plane to the second horizontal plane; and forming the package structure by attaching the cover structure to the bonding assembly such that a thermal interface material (TIM) layer is inserted between at least one semiconductor die and the bottom plate portion, and the solid cube portion is completely located outside the region of at least one semiconductor die in a plan view along the vertical direction.

[0005] This invention provides a packaging structure including: a bonding assembly comprising a composite package and a packaging substrate, wherein the composite package includes at least one semiconductor die and a die frame; and a cover structure attached to the bonding assembly, wherein the cover structure includes a bottom plate portion, a top plate portion, a sidewall frame portion, and a solid cube portion, the top plate portion being vertically spaced from the bottom plate portion, the sidewall frame portion laterally surrounding a cavity located between the bottom plate portion and the top plate portion, the solid cube portion being located within the sidewall frame portion and extending vertically from a first horizontal plane including the bottom surface of the bottom plate portion to a second horizontal plane including the top surface of the top plate portion and located in a corner region of the cover structure, wherein the solid cube portion is completely outside the region of at least one semiconductor die in a plan view along the vertical direction. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a vertical cross-sectional view of an exemplary structure after an interposer through-via (TIV) structure has been formed on a first carrier wafer according to an embodiment of this disclosure.

[0008] Figure 2A This is a vertical cross-sectional view of an exemplary structure after a local silicon interconnect (LSI) bridging element has been attached to a first carrier wafer according to an embodiment of this disclosure. Figure 2B yes Figure 2A A top view of an exemplary structure. Figure 2C yes Figure 2A and Figure 2B An enhanced vertical cross-sectional view of the LSI bridge in an exemplary structure.

[0009] Figure 3 This is a vertical cross-sectional view of an exemplary structure after the formation of the intermediate layer molding compound material layer according to the disclosed embodiment.

[0010] Figure 4 This is a vertical cross-sectional view of an exemplary structure formed after the intermediate hierarchical molding compound matrix of this disclosed embodiment is formed.

[0011] Figure 5 This is a vertical cross-sectional view of an exemplary structure after the first wiring structure of this disclosed embodiment is formed.

[0012] Figure 6A This is a vertical cross-sectional view of an exemplary structure after which a semiconductor die is attached to a first rewiring structure according to an embodiment of the present disclosure. Figure 6B yes Figure 6AA top view of a unit region of an exemplary structure. Vertical plane A-A' is... Figure 6A The cut surface of the vertical sectional view.

[0013] Figure 7 This is a vertical cross-sectional view of an exemplary structure after the bottom filling material portion of the die side of this disclosed embodiment has been formed.

[0014] Figure 8 This is a vertical cross-sectional view of an exemplary structure formed after the die-level molding compound matrix of this disclosed embodiment is formed.

[0015] Figure 9 This is a vertical cross-sectional view of an exemplary structure after the second carrier wafer is attached to the reconstructed wafer and the first carrier wafer is deattached, according to an embodiment of the present disclosure.

[0016] Figure 10 This is a vertical cross-sectional view of an exemplary structure after the second wiring structure of this disclosed embodiment is formed.

[0017] Figure 11A This is a vertical cross-sectional view of a composite package according to an embodiment of the present disclosure. Figure 11B yes Figure 11A A top view of the composite package. Vertical plane A-A' is a vertical cross-section. Figure 11A The cross-section.

[0018] Figure 12 This is a vertical cross-sectional view of a bonding assembly including a composite package and a package substrate according to an embodiment of the present disclosure.

[0019] Figure 13A This is a vertical cross-sectional view of an encapsulation structure formed by attaching a cover structure to a bonding assembly according to an embodiment of this disclosure. Figure 13B It is along Figure 13A A horizontal cross-sectional view of the package structure in horizontal plane B-B', where the components of the composite package are shown in dashed lines. Figure 13B The vertical plane A-A' in the diagram is a vertical section. Figure 13A The cross-section. Figure 13C It is along Figure 13A A horizontal cross-sectional view of the packaging structure in the horizontal plane C-C'. Figure 13B The vertical plane A-A' in the diagram is a vertical section. Figure 13A The cross-section. Figure 13D It is along Figure 13B and Figure 13C A vertical cross-sectional view of the packaging structure in the vertical plane D-D'. Figure 13E It is along Figure 13B and Figure 13C A vertical cross-sectional view of the packaging structure in the vertical plane E-E'.

[0020] Figure 14A This is a vertical cross-sectional view of a first alternative configuration of the packaging structure according to an embodiment of this disclosure. Figure 14B It is along Figure 14A A horizontal cross-sectional view of the first alternative configuration of the package structure in horizontal plane B-B', wherein the components of the composite package are shown in dashed lines. Figure 14B The vertical plane A-A' in the diagram is the vertical section view. Figure 14A The cross-section.

[0021] Figure 15A This is a vertical cross-sectional view of a second alternative configuration of the packaging structure according to an embodiment of this disclosure. Figure 15B It is along Figure 15A A horizontal cross-sectional view of the second alternative configuration of the package structure in horizontal plane B-B', wherein the components of the composite package are shown in dashed lines. Figure 15B The vertical plane A-A' in the diagram is a vertical section. Figure 15A The cross-section.

[0022] Figure 16A This is a vertical cross-sectional view of a third alternative configuration of the packaging structure according to an embodiment of this disclosure. Figure 16B It is along Figure 16A A horizontal cross-sectional view of the third alternative configuration of the package structure in horizontal plane B-B', wherein the components of the composite package are shown in dashed lines. Figure 16B The vertical plane A-A' in the diagram is a vertical section. Figure 16A The cross-section.

[0023] Figure 17A This is a vertical cross-sectional view of a fourth alternative configuration of the packaging structure according to an embodiment of this disclosure. Figure 17B It is along Figure 17A A horizontal cross-sectional view of the fourth alternative configuration of the package structure in horizontal plane B-B', wherein the components of the composite package are shown in dashed lines. Figure 17B The vertical plane A-A' in the diagram is a vertical section. Figure 17A The cross-section.

[0024] Figure 18A This is a vertical cross-sectional view of a fifth alternative configuration of the packaging structure according to an embodiment of this disclosure. Figure 18B It is along Figure 18A A horizontal cross-sectional view of the fifth alternative configuration of the package structure in horizontal plane B-B', wherein the components of the composite package are shown in dashed lines. Figure 18B The vertical plane A-A' in the diagram is a vertical section. Figure 18A The cross-section.

[0025] Figure 19A This is a vertical cross-sectional view of a sixth alternative configuration of the packaging structure according to an embodiment of this disclosure. Figure 19B It is along Figure 19AA horizontal cross-sectional view of the sixth alternative configuration of the package structure in horizontal plane B-B', wherein the components of the composite package are shown in dashed lines. Figure 19B The vertical plane A-A' in the diagram is a vertical section. Figure 19A The cross-section.

[0026] Figure 20 An exemplary X-ray apparatus for testing a packaged structure according to an embodiment of this disclosure is shown.

[0027] Figures 21A to 21G This is a schematic diagram of various X-ray images that can be obtained when testing the packaging structure disclosed herein.

[0028] Figure 22 This is a first flowchart of the steps for manufacturing a packaging structure according to an embodiment of the present disclosure.

[0029] Figure 23 This is a second flowchart of the steps for testing a packaging structure according to an embodiment of the present disclosure. Detailed Implementation

[0030] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are illustrated below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. The drawings are not to scale. Elements with the same reference numerals refer to the same elements and are assumed to have the same material composition and the same thickness range unless explicitly stated otherwise. Unless explicitly disclosed otherwise, all features of the original embodiments are assumed to exist in any derived embodiments. Therefore, the features described with reference to the relevant embodiments in the drawings and / or specification provide support for the features in the embodiments. Unless explicitly stated otherwise, embodiments in which multiple examples of any of the said elements are repeated are expressly contemplated. Some embodiments are expressly contemplated in which non-essential elements are omitted, even if these embodiments are not explicitly disclosed but are known in the art.

[0031] Furthermore, for ease of description, this disclosure may use spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” to describe the relationship of one component or feature to another component(s). In addition to the orientations shown in the figures, the spatially relative terms are also intended to cover different orientations of components in use or operation. Components may be oriented in other directions (rotated 90 degrees or other directions), and the spatially relative terms used in this disclosure may be interpreted accordingly. Unless otherwise expressly stated, each element having the same reference numeral is considered to have the same material composition and a thickness within the same thickness range.

[0032] Semiconductor devices generate heat during operation, necessitating effective cooling to prevent performance degradation and maintain performance levels and reliability. Appropriately applying a thermal interface material (TIM) layer between the semiconductor die and the cap structure is a crucial process for ensuring effective die cooling. The TIM layer transfers the heat generated by the semiconductor die to the cap structure, acting as a heat sink. To ensure proper TIM layer application without voids or defects, X-ray inspection is typically used as part of the quality control process. Inspecting a thin TIM layer through a thick metal layer results in poor X-ray imaging due to reduced image contrast. Conversely, reducing the metal thickness improves X-ray inspection but impacts heat dissipation.

[0033] This disclosure relates to a cover structure for a semiconductor package configured to provide enhanced heat dissipation while allowing X-ray inspection of critical areas of the TIM layer. The cover structure includes a base plate portion contacting the top surface of the TIM layer, a top plate portion perpendicularly spaced from the base plate portion, a sidewall frame portion laterally surrounding a cavity between the base and top plate portions, and a solid cube portion located within the sidewall frame and at a corner region of the cover structure, the corner region being completely outside the area of ​​the semiconductor device, i.e., not overlapping with the semiconductor device in a plan view. X-rays can penetrate the top and base plate portions in areas where the solid cube portion is absent. The location of the solid cube portion is chosen such that the solid cube does not overlap with the semiconductor die in the path of the X-ray beam. Therefore, areas of the TIM layer that overlap with the semiconductor die can be inspected.

[0034] The solid cube portion of the cover structure can be located in the corner region of the cover structure and acts as a thermal mass structure to store heat and radiate it to the surrounding environment. The cavity between the base and top portions reduces the amount of metal material that X-rays need to pass through when inspecting the TIM layer and guides the heat flow in the base portion of the cover structure radially. Therefore, the cavity reduces the amount of metal material blocking X-rays within the TIM layer inspection area and improves the inspection efficiency of the TIM layer. The solid cube portion of the cover structure enhances heat dissipation, dissipating heat that propagates radially outward within the base portion and acting as a heat sink for heat accumulated therein. Therefore, the presence of the solid cube portion in the non-overlapping region outside the semiconductor die region enables X-ray inspection of the semiconductor die region and improves heat dissipation in the corner regions of the package structure. Various configurations of cover structures and threaded fasteners can be used, which will now be described with reference to the accompanying drawings.

[0035] Reference Figure 1An exemplary structure according to an embodiment of this disclosure is shown. The structure includes a first carrier wafer 310. The first carrier wafer 310 may include an optically transparent substrate such as a glass substrate or a sapphire substrate, or a semiconductor substrate such as a silicon substrate. The diameter of the first carrier wafer 310 may range from 150 mm to 450 mm, although smaller or larger diameters may also be used. The thickness of the first carrier wafer 310 may range from 500 micrometers to 2,000 micrometers, but smaller or larger thicknesses may also be used. Alternatively, the first carrier wafer 310 may be provided in a rectangular panel format. A first adhesive layer 311 may be applied to the front surface of the first carrier wafer 310. In one embodiment, the first adhesive layer 311 may be a photothermal conversion (LTHC) layer. Alternatively, the first adhesive layer 311 may include a thermally decomposable adhesive material.

[0036] A two-dimensional repeat of a unit via set can be formed on a first carrier wafer 310. Each instance of the unit via set can be formed within a corresponding unit region UA ​​having a rectangular area. Multiple instances of the unit via set can be repeated along a first horizontal direction hd1 and a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The unit region UA ​​corresponds to the area of ​​the interposer die to be formed subsequently. For example, each unit region UA ​​can have a rectangular shape having a first side length along the first horizontal direction hd1 and a second side length along the second horizontal direction hd2. The first side length can be the length of a pair of first sides of the rectangular shape. The second side length can be the length of a pair of second sides of the rectangular shape. The first side length is referred to herein as the first die lateral dimension dld1. The second side length is referred to herein as the second die lateral dimension dld2. Each of the first die lateral dimension dld1 and the second die lateral dimension dld2 can independently range from 300 micrometers to 6 centimeters, but smaller or larger dimensions can also be used.

[0037] Typically, the TIV structure 486 can be formed on the first adhesive layer 311 by deposition and patterning of a conductive material, or by transfer from above another carrier wafer. In an illustrative example, a sacrificial matrix layer (not shown) can be formed on the first adhesive layer 311. The sacrificial matrix layer includes, for example, amorphous carbon, diamond-like carbon (DLC) sacrificial materials, semiconductor materials (e.g., amorphous silicon or silicon-germanium alloys), or dielectric materials (e.g., silicate glass or organosilicon glass). The thickness of the sacrificial matrix layer can range from 3 micrometers to 60 micrometers, but smaller or larger thicknesses can also be used. A photoresist layer (not shown) can be applied over the sacrificial matrix layer. The photoresist layer can be photolithographically patterned to form openings with the same pattern as that subsequently formed in the top view of the TIV structure 486. An anisotropic etching process can be performed to transfer the opening pattern in the photoresist layer. A cylindrical cavity can be formed through the sacrificial matrix layer below the openings in the photoresist layer. The photoresist layer can be removed, for example, by ashing. At least one conductive material, such as at least one metallic material, can be deposited in the cylindrical cavity. For example, at least one conductive material may include a conductive metal barrier material (e.g., TiN, TaN, WN, or MoN) and a metal filler material (e.g., W, Ti, Ta, Mo, Ru, Co, etc.). Excess portions of the at least one conductive material can be removed from above the horizontal plate comprising the sacrificial matrix layer. The remaining portion of the at least one conductive material filling the cylindrical cavity constitutes the TIV structure 486. Subsequently, the sacrificial matrix layer can be selectively removed relative to the TIV structure 486 and relative to the first adhesive layer 311.

[0038] Alternatively, at least one conductive material layer may be deposited as a blanket material layer, i.e., deposited as an unpatterned material layer with a uniform thickness. For example, at least one conductive material layer may comprise a conductive metal barrier material (e.g., TiN, TaN, WN, or MoN) and a metal filler material (e.g., W, Ti, Ta, Mo, Ru, Co, etc.). The thickness of at least one conductive material layer may range from 3 micrometers to 60 micrometers, but smaller or larger thicknesses may also be used. A photoresist layer (not shown) may be applied over at least one conductive material layer. The photoresist layer may be photolithographically patterned to form discrete photoresist material portions having the same pattern as the TIV structure 486 subsequently formed in the top view. An anisotropic etching process may be performed to transfer the pattern of the discrete photoresist material portions through at least one conductive material layer. The patterned portion of at least one conductive material layer includes the TIV structure 486.

[0039] In another alternative embodiment, the TIV structure 486 may be formed on another carrier wafer and may be attached to the top surface of the first adhesive layer 311. The TIV structure 486 may then be separated from the additional carrier wafer.

[0040] In one embodiment, the pattern of the TIV structure 486 within each unit region UA ​​can be a pattern obtained by omitting a subset of the TIV structures 486 from a rectangular periodic array having a first spacing along a first horizontal direction hd1 and a second spacing along a second horizontal direction hd2. Specifically, a subset of the TIV structures 486 can be omitted such that two rectangular corner regions have no TIV structures 486, and at least one central region has no TIV structures 486. The at least one central region corresponds to at least one region of at least one local silicon interconnect (LSI) bridge to be positioned. In one embodiment, each TIV structure 486 includes a metal via structure.

[0041] Reference Figures 2A to 2C Multiple local silicon interconnect (LSI) bridges 405 may be provided. Each LSI bridge 405 includes a silicon substrate 410 (thinned and diced during the fabrication of the LSI bridge 405), a through-silicon via (TSV) structure 414 extending vertically through the silicon substrate 410, a through-substrate opening extending vertically through the silicon substrate 410, a dielectric liner 412 providing electrical insulation for the TSV structure 414, a back-side dielectric layer 420, and metal interconnect structures 480 located in the dielectric layer 450 and electrically connected to the TSV structure 414 and / or electrically connected to each other. Metal pads, referred to herein as LSI metal pads 488, may be provided on the topmost metal interconnect structure 480.

[0042] LSI bridges 405 can be placed within openings in the array of TIV structures 486 on the top surface of the first adhesive layer 311. Typically, at least one LSI bridge 405 can be placed within each cell region UA ​​using a pick-and-place tool. At least one local silicon interconnect (LSI) bridge 405 can be placed within each repeating cell region UA ​​using a pick-and-place tool. In one embodiment, multiple LSI bridges 405 can be placed within each repeating cell region UA ​​using a pick-and-place tool.

[0043] Reference Figure 3Encapsulations such as molding compounds (MCs) can be applied to the gaps within the assembly of LSI bridge 405 and TIV structure 486. MCs comprise curable (i.e., curable) epoxy-containing compounds to provide dielectric material portions with sufficient stiffness and mechanical strength. MCs may include epoxy resins, hardeners, silica (as fillers), and other additives. Depending on viscosity and flowability, MCs can be supplied in liquid or solid form. Liquid MCs typically offer better workability, good flowability, fewer voids, better filling, and fewer flow marks. Solid MCs typically offer less curing shrinkage, better spacing, and less die drift. High filler content in MCs (e.g., 85% by weight) can reduce mold time, decrease mold shrinkage, and reduce mold warpage. Uniform filler size distribution in MCs reduces flow marks and improves flowability.

[0044] The MC can be cured at a curing temperature to form an MC matrix, referred herein as the first molding compound (MC) material layer or intermediate layer molding compound (MC) material layer 490L. The intermediate layer MC material layer 490L laterally surrounds each of the LSI bridge 405 and the TIV structure 486. The intermediate layer MC material layer 490L may be a continuous material layer extending across the entire region of the reconstructed wafer overlying the first carrier wafer 310.

[0045] Reference Figure 4 Excess portions of the interposer MC material layer 490L are removed from a horizontal plane, including the top surfaces of the LSI bridge 405 and the TIV structure 486, using a planarization process. This planarization process can employ chemical mechanical planarization or chemical mechanical polishing (CMP). After the planarization process, the surface of the through-silicon via structure 414 can be solidly exposed. The remaining portion of the interposer MC material layer 490L is referred to herein as the interposer molding compound (MC) matrix 490M.

[0046] The intermediate layer MC matrix 490M includes a plurality of molded compound (MC) intermediate layer frames located within respective unit regions UA and laterally adjacent to each other. Each MC intermediate layer frame corresponds to a portion of the intermediate layer MC matrix 490M located in the unit region UA ​​(i.e., the region of the single intermediate layer to be subsequently formed). Each MC intermediate layer frame laterally surrounds a respective group of at least one LSI bridge 405 and TIV structure 486 in a respective array.

[0047] Reference Figure 5 A first rewiring structure 500 can be formed on the top side of the two-dimensional repeating MC matrix 490M of the cell via assembly and the intermediate layer. The first rewiring structure 500 includes a first rewiring interconnect 580, a first rewiring dielectric layer 560, and a first bonding structure 588.

[0048] The first multi-layer dielectric layer 560 comprises a corresponding dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Each first multi-layer dielectric layer 560 can be formed by spin-coating and drying the corresponding dielectric polymer material. The thickness of each first multi-layer dielectric layer 560 can range from 2 micrometers to 40 micrometers, for example, from 4 micrometers to 20 micrometers. Each first multi-layer dielectric layer 560 can be patterned, for example by applying and patterning a corresponding photoresist layer thereon, and transferring the pattern in the photoresist layer to the first multi-layer dielectric layer 560 using an etching process (e.g., anisotropic etching). The photoresist layer can then be removed, for example, by ashing.

[0049] Each first-level interconnect 580 can be formed by: depositing a metal seed layer by sputtering; applying and patterning a photoresist layer over the metal seed layer to form an opening pattern through the photoresist layer; electroplating a metal filler material (e.g., copper, nickel, or a stack of copper and nickel); removing the photoresist layer (e.g., by ashing); and etching portions of the metal seed layer located between portions of the electroplated metal filler material. The metal seed layer may include, for example, a stack of a titanium barrier layer and a copper seed layer. The thickness of the titanium barrier layer may range from 50 nm to 300 nm, and the thickness of the copper seed layer may range from 100 nm to 500 nm. The metal filler material of the first-level interconnect 580 may include copper, nickel, or copper and nickel. The thickness of the metal filler material deposited in each first-level interconnect 580 may range from 2 micrometers to 40 micrometers, for example from 4 micrometers to 10 micrometers, but smaller or larger thicknesses may also be used. The total number of cabling layers in the first cabling structure 500 (i.e., the number of layers of interconnects 580 in the first cabling) can be in the range of 1 to 10.

[0050] The first bonding structure 588 may include a microbump structure, which can then be used to attach a semiconductor die. The metal filler material of the microbump structure may include copper. The horizontal cross-sectional shape of the first bonding structure 588 may be rectangular, rounded rectangular, or circular. Other horizontal cross-sectional shapes are also within the scope of this disclosure. Typically, the first bonding structure 588 may be configured for microbump bonding and may have a thickness ranging from 5 micrometers to 100 micrometers, but smaller or larger thicknesses may also be used. In one embodiment, the first bonding structure 588 within each cell region UA ​​may be formed as an array of at least one microbump (e.g., copper pillars). The lateral dimension of each microbump may range from 10 micrometers to 50 micrometers, and their spacing may range from 20 micrometers to 100 micrometers.

[0051] Reference Figure 6A and Figure 6BThe first bonding structure 588 within each cell region UA ​​comprises a set of at least one semiconductor die (701, 702, 703) that can be bonded to a corresponding set of at least one semiconductor die (701, 702, 703). Each set of at least one semiconductor die (701, 702, 703) includes at least one semiconductor die and may include multiple semiconductor dies (701, 702, 703). For example, each set of at least one semiconductor die (701, 702, 703) may include at least one system-on-a-chip (SoC) die 701, at least one memory die 702, and / or at least one input / output (I / O) die 703. Each SoC die 701 may include an application processor die, a central processing unit die, or a graphics processing unit die. In one embodiment, at least one memory die 702 may include a high-bandwidth memory (HBM) die comprising a vertically stacked static random access memory die. In one embodiment, at least one I / O die 703 may include input / output circuitry for interfacing with external inputs and outputs of the SoC die 701 and / or the memory die 702. In one embodiment, at least one semiconductor die (701, 702, 703) may include at least one system-on-a-chip (SoC) die 701 and at least one high-bandwidth memory (HBM) chip. Each HBM die may include a vertical stack of static random access memory (SRAM) dies interconnected by an array of microbumps and laterally enclosed by a corresponding molded material frame.

[0052] Each semiconductor die (701, 702, 703) may include its own array of on-die bump structures 788. Solder portions may be applied to the on-die bump structures 788 of the semiconductor dies (701, 702, 703) or to the first bonding structure 588. These solder portions are referred to herein as die-to-interchange (DIB) solder portions 790, or first solder portions. Each semiconductor die (701, 702, 703) may be positioned face-down such that the on-die bump structures 788 face the first bonding structure 588. Pick-and-place devices may be used to place the semiconductor dies (701, 702, 703) such that each on-die bump structure 788 faces the corresponding first bonding structure 588. At least one semiconductor die (701, 702, 703) in each group may be placed within a corresponding unit area. DIB solder portion 790 is attached to one of the die bump structure 788 and the first bonding structure 588 for each pair of opposing die bump structures 788 and first bonding structures 588.

[0053] In one embodiment, the die-on bump structure 788 and the first bonding structure 588 can be configured for microbump bonding. In this embodiment, both the die-on bump structure 788 and the first bonding structure 588 can be configured as copper pillar structures with a diameter ranging from 10 micrometers to 50 micrometers and a height ranging from 5 micrometers to 100 micrometers. The spacing of the microbumps in the periodic direction can range from 20 micrometers to 100 micrometers, but smaller or larger spacing can also be used. During reflow, the lateral dimension of each DIB solder portion 790 can be in the range of 100% to 150% of the lateral dimension (e.g., diameter) of the adjacent die-on bump structure 788 or the adjacent first bonding structure 588.

[0054] LSI bridge 405 provides electrical interconnection between adjacent pairs of semiconductor dies (701, 702, 703). Generally, LSI bridge 405 can electrically connect SoC die 701 to memory die 702, adjacent pairs of SoC dies 701, or SoC die 701 to input / output die 703.

[0055] Reference Figure 7 Die-side underfill material can be applied to each gap between the first rewiring structure 500 and a corresponding set of at least one semiconductor die (701, 702, 703). The die-side underfill material may include any underfill material known in the art. The die-side underfill material portion 792 can be formed by injecting the die-side underfill material around the corresponding array of DIB solder portions 790 in the corresponding cell region UA. Any known underfill material application method can be used, which may be, for example, capillary underfill, molding underfill, or printed underfill.

[0056] The die-side bottom filler portion 792 may laterally surround and contact a corresponding set of DIB solder portions 790 within the cell region UA. The die-side bottom filler portion 792 may be formed to surround and contact the DIB solder portions 790, the first bonding structure 588, and the die-on bump structure 788 within the cell region. Typically, at least one semiconductor die (701, 702, 703) including a corresponding set of die-on bump structures 788 is attached to the first rewiring structure 500 via a corresponding set of DIB solder portions 790 within each cell region UA.

[0057] Reference Figure 8A molding compound (MC) can be applied to the gap between a corresponding set of semiconductor dies (701, 702, 703) and a corresponding set of die-side bottom filler portions 792. The MC can include any material that can be used in the aforementioned intermediate layer MC matrix 490M. The MC can include epoxy resin, hardener, silica (as filler), and other additives. The MC can be cured at a curing temperature to form an MC matrix, referred to herein as die-level MC matrix 796M or second MC matrix. The die-level MC matrix 796M laterally surrounds and embeds each set of semiconductor dies (701, 702, 703) and each set of die-side bottom filler portions 792. The die-level MC matrix 796M includes a plurality of molding compound (MC) die frames laterally adjacent to each other. Each MC die frame is a portion of the die-level MC matrix 796M located within a corresponding cell region UA. Therefore, each MC die frame laterally surrounds and embeds a corresponding set of corresponding die-side bottom filler material portions 792 of the semiconductor dies (701, 702, 703). The Young's modulus of pure epoxy resin is approximately 3.35 GPa, and the Young's modulus of MC can be higher than that of pure epoxy resin due to the additives present therein. Therefore, the Young's modulus of the die-grade MC matrix 796M can be greater than 3.5 GPa.

[0058] A portion of the die-level MC matrix 796M covering the top surface of the semiconductor dies (701, 702, 703) can be removed using a planarization process. For example, chemical mechanical planarization (CMP) can be used to remove the portion of the die-level MC matrix 796M located above this horizontal plane. The reconstructed wafer covering the first carrier wafer 310 comprises a two-dimensional array of a combination of the die-level MC matrix 796M, semiconductor dies (701, 702, 703), die-side bottom filler portion 792, a first redistribution structure 500, at least one LSI bridge 405, and a TIV structure 486. Each portion of the die-level MC matrix 796M located within the cell region UA ​​constitutes an MC die frame.

[0059] Reference Figure 9 A second adhesive layer 321 can be applied over the die-level MC substrate 796M. Depending on the removal mechanism used subsequently, the second adhesive layer 321 may include a photothermal conversion (LTHC) layer or a thermally decomposable adhesive layer. A second carrier wafer 320 can be attached to the die-level MC substrate 796M and the semiconductor die (701, 702, 703) via the second adhesive layer 321. The second carrier wafer 320 may contain any material used for the first carrier wafer 310 and may typically have approximately the same thickness range as the first carrier wafer 310.

[0060] The first carrier wafer 310 can be separated from the reconstructed wafer. In some embodiments, the first carrier wafer 310 and the first adhesive layer 311 can be removed by back-side grinding. Optionally, at least one selective etching process (e.g., wet etching or reactive ion etching) can be used in conjunction with the back-side grinding process to minimize additional removal of surface portions of the LSI bridge 405 and the TIV structure 486. Optionally or additionally, in embodiments where the first carrier wafer 310 comprises an optically transparent material and the first adhesive layer 311 comprises a photothermal conversion material, the first carrier wafer 310 can be separated by irradiation. In embodiments where the first adhesive layer 311 comprises a thermally decomposable adhesive material, annealing or laser irradiation can be used to separate the first carrier wafer 310. Suitable cleaning processes can be performed to remove residual portions of the first adhesive layer 311.

[0061] Reference Figure 10 A second rewiring structure 600 can be formed on the two-dimensional repeating solid exposed side of the cell via assembly and the interposer layer MC matrix 490M. The second rewiring structure 600 includes a second rewiring interconnect 680, an optional second interconnect-level alignment structure (not shown), a second rewiring dielectric layer 660, and a second bonding structure 688. Typically, the second rewiring structure 600 can be formed in the same manner as the first rewiring structure 500, with appropriate variations in the photolithographic pattern and / or the thickness and material composition of the material layers. The second bonding structure 688 can be formed as a bonding pad configured for controlled collapse chip interconnect (C4) bonding.

[0062] Reference Figure 11A and Figure 11B The second carrier wafer 320 can be separated from the reconstructed wafer. In embodiments where the second carrier wafer 320 comprises an optically transparent material and the second adhesive layer 321 comprises a photothermal conversion material, the second carrier wafer 320 can be separated by irradiation. In embodiments where the second adhesive layer 321 comprises a thermally decomposable adhesive material, the second carrier wafer 320 can be separated using an annealing process or laser irradiation. A suitable cleaning process can be performed to remove any residual portions of the second adhesive layer 321. The horizontal surface of the die-grade MC matrix 796M can be substantially exposed.

[0063] The reconstructed wafer includes a two-dimensional array of interposer dies 400, and also includes a two-dimensional array of a group of at least one semiconductor die (701, 702, 703) bonded to a respective interposer die 400. The reconstructed wafer can be diced along dicing trajectories (corresponding to the aforementioned dicing lines DL) by a dicing process. Dicing trajectories correspond to the boundary between adjacent pairs of cell regions UA. Each diced cell from the reconstructed wafer includes a composite package 800. Each diced portion of the die-level MC matrix 796M constitutes a die-level molding compound (MC) frame 796, also referred to as a die frame 796. Each diced portion of the interposer-level MC matrix 490M constitutes an interposer-level MC frame 490.

[0064] The diced portion of the reconstructed wafer includes a composite package 800, which may be a fan-out package. Each composite package 800 includes at least one semiconductor die (701, 702, 703), an interposer die 400, a die-side bottom filler portion 792, a die frame 796, and at least one array of DIB solder portions 790. Each interposer die 400 includes: an assembly of vias containing a TIV structure 486, at least one LSI bridge 405, an interposer MC frame 490, a first rewiring structure 500, and a second rewiring structure 600.

[0065] Reference Figure 12 The packaging substrate 200 can be bonded to the composite package 800. The packaging substrate 200 can be a core packaging substrate including a core substrate 210, or a coreless packaging substrate excluding the packaging core. Additionally, the packaging substrate 200 can include an integrated system-on-package (SoIS) substrate including a redistribution layer, a dielectric interlayer, and / or at least one embedded interposer (e.g., a silicon interposer). Such an integrated system-on-package substrate can include layer-to-layer interconnects using solder portions, microbumps, underfill material portions (e.g., molded underfill material portions), and / or adhesive films. While this disclosure describes the use of a core packaging substrate, it should be understood that the scope of this disclosure is not limited to any particular type of substrate package. For example, a SoIS can be used instead of a core packaging substrate. In embodiments using SoIS, the core substrate 210 can include a glass epoxy board with an array of through-holes. An array of through-core via structures 214, including a metallic material, can be provided in the through-holes. Each through-core via structure 214 may or may not have a cylindrical hollow portion therein. Optionally, a dielectric pad (not shown) may be used to electrically isolate the through-hole structure 214 from the core substrate 210.

[0066] The packaging substrate 200 may include a surface-mount layered circuit (SLC) 240 and a chip-side surface-mount layered circuit (SLC) 260. The board-side SLC may include a board-side insulating layer 242 that embeds board-side interconnects 244. The chip-side SLC 260 may include a chip-side insulating layer 262 that embeds chip-side interconnects 264. Both the board-side and chip-side insulating layers 242 and 262 may include a photosensitive epoxy resin material that can be photolithographically patterned and subsequently cured. The board-side and chip-side interconnects 244 and 264 may include copper that can be deposited within patterns in the board-side or chip-side insulating layers 242 by electroplating.

[0067] In one embodiment, the chip-side surface-mount circuitry 260 includes chip-side wiring interconnects 264 connected to an array of substrate bonding pads 268. The array of substrate bonding pads 268 may be configured to allow bonding via C4 solder balls. The board-side surface-mount circuitry 240 includes board-side wiring interconnects 244 connected to an array of board-side bonding pads 248. The array of board-side bonding pads 248 is configured to allow bonding via solder joints having a larger size than C4 solder balls. While this disclosure describes embodiments using a package substrate 200 including chip-side surface-mount circuitry 260 and board-side surface-mount circuitry 240, the embodiments herein explicitly contemplate that one of the chip-side surface-mount circuitry 260 and board-side surface-mount circuitry 240 may be omitted or replaced by an array of bonding structures such as microbumps. In illustrative examples, the chip-side surface-mount circuitry 260 may be replaced by an array of microbumps or any other array of bonding structures.

[0068] The composite package 800 can be attached to the package substrate 200 using a second solder portion, referred to herein as an interposer-substrate bonding (ISB) solder portion 290. Specifically, each ISB solder portion 290 can be bonded to a corresponding one of the substrate bonding pads 268 and a corresponding one of the second bonding structures 688 located on the composite package 800. A reflow process can be performed to reflow the ISB solder portions 290 such that each ISB solder portion 290 can be bonded to a corresponding one of the substrate bonding pads 268 and a corresponding one of the second bonding structures 688.

[0069] An underfill material may be applied to the gap between the composite package 800 and the package substrate 200. The underfill material may include any underfill material known in the art. An underfill material portion may be formed to surround an ISB solder material portion 290 in the gap between the composite package 800 and the package substrate 200. This underfill material portion is referred to herein as an interposer-substrate underfill material portion 292, or as an IP underfill material portion 292. An array of solder portions 190 may be formed on an array of board-side bonding pads 248. A bonding assembly (800, 200) comprising the composite package 800 and the package substrate 200 may be formed.

[0070] Reference Figure 13A and Figure 13B A cover structure 900 is provided, configured to be attached to a bonding assembly (800, 200). The cover structure 900 includes a thermally conductive material, which may include a metallic material (e.g., copper, aluminum, or a metal alloy), a thermally conductive ceramic material (e.g., aluminum nitride, alumina, or silicon carbide), or graphite. The cover structure 900 includes a cavity 919, also referred to as a vapor chamber, located in an area overlapping with at least one semiconductor die (701, 702, 703) when mounted to the bonding assembly (800, 200). Furthermore, the cover structure 900 includes a wall portion 930 that laterally surrounds the composite package 800 when mounted to the bonding assembly (800, 200). According to one aspect of this disclosure, the shape of the cavity 919 within the cover structure 900 is selected such that, when the cover structure 900 is mounted to the bonding assembly (800, 200), the region of the cavity 919 in a plan view (e.g., a perspective top-down view) overlaps with the entire region of at least one semiconductor die (7701, 702, 703) in the bonding assembly (800, 200). A plan view refers to a view along a vertical direction in which the outline of each structural element is delineated in a projection onto a horizontal plane, regardless of whether the structural element is visible or not from the outside. For example, although the inner sidewall of the cover structure 900 is not visible from the outside, the inner sidewall of the cover structure 900 defining the lateral extent of the cavity 919 is visible in the plan view.

[0071] According to one aspect of the invention, the cover structure 900 includes a bottom plate portion 912 having a first uniform vertical thickness, a top plate portion 914 perpendicularly spaced from the bottom plate portion 912 and having a second uniform vertical thickness, a sidewall frame portion 910 laterally surrounding a cavity 919 located between the bottom plate portion 912 and the top plate portion 914 and having a uniform sidewall thickness ST, and a solid block portion 920 located within the sidewall frame portion 910 and extending vertically from a first horizontal plane HP1 including the bottom surface of the bottom plate portion 912 to a second horizontal plane HP2 including the top surface of the top plate portion 914, and located in a corner region of the cover structure 900. The first uniform vertical thickness may be in the range of 0.5 mm to 3 mm, and the second uniform vertical thickness may be in the range of 0.5 mm to 3 mm.

[0072] The vertical distance between the base plate portion 912 and the top plate portion 914 can range from 1 mm to 5 mm, but smaller or larger vertical distances can also be used. The uniform sidewall thickness ST can range from 0.5 mm to 5 mm, but smaller or larger thicknesses can also be used. For the purposes of this disclosure, the entire portion of the cover structure 900 is covered by a first horizontal plane HP1 and is laterally spaced from the outer vertical sidewalls of the cover structure 900 by a distance not greater than the uniform sidewall thickness ST; this entire portion is considered the sidewall frame portion 910. The vertical thickness t of each solid block portion 920 can be the same as the vertical spacing between the first horizontal plane HP1 and the second horizontal plane HP2. There can be no gaps in each solid block portion 920.

[0073] In one embodiment, the cover structure 900 includes a wall portion 930 extending downward from the peripheral area of ​​the base plate portion 912. The outer walls of the wall portion 930 may be perpendicularly coincident with the outer walls of the sidewall frame portion 910, i.e., they may lie in the same set of vertical planes. The wall portion 930 may include a set of four adjacent vertically extending walls that laterally enclose the opening. Each wall of the wall portion 930 may have a uniform width, referred to herein as the wall thickness ET. The wall thickness ET may range from 0.5 mm to 5 mm, but smaller or larger thicknesses may also be used.

[0074] The horizontal cross-sectional shape of the sidewall frame portion 910 may include a pair of first outer sidewalls extending laterally along a first horizontal direction hd1 and a pair of second outer sidewalls extending laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In one embodiment, the enclosure portion 930 may include two first outer sidewalls parallel to the first horizontal direction hd1 and two second outer sidewalls parallel to the second horizontal direction hd2. In one embodiment, the first outer sidewalls of the enclosure portion 930 may be perpendicularly coincident with the first outer sidewalls of the sidewall frame portion 910, and the second outer sidewalls of the enclosure portion 930 may be perpendicularly coincident with the second outer sidewalls of the sidewall frame portion 910.

[0075] A thermal interface material can be applied to the top surface of the composite package 800, which includes the top surface of at least one semiconductor die (701, 702, 703) and the die frame 796. Alternatively or additionally, the thermal interface material can be applied to the bottom surface of the base plate portion 912 of the cover structure 900. The thermal interface material applied to the top surface of at least one semiconductor die (701, 702, 703) and / or the bottom surface of the base plate portion 912 can be any thermal interface material known in the art. For example, the thermal interface material may include thermal grease, thermal pads, phase change materials, liquid metal, or thermal adhesive. The thickness of the thermal interface material can range from 10 micrometers to 500 micrometers, but smaller or larger thicknesses are also possible. While it is desirable to apply a thermal interface material with a uniform thickness, variations in the thickness and / or coverage of the thermal interface material on the top surface of the composite package or the bottom surface of the base plate portion 912 may be introduced during the application process. Furthermore, during the subsequent bonding process between the composite package 800 and the cover structure 900, and during the process of converting the applied portion of the thermal interface material into the thermal interface material layer 903, local thickness variations may occur in the applied portion of the thermal interface material. According to one aspect of the invention, the cover structure 900 is configured to facilitate the testing and inspection of the thermal interface material layer 903 after the cover structure 900 is attached to the bonded assembly (800, 200) of the composite package 800 and the package substrate 200.

[0076] An adhesive layer 901 can be used to attach the cover structure 900 to a bonding assembly (800, 200) including at least one semiconductor die (701, 702, 703). In one embodiment, the adhesive layer 901 bonds the cover structure 900 to a package substrate 200. In one embodiment, the adhesive layer 901 can be applied to a first element selected from the package substrate 200 and the cover structure 900, and contact a second element selected from the package substrate 200 and the cover structure 900 that is different from the first element. In an illustrative example, the adhesive layer 901 can be applied to a peripheral portion of the top surface of the package substrate 200. In an illustrative example, the adhesive layer 901 can be applied between the package substrate 200 and the frame-shaped bottom surface of the enclosure portion 930 of the cover structure 900. In this embodiment, the enclosure portion 930 can be attached to the frame-shaped surface segment of the top surface of the package substrate 200 via the adhesive layer 901 and laterally surrounds the composite package 800.

[0077] The thermal interface material applied to the top surface of at least one semiconductor die (701, 702, 703) and / or the bottom surface of the base plate portion 912 of the cap structure 900 is transformed into a thermal interface material (TIM) layer 903, typically having a uniform thickness. Therefore, the cap structure 900 is attached to the bonding assembly (800, 200) such that the TIM layer 903 is inserted between at least one semiconductor die (701, 702, 703) and the base plate portion 912. Typically, the TIM layer 903 is formed by applying the thermal interface material to each top surface of at least one semiconductor die (701, 702, 703) or the bottom surface of the base plate portion 912, and pressing the thermal interface material between at least one semiconductor die (701, 702, 703) and the cap structure 900. According to one aspect of this disclosure, when the cover structure 900 is attached to the package substrate 200, the solid block portion 920 of the cover structure 900 is configured to be completely outside the area of ​​at least one semiconductor die (701, 702, 703) in a planar view along the vertical direction, that is, it does not overlap with any area of ​​at least one semiconductor die (701, 702, 703).

[0078] Typically, the TIM layer 903 has a uniform thickness unless an error occurs during bonding the cover structure 900 to the package substrate 200. Furthermore, unless an error occurs during bonding the cover structure 900 to the package substrate 200, there will be no bald spots (i.e., locations lacking thermal interface material) in the TIM layer 903. Although the general configuration of the components of the cover structure 900, TIM layer 903, and at least one semiconductor die (701, 702, 703) is described below for structures that are processed normally without errors, errors may occur during manufacturing, and the advantage of the embodiments disclosed herein is that defective components or defective configurations due to such errors can be detected, for example, by subsequent X-ray inspection. Therefore, it should be understood that the geometry described below is generally applicable to package structures that pass subsequent X-ray inspection. For example, for a normally processed package structure, the TIM layer 903 has a uniform thickness, while non-uniform thickness of the TIM layer 903 can be a cause of screening out defective package structures. Furthermore, although the TIM layer 903 should cover the entire area of ​​at least one semiconductor die (701, 702, 703), and most package structures conform to this standard, insufficient coverage of at least one semiconductor die (701, 702, 703) by the TIM layer 903 may be a cause of defects in the package structure.

[0079] Typically, for a defect-free package structure after processing, when the cover structure 900 is attached to the bonding assembly (800, 200), the TIM layer 903 has a region of overlap with the entirety of at least one semiconductor die (701, 702, 703) in a plan view. In one embodiment, the cover structure 900 also includes a wall portion 930 of a frame-shaped surface segment extending downward from the peripheral region of the base plate portion 912 and attached to the top surface of the package substrate 200 through the adhesive layer 901. After the cover structure 900 is attached to the package substrate 200, a frame-shaped gap 939 can be formed between the sidewall of the composite package 800 and the inner sidewall of the wall portion 930 and around the composite package 800.

[0080] exist Figures 13A-13EIn the illustrated configuration, the solid cube portion 920 is located outside the area of ​​the composite package 800 in the plan view. In one embodiment, during the attachment of the cover structure 900 to the bonding assemblies (800, 200), the cover structure 900 may be aligned with the bonding assemblies (800, 200) such that the solid cube portion 920 is completely outside the area of ​​the die frame 796, i.e., there is no overlap with the die frame 796. In one embodiment, the solid cube portion 920 may include or may be composed of four solid cube portions 920, each having a horizontal triangular shape and located at the four corners of the cover structure 900. In this embodiment, the X-ray beam used for subsequent X-ray inspection is attenuated in the areas of the solid cube portion 920 and the sidewall frame portion 910, but not in the area of ​​the cavity 919. Therefore, the entire portion of the TIM layer 903 can be inspected in subsequent X-ray inspections.

[0081] Reference Figure 14A and Figure 14B This illustrates a first alternative configuration of the encapsulation structure, which can be modified by altering the pattern of the solid cube portion 920 and the cavity 919. Figures 13A-13E It is derived from the packaging structure shown. Figure 14A and Figure 14B In the first alternative configuration shown, the solid cube portion 920 has a regional overlap with the peripheral region of the composite package 800 in the plan view. In one embodiment, during the attachment of the cover structure 900 to the bonding assemblies (800, 200), the cover structure 900 can be aligned with the bonding assemblies (800, 200) such that, when the cover structure 900 is attached to the bonding assemblies (800, 200), the solid cube portion 920 has a partial regional overlap with the frame-shaped gap 939 and a partial regional overlap with the die frame 796.

[0082] In one embodiment, the solid block portion 920 may include or may consist of four solid block portions 920, each having a rectangular horizontal shape and located at one of the four corners of the cap structure 900. The solid block portions 920 may include areas overlapping with the die frame 796 in a plan view. Specifically, the corner areas of the die frame 796 may overlap with the solid block portions 920 in a plan view. In this embodiment, because the X-ray beam used for subsequent X-ray examinations attenuates within the solid block portions 920 and the sidewall frame portions 910, the corner areas of the die frame 796 are excluded from the examination area in subsequent X-ray examinations.

[0083] Reference Figure 15A and Figure 15B This illustrates a second alternative configuration of the encapsulation structure, which can be modified by altering the pattern of the solid cube portion 920 and the cavity 919. Figures 13A-13E It is derived from the packaging structure shown. Figure 15A and Figure 15B In the second alternative configuration shown, the solid cube portion 920 has a regional overlap with the peripheral region of the composite package 800 in the plan view. In one embodiment, during the attachment of the cover structure 900 to the bonding assemblies (800, 200), the cover structure 900 can be aligned with the bonding assemblies (800, 200) such that, when the cover structure 900 is attached to the bonding assemblies (800, 200), the solid cube portion 920 has a partial regional overlap with the frame-shaped gap 939 and a partial regional overlap with the die frame 796.

[0084] In one embodiment, the solid block portion 920 includes a plurality of solid fins extending laterally along a horizontal direction, wherein the horizontal direction can be a first horizontal direction hd1 or a second horizontal direction hd2. Figure 15A and Figure 15B In the example shown, multiple solid fins of the solid block portion 920 extend laterally along a first horizontal direction hd1. In one embodiment, a first subset of the multiple solid fins lies entirely outside the area of ​​the composite package 800 in a plan view, i.e., without any area overlapping with the composite package 800; while a second subset of the multiple solid fins partially overlaps with the composite package 800 in a plan view. In one embodiment, each solid fin may extend laterally along a lateral elongation direction (e.g., the first horizontal direction hd1) and may have a consistently uniform width. In one embodiment, one or more solid fins may have two sidewalls adjacent to the sidewall frame portion 910.

[0085] Reference Figure 16A and Figure 16B This illustrates a third alternative configuration of the encapsulation structure, which can be modified by altering the pattern of the solid cube portion 920 and the cavity 919. Figures 13A-13E It is derived from the packaging structure shown. Figure 16A and Figure 16B In the third alternative configuration shown, the solid cube portion 920 has a regional overlap with the peripheral region of the composite package 800 in the plan view. In one embodiment, during the attachment of the cover structure 900 to the bonding assemblies (800, 200), the cover structure 900 can be aligned with the bonding assemblies (800, 200) such that, when the cover structure 900 is attached to the bonding assemblies (800, 200), the solid cube portion 920 has a partial regional overlap with the frame-shaped gap 939 and a partial regional overlap with the die frame 796.

[0086] In one embodiment, the solid block portion 920 includes a plurality of solid fins extending laterally along a horizontal direction, wherein the horizontal direction can be a first horizontal direction hd1 or a second horizontal direction hd2. Figure 16A and Figure 16B In the example shown, multiple solid fins of the solid block portion 920 extend laterally along a second horizontal direction hd2. In one embodiment, a first subset of the multiple solid fins lies entirely outside the area of ​​the composite package 800 in a plan view, i.e., without any area overlapping with the composite package 800; while a second subset of the multiple solid fins partially overlaps with the composite package 800 in a plan view. In one embodiment, each solid fin may extend laterally along a lateral elongation direction (e.g., the second horizontal direction hd1) and may have a consistently uniform width. In one embodiment, one or more solid fins may have two sidewalls adjacent to the sidewall frame portion 910.

[0087] Reference Figure 17A and Figure 17B This illustrates a fourth alternative configuration of the encapsulation structure, which can be modified by altering the pattern of the solid cube portion 920 and the cavity 919. Figures 13A-13E It is derived from the packaging structure shown. Figure 17A and Figure 17B In the fourth alternative configuration shown, each solid cube portion 920 can be separated from the sidewall frame portion 910 by its respective lateral gap, which forms part of the cavity 919. The solid cube portion 920 may have regional overlap with the peripheral region of the composite package 800 in a plan view. In this embodiment, each sidewall of the solid cube portion 920 may be substantially exposed outside the cavity 919. In one embodiment, each solid cube portion 920 may have its own rectangular or triangular horizontal cross-sectional shape, which partially overlaps with the die frame 796 but does not overlap with any of the at least one semiconductor die (701, 702, 703).

[0088] Reference Figure 18A and Figure 18B This illustrates a fifth alternative configuration of the packaging structure, which can be derived from... Figures 13A-13E , Figure 14A and Figure 14B , Figure 15A and Figure 15B or Figure 16A and Figure 16BThe package structure shown is derived from the one where at least one solid cube portion 920 is removed from at least one corner of the cover structure 900, without removing at least another solid cube portion 920 from at least another corner of the cover structure 900. In a fifth alternative configuration, at least one solid cube portion 920 is present, which may be present in one corner region, two corner regions, or three corner regions. Each solid cube portion 920 may or may not have regional overlap with a corresponding peripheral region of the composite package 800 in a plan view. In one embodiment, each solid cube portion 920 may have a corresponding rectangular or triangular horizontal cross-sectional shape, or a fin shape. Each solid cube portion 920 may not overlap with the die frame 796, or may partially overlap with the die frame 796. Each solid cube portion 920 does not overlap with any of the at least one semiconductor die (701, 702, 703). Figure 18A and Figure 18B In the example shown, the solid block portion 920 is located in two corner regions that are diagonally opposite each other.

[0089] Reference Figure 19A and Figure 19B This illustrates a sixth alternative configuration of the packaging structure, which can be derived from... Figure 17A and Figure 17B Derived from the package structure shown, it removes at least one solid cube portion 920 from at least one corner of the cover structure 900 without removing at least another solid cube portion 920 from at least another corner of the cover structure 900. In a sixth alternative configuration, at least one solid cube portion 920 is provided, which may be present in one corner region, two corner regions, or three corner regions. Each solid cube portion 920 may or may not have regional overlap with a corresponding peripheral region of the composite package 800 in a plan view. In one embodiment, each solid cube portion 920 may have a corresponding rectangular or triangular horizontal cross-sectional shape. Each solid cube portion 920 may not overlap with the die frame 796, or may partially overlap with the die frame 796. Each solid cube portion 920 does not overlap with any of the at least one semiconductor die (701, 702, 703). Figure 19A and Figure 19B In the example shown, the solid block portion 920 is located in two corner regions that are diagonally opposite each other.

[0090] Then you can test the reference. Figures 13A-13E , Figure 14A and Figure 14B , Figure 15A and Figure 15B , Figure 16A and Figure 16B , Figure 17A and Figure 17B , Figure 18A and Figure 18B as well as Figure 19A and Figure 19B The package structure is described to determine whether the TIM layer 903 covers the entire area of ​​at least one semiconductor die (701, 702, 703) and / or whether the TIM layer 903 contains any voids or thin areas.

[0091] Reference Figure 20 An exemplary X-ray apparatus for non-destructive testing of the packaged structure disclosed herein is illustrated. The exemplary X-ray apparatus includes an X-ray generator 610, which includes an X-ray tube and circuitry for generating an X-ray beam from the X-ray tube. The exemplary X-ray apparatus also includes an X-ray imaging transducer 690, which includes a two-dimensional X-ray sensor pixel array. For example, the X-ray imaging transducer 690 may include a flat panel detector, a scintillator layer coupled to a photodiode array, or a charge-coupled device (CCD) sensor array. A pre-configured process controller 680 can be configured to control the operation of the X-ray generator 610 and the X-ray imaging transducer 690.

[0092] As described above, an encapsulation structure can be formed by attaching a cover structure 900 to the bonding assemblies (800, 200) such that a thermal interface material (TIM) layer 903 is inserted between at least one semiconductor die (701, 702, 703) and a base plate portion 912, and a solid cube portion 920 is completely outside the area of ​​at least one semiconductor die (701, 702, 703), i.e., the solid cube portion 920 does not overlap with at least one semiconductor die (701, 702, 703) in a planar view along the vertical direction. The TIM layer 903 can be tested for defects by generating and inspecting an X-ray image of the encapsulation structure using an X-ray beam 617 passing through the cover structure 900, the TIM layer 903, and the bonding assemblies (800, 200). Specifically, the encapsulation structure can be inserted between an X-ray generator 610 and an X-ray imaging transducer 690 such that the vertical direction of the encapsulation structure is parallel to the direction of the X-ray beam 617 generated from the X-ray generator 610. The X-ray imaging transducer 690 can be oriented such that the X-ray sensor pixel array in the X-ray imaging transducer 690 is aligned in a plane perpendicular to the X-ray beam 617. The X-ray beam 617 is turned on such that the dose of the X-ray beam 617 can produce an X-ray image of the encapsulated structure, so that the structural features of the TIM layer 903 are displayed with optimal contrast relative to the background of the X-ray image of the encapsulated structure.

[0093] Typically, defects in the TIM layer 903 can be tested by generating and inspecting X-ray images of the package structure using an X-ray beam that passes through the cover structure 900, the TIM layer 903, and the bonding assemblies (800, 200). In one embodiment, the X-ray beam is guided vertically and irradiates an area encompassing the entire region of the composite package 800 in the plan view.

[0094] Depending on the configuration of the solid cube portion 920, the solid cube portion 920 can be completely outside the area of ​​the composite package 800 during exposure to an X-ray beam irradiating in the direction perpendicular to the package structure; that is, it can have no area overlap with the composite package 800. In this embodiment, the solid cube portion 920 does not produce any shaded areas (i.e., areas partially blocked by the cover structure 900 having a vertical thickness t), and the entire area of ​​the composite package 800 can be inspected to confirm whether the coverage and / or thickness of the TIM layer 903 is abnormal.

[0095] In an alternative configuration, the solid cube portion 920 may partially overlap with the composite package 800. For example, the solid cube portion 920 may partially overlap with a corner portion of the die frame 796. In one embodiment, the TIM layer 903 may be formed such that the solid cube portion 920 partially overlaps with the TIM layer 903, and the TIM layer 903 does not cover the entire top surface of the die frame 796. In some embodiments, the TIM layer 903 may cover the entire top surface region of at least one semiconductor die (701, 702, 703), and may cover a first region of the top surface of the die frame 796 in a planar view along the direction of the X-ray beam 617 without covering a second region of the top surface of the die frame 796.

[0096] In embodiments where the solid cube portion 920 partially overlaps with the die frame 796, the overlapping area can be excluded when examining X-ray images. The thermal contact between each semiconductor die (701, 702, 703) and the TIM layer 903 affects heat dissipation from at least one semiconductor die (701, 702, 703) to the cap structure 900, while the thermal contact between the die frame 796 and the TIM layer 903 is not critical for providing good thermal contact between at least one semiconductor die (701, 702, 703) and the cap structure 900. Therefore, excluding the overlapping area between the solid cube portion 920 and the die frame 796 is not detrimental to the effective inspection of the thermal contact of the TIM layer 903, i.e., determining whether the TIM layer 903 can provide sufficient thermal contact between at least one semiconductor die (701, 702, 703) and the cap structure 900.

[0097] Typically, X-ray image inspection involves locating any areas of the TIM layer 903 where the thermal interface material is absent or thinner than the surrounding area. This inspection can be performed by identifying any portion of the X-ray image that exhibits a higher detected X-ray dose level relative to the surrounding area. In one embodiment, inspecting the X-ray image involves locating areas of the TIM layer 903 where the thermal interface material is absent or thinner than the surrounding area by identifying portions of the X-ray image that exhibit a higher detected X-ray dose level relative to the surrounding area. Specifically, if the TIM layer 903 contains voids or thinned regions, for example, voids or thinned regions that cause more X-ray photons to pass through, and the X-ray image contains regions in which more X-ray photons are detected within a region corresponding to the volume of the voids or thinned regions, X-ray inspection can screen out defective encapsulation structures with anomalous features in the TIM layer 903.

[0098] Figures 21A to 21G These are schematic diagrams of various X-ray images that can be obtained when testing the packaging structure disclosed herein. For ease of explanation, Figures 21A-21G Each X-ray image shown contains an anomalous region 909, in which more X-ray photons are detected due to voids in the TIM layer 903 or due to local thinning of the TIM layer 903. Figures 21A-21G The X-ray images shown correspond to those that can be obtained from Figures 13A-13E , Figure 14A and Figure 14B , Figure 15A and Figure 15B , Figure 16A and Figure 16B , Figure 17A and Figure 17B , Figure 18A and Figure 18B or Figure 19A and Figure 19B The resulting package structure is configured within the package structure. Each structural component within the corresponding package structure is labeled with a corresponding reference numeral for easy reference. Figures 21A-21G X-ray images in Figures 13A-13E , Figure 14A and Figure 14B , Figure 15A and Figure 15B , Figure 16A and Figure 16B , Figure 17A and Figure 17B , Figure 18A and Figure 18B or Figure 19A and Figure 19BThe various physical structural elements within the package structure shown are interconnected. It is understood that the X-ray image only shows a two-dimensional distribution of the detected X-ray photon density; image interpretation is required to correlate the features in the X-ray image with the physical structure within the package substrate. This can be done manually or using image analysis programs. Furthermore, it is understood that most of the inspected package structure does not have any defects or anomalies in the TIM layer 903, and only a small portion of the inspected package structure may contain any defects in the TIM layer 903.

[0099] Reference Figures 1 to 21G According to various embodiments of the present invention, a packaging structure is provided comprising: a bonding assembly (800, 200) including a composite package 800 and a packaging substrate 200, wherein the composite package 800 includes at least one semiconductor die (701, 702, 703) and a die frame 796; and a cover structure 900 attached to the bonding assembly (800, 200), wherein the cover structure 900 includes a base plate portion 912, a top plate portion 914 perpendicularly spaced from the base plate portion 912, and a lateral surrounding portion 914 located on the base plate portion 912. A sidewall frame portion 910 of the cavity 919 between the bottom plate portion 912 and the top plate portion 914, and a second horizontal plane HP2 located within the sidewall frame portion 910 and extending vertically from a first horizontal plane HP1 including the bottom surface of the bottom plate portion 912 to the top surface of the top plate portion 914, wherein the solid cube portion 920 is completely outside the area of ​​at least one semiconductor die (701, 702, 703) in a plan view along the vertical direction, i.e., it does not overlap with any area of ​​at least one semiconductor die (701, 702, 703). A thermal interface material (TIM) layer 903 is inserted between at least one semiconductor die (701, 702, 703) and the bottom plate portion 912. In a plan view along the vertical direction, the solid cube portion 920 is completely outside the area of ​​at least one semiconductor die (701, 702, 703), i.e., it does not overlap with any area of ​​at least one semiconductor die (701, 702, 703).

[0100] In one embodiment, the TIM layer 903 covers the entirety of at least one semiconductor die (701, 702, 703) in a plan view. In one embodiment, when the cover structure 900 is attached to the bonding assembly (800, 200), the TIM layer 903 has regional overlap with the entirety of at least one semiconductor die (701, 702, 703) in a plan view. Typically, if there are no defects during formation, the TIM layer 903 will cover the entire top surface of each semiconductor die (701, 702, 703). In the absence of defects during formation, the TIM layer 903 may or may not cover the entire top surface of the die frame 796.

[0101] In one embodiment, during the attachment of the cap structure 900 to the mating assemblies (800, 200), the cap structure 900 is aligned with the mating assemblies (800, 200) such that the solid cube portion 920 is completely outside the area of ​​the die frame 796, i.e., it does not overlap with the die frame 796 in any area, as shown in the figure. Figures 13A-13E As stated above.

[0102] In one embodiment, the solid block portion 920 partially overlaps with the core frame 796 in a plan view, such as... Figures 14A to 19B As shown. In one embodiment, the solid cube portion 920 partially overlaps with the outer portion of the TIM layer 903 in a plan view. In one embodiment, when the cap structure 900 is attached to the bonding assembly (800, 200), the solid cube portion 920 partially overlaps with the frame-shaped gap 939 and partially overlaps with the core frame 796.

[0103] In one embodiment, the solid block portion 920 includes a plurality of solid fins extending laterally along a horizontal direction; a first subset of the plurality of solid fins is completely outside the area of ​​the composite package 800 in a plan view, i.e., it does not overlap with any area of ​​the composite package 800; and a second subset of the plurality of solid fins partially overlaps with the composite package 800.

[0104] Figure 22 This is a first flowchart of the steps for manufacturing a packaging structure according to an embodiment of the present disclosure.

[0105] Refer to step 2210 and Figures 1 to 11B A composite package 800 is provided, comprising at least one semiconductor die (701, 702, 703) and a die frame 796.

[0106] Refer to step 2220 and Figure 12 The composite package 800 is attached to the package substrate 200 to form a bonding assembly (800, 200).

[0107] Refer to steps 2230 and Figures 13A-19B A cover structure 900 is provided, which includes a bottom plate portion 912, a top plate portion 914 perpendicularly spaced from the bottom plate portion 912, a side wall frame portion 910 laterally surrounding a cavity 919 located between the bottom plate portion 912 and the top plate portion 914, and a second horizontal plane HP2 located within the side wall frame portion 910 and extending vertically from a first horizontal plane HP1 including the bottom surface of the bottom plate portion 912 to the top surface including the top plate portion 914.

[0108] Refer to step 2240 and Figures 13A-21GThe cover structure 900 can be attached to the bonding assembly (800, 200) such that the thermal interface material (TIM) layer 903 is inserted between at least one semiconductor die (701, 702, 703) and the base plate portion 912, wherein the solid cube portion 920 is completely outside the area of ​​at least one semiconductor die (701, 702, 703) in the vertical plan view, i.e., it does not overlap with any area of ​​at least one semiconductor die (701, 702, 703). It is worth noting that this plan view shows all structural elements regardless of whether they are covered by any overlying structural elements. Therefore, the plan view used in this disclosure is a perspective plan view.

[0109] Figure 23 This is a second flowchart illustrating the steps of testing a packaging structure according to an embodiment of this disclosure.

[0110] Refer to step 2310 and Figures 1 to 11B A composite package 800 is provided, comprising at least one semiconductor die (701, 702, 703) and a die frame 796.

[0111] Refer to step 2320 and Figure 12 The composite package 800 can be attached to the package substrate 200 to form a bonding assembly (800, 200).

[0112] Refer to steps 2330 and Figures 13A-19B A cover structure 900 is provided, comprising: a base plate portion 912, the bottom surface of which lies within a first horizontal plane HP1; a top plate portion 914, which is perpendicularly spaced from the base plate portion 912 and the top surface of which lies within a second horizontal plane HP2; a side wall frame portion 910, which laterally surrounds a cavity 919 located between the base plate portion 912 and the top plate portion 914; and a solid block portion 920, which is located within the side wall frame portion 910 and extends perpendicularly from the first horizontal plane HP1 to the second horizontal plane HP2.

[0113] Refer to steps 2340 and Figures 13A-19B The cover structure 900 can be attached to the bonding assembly (800, 200) to form a package structure, such that the thermal interface material (TIM) layer 903 is inserted between at least one semiconductor die (701, 702, 703) and the base plate portion 912, and the solid cube portion 920 is completely outside the area of ​​at least one semiconductor die (701, 702, 703) in a plan view along the vertical direction, that is, it does not overlap with any area of ​​at least one semiconductor die (701, 702, 703). It is worth noting that this plan view shows all structural elements, regardless of whether they are covered by any overlying structural elements.

[0114] Refer to step 2350 and Figures 20-21GThe presence of defects in the TIM layer 903 can be tested by generating and inspecting X-ray images of the encapsulation structure using an X-ray beam passing through the cover structure 900, the TIM layer 903, and the bonding assemblies (800, 200).

[0115] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the scope of this disclosure. Unless otherwise explicitly disclosed herein, each embodiment described using the term "comprises" inherently discloses additional embodiments in which the term "comprises" is replaced by "consists essentially of" or "composes of". Whenever two or more elements are listed as alternatives in the same paragraph or different paragraphs, a Markush group comprising the list of said two or more elements is also implicitly disclosed. Whenever the auxiliary verb "can" is used in this disclosure to describe forming an element or performing a processing step, embodiments in which such an element or processing step is not performed are expressly contemplated, provided that the resulting apparatus or device provides an equivalent result. Therefore, whenever omitting a forming element or processing step can provide the same or equivalent result, the auxiliary verb "may" applied to forming such an element or performing such a processing step should also be interpreted as "may" or "may, or may not," where the equivalent result includes results that are somewhat better or worse. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a packaging structure, characterized in that, The method includes: Provide a composite package comprising at least one semiconductor die and a die frame; The composite package is attached to the package substrate to form a bonding assembly; A cover structure is provided, the cover structure including a base plate portion, a top plate portion, a sidewall frame portion, and a solid block portion, the top plate portion being perpendicularly spaced from the base plate portion, the sidewall frame portion laterally surrounding a cavity located between the base plate portion and the top plate portion, the solid block portion being located within the sidewall frame portion and extending perpendicularly from a first horizontal plane including the bottom surface of the base plate portion to a second horizontal plane including the top surface of the top plate portion, and located in a corner region of the cover structure; and The cover structure is attached to the bonding assembly such that a thermal interface material (TIM) layer is inserted between the at least one semiconductor die and the base plate portion, wherein the solid cube portion is completely outside the region of the at least one semiconductor die in a plan view along the vertical direction.

2. The method according to claim 1, characterized in that, When the cover structure is attached to the bonding assembly, the TIM has an area of ​​overlap with the entirety of at least one semiconductor in the plan view.

3. The method according to claim 1, characterized in that, During the attachment of the cover structure to the bonding assembly, the cover structure is aligned with the bonding assembly such that the solid block portion does not overlap with the core frame in any area.

4. The method according to claim 1, characterized in that: The cover structure also includes a wall portion extending downward from the peripheral region of the base plate portion; and attaching the cover structure to the bonding assembly includes attaching the wall portion to the encapsulation substrate.

5. The method according to claim 1, characterized in that, It also includes testing the TIM layer for defects by generating and inspecting X-ray images of the encapsulation structure using an X-ray beam passing through the cover structure, the TIM layer, and the bonding assembly.

6. A method for manufacturing a packaging structure, characterized in that, The method includes: Provide a composite package comprising at least one semiconductor die and a die frame; The composite package is attached to the package substrate to form a bonding assembly; A cover structure is provided, the cover structure including a base plate portion, a top plate portion, a sidewall frame portion, and a solid block portion, wherein the bottom surface of the base plate portion is located in a first horizontal plane, the top plate portion is perpendicularly spaced from the base plate portion and its top surface is located in a second horizontal plane, the sidewall frame portion laterally surrounds a cavity located between the base plate portion and the top plate portion, and the solid block portion is located within the sidewall frame portion and extends perpendicularly from the first horizontal plane to the second horizontal plane; and An encapsulation structure is formed by attaching the cover structure to the bonding assembly, such that a thermal interface material (TIM) layer is inserted between the at least one semiconductor die and the base plate portion, and the solid cube portion is completely outside the region of the at least one semiconductor die in a plan view along the vertical direction.

7. The method according to claim 6, characterized in that, It also includes testing the TIM layer for defects by generating and inspecting X-ray images of the encapsulation structure using an X-ray beam passing through the cover structure, the TIM layer, and the bonding assembly.

8. The method according to claim 7, characterized in that, Examining the X-ray image includes locating areas where the thermal interface material of the TIM layer is absent or thinner than the surrounding area by identifying portions of the X-ray image that exhibit a higher detected X-ray dose level relative to the surrounding area.

9. The method according to claim 6, characterized in that: The solid block portion overlaps with the core frame in a partial area; and The method includes excluding the area where the solid block portion overlaps with the core frame when examining the X-ray image.

10. A packaging structure, characterized in that, include: The bonding assembly includes a composite package and a package substrate, wherein the composite package includes at least one semiconductor die and a die frame; as well as A cover structure is attached to the bonding assembly, wherein the cover structure includes a base plate portion, a top plate portion, a sidewall frame portion, and a solid block portion, the top plate portion being perpendicularly spaced from the base plate portion, the sidewall frame portion laterally surrounding a cavity located between the base plate portion and the top plate portion, the solid block portion being located within the sidewall frame portion and extending perpendicularly from a first horizontal plane including the bottom surface of the base plate portion to a second horizontal plane including the top surface of the top plate portion and located in a corner region of the cover structure, wherein the solid block portion is completely outside the region of the at least one semiconductor die in a plan view along the vertical direction.

Images