Stacked die electronic device with integrated magnetic elements

Abstract

The present application relates to a stacked-die electronic device with integrated magnetic elements. The electronic device includes a first semiconductor die (110) having a first terminal (115) and a first metallization structure (114) having a first coil (117), and a second semiconductor die (120) having opposite first and second sides (121, 122), a second terminal (125), a second metallization structure (124) including a second coil (127), and a dielectric layer (128) on the second side (122) of the second semiconductor die (120), the first semiconductor die (110) being bonded to the dielectric layer (128) of the second semiconductor die (120), and the second coil (127) being aligned with the first coil (117).

Description

Technical Field

[0001] This application generally relates to semiconductors, and more particularly to a stacked die electronic device having integrated magnetic elements. Background Technology

[0002] Power modules and communication devices may have circuitry that operates in different voltage domains connected to separate supply voltages. Device designs may include multi-chip modules (MCMs) with multiple dies having dedicated wafer fabrication process nodes with unique isolation dielectrics and components to provide isolation barriers between different voltage domains. However, these MCM devices typically require custom leadframe designs to provide split die-on-pads for isolation, increasing device size and cost. Silicon-on-insulator (SOI) devices allow monolithic isolation but are typically limited by lower isolation voltage ratings and are generally capacitive, making them unsuitable for power delivery across isolation barriers. Another monolithic isolation method uses back-side silicon trenches filled with dielectrics to form the isolation barrier, which is also limited by lower isolation voltage ratings and increases wafer handling costs. Capacitive isolation methods have very tight tolerance requirements for die assemblies, making them complex and expensive to manufacture. Summary of the Invention

[0003] In one aspect, an electronic device includes: a first semiconductor die having a first terminal and a first metallization structure having a first coil; and a second semiconductor die having opposing first and second sides, a second terminal, a second metallization structure containing a second coil, and a dielectric layer on the second side of the second semiconductor die, wherein the first semiconductor die is attached to the dielectric layer of the second semiconductor die, and the second coil is aligned with the first coil.

[0004] In another aspect, a system includes a circuit board having a first conductive feature and a second conductive feature, and an electronic device. The electronic device has a first semiconductor die and a second semiconductor die. The first semiconductor die has a first terminal coupled to the first conductive feature of the circuit board and a first metallization structure having a first coil. The second semiconductor die has opposing first and second sides, a second terminal coupled to the second conductive feature of the circuit board, a second metallization structure containing a second coil, and a dielectric layer on the second side of the second semiconductor die. The first semiconductor die is attached to the dielectric layer of the second semiconductor die, and the second coil is aligned with the first coil.

[0005] In another aspect, a method of manufacturing an electronic device includes: attaching a first semiconductor die to a second side of a second semiconductor die, wherein a first coil of the first semiconductor die is aligned with a second coil of the second semiconductor die; attaching a first opposite side of the second semiconductor die to a lead frame; electrically coupling a first terminal of the first semiconductor die to a first lead of the lead frame; and electrically coupling a second terminal of the second semiconductor die to a second lead of the lead frame. Attached Figure Description

[0006] Figure 1 A cross-sectional side view of an electronic device having a stacked first die and a second die, the first die and the second die having aligned corresponding first coils and second coils.

[0007] Figure 2 A flowchart of a first example method for manufacturing an electronic device.

[0008] Figure 2A A flowchart of another example method for manufacturing an electronic device.

[0009] Figures 3 to 11 for Figure 1 Electronic devices have undergone a process according to Figure 2 A partial side view of the manufacturing process of the implementation scheme of the method.

[0010] Figures 12 to 20 for Figure 1 Electronic devices have undergone a process according to Figure 2A A partial side view of the manufacturing process of the implementation scheme of the method.

[0011] Figure 21 A cross-sectional side view of an electronic device having a stacked first die and a second die, the first die and the second die having aligned corresponding first coils and second coils.

[0012] Figure 22 A cross-sectional side view of another electronic device having a stacked first die and a second die, the first die and the second die having aligned corresponding first coils and second coils.

[0013] Figure 23 A cross-sectional side view of another electronic device having a stacked first die and a second die, the first die and the second die having aligned corresponding first coils and second coils.

[0014] Figure 24 A cross-sectional side view of another electronic device having a stacked first die and a second die, the first die and the second die having aligned corresponding first coils and second coils. Detailed Implementation

[0015] In the figures, the same reference numerals refer to the same elements throughout, and the various features are not necessarily drawn to scale. Furthermore, the terms "coupled" or "couples" include indirect or direct electrical or mechanical connections or combinations thereof. For example, if a first device is coupled to or with a second device, the connection can be a direct electrical connection or an indirect electrical connection via one or more intervening devices and connections. The following describes one or more operational characteristics of various circuits, systems, and / or components in the context of function, which in some cases arise from the configuration and / or interconnection of various structures when the circuit system is energized and operated. Example structures include layers or materials described as being on or above another layer or material, which may be directly on and in contact with the other layer or material, wherein other materials (e.g., impurities or man-made products or residual materials from manufacturing processes) may be present between the layer or material and the other layer or material.

[0016] Unless otherwise stated, the words “about,” “approximately,” or “generally” preceding a value mean + / - 10% of the stated value. For ease of description in conjunction with specific figures, one or more structures, features, aspects, components, etc., may be referred to herein as first, second, third, etc., e.g., first terminal and second terminal, etc., where these should not be construed as limiting the claims. The various structures and methods disclosed herein can be advantageously applied to the manufacture of electronic devices, such as integrated circuits. While such examples may provide various improvements, this disclosure does not require a particular result unless expressly stated in a particular claim.

[0017] Figure 1 A compact electronic device 100 is shown, comprising a first semiconductor die 110 and a second semiconductor die 120. In this example, the first semiconductor die 110 is attached to the second semiconductor die 120 (e.g., stacked on top of the second semiconductor die). The first semiconductor die 110 in this example arrangement may be referred to as the stack or top die, and the second semiconductor die 120 may be referred to as the substrate or bottom die. The electronic device 100 also has onboard integrated magnetic features, such as transformer coils, providing isolation between the first semiconductor die 110 and the second semiconductor die 120 for induced power and / or signal transmission. The electronic device also includes conductive metal leads 107. The electronic device 100 is shown in an example three-dimensional space having a first direction X, a perpendicular (orthogonal) second direction (entering) Figure 1 (within the page) and a third direction Z perpendicular (or orthogonal) to the respective first and second directions. Structures or features along any two of these directions are orthogonal to each other.

[0018] Electronic device 100 has a molded package structure 108 having corresponding opposing first sides 101 and second sides 102 (e.g., bottom and top), the first and second sides being spaced apart from each other along a third direction Z in the illustrated location. The package structure 108 encloses an internal portion of a lead 107, and an external portion of the lead 107 extends outside corresponding third sides 103 and fourth sides 104 of the package structure 108. Electronic device 100 also has laterally opposing third sides 103 and fourth sides 104 spaced apart from each other along a first direction X, and fifth and sixth sides spaced apart from each other along a second direction. Figure 1 (Not shown). The package structure 108 at least partially encloses the semiconductor dies 110 and 120. The electronic device 100 also includes die bonding pads 109 supporting the second semiconductor die 120.

[0019] The vertically stacked arrangement of semiconductor dies 110 and 120 facilitates a compact form factor device with integrated transformer coupling between separate isolated voltage domains. In this example, dies 110 and 120 are stacked face-to-face, with the front sides of the dies facing each other. The first semiconductor die 110 has a first side 111 (e.g., the back side of the die) and an opposing second side 112 (e.g., the front side of the die), and the sides 111 and 112 are spaced apart from each other along a third direction Z. The first semiconductor die 110 includes a semiconductor layer 113, such as silicon, and a first metallization structure 114 on the semiconductor layer 113.

[0020] The first metallization structure 114 has multiple levels or layers, each individually including conductive metal features (e.g., copper, aluminum, etc.) and an interlayer dielectric (ILD) material such as silicon dioxide (SiO2, etc.). The first terminal 115 includes a metal feature in the first or lowest layer of the first metallization structure 114 that is closest to the semiconductor layer 113 and furthest from the second semiconductor die 120. In one example, the first terminal 115 is a first bonding pad 115, which is or includes conductive metal, such as aluminum or copper, exposed along a first side 111 of the first semiconductor die 110. In other examples, the first terminal may be a conductive metal via, such as a through-silicon via (TSV), or coupled to a conductive metal via, as follows: Figure 21 As shown in the image.

[0021] Figure 1 The first metallization structure 114 in the coil also has one or more conductive metal features 116 (e.g., turns) forming the first coil 117. Figure 1In one example, the first coil 117 includes the final or uppermost metal feature 116 of the first metallization structure 114, which is furthest from the semiconductor layer 113 and closest to the second semiconductor die 120. In the illustrated example, the first semiconductor die 110 has a first dielectric layer 118, such as silicon dioxide (SiO2, etc.). The first dielectric layer 118 extends over the first metallization structure 114 on a second side 112 of the first semiconductor die 110. A back-side trench 119 extends into a first side 111 of the first semiconductor die 110 to expose one side of a first terminal 115. The first terminal 115 is contacted by a first bonding wire 131 passing through the trench 119, and the bonding wire 131 is enclosed by a package structure 108.

[0022] The second semiconductor die 120 has a back side or first side 121 bonded to a die bonding pad 109, and a contrasting front side or second side 122 facing a second side 112 of the first semiconductor die 110. The second semiconductor die 120 includes a semiconductor layer 123, such as silicon, along the first side 121, and a second metallization structure 124 on the semiconductor layer 123. The second metallization structure 124 includes a second terminal 125 and conductive metal features 126 (e.g., turns) forming a second coil 127 of the second semiconductor die 120. The second semiconductor die 120 also includes a second dielectric layer 128 (e.g., SiO2, etc.) on the second side 122 of the second semiconductor die 120. The second dielectric layer 128 has an opening 129 exposing a portion of the top side of the second terminal 125. In one example, the second terminal 125 is a second bonding pad 125, which is or includes a conductive metal, such as aluminum or copper, exposed along the second side 122 of the second semiconductor die 120. The second terminal 125 is contacted by the second bonding wire 132 passing through the opening 129, and the package structure 108 fills the opening 129 and encloses the second bonding wire 132. The example electronic device 100 may also include additional surface mount components (not shown), such as one or more capacitors, resistors, diodes, etc., which may be enclosed by the package structure 108 and electrically coupled to one or more circuit systems in the semiconductor dies 110 and 120.

[0023] Figure 1The electronic device 100 has a face-to-face stacked die configuration, wherein the front side or second side 112 of a first semiconductor die 110 faces the front side or second side 122 of a second semiconductor die 120. A first dielectric layer 118 of the first semiconductor die 110 is bonded to the dielectric layer 128 of the second semiconductor die 120 via a non-conductive die bonding film or adhesive 130, such that the second side 112 of the first semiconductor die 110 is bonded to the second side 122 of the second semiconductor die 120 and faces the second side. The thicknesses of the dielectric layers 118 and 128 and the non-conductive adhesive 130 are set to a desired spacing distance 134 along the third direction Z between coils 117 and 127 to accommodate the design electrical isolation ratings of the electronic device 100.

[0024] The first bonding wire 131 has a first end coupled to the first terminal 115 and a second end coupled to a first conductive metal lead 107 inside the package structure 108. The second bonding wire 132 has a first end coupled to the second terminal 125 and a second end coupled to a second conductive metal lead 107 inside the package structure 108. Figure 1 A partial system view of a system having a circuit board 160 with a first conductive feature and a second conductive feature 162 is shown. The system includes an electronic device 100, wherein a first terminal 115 is electrically coupled to the first conductive feature 162 of the circuit board 160 via a bonding wire 131 and solder 161, the solder connecting a first lead 107 to the first conductive feature 162. A second terminal 125 is electrically coupled to the second conductive feature 162 of the circuit board 160 via corresponding solder connections 161 and the second lead 107.

[0025] Semiconductor dies 110 and 120 are along the first direction X and orthogonal to the second direction (to). Figure 1(In the view of the page) Laterally aligned such that the second coil 127 is aligned with the first coil 117. Lateral alignment of coils 117 and 127 facilitates operational magnetic coupling for signal and / or power transmission between coils 117 and 127, while maintaining electrical isolation between them. As used herein, the first coil 117 is aligned with the second coil 127 when the positions of corresponding conductive features 116 and 126 are within 10% of the designed position (as a percentage of the smaller of the line or conductive feature widths of conductive features 116 and 126). In some instances, the lateral alignment of coils 117 and 127 is affected by wafer processing variations during the manufacture of the first semiconductor die 110 and the second semiconductor die 120, and during the bonding of the first semiconductor die 110 to the second semiconductor die 120 when conductive features 116, 126 are generated. Perfect alignment is not required, and the first coil 117 is aligned with the second coil 127, such that the operational magnetic coupling of coils 117 and 127 allows power and / or signal transmission between coils 117 and 127.

[0026] In one example, the first coil 117 and the second coil 127 are designed to have the same feature width (e.g., conductive features 116 and 126 along...). Figure 1 The coils 117 and 127 are aligned such that the center of the common extension of the lines or features 116 and 126 is within 10% of the width of the design line or conductive feature at the relative design center position in the first and second directions. Coils 117 and 127 are also aligned when the coil structures in the corresponding metallized structures 114 and 124 are coplanar within 10 degrees. Coils 117 and 127 may have any suitable shape or pattern that provides magnetic coupling to allow power and / or signal transmission, such as a helix. Coils 117 and 127, and their conductive features 116 and 126, need not be designed to be common extensions or identical, and may have different sizes and shapes or patterns. Coils 117 and 127 may have the same or different numbers of turns. Individual coils 117 and 127 may have turns or portions 116 and 126 in a single layer or level of the respective metallization structures 114 and 124, or may have turns or portions 116 and 126 in more than one layer or level of the respective metallization structures 114 and 124. Any one or two of semiconductor dies 110 or 120 may have more than one coil to form a transformer with two or more windings (e.g., primary and secondary), or a single primary winding of one die 110 or 120 and two or more secondary windings of another die 120 or 110, and / or multiple transformers may have transformer coupling between the respective coils of the first die 110 and the second die 120.

[0027] For reference Figures 2 to 11, Figure 2 This demonstrates a first example method 200 for manufacturing electronic devices using chip-to-wafer bonding, and Figures 3 to 11 exhibit Figure 1 Example electronic devices 100 experience according to Figure 2 A partial side view of the manufacturing process of the embodiment of method 200. Figure 2A This demonstrates another example method 250 for manufacturing electronic devices using die-to-die bonding, and Figures 12 to 20 exhibit Figure 1 The example electronic device 100 undergoes a manufacturing process according to an embodiment of method 250, as further described below.

[0028] Methods 200 and 250 can be implemented to produce face-to-face stacked die arrangements, as by Figure 1 Semiconductor device 100 and further described below Figure 21 , 23 Examples of 24 and 250. Other implementations of method 200 or 250 can be used to produce different stacking arrangements, such as face-up stacking (e.g., bottom). Figure 22 Various implementations may include a variety of different electrical coupling techniques, including flip-chip die bonding, wire bonding, etc., and may be used in packages that include conductive metal features resulting from leadframe and / or substrate-based packaging, and may be adapted to incorporate other components (e.g., surface-mount capacitors, resistors, diodes, etc.) within the packaged electronics.

[0029] Figure 2 Method 200 begins at 202 with chip-to-wafer bonding to bond an instance of the first semiconductor die 110 to the second side 122 of the second semiconductor die cell region of the wafer. Figure 3 An example is shown in which a die bonding process 300 is performed relative to the illustrated cell regions 301 of a wafer 302 having multiple cell regions 301. In one example, the wafer 302 is processed to produce an example of the aforementioned second semiconductor die 120 in each cell region 301, for example, along a number of rows of cell regions 301 of the wafer 302 corresponding to the front or top side 122 of the second side 122 of each manufactured second semiconductor die 120. Furthermore, in the illustrated example, a first semiconductor die 110 is shown after previous wafer processing and die splitting (not shown), wherein the total die thickness T1 has an initial value taking into account subsequent backside grinding of the back side or first side 111 of the semiconductor die 110.

[0030] Figure 3The die bonding process 300 in the wafer 302 bonds a first semiconductor die 110 to a second side 122 of a desired second semiconductor die 120 of the wafer, wherein, for example, an automated pick-and-place device (not shown) is used to align a first coil 117 of the first semiconductor die 110 with a second coil 127 of the desired second semiconductor die 120. In one example, alignment is performed by controlling the position of the pick-and-place device relative to the position of the first semiconductor die 110 relative to an associated cell region of the processed wafer, such that, for example, an optical alignment device (not shown) is used to align the first coil 117 of the first semiconductor die 110 with the second coil 127 of the corresponding wafer cell region. In the illustrated example, a first dielectric layer 118 of the first semiconductor die 110 is bonded to the top side 122 of the second dielectric layer 128 of the wafer 302 by a die bonding film or adhesive 130. The bonding process 300 sets a spacing 134 along the third direction Z between the coils 117 and 127 according to the designed electrical isolation rating of the electronic device 100. In one example, process 300 includes initially forming (e.g., deposition, dispensing, screen printing, etc.) a die bonding film or adhesive 130 to an initial thickness along a third direction Z, such that subsequent bonding forces for bonding the first semiconductor die 110 to the die bonding film or adhesive 130 and any subsequent adhesive curing processes provide a desired spacing 134 between the first coil 117 and the second coil 127 along the third direction Z.

[0031] In one instance, method 200 is... Figure 2 The process continues at point 204, where the first semiconductor die 110 is back-grinded. In one instance, back-grinding may be a concurrent process of grinding the back side or first side 111 of each instance of the first semiconductor die 110 in the corresponding cell region 301 of the wafer 302. Figure 4 An example is shown in which a back-side grinding process 400 is performed to selectively remove material from a first side 111 of a first semiconductor die 110, and the process 400 continues until a final desired thickness T2 of the first semiconductor die 110 is achieved. The final thickness T2 of the first semiconductor die 110 can be adjusted according to the final package size specification of a given electronic device design (e.g., approximately 20 µm). In another embodiment, the thickness T2 can be omitted. Figure 2 Backside grinding at 204, for example, wherein backside grinding of the first semiconductor die 110 is performed during wafer processing before the first semiconductor die 110 is separated from or snapped into the first wafer (not shown).

[0032] Method 200 in Figure 2 The etching continues at 206, where etching is performed to form a trench in the back side or first side 111 of the first semiconductor die 110 to expose the first terminal 115 (e.g., bonding pad). Figure 5 An example is shown in which an etching process 500 is performed using a patterned etch mask 502, which exposes a portion of a first side 111 of a first semiconductor die 110 in each unit region 301. The patterned mask 502 can be formed using any suitable mask forming and patterning steps and materials (e.g., spraying a resist layer, exposing the deposited resist layer, and developing the exposed photoresist). Alternatively, any suitable etching chemical can be used in process 500 (e.g., plasma etching), which selectively removes semiconductor material (e.g., silicon) to form a trench 119 exposing one side of a first conductive terminal 115, followed by resist removal (e.g., stripping). In the illustrated example, the first terminal 115 is located in the initial layer of a multilayer metallization structure 114 of the first semiconductor die 110, which is closest to the semiconductor layer 113 and furthest from the first dielectric layer 118. The etching process 500 may include additional cleaning steps (not shown) to prepare the exposed surface of the first terminal 115 for subsequent electrical connection processing (e.g., wire bonding).

[0033] In one implementation, method 200 may include Figure 2 A through-silicon via (TSV) is formed at position 208. Figure 6 One example illustrates a deposition process 600 in which a conductive metal (e.g., copper, aluminum, etc.) is deposited in a previously formed trench 119 to form a conductive metal via 604 in the trench 119. In one example, a deposition mask 602 is used to perform the deposition process 600. In other embodiments, the mask 602 may be omitted. In one example, the deposition process 600 may be a copper plating process that selectively deposits copper 604 onto the first terminal 115 and continues deposition until the top side of the deposited copper via 604 is substantially planar with the first side 111 of the first semiconductor die 110. In other embodiments, the mask 602 may be omitted. Figure 2 Silicon via processing at position 208.

[0034] Method 200 continues at 210, wherein the second semiconductor die 120 is separated from the wafer 302. Figure 7 An example is shown (where a portion of the first terminal 115 is exposed in trench 119 without optional through-silicon vias), in which a die-separation process 700 is performed to separate an instance of the second semiconductor die 120 from the wafer 302 along a separation line 702. Any suitable package separation process 700 can be used, such as sawing, laser cutting, chemical etching, etc., or combinations thereof. The separated second semiconductor die 120 has an instance of the first semiconductor die 110 attached to it to provide a stacked die assembly, which can be further processed for use in a package as described below.

[0035] exist Figure 2 At position 212, method 200 further includes a second die bonding to bond the second semiconductor die 120 to a substrate or lead frame. Figure 8 An example is shown using a starting leadframe. In one example, the leadframe is a panel array structure with several rows and columns of cell regions, each cell region having a die bonding pad 109 and a desired lead 107. Figure 8 An example cell region of the starting lead frame is shown, in which a die bonding process 800 is performed to bond the back side or first side 121 of the second semiconductor die 120 to the top side of the die bonding pad 109. Any suitable die bonding process 800 can be used, for example, forming a die bonding film or adhesive (not shown) on a portion of the top side of the die bonding pad 109 in each cell region, and then, for example, using an automated pick-and-place device (not shown), bonding the second semiconductor die 120 to the die bonding film on the die bonding pad 109.

[0036] Method 200 in Figure 2 Continue at point 214, where in one instance, the electrical connection includes wire bonding. Figure 9 One example is shown where a wire bonding process 900 is performed to form a first bonding wire 131 between a first terminal 115 of a first semiconductor die 110 and a first intended lead 107 in the illustrated cell region of a leadframe panel array. The first bonding wire 131 is connected to the exposed top side of the first terminal 115 via a trench 119 etched in the semiconductor layer 113 of the first semiconductor die 110. The wire bonding process 900 also forms a second bonding wire 132 connecting a second terminal 125 of a second semiconductor die 120 to the second intended lead 107 in the illustrated cell region. The second bonding wire 132 is connected to the exposed top side of the second terminal 125 via an opening 129 in the second dielectric layer 123 of the second semiconductor die 120. In other embodiments, other types and forms of electrical connection processing may be performed, for example alone or in combination with wire bonding, using conductive metal jigs, flip-chip electrical interconnects (not shown).

[0037] Method 200 in Figure 2 Continue at point 216, where molding is performed to form a molded package structure 108. Figure 10An example is shown where a molding process 1000 is performed to form a molded package structure 108 that encloses bonding wires 131, 132, semiconductor dies 110, 120, die bonding pads 109, and the internal portion of a desired lead 107 in each cell region of the leadframe panel array. In one example, a single cavity may be used to form a monolithic magnetic molded structure 108 extending across all rows and columns of the leadframe panel array structure. In another embodiment, individual cavities may be used to form a corresponding molded magnetic package structure 108 in each cell region. In other embodiments, individual cavities may extend across two or more cell regions of the leadframe panel array structure, for example, to form the package structure 108 along rows or columns of the array structure.

[0038] exist Figure 2 At point 218, method 200 includes trimming and forming operations. Figure 11 An example is shown where a trimming and forming process 1100 is performed, in which the desired leads 107 between adjacent unit regions of the initial lead frame panel array structure are separated using a cutting blade or other suitable equipment (not shown), and the leads are formed into the final desired shape (e.g., gull-wing leads) using a stamping die or other suitable processing tool (not shown). In one example, method 200 may include optionally plating (not shown) the leads in each unit region of the panel array after molding at 216, the plating being possible... Figure 2 The lead wires at position 218 are trimmed and formed before, after, or in between.

[0039] In one instance, method 200 includes Figure 2 Further encapsulation and separation processing at position 220. Figure 11 Further illustrating an example in which an optional package separation process 1102 is performed to separate adjacent packaged electronics from each other along columns of the initial leadframe panel array structure, to provide the combination as described above. Figure 1 The described discrete packaged electronic device 100. In one example, the package separation process 1102 includes sawing to cut and separate the packaged electronic device. Figure 2 The column-length molded package structures formed at 216 in the array are separated from each other and cut through the connecting rod (not shown), which initially connects the die bonding pads 109 of the adjacent cell regions along the array column.

[0040] For reference Figure 2A and 12 Up to 20, Figure 2A Another example method 250 for manufacturing electronic devices is shown, and Figures 12 to 20 exhibit Figure 1 The example electronic device 100 undergoes a manufacturing process according to the embodiment of method 250.

[0041] Figure 2AMethod 250 begins at 252, in which the back of the first wafer is ground. Figure 12 An example of performing a back-side polishing process 1200 using a first wafer 1202 having a first side 111 and a second side 112 is shown. The wafer 1202 includes one or more cell regions 1201, each individually corresponding to a subsequently separated instance of a first semiconductor die 110. The wafer-level back-side polishing in this example alleviates or avoids the difficulties associated with polishing stack arrangements, as described above. Figure 2 In method 200, the back-side polishing process 1200 removes material from the first side 111 of the wafer 1202, and the process 1200 continues until the final desired thickness T2 of the first semiconductor die 110 is achieved. The final thickness T2 of the first semiconductor die 110 can be adjusted according to the final package size specification (e.g., approximately 20 µm) of a given electronic device design.

[0042] Method 250 in Figure 2A The etching continues at 254, wherein etching is performed to form trenches in each corresponding cell region 1201 of the back side or first side 111 of the wafer 1202 corresponding to the individual first semiconductor die 110. The etching at 254 exposes the first terminals 115 (e.g., bonding pads) of the metallization structure 114 of the wafer 1202 in each cell region 1201. Figure 13 An example is shown where an etching process 1300 is performed using a patterned etch mask 1302 to expose a portion of a first side 111 of a wafer 1202 in each unit region 1201. The patterned mask 1302 can be formed using any suitable mask forming and patterning steps and materials (e.g., spraying a resist layer, exposing the deposited resist layer, and developing the exposed photoresist). Alternatively, any suitable etching chemical can be used in process 1300 (e.g., plasma etching), which selectively removes semiconductor material (e.g., silicon) to form a trench 119 exposing one side of a first conductive terminal 115, followed by resist removal (e.g., stripping). In the illustrated example, the first terminal 115 is located in the initial layer of a multilayer metallization structure 114 of the first semiconductor die 110, which is closest to the semiconductor layer 113 and furthest from the first dielectric layer 118. The etching process 1300 may include additional cleaning steps (not shown) to prepare the exposed surface of the first terminal 115 for subsequent electrical connection processing (e.g., wire bonding).

[0043] In one implementation, method 250 may include Figure 2A The 256th silicon via (TSV) is formed. Figure 14An example is shown in which a deposition process 1400 is performed to deposit conductive metal (e.g., copper, aluminum, etc.) into a previously formed trench 119 to form a conductive metal via 1404 in the trench 119. In one example, a deposition mask 1402 is used to perform the deposition process 1400. In other embodiments, the mask 1402 may be omitted. In one example, the deposition process 1400 may be a copper plating process, selectively depositing copper 1404 onto the first terminal 115 and continuing deposition until the top side of the deposited copper via 1404 is substantially planar with the first side 111 of the first semiconductor die 110. In other embodiments, this may be omitted. Figure 2A Silicon via processing at position 256.

[0044] Method 250 in Figure 2A The process continues at point 258, where the first semiconductor die 110 is separated from the wafer 1202. Figure 15 An example is shown (in which a portion of the first terminal 115 is exposed in the trench 119 without optional through-silicon vias), wherein a die separation process 1500 is performed to separate an instance of the first semiconductor die 110 from the wafer 1202 along a separation line 1502. Any suitable package separation process 1500 can be used, such as sawing, laser cutting, chemical etching, or combinations thereof.

[0045] exist Figure 2A At position 260, method 250 continues with the first die bonding process to bond the second semiconductor die 120 to the substrate or lead frame. In this example, the instance of the second semiconductor die 120 has previously been processed at the wafer level and separated from the wafer. Figure 16 This example demonstrates 260 bonding operations using a starting leadframe. In one example, the leadframe is a panel array structure with several rows and columns of cell regions, each cell region having a die bonding pad 109 and a desired lead 107. Figure 16 An example cell region of the starting lead frame is shown, in which a die bonding process 1600 is performed to bond the back side or first side 121 of the second semiconductor die 120 to the top side of the die bonding pad 109. Any suitable die bonding process 1600 can be used, for example, forming a die bonding film or adhesive (not shown) on a portion of the top side of the die bonding pad 109 in each cell region, and then, for example, using an automated pick-and-place device (not shown), bonding the second semiconductor die 120 to the die bonding film on the die bonding pad 109.

[0046] Method 250 in Figure 2AContinue at position 262, perform chip-to-chip die bonding, so that after the second semiconductor die 120 has been bonded to the lead frame or substrate, the separated first semiconductor die 110 is bonded to the second side 122 of the second semiconductor die 120. Figure 17 An example is shown in which a die bonding process 1700 is performed to bond a first semiconductor die 110 to a second side 122 of a second semiconductor die 120, wherein, for example, an automated pick-and-place device (not shown) is used to align a first coil 117 of the first semiconductor die 110 with a second coil 127 of the second semiconductor die 120. In one example, alignment is performed by controlling the position of the pick-and-place device relative to the position of the first semiconductor die 110 relative to an associated cell region of the processed wafer, such that, for example, an optical alignment device (not shown) is used to align the first coil 117 of the first semiconductor die 110 with the second coil 127 of the corresponding wafer cell region. In the illustrated example, a first dielectric layer 118 of the first semiconductor die 110 is bonded to the top side 122 of the second dielectric layer 128 of the wafer 1702 by a die bonding film or adhesive 130. The bonding process 1700 sets a spacing 134 along the third direction Z between the coils 117 and 127 according to the design electrical isolation rating of the electronic device 100. In one example, process 1700 includes initially forming (e.g., deposition, dispensing, screen printing, etc.) a die bonding film or adhesive 130 to an initial thickness along a third direction Z, such that subsequent bonding forces for bonding the first semiconductor die 110 to the die bonding film or adhesive 130 and any subsequent adhesive curing processes provide a desired spacing 134 between the first coil 117 and the second coil 127 along the third direction Z.

[0047] Method 250 in Figure 2A Continue at point 264, where in one instance, electrical connections are made via wire bonding. Figure 18 One example is shown where a wire bonding process 1800 is performed to form a first bonding wire 131 between a first terminal 115 of a first semiconductor die 110 and a first intended lead 107 in the illustrated cell region of a leadframe panel array. The first bonding wire 131 is connected to the exposed top side of the first terminal 115 via a trench 119 in the semiconductor layer 113 of the first semiconductor die 110. The wire bonding process 1800 also forms a second bonding wire 132 between a second terminal 125 of a second semiconductor die 120 and a second intended lead 107 in the illustrated cell region. The second bonding wire 132 is connected to the exposed top side of the second terminal 125 via an opening 129 in the second dielectric layer 123 of the second semiconductor die 120. In other embodiments, other types and forms of electrical connection processing may be performed, for example alone or in combination with wire bonding, using conductive metal jigs, flip-chip electrical interconnects (not shown).

[0048] Method 250 in Figure 2A Continue at position 266, where molding is performed to form a molded package structure 108. Figure 19 An example is shown where a molding process 1900 is performed to form a molded package structure 108. In this example, the package structure encloses the internal portions of the intended leads 107 in each cell region of the bonding wires 131, 132, semiconductor dies 110, 120, die bonding pads 109, and the leadframe panel array. In one example, a single cavity may be used to form a monolithic magnetic molded structure 108 extending across all rows and columns of the leadframe panel array structure. In another embodiment, individual cavities may be used to form a corresponding molded magnetic package structure 108 in each cell region. In other embodiments, individual cavities may extend across two or more cell regions of the leadframe panel array structure, for example, to form the package structure 108 along rows or columns of the array structure.

[0049] exist Figure 2A At point 268, method 250 includes trimming and forming operations. Figure 20 An example is shown where a trimming and forming process 2000 is performed, in which the desired leads 107 between adjacent unit regions of the initial lead frame panel array structure are separated using a cutting blade or other suitable equipment (not shown), and the leads are formed into the final desired shape (e.g., gull-wing leads) using a stamping die or other suitable processing tool (not shown). In one example, method 250 may include optionally plating (not shown) the leads in each unit region of the panel array after molding at 266, the plating being possible... Figure 2A The 268 leads are trimmed and formed before, after, or in between.

[0050] In one instance, method 250 includes Figure 2A Further encapsulation and separation processing at position 270. Figure 20 Further illustrating an example in which an optional package separation process 2002 is performed, separating adjacent packaged electronics from each other along columns of the initial leadframe panel array structure to provide the combination described above. Figure 1 The described discrete packaged electronic device 100. In one example, the package separation process 2002 includes sawing to cut and separate the packaged electronic device. Figure 2A The column-length molded package structures formed at position 266 are separated from each other and cut through connecting rods (not shown), which initially connect the die bonding pads 109 of adjacent cell regions along the array column.

[0051] Figure 21A cross-sectional side view of an electronic device 2100 is shown, comprising a stacked first semiconductor die 110 and a second semiconductor die 120 (face-to-face), the first and second semiconductor dies having aligned first coils 117 and second coils 127, respectively. The electronic device 2100 includes, as described above... Figure 1 The electronic device 100 describes similarly numbered structures, features, components, etc. In this example, the first terminal of the first semiconductor die 110 includes a conductive metal via 604 (e.g., copper), which extends in a trench 119 on the top surface of the conductive metal terminal 115 of the first metallized structure 114 and is exposed along a first side 111 of the first semiconductor die 110. As described above... Figure 6 and 14 As described, the conductive metal via 604 can be used during wafer processing (e.g., during the separation of the first wafer from the first semiconductor die 110) Figure 2 and 6 Method 200) forms, or trench 119 and conductive metal via 604 can be formed during packaging after the first semiconductor die 110 is attached to the second semiconductor die 120 (e.g., on top). Figure 2A and 14 The method 250) is used to form the electronic device 2100. In this example, the first bonding wire 131 of the electronic device 2100 has a first end connected to the top side of the conductive metal via 604 and a second end connected to the first lead 107.

[0052] Figure 22 Another example of an electronic device 2200 is shown, having a first semiconductor die 2210 and a second semiconductor die 120 stacked accordingly, the first semiconductor die and the second semiconductor die having an aligned first coil 117 and a second coil 127, respectively. Figure 22 The electronic device 2200 in the middle has the same characteristics as described above. Figure 1 The electronic device 100 describes similarly numbered structures, features, components, etc. In this example, a first side 111 of a first semiconductor die 2210 is attached to a second side 122 of a second semiconductor die 120 and faces the second side. The front side or second side 112 of the first semiconductor die 2210 faces away from the second semiconductor die 120 (e.g., in a face-up stacked arrangement), and the back side or first side 111 of the first semiconductor die 2210 is attached to the front side or second side 122 of the second semiconductor die 120 by die bonding adhesive 130. Figure 22In the electronic device 2200, the first coil 117 of the first semiconductor die 2200 includes a metal feature 116 of the first metallization structure 114 that is closest to the lowest layer of the second semiconductor die 120. The first terminal 115 includes a metal feature 116 of the first metallization structure 114 that is furthest from the uppermost layer of the second semiconductor die 120, and the first terminal 115 is contacted by a first bonding wire 131 passing through an opening 2219 in the first dielectric layer 118 of the first semiconductor die 110.

[0053] Figure 23 Another example of an electronic device 2300 is shown, having a first die 2310 and a second die 2320 stacked face-to-face, the first die and the second die having aligned first coil 2307 and second coil 2327, respectively. Unless otherwise described below, Figure 23 The electronic device 2300 includes components substantially corresponding to those described above. Figure 1 The electronic device 100 is illustrated and described with structures, features, components, etc. 101 to 104, 107, 108 and 110 to 130, and structures, features, components, etc. 2301 to 2304, 2307, 2308 and 2310 to 2330. The electronic device 2300 is shown mounted using conductive feature 2362. Figure 23 The system configuration is located on circuit board 2360. The system includes electronic device 2300, wherein a first terminal 2315 is electrically coupled to a first conductive feature 2362 of circuit board 2360 via bonding wire 2331 and solder 2361, the solder connecting a first lead 2307 to the first conductive feature 2362. A second terminal 2325 is electrically coupled to a second conductive feature 2362 of circuit board 2360 via corresponding solder connection 2361 and the second lead 2307.

[0054] Electronic device 2300 has a multilayer package substrate 2350 (e.g., also referred to as a wireable leadframe) with leads 2307 configured to be soldered to conductive features 2362 of a circuit board 2360. In this example, terminals 2315 and 2325 of corresponding first semiconductor dies 2310 and second semiconductor dies 2320 are flip-chip soldered to corresponding conductive features on the top side of the multilayer package substrate 2350. The illustrated example also includes surface mount components (e.g., resistors, capacitors, inductors, additional dies, etc.), such as capacitors C1 and C2, which are soldered to pads on the top side of the multilayer package substrate 2350 and couple leads 2307 to corresponding terminals 2315 and 2325 (e.g., for AC or capacitive differential signal coupling). In other embodiments, passive components C1 and C2 may be omitted, and / or terminals 2315 and 2325 may be directly coupled to the corresponding leads 2307 of electronic device 2300.

[0055] The first semiconductor die 2310 has a back side or a first side 2311, which is connected to the front side or a second side 2322 of the second semiconductor die 2320 by a die bonding adhesive 2330. The front side or the second side 2312 of the first semiconductor die has a first semiconductor layer 2313, which is spaced apart from and faces the top side of the multilayer packaging substrate 2350. The first terminal 2315 of the first semiconductor die 2310 is a first metal pillar 2341 coupled to the die terminal 2315 and the conductive metal via 604 in the back trench 2319 (e.g., as described above). Figure 6 , 14 (As described in section 21). In one example, the first metal pillar 2341 is or comprises a conductive metal (e.g., copper, aluminum, etc.) and is formed during manufacturing, for example, by a bumping process or electroplating (not shown). The pillar 2341 is flip-chip bonded (e.g., soldered) to a corresponding conductive metal feature (e.g., a pad) on the top side of the multilayer package substrate 2350. The second terminal 2325 of the second semiconductor die 2320 has a die terminal 2315 coupled to the second metal pillar 2342, which is coupled (e.g., flip-chip soldered) to a second conductive feature along the top side of the multilayer package substrate 2360. The coupled metal pillars 2341 and 2342 of the substrate 2352 can be routed to any suitable connection point, such as the counterpart in lead 2307 of electronic device 2300, other components, or dies (e.g., the counterparts in capacitors C1, C2, etc.). In the illustrated example, a metal via 604 in a trench 2319 extending into a first side 2311 of a first semiconductor die 2310 contacts a first terminal 2315 of the first semiconductor die 2310 to provide a back-side flip-chip terminal connection to a substrate 2350, while positioning a first coil 2317 close to a second coil 2327.

[0056] Figure 24 Another electronic device 2400 is shown, having a first die 2410 and a second die 2420 stacked in a face-to-face arrangement, the first die and the second die having aligned corresponding first coils and second coils. Unless otherwise described below, Figure 24 The electronic device 2400 includes components generally corresponding to those described above. Figure 1 The electronic device 100 is illustrated and described with structures, features, components, etc. 101 to 104 and 107 to 132, and structures, features, components, etc. 2401 to 2404 and 2407 to 2432. The electronic device 2400 is shown as being mounted using conductive feature 2462. Figure 24The system configuration is on circuit board 2460. The system includes electronic device 2400, wherein a first terminal 2415 is electrically coupled to a first conductive feature 2462 of circuit board 2460 via bonding wire 2431 and solder 2461, the solder connecting a first lead 2407 to the first conductive feature 2462. A second terminal 2425 is electrically coupled to a second conductive feature 2462 of circuit board 2460 via corresponding solder connection 2461 and the second lead 2407.

[0057] Figure 24 The electronic device 2400 has a face-to-face flip-chip die-to-die bonding structure, wherein a first terminal 2415 of a first semiconductor die 2410 includes a conductive metal pillar 2441 (e.g., copper, aluminum, etc.). In one example, the metal pillar 2441 is formed during the fabrication of the first semiconductor die 2410, for example, by a bumping process (e.g., electroplating). The conductive metal pillar 2441 is coupled to a first top metal feature 2425 of a second semiconductor die 2420, for example, by flip-chip bonding. A first bonding wire 2431 has a first end coupled (e.g., bonded) to the first top metal feature 2425 through a corresponding opening in the dielectric layer 2428 of the second semiconductor die 2420, and a second end coupled to a first of device leads 2407. A second terminal 2425 of the second semiconductor die 2420 is coupled to another of the device leads 2407 via a second bonding wire 2432. Flip-chip bonding of the first semiconductor die 2410 to the second semiconductor die 2420 facilitates low-cost manufacturing while providing face-to-face proximity positioning of the first coil 2417 and the second coil 2427, spaced apart by a pitch distance 2434. Additionally... Figure 24 This example avoids back-side etching of the first semiconductor die 2410 to provide connection points for the first bonding wire 2431. Additionally, Figure 24 The electronic device 2400 does not require any through-silicon via (TSV) processing. The vertical coil spacing distance 2434 and the lateral spacing distance D between the second coil 2427 and the first terminal 2425 are adjustable to suit the desired isolation level for a given design.

[0058] The described examples and variations can be used to provide voltage isolation and signal and / or power transfer between different voltage domains in a compact package using operatively coupled coils with stacked dies, such as low-voltage and high-voltage power / signal transfer, receive and transmit signal transfer, etc. Various stacking arrangements can be used, such as face-to-face (...). Figure 1 , 21 23 and 24), facing up ( Figure 22 ), and via bond lines (e.g., Figure 1 , 21 22 and 24) and / or flip chip soldering / bonding ( Figure 23 and24 Interconnection. In face-to-face stacking configurations, the dielectric layer of the die (e.g., SiO2 or other passivation protective outer coating (PO) layer) contributes to the dielectric to achieve the desired amount of voltage isolation. The described examples provide inductive isolation, where die placement tolerances from standard pick-and-place equipment can be used without any performance degradation, and robust power delivery and signal isolation are provided. Different assembly methods can be used to bond stacked dies, including die-to-die bonding (individual die stacking), chip-to-wafer (C2W) die stacking, wafer-to-wafer bonding, or other methods. In any stacking method, no custom leadframe design is required, and low-cost (e.g., stamped) leadframes or single-level or multi-level substrates can be used. Various implementations have specific benefits and advantages, such as in chip-to-wafer stacking (e.g., Figure 2 In the case of method 200), die stacking is decoupled from packaging or assembly processes, and the costs associated with multi-chip modules (MCMs) can be reduced or avoided. Some instances may use any suitable electrical coupling for interconnects, such as back-side etching to expose wire bonding pads, using through-silicon vias (TSVs) to provide interconnects, etc.

[0059] Within the scope of the claims, modifications may be made to the described examples, and other embodiments are possible.

Claims

1. An electronic device comprising: A first semiconductor die having a first terminal and a first metallization structure having a first coil; and The second semiconductor die has opposing first and second sides, a second terminal, a second metallization structure containing a second coil, and a dielectric layer on the second side of the second semiconductor die, wherein the first semiconductor die is attached to the dielectric layer of the second semiconductor die, and the second coil is aligned with the first coil.

2. The electronic device of claim 1, wherein the second terminal of the second semiconductor die is exposed through an opening in the dielectric layer of the second semiconductor die.

3. The electronic device according to claim 2, wherein: The first bonding wire is coupled to the first terminal; The first terminal of the first semiconductor die is a first bonding pad or a first via exposed along a first side of the first semiconductor die; The opposite second side of the first semiconductor die is attached to the second side of the second semiconductor die; The second bonding wire is coupled to the second terminal; and The second terminal of the second semiconductor die is the second bonding pad.

4. The electronic device according to claim 1, wherein: The first terminal of the first semiconductor die is a first metal pillar coupled to the substrate; and The second terminal of the second semiconductor die is a second metal pillar coupled to the substrate.

5. The electronic device of claim 1, wherein the first semiconductor die is bonded to the dielectric layer of the second semiconductor die by a non-conductive adhesive.

6. The electronic device according to claim 1, wherein: The first semiconductor die has opposing first and second sides; The first semiconductor die has a first dielectric layer on the first metallization structure on the second side of the first semiconductor die; The dielectric layer of the second semiconductor die is a second dielectric layer; and The second side of the first semiconductor die is attached to the second side of the second semiconductor die and faces the second side.

7. The electronic device according to claim 6, wherein: The first coil includes the metal feature of the first metallization structure that is closest to the topmost layer of the second semiconductor die; The first terminal includes a metal feature in the lowest layer of the first metallization structure furthest from the second semiconductor die; and The first terminal is a trench contact that extends from the first bonding wire through the first side of the first semiconductor die.

8. The electronic device of claim 6, wherein the first terminal of the first semiconductor die is contacted by a metal via extending into a trench in the first side of the first semiconductor die.

9. The electronic device of claim 6, wherein the first terminal of the first semiconductor die is contacted by a first metal pillar coupled to a substrate or coupled to the second semiconductor die.

10. The electronic device according to claim 1, wherein: The first semiconductor die has opposing first and second sides; The first semiconductor die has a first dielectric layer on the first metallization structure on the second side of the first semiconductor die; The dielectric layer of the second semiconductor die is a second dielectric layer; and The first side of the first semiconductor die is attached to the second side of the second semiconductor die and faces the second side.

11. The electronic device according to claim 10, wherein: The first coil includes the metal feature of the lowest layer of the first metallization structure that is closest to the second semiconductor die; The first terminal includes a metal feature in the uppermost layer of the first metallization structure furthest from the second semiconductor die; and The first terminal is contacted by a first bonding wire passing through an opening in the first dielectric layer of the first semiconductor die.

12. The electronic device of claim 1, wherein the first semiconductor die flip chip is bonded to the second semiconductor die.

13. A system comprising: A circuit board having a first conductive characteristic and a second conductive characteristic; and An electronic device having a first semiconductor die and a second semiconductor die, the first semiconductor die having a first terminal coupled to a first conductive feature of a circuit board and a first metallization structure having a first coil, the second semiconductor die having opposing first and second sides, a second terminal coupled to the second conductive feature of the circuit board, a second metallization structure containing a second coil, and a dielectric layer on the second side of the second semiconductor die, the first semiconductor die being attached to the dielectric layer of the second semiconductor die, and the second coil being aligned with the first coil.

14. The system of claim 13, wherein the second terminal of the second semiconductor die is exposed through an opening in the dielectric layer of the second semiconductor die.

15. The system according to claim 13, wherein: The first bonding wire is coupled to the first terminal; The first terminal of the first semiconductor die is a first bonding pad or a first via exposed along a first side of the first semiconductor die; The opposite second side of the first semiconductor die is attached to the second side of the second semiconductor die; The second bonding wire is coupled to the second terminal; and The second terminal of the second semiconductor die is the second bonding pad.

16. The system of claim 13, wherein the first semiconductor die is bonded to the dielectric layer of the second semiconductor die by a non-conductive adhesive.

17. The system according to claim 13, wherein: The first semiconductor die has opposing first and second sides; The first semiconductor die has a first dielectric layer on the first metallization structure on the second side of the first semiconductor die; The dielectric layer of the second semiconductor die is a second dielectric layer; and The second side of the first semiconductor die is attached to the second side of the second semiconductor die and faces the second side.

18. A method of manufacturing an electronic device, the method comprising: A first semiconductor die is attached to the second side of a second semiconductor die, wherein a first coil of the first semiconductor die is aligned with a second coil of the second semiconductor die; The second semiconductor die is attached to the lead frame from the opposite first side. The first terminal of the first semiconductor die is electrically coupled to the first lead of the lead frame; and The second terminal of the second semiconductor die is electrically coupled to the second lead of the lead frame.

19. The method of claim 18, wherein: The first semiconductor die has opposing first and second sides; The first semiconductor die has a first dielectric layer on a first metallization structure on the second side of the first semiconductor die; The second semiconductor die has a second dielectric layer on the second metallization structure on the second side of the second semiconductor die; and Attaching the first semiconductor die to the second side of the second semiconductor die includes attaching the second side of the first semiconductor die to the second side of the second semiconductor die using a non-conductive adhesive.

20. The method of claim 19, wherein electrically coupling the first terminal of the first semiconductor die to the first lead of the lead frame comprises: A trench is formed that extends into the second side of the first semiconductor die to expose the first terminal; and A bonding wire connection is formed through the groove to the first terminal.

21. The method of claim 19, wherein electrically coupling the first terminal of the first semiconductor die to the first lead of the lead frame comprises: A trench is formed that extends into the second side of the first semiconductor die to expose the first terminal; Metal through-holes are formed in the trench; and A bonding wire connection is formed to the metal via.

22. The method of claim 18, wherein attaching the first semiconductor die to the second side of the second semiconductor die comprises attaching a flip chip of the first semiconductor die to the second semiconductor die.

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