A power chip packaging structure and method based on aEASI technology

Abstract

The application discloses a power chip packaging structure and method based on aEASI technology, which comprises etching a cavity on an organic substrate; preparing a W-shaped lead frame with a notch; mounting Mosfet chips and power chips on the upper and lower surfaces of the lead frame respectively to form a symmetrical layout; embedding the chip-lead frame assembly into the cavity, filling dielectric material and laminating copper foil to form a package; forming a through hole by laser drilling, filling and forming a vertical conductive column by electroplating, and forming a copper layer on the upper and lower surfaces; sequentially manufacturing fan-out conductive structures on the copper layers on both sides; finally, performing solder mask processing, setting pads, planting solder balls on the lower surface, and attaching heat sinks on the upper surface through eutectic and high-thermal-conductivity glue. The structure replaces gold wires with vertical conductive columns, greatly reducing parasitic inductance; in combination with the W-shaped lead frame and double-sided heat dissipation design, the heat dissipation efficiency and power density are significantly improved, and the structure is suitable for high-power and high-frequency switching application scenarios.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology for filling equipment, and relates to a power chip packaging structure and method based on aEASI technology. Background Technology

[0002] As electronic devices evolve towards higher performance, smaller size, and lower power consumption, semiconductor packaging technology faces numerous challenges. Traditional packaging methods typically use gold wires to connect the chip to the substrate, but this generates significant parasitic inductance during high-frequency switching, affecting circuit efficiency. Simultaneously, if the heat generated by high-power components (such as automotive inverters) cannot be effectively dissipated, it can lead to package delamination or die cracks, reducing product reliability.

[0003] While existing embedded packaging technologies such as aEASI P1 and P2 have made some improvements, they still have limitations. aEASI P1 has a simple structure, but its parasitic resistance and inductance are high, making it only suitable for simple power conversion. aEASI P2 introduces a single-sided redistribution layer (RDL), which improves heat dissipation and electrical performance, but under extremely high frequency currents (e.g., >60A), its thermal stress management and dielectric layer thickness control precision are insufficient, which can easily lead to reliability issues. Summary of the Invention

[0004] The purpose of this invention is to provide a power chip packaging structure and method based on aEASI technology, which achieves lower parasitic inductance, excellent heat dissipation performance and high reliability, and meets the requirements of high power application scenarios.

[0005] The objective of this invention is achieved through the following technical solution: A method for manufacturing a power chip package structure based on aEASI technology includes the following steps: Step 1: Etch to form cavities on an organic substrate; Step 2: Provide a copper alloy substrate and form a W-shaped lead frame with notches through a stamping process; Step 3: Mount a MOSFET chip in the recessed area of ​​the lead frame and attach a temporary substrate to the upper surface of the lead frame; flip the assembly over and mount a power chip on the protruding position on the back of the lead frame, with the power chip positioned opposite to a MOSFET chip. Step 4: The dielectric material board is pre-placed in the cavity of the organic substrate. The lead frame is cut along the notch, the temporary substrate is removed, and it is placed into the cavity. The same dielectric material as the dielectric material board is used for encapsulation and filling to form an encapsulation body. The encapsulation body is laminated with copper foil at the opening of the organic substrate. Step 5: Using a CO2 laser, drill holes in the package from the top surface of the copper foil and the bottom of the organic substrate to form a micro-hole interconnection path. The micro-hole interconnection path consists of several through holes, which are in contact with the power chip, MOSFET chip and lead frame. Step 6: Electroplating is performed on the upper and lower surfaces of the package to fill the through holes and form conductive pillars, and a first copper layer and a second copper layer are formed on the upper surface of the copper foil and the bottom of the organic substrate. Step 7: Attach a temporary substrate to one side of the first copper layer, and then expose, develop and etch the second copper layer to remove excess copper layer, retaining the portion of copper layer connected to the conductive pillar. On this basis, a redistribution layer preparation process is used to form the first fan-out conductive structure. Step 8: Remove the temporary substrate attached to the first copper layer and attach a new temporary substrate to the first fan-out conductive structure; then expose, develop and etch the first copper layer to remove excess copper layer and retain the portion of copper layer connected to the conductive pillars. On this basis, a redistribution layer preparation process is used to form the second fan-out conductive structure. Step 9: Apply solder resist green paint to the surfaces of the first fan-out conductive structure and the second fan-out conductive structure and set pads; form BGA solder balls on the pads on one side of the first fan-out conductive structure, first eutecticly set a pre-formed metal layer on the pads on one side of the second fan-out conductive structure, and then attach a heat sink to the pre-formed metal layer with high thermal conductivity adhesive.

[0006] As a further improvement of the present invention, the copper alloy substrate used in step 2 is a Cu-Fe-P alloy.

[0007] As a further improvement of the present invention, in step 3, transient liquid phase diffusion bonding technology is used to mount the MOSFET chip and the power chip.

[0008] As a further improvement of the present invention, the current density of the electroplating process in step 6 is 1-3 A / dm², and the temperature is 20-30℃.

[0009] As a further improvement of the present invention, the lamination process in step 4 is carried out at a pressure of 0.8-1.2 MPa and a temperature of 120-150°C.

[0010] A power chip packaging structure based on aEASI technology, fabricated using the above method, includes: An organic substrate with an internal cavity; A package is disposed within the cavity, and the package contains a lead frame and a MOSFET chip and a power chip respectively mounted on the upper and lower surfaces of the lead frame. Multiple vertically interconnected conductive pillars penetrate the package and are electrically connected to the power chip, MOSFET chip and lead frame, respectively. The first fan-out conductive structure and the second fan-out conductive structure are respectively disposed on the upper and lower sides of the package and electrically connected to the conductive pillar; Solder resist and pads are disposed on the surfaces of the first fan-out conductive structure and the second fan-out conductive structure; In this design, BGA solder balls are provided on the pads on one side of the first fan-out conductive structure, and heat sinks are attached to the pads on one side of the second fan-out conductive structure using high thermal conductivity adhesive.

[0011] As a further improvement of the present invention, the lead frame is a W-shaped structure made of Cu-Fe-P alloy material, and the thickness of its chip mounting area is 300μm.

[0012] As a further improvement of the present invention, the conductive pillar is formed by electroplated copper filling through holes with a diameter of 50μm-100μm.

[0013] The above technical solution has the following beneficial effects: 1. By replacing gold wires with vertical conductive posts, an extremely short electrical path is achieved, which significantly reduces parasitic inductance and resistance, making it particularly suitable for high-frequency, high-efficiency power switching applications; 2. The combination of a double-sided chip layout and a W-shaped thick copper lead frame creates a symmetrical and efficient heat conduction path. Simultaneously, BGA solder balls and external heat sinks are integrated on both sides of the package, achieving active heat dissipation on both sides, significantly reducing thermal resistance and ensuring reliable operation in high-power scenarios. 3. Optimized lamination process and dielectric material filling ensure the compactness of the package, effectively preventing delamination and bubbles. The double-sided fan-out conductive structure improves wiring flexibility and I / O density, enabling high power density miniaturized packaging. Attached Figure Description

[0014] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0015] The structures, proportions, sizes, etc. shown in this specification are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0016] Figure 1 This is a schematic diagram of the process provided by the present invention.

[0017] Figure 2 This is a schematic diagram of the power chip packaging structure provided by the present invention.

[0018] In the picture: 1. Organic substrate; 101. Cavity; 2. Conductor frame; 201. Notch; 3. MOSFET chip; 4. Power supply chip; 5. Encapsulation body; 51. Dielectric material board; 52. Copper foil; 61. Via; 62. Conductive post; 63. First copper layer; 64. Second copper layer; 65. Bump; 71. First fan-out conductive structure; 72. Second fan-out conductive structure; 81. Solder resist green paint; 82. Solder pads; 83. High thermal conductivity adhesive; 84. Heat sink. Detailed Implementation

[0019] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction of the component itself; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not intended to limit this invention.

[0020] First embodiment, such as Figure 1 As shown, a method for manufacturing a power chip package structure based on aEASI technology aims to improve the conductivity, structural stability, and thermal conductivity of the package structure. The specific implementation steps are as follows: Step 1: The organic substrate 1 can be a commonly used packaging organic substrate such as epoxy resin substrate or BT resin substrate. The cavity 101 that conforms to the size of Power IC is precisely processed by etching process, with the tolerance controlled within ±5μm to ensure the compatibility of subsequent chip mounting.

[0021] Step 2: Select a Cu-Fe-P alloy material (such as C19400 alloy) as the leadframe substrate. This substrate has a copper content of approximately 97%, a softening temperature of 1250℃, and a conductivity ≥60%, effectively ensuring the conductivity and structural stability of the packaging structure. The leadframe substrate is then processed into a W-shaped leadframe 2 using a stamping process. The stamped leadframe 2 has pre-drilled notches 201 for subsequent cutting. The number and position of the notches 201 can be adjusted according to the subsequent cutting process. The thickness of the area used for chip placement can be adapted within the range of 280μm-320μm, preferably 300μm, to ensure the flatness of the structure after chip mounting.

[0022] Step 3: Precisely mount the MOSFET chip 3 within the recessed area of ​​the leadframe 1. Eutectic bonding can be used during mounting, relying on TLPB (Transient Liquid Phase Diffusion Bonding) technology to achieve high-strength mechanical and electrical interconnection of the MOSFET chip 3. After mounting, attach a temporary substrate to the upper surface of the leadframe 1 to temporarily protect and position the MOSFET chip 3 and the upper structure of the leadframe 2. Then, rotate the entire leadframe 2 180 degrees so that the back side faces upwards. Subsequently, mount the power chip 4 on the protruding position on the back side of the leadframe 2. The power chip 4 and one of the MOSFET chips 3 are symmetrically distributed on both sides of the leadframe 2, with a symmetry deviation not exceeding 10μm, forming a balanced symmetrical heat conduction path. This effectively improves the heat dissipation efficiency of the package structure and is suitable for the high-temperature operating scenarios of the power chip.

[0023] In step 4, after the power chip 4 and MOSFET chip 3 are installed, they are cut along the notch 201 of the leadframe 2. The cutting process can be mechanical cutting or laser cutting to ensure that each MOSFET chip 3 forms an independent unit and the cut surface is flat and burr-free. The dielectric material board 51 pre-placed in the cavity 101 of the organic substrate 1 can be an epoxy resin board. After the leadframe 2 with assembled chips is placed into the cavity 101, the dielectric material used for filling is epoxy resin. After filling, copper foil 52 is laminated, with the pressure controlled at 0.8-1.2 MPa and the temperature at 120-150℃ to ensure that the dielectric material fully fills all gaps and effectively avoids defects such as delamination and bubbles in the package 5.

[0024] Step 5: Using a CO2 laser, drill holes in the package 5 from the top surface of the copper foil 52 and the bottom of the organic substrate 1 to form micro-via interconnect paths. These micro-via interconnect paths consist of several vias 61. The diameter of the vias 61 can be adjusted within the range of 50-100μm according to interconnection requirements. After drilling, remove any residue from the holes to ensure that the vias 61 reliably contact and conduct with the power chip 4, the MOSFET chip 3, and the lead frame 2, respectively, thereby achieving stable electrical connections between the components and ensuring the overall performance of the package structure.

[0025] Step 6: Completely fill the via 61 with electroplating to form conductive pillars 62. During electroplating, control the current density to 1-3 A / dm² and the plating temperature to 20-30℃ to ensure that the conductive pillars 62 completely fill the via 61 without voids, incomplete plating, or other defects, thereby establishing a stable vertical electrical interconnect and effectively reducing parasitic inductance and resistance. During electroplating, simultaneously form a first copper layer 63 and a second copper layer 64 connected to the conductive pillars 62 on the upper surface of the copper foil 52 and the bottom of the organic substrate 1, with the copper layer thickness controlled at 10-20 μm. Simultaneously, bumps 65 corresponding to the conductive pillars 62 are reserved on the first copper layer 63 and the second copper layer 64. The bumps 65 can adopt circular, square, or other adaptable structures, and their dimensions match the subsequent fan-out conductive structure.

[0026] Step 7: Attach a temporary substrate to one side of the first copper layer 63. A glass substrate, ceramic substrate, or rigid organic substrate can be used to protect and position the structure on the first copper layer 63 side. Then, expose and develop the second copper layer 64, removing excess copper layer using photolithography, retaining only the copper layer corresponding to the bumps 65. Based on this, use conventional RDL (redistribution layer) fabrication processes in the art, such as sputtering, electroplating, photolithography, etc., combined with other technologies, to form the first fan-out conductive structure 71. The line width of the first fan-out conductive structure 71 is controlled between 20-50 μm to ensure the high-density electrical interconnection requirements of the package structure.

[0027] In step 8, when removing the temporary substrate attached to the first copper layer 63, care should be taken to avoid damaging the first copper layer 63 and the surrounding packaging structure during the peeling process. The newly attached temporary substrate to the first fan-out conductive structure 71 can be a glass substrate, a ceramic substrate, or a rigid organic substrate. After attachment, it is laminated and cured to achieve reliable positioning and protection. After the overall structure is rotated 180 degrees, the first copper layer 63 is exposed and developed. The excess copper layer is removed by photolithography, leaving only the core copper layer portion connected to the conductive pillar 62. The circuit dimensions and spacing of the second fan-out conductive structure 72 match those of the first fan-out conductive structure 71 to ensure structural compatibility and reliable electrical connection.

[0028] Step 9: Apply solder resist 81 to the surfaces of the first fan-out conductive structure 71 and the second fan-out conductive structure 72 as needed. The solder resist 81 can be an epoxy resin-based solder resist material, and the application method can be screen printing or spraying. Cover the non-connected areas of the first fan-out conductive structure 71 and the second fan-out conductive structure 72 as needed, ensuring insulation protection after curing. Set the pads 82 at preset positions using reflow soldering, ensuring precise alignment with subsequent interconnection requirements. Then, complete the ball placement operation on the pads 82 on one side of the first fan-out conductive structure 71 to form BGA-type package external contacts. The solder ball material can be tin-lead alloy or lead-free tin alloy.

[0029] On one side of the second fan-out conductive structure 72, a pre-placed metal layer (such as gold-tin) is first melted at a eutectic temperature (363℃, 10-50MPa). After cooling, a metallurgical bond is formed, achieving high-strength mechanical and electrical interconnection. Then, a heat sink 84 is attached using a high thermal conductivity adhesive 83. The high thermal conductivity adhesive 83 can be silicone-based or epoxy-based, ensuring a tight fit between the heat sink 95 and the pads and conductive structure. This achieves efficient active heat dissipation, significantly improving the overall heat dissipation performance of the package structure and adapting to high-power operating scenarios of power chips.

[0030] A power chip packaging structure based on aEASI technology, which is fabricated using the above-described method, such as... Figure 2 As shown, the package includes an organic substrate 1, within which a package 5 is disposed. The package 5 encapsulates a leadframe 2, a MOSFET chip 3, and a power chip 4, forming the core functional unit of the package. The leadframe 1 is made of a Cu-Fe-P alloy or other suitable conductive material and has two opposing upper and lower surfaces. The MOSFET chip 3 and the power chip 4 are precisely attached to the upper and lower surfaces of the leadframe 1, achieving a double-sided layout of the functional components and significantly improving space utilization.

[0031] The package 5 has a first fan-out conductive structure 71 and a second fan-out conductive structure 72 respectively on its upper and lower sides. The package 5 contains several conductive posts 62 that are electrically connected to the lead frame 1, the MOSFET chip 3, and the power chip 4, thus shortening the power and signal paths. The conductive posts 62 penetrate vertically downwards through the bottom of the organic substrate 1 and are electrically connected to the second fan-out conductive structure 72.

[0032] Both the first fan-out conductive structure 71 and the second fan-out conductive structure 72 are coated with solder resist 81, and pads 82 are installed at preset positions. The pads 82 are designed with either "locally thickened pads" or "mesh-like heat dissipation pads" to increase the heat conduction area and improve heat dissipation efficiency. Ball placement is performed on the pads 82 on one side of the first fan-out conductive structure 71 to form BGA-type package external contacts; heat sinks 84 are attached to the pads on the second fan-out conductive structure 72 using high thermal conductivity adhesive 83 to ensure efficient heat dissipation of the package structure.

[0033] The core technological advantages of this invention lie in optimizing the packaging structure and process, improving electrical performance, heat dissipation, and integration, specifically as follows: This invention uses vertical conductive pillars instead of traditional gold wire interconnects. In equivalent implementations, vertical conductive pins or similar vertical conductive structures can also be used, both achieving extremely short electrical paths and significantly reducing parasitic inductance and resistance. Parasitic inductance can be controlled below 5nH, and parasitic resistance is no greater than 5mΩ, making it particularly suitable for high-frequency, high-efficiency power switching applications. A double-sided chip layout combined with a W-shaped thick copper leadframe is used. In equivalent solutions, the leadframe can also be designed as a W-shaped or other symmetrical conductive structure, forming a symmetrical and efficient heat conduction path. BGA solder balls and external heat sinks are integrated on both sides of the package, achieving double-sided active heat dissipation and significantly reducing thermal resistance to below 15℃ / W, ensuring stable operation in high-power scenarios. Optimized lamination processes combined with dielectric material filling ensure package density and effectively avoid defects such as delamination and bubbles. The double-sided fan-out conductive structure improves wiring flexibility and I / O density, enabling high-power-density miniaturized packaging that meets the application requirements of miniaturized and high-power power chips.

[0034] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0035] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0036] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for manufacturing a power chip package structure based on aEASI technology, characterized in that, Includes the following steps: Step 1: Etch a cavity (101) on an organic substrate (1). Step 2: Provide a copper alloy substrate and form a W-shaped lead frame (2) with a notch (201) by a stamping process. Step 3: Mount a MOSFET chip (3) in the groove area of ​​the lead frame (2) and attach a temporary substrate to the upper surface of the lead frame (2); flip the assembly over and mount a power chip (4) on the protruding position on the back of the lead frame (2), with the power chip (4) and a MOSFET chip (3) positioned opposite each other. Step 4: The dielectric material board (51) pre-placed in the cavity (101) of the organic substrate (1) is cut along the notch (201) to remove the temporary substrate and place it into the cavity (101); the same dielectric material as the dielectric material board (51) is used for encapsulation and filling to form an encapsulation body (5); and the encapsulation body (5) is laminated with copper foil (52) at the opening of the organic substrate (1). Step 5: Using a CO2 laser, the package (5) is drilled from the top surface of the copper foil (52) and the bottom of the organic substrate (1) to form a micro-hole interconnection path. The micro-hole interconnection path consists of several through holes (61). The through holes (61) are respectively in contact with the power chip (4), the MOSFET chip (3) and the lead frame (2). Step 6: Electroplating is performed on the upper and lower surfaces of the package (5), the through hole (61) is filled to form a conductive pillar (62), and a first copper layer (63) and a second copper layer (64) are formed on the upper surface of the copper foil (52) and the bottom of the organic substrate (1). Step 7: Attach a temporary substrate to one side of the first copper layer (63), and then expose, develop and etch the second copper layer (64) to remove excess copper layer and retain the portion of copper layer connected to the conductive pillar (62). On this basis, a redistribution layer preparation process is used to form the first fan-out conductive structure (71). Step 8: Remove the temporary substrate attached to the first copper layer (63) and attach a new temporary substrate to the first fan-out conductive structure (71); then expose, develop and etch the first copper layer (63) to remove excess copper layer and retain the portion of copper layer connected to the conductive pillar (81). On this basis, a redistribution layer preparation process is used to form the second fan-out conductive structure (72). Step 9: Apply solder resist green paint (81) to the surface of the first fan-out conductive structure (71) and the second fan-out conductive structure (72) and set pads (82); form BGA solder balls on the pads on one side of the first fan-out conductive structure (71), first eutectic set a pre-formed metal layer on the pads on one side of the second fan-out conductive structure (72), and then attach heat sinks (84) to the pre-formed metal layer with high thermal conductivity adhesive (83).

2. The manufacturing method according to claim 1, characterized in that, The copper alloy substrate used in step 2 is a Cu-Fe-P alloy.

3. The manufacturing method according to claim 1, characterized in that, In step 3, transient liquid phase diffusion bonding technology is used to mount the MOSFET chip (3) and the power chip (4).

4. The manufacturing method according to claim 1, characterized in that, In step 6, the current density of the electroplating process is 1-3 A / dm², and the temperature is 20-30℃.

5. The manufacturing method according to claim 1, characterized in that, In step 4, the lamination process involves a pressure of 0.8-1.2 MPa and a temperature of 120-150℃.

6. A power chip packaging structure based on aEASI technology, fabricated using the method described in any one of claims 1-5, characterized in that, include: An organic substrate (1) has a cavity (101) inside it. The package (5) is disposed in the cavity (101). The package (5) contains a lead frame (2) and a MOSFET chip (3) and a power chip (4) respectively attached to the upper and lower surfaces of the lead frame (2). Multiple vertically interconnected conductive pillars (62) penetrate the package (5) and are electrically connected to the power chip (4), MOSFET chip (3) and lead frame (2) respectively; The first fan-out conductive structure (71) and the second fan-out conductive structure (72) are respectively disposed on the upper and lower sides of the package (5) and electrically connected to the conductive post (62); Solder resist (81) and pads (82) are disposed on the surfaces of the first fan-out conductive structure (71) and the second fan-out conductive structure (72); Among them, BGA solder balls are provided on the pads on one side of the first fan-out conductive structure (71), and heat sinks (84) are attached to the pads on one side of the second fan-out conductive structure (72) by high thermal conductivity adhesive (83).

7. The power chip packaging structure according to claim 6, characterized in that, The lead frame (2) has a W-shaped structure and is made of Cu-Fe-P alloy material. The thickness of its chip mounting area is 300μm.

8. The power chip packaging structure according to claim 6, characterized in that, The conductive pillar (62) is formed by electroplated copper filling the through hole (61), and its diameter is 50μm-100μm.

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