Sic mosfet ssc power switch module

Abstract

The present application relates to a SIC MOSFET SSC power switching module using a gate rail and an auxiliary substrate, which increases a pattern of transmitting a large current, improves a high input impedance electrical characteristic of a gate terminal of a SIC MOSFET module by applying an auxiliary substrate insulated from an SSC substrate, and enables a wiring terminal led to the outside to be arranged in a single axis direction.

Description

Technical Field

[0001] This invention takes as its technical field the SIC MOSFET (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor) SSC (Single-Sided Cooling) power switching module that utilizes gate rails and auxiliary substrates. Background Technology

[0002] As background technology related to this invention, there is a power semiconductor module technology disclosed in PCT Publication WO2013 / 008424 A1. This technology suppresses the temperature increase of wide-bandgap semiconductor elements, suppresses the increase in the total chip area of ​​wide-bandgap semiconductor elements, and can be manufactured at low cost when silicon semiconductor elements and wide-bandgap semiconductor elements are arranged in the same power semiconductor module. Its characteristic is that a switching element 4 made of Si is arranged in the central region of the power semiconductor module 100, and a diode element 5 made of SiC is arranged on both sides of the central region of the power semiconductor module 100 or in the periphery surrounding the central region. However, because the switching element 4 made of Si is arranged in the central region of the power semiconductor module 100, and the diode element 5 made of SiC is arranged on both sides of the central region of the power semiconductor module 100 or in the periphery surrounding the central region, the power semiconductor module is concentrated in the central region, resulting in complex connections and limitations in heat dissipation efficiency.

[0003] As another background technology related to this invention, there is a high-speed, high-efficiency SiC power module technology described in Chinese Patent Publication CN 112103272 A. This technology's power conversion module includes an active metal brazing (AMB) substrate, power converter circuit elements, and a housing. The AMB substrate includes an aluminum nitride substrate layer on opposite sides of a first surface, a first conductive film on the first surface of the aluminum nitride substrate layer, and a second conductive layer on the second surface of the aluminum nitride substrate layer. The power converter circuit elements include multiple silicon carbide switching elements coupled to each other through the first conductive film. The housing is a casting covering the power conversion circuit elements and the AMB substrate. By using an AMB substrate with an aluminum nitride substrate layer, the heat dissipation characteristics of the power conversion module are substantially improved while maintaining the structural integrity of the power conversion module. However, this technology suffers from limited heat dissipation due to the limited area of ​​the first surface of the multiple silicon carbide switching components with the first conductive layer, and the structure where I / O pins for external connections to the switching components are scattered around the module, leading to complex external circuit connections.

[0004] [Patent Literature] (Patent Document 1) WO 2013008424 A1 (Patent Document 2) CN 112103272 A Summary of the Invention

[0005] (a) Technical problems to be solved This invention provides a structure for a SiC MOSFET SSC power switch module utilizing a gate rail and an auxiliary substrate. This structure increases the pattern for transmitting large currents in the SSC power switch module and provides efficient heat dissipation characteristics. By applying an auxiliary substrate that is insulated from the SSC substrate, the effects caused by leakage current, parasitic voltage, etc., are eliminated, thereby improving the high input impedance electrical characteristics of the gate terminal of the SiC MOSFET module. Furthermore, it enables the miniaturization of the SiC MOSFET module and allows the externally led-out terminals to be configured along a uniaxial direction.

[0006] (II) Technical Solution This invention provides a SiC MOSFET SSC power switch module utilizing a gate rail and an auxiliary substrate, which increases the pattern for transmitting large currents in the SSC power switch module. By applying an auxiliary substrate that is insulated from the SSC substrate, the high input impedance electrical characteristics of the gate terminal of the SiC MOSFET module are improved, and the external wiring terminals can be configured along a uniaxial direction.

[0007] (III) Beneficial Effects The SiC MOSFET SSC power switch module of the present invention, utilizing gate rails and an auxiliary substrate, provides efficient heat dissipation characteristics under high current, improves the high input impedance electrical characteristics of the gate terminal of the SiC MOSFET module, and enables the externally led-out terminals to be configured along a uniaxial direction. Attached Figure Description

[0008] Figure 1 The power semiconductor module technology shown is presented in PCT Publication No. WO2013 / 008424 A1, which serves as background technology.

[0009] Figure 2 The high-speed, high-efficiency SiC power module technology is shown in Chinese Patent Application No. 201680025081.8, which is another background technology.

[0010] Figure 3 An example of a SiC MOSFET is shown.

[0011] Figure 4 The circuit of the SiC MOSFET SSC module of the present invention is shown.

[0012] Figure 5 The SSC (Single-Sided Cooling) substrate configuration of the present invention is shown.

[0013] Figure 6 The arrangement of the components on the SSC substrate of the present invention is shown.

[0014] Figure 7 The fixed attachment structure of the components in the SSC power switch module of the present invention is shown.

[0015] Figure 8 The configuration of the SiC MOSFET SSC power switch module of the present invention is shown.

[0016] Figure 9 The package and pinout of the external terminals of the SiC MOSFET SSC power switch module of the present invention are shown.

[0017] Figure 10 This invention illustrates a surface-mount resistor that can be added to the SiC MOSFET SSC power switch module.

[0018] Figure 11 The circuit diagram of the SiC MOSFET SSC power switch module with an additional gate resistor is shown in this invention.

[0019] Figure 12 The arrangement of components on the SSC substrate of the SiC MOSFET SSC power switch module with additional gate resistor of the present invention is shown.

[0020] Figure 13 This invention illustrates a SiC MOSFET SSC power switch module with an additional gate resistor.

[0021] Figure 14 The package and pinout of the external terminals of the SiC MOSFET SSC power switch module with an additional gate resistor according to the present invention are shown.

[0022] Explanation of reference numerals in the attached figures: 100: SSC substrate; 102: Left-side Vdd power supply pattern. 104: Vss power supply icon; 106: Right side Vdd power supply icon. 108: Kelvin terminal rail of Vss-side SiC MOSFET 110: Drain connection pattern of the Vss-side SiC MOSFET 112: First gate connection pattern of Vss-side SiC MOSFET 112s: The first gate of the Vss-side SiC MOSFET is connected to the auxiliary substrate. 114: Second gate connection pattern of Vss-side SiC MOSFET 114s: The second gate of the Vss-side SiC MOSFET is connected to the auxiliary substrate. 116: Kelvin terminal relay pattern of Vss-side SiC MOSFET 118: Gate rail of the Vss-side SiC MOSFET 120: Kelvin terminal lead-out pattern of Vss-side SiC MOSFET 120s: The Kelvin terminal of the Vss-side SiC MOSFET is led out onto the auxiliary substrate. 122: First gate connection pattern of Vdd-side SiC MOSFET 122s: The first gate of the Vdd-side SiC MOSFET is connected to the auxiliary substrate. 124: Second gate connection pattern of Vdd-side SiC MOSFET 124s: The second gate of the Vdd-side SiC MOSFET is connected to the auxiliary substrate. 126: Third gate connection pattern of Vdd-side SiC MOSFET 126s: The third gate of the Vdd-side SiC MOSFET is connected to the auxiliary substrate. 128: Kelvin terminal rail of Vdd-side SiC MOSFET 129: Kelvin terminal of the Vdd-side SiC MOSFET 130: Gate rail of the Vdd-side SiC MOSFET 134: Pout pattern 135: NTC1 External Terminal Connection Diagram 136: Kelvin terminal connection pattern of Vss-side SiC MOSFET 137: Gate connection pattern of the Vss-side SiC MOSFET 138: NTC2 External Terminal Connection Diagram 139: NTC_COM External Terminal Connection Diagram 200: SIC MOSFET1 202: SIC MOSFET2 204: SIC MOSFET3 206: SIC MOSFET4 208: SIC MOSFET5 210: SIC MOSFET6 212: SIC MOSFET7 214: SIC MOSFET8 216: SIC MOSFET9 218: SIC MOSFET10 220: SIC MOSFET11 222: SIC MOSFET12 224: NTC1 226: NTC2 Detailed Implementation

[0023] The following description is merely illustrative of the principles of the invention. Therefore, although not explicitly stated or illustrated in this specification, those skilled in the art to which this invention pertains can implement the principles of the invention and realize various devices included within the concept and scope of the invention. Furthermore, all terms and embodiments listed in this specification are intended solely for the purpose of understanding the concept of the invention and should be understood as not being limited to the embodiments and states specifically listed above. Moreover, it should be understood that listing the principles, ideas, and embodiments of the invention, as well as all detailed descriptions of specific embodiments, is intended to include structural and functional equivalents of these matters.

[0024] The above-described objects, features, and advantages will become clearer from the following detailed description taken in conjunction with the accompanying drawings. In describing the invention, detailed descriptions of well-known techniques are omitted where it is determined that such descriptions might unnecessarily obscure the essence of the invention. Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings.

[0025] SiC (Silicon Carbide) is a compound semiconductor material composed of silicon (Si) and carbon (C). It exhibits excellent dielectric breaking electric field strength, being 10 times that of Si, and a band gap three times that of Si. Because the resistance of the drift layer is lower than that of Si devices, there is no need for conductivity modulation, making it a suitable material for high-voltage and low-resistance MOSFETs. (Hereinafter referred to as SiC.) SiC MOSFETs have low switching losses, which allows for miniaturization of heat dissipation devices and high-frequency driving. Therefore, they are used in the manufacture of high-power devices such as electric vehicles, drones, and high-power inverter / converter circuits.

[0026] SSC is a single-sided cooled thermoplastic power module structure with optimized heat dissipation, electrical characteristics and reliability, which can be used in power modules composed of multiple SiC MOSFETs.

[0027] The present invention provides an SSC power switching element utilizing SiC MOSFETs, which is a switching element that forms an SSC structure by combining multiple SiC MOSFETs.

[0028] Figure 3An example of a SiC MOSFET is shown. A SiC MOSFET has a structure where one side of the SiC substrate serves as the drain, and the source and gate are formed as a MOSFET on the other side of the substrate. In this SiC MOSFET, to minimize errors caused by low contact and lead resistance values ​​and thus measure resistance with high accuracy, external circuitry controls the SiC MOSFET through a Kelvin terminal that is configured in common with the source terminal.

[0029] In the SiC MOSFET, since the Kelvin terminal detects the change in resistance of the source terminal, the Kelvin terminal can also be selectively connected to an external circuit for control in the parallel-connected SiC MOSFET.

[0030] Figure 4 The circuit diagram of the SiC MOSFET module of the present invention is shown. The SiC MOSFET module of the present invention is composed of... Figure 3 The invention is based on a half-bridge circuit constructed from SiC MOSFETs as described herein. Furthermore, the SiC MOSFET module of this invention also incorporates two series-connected negative temperature coefficient (NTC) thermistors for temperature detection, and provides NTC terminals NTC1 and NTC2, as well as an NTC_COM terminal for the common connection of the NTC terminals.

[0031] The half-bridge structure shown in the figure can be illustrated as separate MOSFETs on the Vdd and Vss sides. However, to achieve high-power switching, this invention provides a SiC MOSFET module with a half-bridge structure consisting of two or more MOSFET pairs connected in parallel. Therefore, this invention provides a half-bridge SiC MOSFET module that connects the drain, source, and gate of two or more MOSFET pairs in parallel.

[0032] The SiC MOSFET module has a complex topology due to the arrangement of half-bridge terminals consisting of two or more MOSFET pairs and the drain, source, and gate terminals of each MOSFET. As a result, the heat dissipation performance of the SiC module and its electrical characteristics caused by leakage current, parasitic voltage, etc. are limited.

[0033] The present invention addresses this limitation by providing a SiC MOSFET module with a structure that ensures the thermal performance and electrical characteristics of the SiC module.

[0034] Figure 5 The SSC substrate configuration of the present invention is shown. A typical SSC substrate is a ceramic substrate on both sides of an alumina (Al2O3) or high-strength aluminum nitride (AlN) plate with excellent thermal conductivity, insulation, and mechanical strength, to which metal foil is bonded. Components and circuits are disposed on the front side of the substrate, while the back side is used for contact with heat dissipation devices. The substrate is manufactured using either direct bonded copper (DBC) technology, where copper and ceramic are directly bonded through a high-temperature process, or active metal brazing (AMB) technology, where copper or other metal foil is brazed onto a ceramic substrate with solder paste under vacuum at high temperature.

[0035] In this invention, the SiC MOSFET module formed on the SSC substrate in the SiC MOSFET SSC power switch module utilizing the gate rail and auxiliary substrate is characterized in that, firstly, since the current path is located on one side of the copper foil on the front side of the SSC, the high current conduction path is designed to be wide in the half-bridge structure SiC MOSFET module, and heat dissipation is dispersed.

[0036] Secondly, in a half-bridge SiC MOSFET module, in order to eliminate the effects of leakage current and parasitic voltage at the gate terminal and ensure high input impedance electrical characteristics, a gate rail and an auxiliary substrate insulated from the SSC substrate are used.

[0037] Third, minimize the size of the SiC MOSFET module and align the externally led-out terminals along a single axis, either laterally or longitudinally.

[0038] The following quote Figure 5 This invention describes the SSC substrate configuration of an SSC power switching module utilizing SiC MOSFETs. The invention uses an SSC substrate where copper film is bonded by directly bonding copper (DBC) to both sides of an alumina (Al2O3) or high-strength aluminum nitride (AlN) plate, or by active metal brazing (AMB) where copper foil or other metal foil is brazed to a ceramic substrate with solder paste under high temperature and vacuum. Components and circuits are arranged on the front side of the substrate, while the back side is used for contact with heat dissipation devices.

[0039] The SSC substrate 100 has etched patterns on its front side, which electrically insulate the boundaries of each pattern, to facilitate the placement of components and circuits. The patterns on the front side of the SSC substrate 100 are described below by dividing it into upper, lower, left, and right sections, with reference to the accompanying drawings.

[0040] The SiC MOSFET SSC power switch module of the present invention, which utilizes a gate rail and an auxiliary substrate, includes an SSC substrate 100. On the left side of the component arrangement surface of the SSC substrate 100, a left Vdd power supply pattern 102 connected to the positive power supply (Vdd) of the half-bridge circuit is arranged. On the right side of the component arrangement surface of the SSC substrate 100, a right Vdd power supply pattern 106 is arranged, which extends from the lower end of the left Vdd power supply pattern 102 to the right side to form the right Vdd power supply pattern 106.

[0041] At the upper end between the left Vdd power supply pattern 102 and the right Vdd power supply pattern 106, a Vss power supply pattern 104 is configured to connect the negative power supply (Vss) of the half-bridge circuit. At the lower end of the Vss power supply pattern 104, a Kelvin terminal rail 108 of the Vss-side SiC MOSFET is formed. At the lower end of the Kelvin terminal rail 108 of the Vss-side SiC MOSFET, between the left Vdd power supply pattern 102 and the right Vdd power supply pattern 106, a drain connection pattern 110 of the Vss-side SiC MOSFET is configured.

[0042] Inside the drain connection pattern 110 of the Vss-side SiC MOSFET, there are a first gate connection pattern 112 and a second gate connection pattern 114 of the Vss-side SiC MOSFET. Between the drain connection pattern 110 of the Vss-side SiC MOSFET and the right-side Vdd power supply pattern 106, there is a Kelvin terminal relay pattern 116 of the Vss-side SiC MOSFET.

[0043] At the lower end of the drain connection pattern 110 of the Vss-side SiC MOSFET, a gate rail 118 of the Vss-side SiC MOSFET is provided.

[0044] Inside the right Vdd power pattern 106 extension extending from the lower end of the left Vdd power pattern 102 to the right end, there are a Kelvin terminal lead-out pattern 120 for the Vss-side SiC MOSFET, a first gate connection pattern 122 for the Vdd-side SiC MOSFET, a second gate connection pattern 124 for the Vdd-side SiC MOSFET, and a third gate connection pattern 126 for the Vdd-side SiC MOSFET. At the lower end of the right Vdd power pattern 106 extension extending from the lower end of the left Vdd power pattern 102 to the right end, there is a Kelvin terminal rail 128 for the Vdd-side SiC MOSFET. At the lower end of the Kelvin terminal rail 128 for the Vdd-side SiC MOSFET, there is a gate rail 130 for the Vdd-side SiC MOSFET.

[0045] On the lower left side of the SSC substrate 100, the end of the left Vdd power supply pattern 102 extends, and on the right side of the extended end of the left Vdd power supply pattern 102, a plurality of external terminal connection patterns 129-139 are formed, wherein the Kelvin terminal 129 of the Vdd-side SiC MOSFET and the gate rail 130 of the Vdd-side SiC MOSFET extend and are formed as external terminal connection patterns.

[0046] On the right side of the multiple external terminal connection patterns 129-133 and at the lower end of the gate rail 130 of the Vdd-side SiC MOSFET, the Pout pattern 134 of the half-bridge circuit composed of SiC MOSFETs is formed as an external terminal connection pattern. On the right side of the Pout pattern 134, the external terminal connection patterns 135 of NTC1, 138 of NTC2, and the external terminal connection pattern 139 of the common terminal of NTC1 and NTC2, NTC_COM, are arranged. On the right side of the external terminal connection pattern 139 of NTC_COM, the Pout pattern 134 extends and forms an external terminal connection pattern.

[0047] Furthermore, on the right side of the external terminal connection pattern 135 of the NTC1, a Kelvin terminal connection pattern 136 for the Vss-side SiC MOSFET and a gate connection pattern 137 for the Vss-side SiC MOSFET are formed.

[0048] Among the plurality of external terminal connection patterns 129-139, the remaining external terminal connection patterns 131, 132, and 133 may be assigned as non-connection (NC) patterns.

[0049] Figure 6This diagram illustrates the configuration of components on the SSC substrate of the SSC power switch module utilizing SiC MOSFETs according to the present invention. The components of the SSC power switch module utilizing SiC MOSFETs of the present invention constitute the above-described... Figure 4 The half-bridge circuit consists of multiple SiC MOSFETs, two NTC thermistors, and an auxiliary substrate electrically insulated from the SSC substrate.

[0050] On the SSC substrate of the SSC power switch module of the present invention, Figure 5 The first gate connection auxiliary substrate 112s of the Vss-side SiC MOSFET described herein is attached to the first gate connection pattern 112 of the Vss-side SiC MOSFET, and the second gate connection auxiliary substrate 114s of the Vss-side SiC MOSFET is attached to the second gate connection pattern 114 of the Vss-side SiC MOSFET. Furthermore, the Kelvin terminal lead-out auxiliary substrate 120s of the Vss-side SiC MOSFET is attached to the Kelvin terminal lead-out pattern 120 of the Vss-side SiC MOSFET, the first gate connection auxiliary substrate 122s of the Vdd-side SiC MOSFET is attached to the first gate connection pattern 122 of the Vdd-side SiC MOSFET, the second gate connection auxiliary substrate 124s of the Vdd-side SiC MOSFET is connected to the second gate connection pattern 124 of the Vdd-side SiC MOSFET, and the third gate connection auxiliary substrate 126s of the Vdd-side SiC MOSFET is attached to the third gate connection pattern 126 of the Vdd-side SiC MOSFET. The auxiliary substrate described above is a DBC or AMB substrate and is designed to be smaller in size than the fixed-configuration pattern.

[0051] On the left side of the first gate connection auxiliary substrate 112s of the Vss-side SiC MOSFET, SiC MOSFET1 200 and SiC MOSFET2 202 are attached to the drain connection pattern 110 of the Vss-side SiC MOSFET, so that the drains of SiC MOSFET1 200 and SiC MOSFET2 202 are conductive. At this time, the gate terminals and Kelvin terminals of SiC MOSFET1 200 and SiC MOSFET2 202 are arranged in a direction opposite to the first gate connection auxiliary substrate 112s of the Vss-side SiC MOSFET.

[0052] On the drain connection pattern 110 of the Vss-side SiC MOSFET between the first gate connection auxiliary substrate 112s of the Vss-side SiC MOSFET and the second gate connection auxiliary substrate 114s of the Vss-side SiC MOSFET, SiC MOSFET 3204 and SiC MOSFET 4206 are attached to the drain connection pattern 110, so that the drains of SiC MOSFET 3204 and SiC MOSFET 4206 are conductive. At this time, the gate terminals and Kelvin terminals of SiC MOSFET 3204 and SiC MOSFET 4206 are arranged in a direction opposite to the first gate connection auxiliary substrate 112s of the Vss-side SiC MOSFET.

[0053] On the drain connection pattern 110 of the Vss-side SiC MOSFET on the right side of the second gate connection auxiliary substrate 114s of the Vss-side SiC MOSFET, SiC MOSFET 5 208 and SiC MOSFET 6 210 are attached to the drain connection pattern 110 of the Vss-side SiC MOSFET, so that the drains of SiC MOSFET 5 208 and SiC MOSFET 6 210 are conductive. At this time, the gate terminals and Kelvin terminals of SiC MOSFET 5 208 and SiC MOSFET 6 210 are arranged in a direction opposite to the second gate connection auxiliary substrate 114s of the Vss-side SiC MOSFET.

[0054] On the right-side Vdd power pattern 106 between the auxiliary substrate 120s for the Kelvin terminal lead-out of the Vss-side SiC MOSFET and the first gate connection auxiliary substrate 122s of the Vdd-side SiC MOSFET, SiC MOSFET 7 212 and SiC MOSFET 8 214 are attached to the right-side Vdd power pattern 106, such that the drains of SiC MOSFET 7 212 and SiC MOSFET 8 214 are conductive. At this time, the gate terminals and Kelvin terminals of SiC MOSFET 7 212 and SiC MOSFET 8 214 are arranged in a direction opposite to the first gate connection auxiliary substrate 122s of the Vdd-side SiC MOSFET.

[0055] On the right-side Vdd power pattern 106 between the first gate connection auxiliary substrate 122s of the Vdd-side SiC MOSFET and the second gate connection auxiliary substrate 124s of the Vdd-side SiC MOSFET, SiC MOSFET 9 216 and SiC MOSFET 10 218 are attached to the right-side Vdd power pattern 106, such that the drains of SiC MOSFET 9 216 and SiC MOSFET 10 218 are conductive. At this time, the gate terminals and Kelvin terminals of SiC MOSFET 9 216 and SiC MOSFET 10 218 are arranged in a direction opposite to the second gate connection auxiliary substrate 124s of the Vdd-side SiC MOSFET.

[0056] On the left Vdd power pattern 102, which is connected to the right Vdd power pattern 106, between the second gate connection auxiliary substrate 124s of the Vdd-side SiC MOSFET and the third gate connection auxiliary substrate 126s of the Vdd-side SiC MOSFET, SiC MOSFETs 11 220 and 12 222 are attached to the left Vdd power pattern 102, such that the drains of SiC MOSFETs 11 220 and 12 222 are conductive. At this time, the gate terminals and Kelvin terminals of SiC MOSFETs 11 220 and 12 222 are arranged in a direction opposite to the third gate connection auxiliary substrate 126s of the Vdd-side SiC MOSFET.

[0057] One end of NTC1 224 is connected to external terminal connection pattern 135 of NTC1, and one end of NTC2 226 is connected to external terminal connection pattern 138 of NTC2. The other ends of NTC1 and NTC2 are connected to external terminal connection pattern 139 of NTC_COM.

[0058] Figure 7 The fixed attachment structure of components in the SSC power switch module of the present invention is shown. As described above, the components arranged on the SSC substrate of the SSC power switch module utilizing SiC MOSFETs of the present invention are fixedly attached to each pattern. In this case, the SiC MOSFET uses one side of the SiC substrate as the drain, and forms the source and gate on the other side of the substrate. The drain terminal is attached to each pattern by soldering or sintering with silver epoxy, etc., so that sufficient current can flow through the corresponding pattern. Furthermore, the NTC thermistor is also fixedly attached to the corresponding pattern by soldering or sintering with silver epoxy, etc., in the same manner as the SiC MOSFET.

[0059] The auxiliary substrate (added PCB) of the present invention is fixedly attached to the corresponding pattern by an insulating adhesive such as an insulating epoxy adhesive.

[0060] As described above, the fixedly attached components are connected by bonding wires to form a half-bridge circuit. The bonding wires of the present invention are connected with the shortest distance and are joined so as not to overlap with other bonding wires.

[0061] Figure 8 This illustrates the configuration of the SiC MOSFET SSC power switch module utilizing a gate rail and an auxiliary substrate according to the present invention. Because... Figure 8 Some figure labels have been omitted, therefore, in combination with Figure 6 Please provide an explanation.

[0062] For the preceding Figure 6 As described above, the drain terminals of SiC MOSFET1 200, SiC MOSFET2 202, SiC MOSFET3 204, SiC MOSFET4 206, SiC MOSFET5 208, and SiC MOSFET6 210 are attached to the drain connection pattern 110 of the SiC MOSFET on the Vss side by soldering or sintering. Furthermore, the drain terminals of SiC MOSFET7 212, SiC MOSFET8 214, SiC MOSFET9 216, SiC MOSFET10 218, SiC MOSFET11 220, and SiC MOSFET12 222 are attached to the left Vdd power supply pattern 102 and the right Vdd power supply pattern 106 connected to the left Vdd power supply pattern 102 by soldering or sintering.

[0063] The source terminals of SiC MOSFET1 200 and SiC MOSFET2 202 are connected in parallel via multiple bond wires to carry a large current and are bonded to the Vss power pattern 104 of the half-bridge circuit. The source terminals of SiC MOSFET3 204 and SiC MOSFET4 206 are connected in parallel via multiple bond wires to carry a large current and are bonded to the Vss power pattern 104 of the half-bridge circuit. The source terminals of SiC MOSFET5 208 and SiC MOSFET6 210 are connected in parallel via multiple bond wires to carry a large current and are bonded to the Vss power pattern 104 of the half-bridge circuit.

[0064] The source terminals of SiC MOSFET7 212 and SiC MOSFET8 214 are connected in parallel via multiple bond wires to carry a large current, with one end bonded to the drain connection pattern 110 of the Vss-side SiC MOSFET and the other end extending to and bonded to the Pout pattern 134. The source terminals of SiC MOSFET9 216 and SiC MOSFET10 218 are connected in parallel via multiple bond wires to carry a large current, with one end bonded to the drain connection pattern 110 of the Vss-side SiC MOSFET and the other end extending to and bonded to the Pout pattern 134. The source terminals of SiC MOSFET11 220 and SiC MOSFET12 222 are connected in parallel via multiple bond wires to carry a large current, with one end bonded to the drain connection pattern 110 of the Vss-side SiC MOSFET and the other end extending to and bonded to the Pout pattern 134.

[0065] The gate terminals of SiC MOSFET1 200 and SiC MOSFET2 202 and the gate terminals of SiC MOSFET3 204 and SiC MOSFET4 206 are respectively bonded to the first gate connection auxiliary substrate 112s of the Vss-side SiC MOSFET. The gate terminals of SiC MOSFET5 208 and SiC MOSFET6 210 are respectively bonded to the second gate connection auxiliary substrate 114s of the Vss-side SiC MOSFET. The first gate connection auxiliary substrate 112s and the second gate connection auxiliary substrate 114s of the Vss-side SiC MOSFET are respectively bonded to the gate rail 118 of the Vss-side SiC MOSFET. The gate rail 118 of the Vss-side SiC MOSFET is bonded to the gate connection pattern 137 of the Vss-side SiC MOSFET.

[0066] The Kelvin terminals of SiC MOSFET1 200, SiC MOSFET3 204, and SiC MOSFET5 208 are respectively bonded to the Kelvin terminal rail 108 of the Vss-side SiC MOSFET. One end of the Kelvin terminal rail 108 of the Vss-side SiC MOSFET is bonded to the Kelvin terminal relay pattern 116 of the Vss-side SiC MOSFET. After the Kelvin terminal relay pattern 116 of the Vss-side SiC MOSFET is bonded to the Kelvin terminal lead-out auxiliary substrate of the Vss-side SiC MOSFET, the Kelvin terminal lead-out auxiliary substrate of the Vss-side SiC MOSFET is bonded to the Kelvin terminal connection pattern 136 of the Vss-side SiC MOSFET.

[0067] The gate terminals of SIC MOSFET7 212 and SIC MOSFET8 214 are respectively bonded to the first gate connection auxiliary substrate 122s of the Vdd-side SIC MOSFET, and the first gate connection auxiliary substrate 122s of the Vdd-side SIC MOSFET is bonded to the gate rail 130 of the Vdd-side SIC MOSFET which extends to form an external terminal connection pattern.

[0068] The gate terminals of SiC MOSFET9 216 and SiC MOSFET10 218 are respectively bonded to the second gate connection auxiliary substrate 124s of the Vdd-side SiC MOSFET, and the second gate connection auxiliary substrate 124s of the Vdd-side SiC MOSFET is bonded to the gate rail 130 of the Vdd-side SiC MOSFET which extends to form an external terminal connection pattern.

[0069] The gate terminals of SiC MOSFET11 220 and SiC MOSFET12 222 are respectively bonded to the third gate connection auxiliary substrate 126s of the Vdd-side SiC MOSFET, and the third gate connection auxiliary substrate 126s of the Vdd-side SiC MOSFET is bonded to the gate rail 130 of the Vdd-side SiC MOSFET which is extended and has an external terminal connection pattern.

[0070] The Kelvin terminals of SiC MOSFET 8 214, SiC MOSFET 10 218, and SiC MOSFET 12 222 are respectively bonded to the Kelvin terminal rail 128 of the Vdd-side SiC MOSFET, and the Kelvin terminal rail 128 of the Vdd-side SiC MOSFET is bonded to the Kelvin terminal 129 of the Vdd-side SiC MOSFET.

[0071] Figure 9 The diagram illustrates the package and pinout of the SiC MOSFET SSC power switch module utilizing a gate rail and an auxiliary substrate according to the present invention. For ease of understanding, the diagram shows the exposed state of the SSC substrate inside the package, with the other side of the package contacting an external heat sink, and the front side, where components are connected, being resin-impregnated and located within the package.

[0072] The pins of the external terminals provided from the package of the SSC power switch module of the present invention include: power supply terminals Vdd and Vss of a half-bridge circuit structure, output terminal Pout, gate G1 and Kelvin terminal K1 on the Vdd side, gate G2 and Kelvin terminal K2 on the Vss side, terminals NTC1 and NTC2 of the NTC thermistor, and the common terminal NTC_COM of the thermistor.

[0073] Figure 10 This invention illustrates a surface-mount resistor that can be added to a SiC MOSFET SSC power switch module utilizing a gate rail and an auxiliary substrate. The SiC MOSFET SSC power switch module of this invention, by applying an auxiliary substrate (added PCB) and gate rails, allows the gate terminal of the SiC MOSFET to have high input impedance electrical characteristics within the package and be brought out. Therefore, the SiC MOSFET SSC power switch module of this invention generates noise during high-speed or high-voltage switching due to charge accumulation at the gate terminal, which may lead to heating due to uneven switching of the SiC MOSFET. Although the noise generated by the charge accumulation at the gate terminal occurs within a very short time interval of tens of nsec to several µsec, it can lead to reduced efficiency accompanied by heat loss during long-term high-power operation.

[0074] In the SSC power switching module utilizing SiC MOSFETs of the present invention, this characteristic is improved by connecting a resistor to the gate terminal of the SiC MOSFET.

[0075] This invention illustrates a resistor connected to a gate terminal, which utilizes a surface-mount chip resistor. The gate resistor (GR) has a top contact and a back contact as joints, and incidentally, a test pad is provided on the top contact.

[0076] Figure 11 The circuit diagram of the SiC MOSFET module with added gate resistors according to the present invention is shown. The SiC MOSFET module of the present invention can improve switching characteristics by adding gate resistors GR1 and GR2 to the gate terminals G1 and G2 of the half-bridge circuit, respectively.

[0077] Although the half-bridge structure of the present invention is shown as MOSFETs and gate terminals G1, G2 on the Vdd side and Vss side respectively, and gate resistors GR1 and GR2, since the present invention is a SiCMOSFET module with a half-bridge structure composed of multiple MOSFET pairs for power control, gate resistors are connected to the gate terminals of the multiple MOSFET pairs that are connected in parallel.

[0078] Figure 12 The illustration shows the configuration of the components with an additional gate resistor on the SSC substrate of the SiC MOSFET SSC power switch module utilizing a gate rail and an auxiliary substrate according to the present invention. The components of the SiC MOSFET SSC power switch module of the present invention are as described above. Figure 4The circuit consists of multiple SiC MOSFETs and two NTC thermistors, as well as an auxiliary substrate that is electrically insulated from the SSC substrate.

[0079] On the SSC substrate of the SSC power switch module of the present invention, Figure 5 The first gate connection auxiliary substrate 112s of the Vss-side SiC MOSFET described herein is attached to the first gate connection pattern 112 of the Vss-side SiC MOSFET. The four gate resistors corresponding to the SiC MOSFET are attached to the first gate connection auxiliary substrate 112s of the Vss-side SiC MOSFET by soldering or sintering with silver epoxy.

[0080] On the second gate connection pattern 114 of the Vss-side SiC MOSFET, a second gate connection auxiliary substrate 114s of the Vss-side SiC MOSFET is attached. The two gate resistors corresponding to the SiC MOSFET are attached to the second gate connection auxiliary substrate 114s of the Vss-side SiC MOSFET by soldering or silver epoxy sintering.

[0081] Furthermore, on the Kelvin terminal lead-out pattern 120 of the Vss-side SiC MOSFET, a Kelvin terminal lead-out auxiliary substrate 120s of the Vss-side SiC MOSFET is attached, and on the first gate connection pattern 122 of the Vdd-side SiC MOSFET, a first gate connection auxiliary substrate 122s of the Vdd-side SiC MOSFET is attached. The two gate resistors corresponding to the SiC MOSFET are attached to the first gate connection auxiliary substrate 122s of the Vdd-side SiC MOSFET by soldering or silver epoxy sintering.

[0082] On the second gate connection pattern 124 of the Vdd-side SiC MOSFET, a second gate connection auxiliary substrate 124s of the Vdd-side SiC MOSFET is connected. The two gate resistors corresponding to the SiC MOSFET are attached to the second gate connection auxiliary substrate 124s of the Vdd-side SiC MOSFET by soldering or silver epoxy sintering.

[0083] On the third gate connection pattern 126 of the Vdd-side SiC MOSFET, a third gate connection auxiliary substrate 126s of the Vdd-side SiC MOSFET is attached. The two gate resistors corresponding to the SiC MOSFET are attached to the third gate connection auxiliary substrate 126s of the Vdd-side SiC MOSFET by soldering or silver epoxy sintering.

[0084] The auxiliary substrate described above is a DBC or AMB substrate and is designed to be smaller in size than the fixed-configuration pattern.

[0085] On the left side of the first gate connection auxiliary substrate 112s of the Vss-side SiC MOSFET, SiC MOSFET1 200 and SiC MOSFET2 202 are attached to the drain connection pattern 110 of the Vss-side SiC MOSFET, so that the drains of SiC MOSFET1 200 and SiC MOSFET2 202 are conductive. At this time, the gate terminals and Kelvin terminals of SiC MOSFET1 200 and SiC MOSFET2 202 are arranged in a direction opposite to the first gate connection auxiliary substrate 112s of the Vss-side SiC MOSFET.

[0086] On the drain connection pattern 110 of the Vss-side SiC MOSFET between the first gate connection auxiliary substrate 112s of the Vss-side SiC MOSFET and the second gate connection auxiliary substrate 114s of the Vss-side SiC MOSFET, SiC MOSFET 3204 and SiC MOSFET 4206 are attached to the drain connection pattern 110, so that the drains of SiC MOSFET 3204 and SiC MOSFET 4206 are conductive. At this time, the gate terminals and Kelvin terminals of SiC MOSFET 3204 and SiC MOSFET 4206 are arranged in a direction opposite to the first gate connection auxiliary substrate 112s of the Vss-side SiC MOSFET.

[0087] On the drain connection pattern 110 of the Vss-side SiC MOSFET on the right side of the second gate connection auxiliary substrate 114s of the Vss-side SiC MOSFET, SiC MOSFET 5 208 and SiC MOSFET 6 210 are attached to the drain connection pattern 110 of the Vss-side SiC MOSFET, so that the drains of SiC MOSFET 5 208 and SiC MOSFET 6 210 are conductive. At this time, the gate terminals and Kelvin terminals of SiC MOSFET 5 208 and SiC MOSFET 6 210 are arranged in a direction opposite to the second gate connection auxiliary substrate 114s of the Vss-side SiC MOSFET.

[0088] On the right-side Vdd power pattern 106 between the auxiliary substrate 120s for the Kelvin terminal lead-out of the Vss-side SiC MOSFET and the first gate connection auxiliary substrate 122s of the Vdd-side SiC MOSFET, SiC MOSFET 7 212 and SiC MOSFET 8 214 are attached to the right-side Vdd power pattern 106, such that the drains of SiC MOSFET 7 212 and SiC MOSFET 8 214 are conductive. At this time, the gate terminals and Kelvin terminals of SiC MOSFET 7 212 and SiC MOSFET 8 214 are arranged in a direction opposite to the first gate connection auxiliary substrate 122s of the Vdd-side SiC MOSFET.

[0089] On the right-side Vdd power pattern 106 between the first gate connection auxiliary substrate 122s of the Vdd-side SiC MOSFET and the second gate connection auxiliary substrate 124s of the Vdd-side SiC MOSFET, SiC MOSFET 9 216 and SiC MOSFET 10 218 are attached to the right-side Vdd power pattern 106, such that the drains of SiC MOSFET 9 216 and SiC MOSFET 10 218 are conductive. At this time, the gate terminals and Kelvin terminals of SiC MOSFET 9 216 and SiC MOSFET 10 218 are arranged in a direction opposite to the second gate connection auxiliary substrate 124s of the Vdd-side SiC MOSFET.

[0090] On the left Vdd power pattern 102, which is connected to the right Vdd power pattern 106, between the second gate connection auxiliary substrate 124s of the Vdd-side SiC MOSFET and the third gate connection auxiliary substrate 126s of the Vdd-side SiC MOSFET, SiC MOSFETs 11 220 and 12 222 are attached to the left Vdd power pattern 102, such that the drains of SiC MOSFETs 11 220 and 12 222 are conductive. At this time, the gate terminals and Kelvin terminals of SiC MOSFETs 11 220 and 12 222 are arranged in a direction opposite to the third gate connection auxiliary substrate 126s of the Vdd-side SiC MOSFET.

[0091] One end of NTC1 224 is connected to external terminal connection pattern 135 of NTC1, and one end of NTC2 226 is connected to external terminal connection pattern 138 of NTC2. The other ends of NTC1 and NTC2 are connected to external terminal connection pattern 139 of NTC_COM.

[0092] Figure 13This invention illustrates a SiC MOSFET SSC power switch module with an added gate resistor, utilizing a gate rail and an auxiliary substrate. In the SiC MOSFET module with an added gate resistor of this invention, for the preceding... Figure 12 As described above, the drain terminals of SiC MOSFET1 200, SiC MOSFET2 202, SiC MOSFET3 204, SiC MOSFET4 206, SiC MOSFET5 208, and SiC MOSFET6 210 are attached to the drain connection pattern 110 of the SiC MOSFET on the Vss side by soldering or sintering. Furthermore, the drain terminals of SiC MOSFET7 212, SiC MOSFET8 214, SiC MOSFET9 216, SiC MOSFET10 218, SiC MOSFET11 220, and SiC MOSFET12 222 are attached to the left Vdd power supply pattern 102 and the right Vdd power supply pattern 106 connected to the left Vdd power supply pattern 102 by soldering or sintering.

[0093] The source terminals of SiC MOSFET1 200 and SiC MOSFET2 202 are connected in parallel via multiple bond wires to carry a large current and are bonded to the Vss power pattern 104 of the half-bridge circuit. The source terminals of SiC MOSFET3 204 and SiC MOSFET4 206 are connected in parallel via multiple bond wires to carry a large current and are bonded to the Vss power pattern 104 of the half-bridge circuit. The source terminals of SiC MOSFET5 208 and SiC MOSFET6 210 are connected in parallel via multiple bond wires to carry a large current and are bonded to the Vss power pattern 104 of the half-bridge circuit.

[0094] The source terminals of SiC MOSFET7 212 and SiC MOSFET8 214 are connected in parallel via multiple bond wires to carry a large current, with one end bonded to the drain connection pattern 110 of the Vss-side SiC MOSFET and the other end extending to and bonded to the Pout pattern 134. The source terminals of SiC MOSFET9 216 and SiC MOSFET10 218 are connected in parallel via multiple bond wires to carry a large current, with one end bonded to the drain connection pattern 110 of the Vss-side SiC MOSFET and the other end extending to and bonded to the Pout pattern 134. The source terminals of SiC MOSFET11 220 and SiC MOSFET12 222 are connected in parallel via multiple bond wires to carry a large current, with one end bonded to the drain connection pattern 110 of the Vss-side SiC MOSFET and the other end extending to and bonded to the Pout pattern 134.

[0095] The gate terminals of SiC MOSFET1 200 and SiC MOSFET2 202 and the gate terminals of SiC MOSFET3 204 and SiC MOSFET4 206 are respectively bonded to the gate resistors of the first gate connection auxiliary substrate 112s fixedly attached to the Vss-side SiC MOSFET. The gate terminals of SiC MOSFET5 208 and SiC MOSFET6 210 are respectively bonded to the gate resistors of the second gate connection auxiliary substrate 114s fixedly attached to the Vss-side SiC MOSFET. The first gate connection auxiliary substrate 112s and the second gate connection auxiliary substrate 114s of the Vss-side SiC MOSFET are respectively bonded to the gate rail 118 of the Vss-side SiC MOSFET. The gate rail 118 of the Vss-side SiC MOSFET is bonded to the gate connection pattern 137 of the Vss-side SiC MOSFET.

[0096] The Kelvin terminals of SiC MOSFET1 200, SiC MOSFET3 204, and SiC MOSFET5 208 are respectively bonded to the gate resistors of the Kelvin terminal rail 108 fixedly attached to the Vss-side SiC MOSFET. One end of the Kelvin terminal rail 108 of the Vss-side SiC MOSFET is bonded to the Kelvin terminal relay pattern 116 of the Vss-side SiC MOSFET. After the Kelvin terminal relay pattern 116 of the Vss-side SiC MOSFET is bonded to the Kelvin terminal lead-out auxiliary substrate of the Vss-side SiC MOSFET, the Kelvin terminal lead-out auxiliary substrate of the Vss-side SiC MOSFET is bonded to the Kelvin terminal connection pattern 136 of the Vss-side SiC MOSFET.

[0097] The gate terminals of SIC MOSFET7 212 and SIC MOSFET8 214 are respectively bonded to the gate resistors of the first gate connection auxiliary substrate 122s fixedly attached to the Vdd-side SIC MOSFET. The first gate connection auxiliary substrate 122s of the Vdd-side SIC MOSFET is bonded to the gate rail 130 of the Vdd-side SIC MOSFET which extends to form an external terminal connection pattern.

[0098] The gate terminals of SIC MOSFET9 216 and SIC MOSFET10 218 are respectively corresponding to and bonded to the gate resistors of the second gate connection auxiliary substrate 124s fixedly attached to the Vdd-side SIC MOSFET. The second gate connection auxiliary substrate 124s of the Vdd-side SIC MOSFET is bonded to the gate rail 130 of the Vdd-side SIC MOSFET which extends to form an external terminal connection pattern.

[0099] The gate terminals of SiC MOSFET11 220 and SiC MOSFET12 222 are respectively bonded to the gate resistors of the third gate connection auxiliary substrate 126s fixedly attached to the Vdd-side SiC MOSFET. The third gate connection auxiliary substrate 126s of the Vdd-side SiC MOSFET is bonded to the gate rail 130 of the Vdd-side SiC MOSFET, which is extended and has an external terminal connection pattern.

[0100] The Kelvin terminals of SiC MOSFET 8 214, SiC MOSFET 10 218, and SiC MOSFET 12 222 are respectively bonded to the Kelvin terminal rail 128 of the Vdd-side SiC MOSFET, and the Kelvin terminal rail 128 of the Vdd-side SiC MOSFET is bonded to the Kelvin terminal 129 of the Vdd-side SiC MOSFET.

[0101] The SiC MOSFET SSC power switch module configuration of the present invention, utilizing gate rails and an auxiliary substrate, provides wide-area Vdd power patterns 102, 106, Vss power pattern 104, and Pout pattern 134, thereby increasing the cross-sectional area of ​​the current flow patterns, enabling the transmission of large currents, and providing efficient heat dissipation characteristics. Furthermore, by applying an auxiliary substrate insulated from the SSC substrate, the effects caused by leakage current, parasitic voltage, etc., are eliminated, thereby further improving the high input impedance electrical characteristics of the SiC MOSFET module's gate terminals. This minimizes the size of the SiC MOSFET module, allowing externally led-out terminals to be configured along a uniaxial direction.

[0102] Figure 14 The diagram illustrates the package and pinout of the SSC power switch module of the present invention, which utilizes a SiC MOSFET with an additional gate resistor. For ease of understanding, the SSC substrate inside the package is exposed in the figure, with the other side of the package contacting an external heat sink. The upper surface of the package, to which the components are attached, is impregnated with resin and located within the package.

[0103] and Figure 9 Similarly, the pins of the external terminals provided in the package of the SSC power switch module of the present invention include: power supply terminals Vdd and Vss of a half-bridge circuit structure, output terminal Pout, gate terminal G1 and Kelvin terminal K1 on the Vdd side, gate terminal G2 and Kelvin terminal K2 on the Vss side, terminals NTC1 and NTC2 of the NTC thermistor, and the common terminal NTC_COM of the thermistor.

[0104] The configuration of the SiC MOSFET SSC power switch module of the present invention, as described above, utilizing gate rails and an auxiliary substrate, is characterized by providing wide-area Vdd power supply patterns 102, 106, Vss power supply pattern 104, and Pout pattern 134, thereby increasing the cross-sectional area of ​​the current flow patterns, enabling the transmission of large currents, and providing efficient heat dissipation characteristics. Furthermore, by applying an auxiliary substrate insulated from the SSC substrate, the effects caused by leakage current, parasitic voltage, etc., are eliminated, thereby improving the high input impedance electrical characteristics of the SiC MOSFET module's gate terminals. This minimizes the size of the SiC MOSFET module, allowing the externally led-out terminals to be configured along a uniaxial direction.

[0105] Furthermore, regarding the configuration of the SiC MOSFET SSC power switch module of the present invention utilizing gate rails and auxiliary substrates, although it is described as utilizing SiC MOSFETs for the purpose of clearly illustrating the invention, it may also be composed of other switching elements such as bipolar junction transistors (BJTs) or insulated gate bipolar transistors (IGBTs).

[0106] Although the SiC MOSFET SSC power switch module utilizing gate rails and auxiliary substrates of the present invention has been described with reference to specific embodiments and drawings, the present invention is not limited thereto. It will be understood by those skilled in the art that various modifications and variations can be made within the equivalent scope of the technical concept and claims of the present invention.

[0107] [Industry Applicability] The SiC MOSFET SSC power switch module of the present invention, which utilizes a gate rail and an auxiliary substrate, can be used in industries such as semiconductor manufacturing and application, electric vehicles, drones, and high-power inverters / converters.

Claims

1. A SiC MOSFET SSC power switch module utilizing a gate rail and an auxiliary substrate, comprising: The SiC MOSFET SSC power switch module includes an SSC substrate (100). On the left side of the component arrangement surface of the SSC substrate (100), there is a left Vdd power supply pattern (102) that connects to the positive power supply of the half-bridge circuit, namely Vdd. On the right side of the component configuration surface of the SSC substrate (100), a right-side Vdd power supply pattern (106) is provided. The right Vdd power pattern (106) extends from the lower end of the left Vdd power pattern (102) to the right end. At the upper end between the left Vdd power supply pattern (102) and the right Vdd power supply pattern (106), a Vss power supply pattern (104) is configured to connect to the negative power supply of the half-bridge circuit, namely Vss. At the lower end of the Vss power pattern (104), a Kelvin terminal rail (108) of the Vss-side SiC MOSFET is formed. At the lower end of the Kelvin terminal rail (108) of the Vss-side SiC MOSFET, a drain connection pattern (110) of the Vss-side SiC MOSFET is formed between the left Vdd power supply pattern (102) and the right Vdd power supply pattern (106). Inside the drain connection pattern (110) of the Vss-side SiC MOSFET, there are a first gate connection pattern (112) and a second gate connection pattern (114) of the Vss-side SiC MOSFET. Between the drain connection pattern (110) of the Vss-side SiC MOSFET and the right-side Vdd power supply pattern (106), there is a Kelvin terminal relay pattern (116) of the Vss-side SiC MOSFET. At the lower end of the drain connection pattern (110) of the Vss-side SiC MOSFET, a gate rail (118) of the Vss-side SiC MOSFET is provided. Inside the extension of the right Vdd power pattern (106) extending from the lower end of the left Vdd power pattern (102) to the right end, there are provided a Kelvin terminal lead-out pattern (120) of the Vss-side SiC MOSFET, a first gate connection pattern (122) of the Vdd-side SiC MOSFET, a second gate connection pattern (124) of the Vdd-side SiC MOSFET, and a third gate connection pattern (126) of the Vdd-side SiC MOSFET. At the lower end of the extension of the right Vdd power pattern (106) extending from the lower end of the left Vdd power pattern (102) to the right end, a Kelvin terminal rail (128) of the Vdd-side SiC MOSFET is provided. At the lower end of the Kelvin terminal rail (128) of the Vdd-side SiC MOSFET, the gate rail (130) of the Vdd-side SiC MOSFET is provided. On the lower left side of the SSC substrate (100), the end of the left Vdd power supply pattern (102) extends. On the right side of the end of the extended left-side Vdd power supply pattern (102), a plurality of external terminal connection patterns (129-139) are formed, wherein the Kelvin terminal (129) of the Vdd-side SiC MOSFET and the gate rail (130) of the Vdd-side SiC MOSFET extend and are formed as external terminal connection patterns. On the right side of the multiple external terminal connection patterns (129-133) and at the lower end of the gate rail (130) of the Vdd-side SiC MOSFET, the Pout pattern (134) of the half-bridge circuit composed of SiC MOSFETs is formed as an external terminal connection pattern. On the right side of the Pout pattern (134), there are NTC1 external terminal connection pattern (135), NTC2 external terminal connection pattern (138), and NTC_COM external terminal connection pattern (139) for the common terminal of NTC1 and NTC2. To the right of the NTC_COM external terminal connection pattern (139), the Pout pattern (134) extends and forms an external terminal connection pattern. On the right side of the external terminal connection pattern (135) of the NTC1, a Kelvin terminal connection pattern (136) of the Vss-side SiC MOSFET and a gate connection pattern (137) of the Vss-side SiC MOSFET are formed.

2. The SiC MOSFET SSC power switch module utilizing a gate rail and an auxiliary substrate according to claim 1, characterized in that, On the SSC substrate (100), A first gate connection auxiliary substrate (112s) of the Vss-side SiC MOSFET is attached to the first gate connection pattern (112) of the Vss-side SiC MOSFET. A second gate connection auxiliary substrate (114s) of the Vss-side SiC MOSFET is attached to the second gate connection pattern (114) of the Vss-side SiC MOSFET. An auxiliary substrate (120s) for the Kelvin terminal lead-out pattern (120) of the Vss-side SiC MOSFET is attached. A first gate connection auxiliary substrate (122s) of the Vdd-side SiC MOSFET is attached to the first gate connection pattern (122) of the Vdd-side SiC MOSFET. A second gate connection auxiliary substrate (124s) of the Vdd-side SiC MOSFET is connected to the second gate connection pattern (124) of the Vdd-side SiC MOSFET. A third gate connection auxiliary substrate (126s) for the Vdd-side SiC MOSFET is attached to the third gate connection pattern (126) of the Vdd-side SiC MOSFET. On the left side of the first gate connection auxiliary substrate (112s) of the Vss-side SiC MOSFET, SiC MOSFET1 (200) and SiC MOSFET2 (202) are attached to the drain connection pattern (110) of the Vss-side SiC MOSFET, making the drains of SiC MOSFET1 (200) and SiC MOSFET2 (202) respectively conductive. On the drain connection pattern (110) of the Vss-side SiC MOSFET between the first gate connection auxiliary substrate (112s) and the second gate connection auxiliary substrate (114s) of the Vss-side SiC MOSFET, SiC MOSFET3 (204) and SiC MOSFET4 (206) are attached to the drain connection pattern (110), making the drains of SiC MOSFET3 (204) and SiC MOSFET4 (206) respectively conductive. On the drain connection pattern (110) of the Vss-side SiC MOSFET on the right side of the second gate connection auxiliary substrate (114s) of the Vss-side SiC MOSFET, SiC MOSFET5 (208) and SiC MOSFET6 (210) are attached to the drain connection pattern (110) of the Vss-side SiC MOSFET, so that the drains of SiC MOSFET5 (208) and SiC MOSFET6 (210) are respectively conductive. On the right-side Vdd power supply pattern (106) between the auxiliary substrate (120s) for the Kelvin terminal lead-out of the Vss-side SiC MOSFET and the auxiliary substrate (122s) for the first gate connection of the Vdd-side SiC MOSFET, SiC MOSFET 7 (212) and SiC MOSFET 8 (214) are attached to the right-side Vdd power supply pattern (106), making the drains of SiC MOSFET 7 (212) and SiC MOSFET 8 (214) conductive. On the right-side Vdd power supply pattern (106) between the first gate connection auxiliary substrate (122s) and the second gate connection auxiliary substrate (124s) of the Vdd-side SiC MOSFET, SiC MOSFET 9 (216) and SiC MOSFET 10 (218) are attached to the right-side Vdd power supply pattern (106), such that the drains of SiC MOSFET 9 (216) and SiC MOSFET 10 (218) are conductive. On the left Vdd power pattern (102) connected to the right Vdd power pattern (106) between the second gate connection auxiliary substrate (124s) and the third gate connection auxiliary substrate (126s) of the Vdd-side SiC MOSFET, SiC MOSFET 11 (220) and SiC MOSFET 12 (222) are attached to the left Vdd power pattern (102), making the drains of SiC MOSFET 11 (220) and SiC MOSFET 12 (222) respectively conductive. One end of NTC1 (224) is connected to the external terminal connection pattern (135) of NTC1, and one end of NTC2 (226) is connected to the external terminal connection pattern (138) of NTC2. The other ends of NTC1 and NTC2 are connected to the external terminal connection pattern (139) of NTC_COM.

3. The SiC MOSFET SSC power switch module utilizing a gate rail and an auxiliary substrate according to claim 2, characterized in that, On the SSC substrate (100), The gate terminals and Kelvin terminals of the SiC MOSFET1 (200) and the SiC MOSFET2 (202) are arranged in a direction opposite to the first gate connection auxiliary substrate (112s) of the Vss-side SiC MOSFET. The gate terminals and Kelvin terminals of the SiC MOSFET3 (204) and the SiC MOSFET4 (206) are arranged in a direction opposite to the first gate connection auxiliary substrate (112s) of the Vss-side SiC MOSFET. The gate terminals and Kelvin terminals of the SiC MOSFET5 (208) and the SiC MOSFET6 (210) are arranged in a direction opposite to the second gate connection auxiliary substrate (114s) of the Vss-side SiC MOSFET. The gate terminals and Kelvin terminals of the SiC MOSFET7 (212) and the SiC MOSFET8 (214) are configured in an orientation opposite to the first gate connection auxiliary substrate (122s) of the Vdd-side SiC MOSFET. The gate terminals and Kelvin terminals of the SiC MOSFET9 (216) and the SiC MOSFET10 (218) are configured in an orientation opposite to the second gate connection auxiliary substrate (124s) of the Vdd-side SiC MOSFET. The gate terminals and Kelvin terminals of the SiC MOSFET11 (220) and the SiC MOSFET12 (222) are configured in an orientation opposite to the third gate connection auxiliary substrate (126s) of the Vdd-side SiC MOSFET.

4. The SiC MOSFET SSC power switch module utilizing a gate rail and an auxiliary substrate according to claim 3, characterized in that, On the SSC substrate (100), The drain terminals of the SiC MOSFET1 (200), SiC MOSFET2 (202), SiC MOSFET3 (204), SiC MOSFET4 (206), SiC MOSFET5 (208), and SiC MOSFET6 (210) are attached to the drain connection pattern (110) of the SiC MOSFET on the Vss side by soldering or sintering. The drain terminals of the SiC MOSFET7 (212), SiC MOSFET8 (214), SiC MOSFET9 (216), SiC MOSFET10 (218), SiC MOSFET11 (220), and SiC MOSFET12 (222) are attached to the left Vdd power pattern (102) and the right Vdd power pattern (106) connected to the left Vdd power pattern (102) by soldering or sintering. The auxiliary substrate is fixedly attached to the corresponding pattern using an insulating adhesive.

5. The SiC MOSFET SSC power switch module utilizing a gate rail and an auxiliary substrate according to claim 3, characterized in that, On the SSC substrate (100), The source terminals of SIC MOSFET1 (200) and SIC MOSFET2 (202) are connected in parallel by multiple bond wires to carry large current and are bonded to the Vss power pattern (104) of the half-bridge circuit. The source terminals of SIC MOSFET3 (204) and SIC MOSFET4 (206) are connected in parallel by multiple bond wires to carry large currents and are bonded to the Vss power pattern (104) of the half-bridge circuit. The source terminals of SIC MOSFET5 (208) and SIC MOSFET6 (210) are connected in parallel by multiple bond wires to carry large currents and are bonded to the Vss power pattern (104) of the half-bridge circuit. The source terminals of SIC MOSFET7 (212) and SIC MOSFET8 (214) are connected in parallel via multiple bonding wires to carry large currents, and one end is bonded to the drain connection pattern (110) of the SIC MOSFET on the Vss side, while the other end extends to and is bonded to the Pout pattern (134). The source terminals of SIC MOSFET9 (216) and SIC MOSFET10 (218) are connected in parallel via multiple bond wires to carry large currents, and one end is bonded to the drain connection pattern (110) of the SIC MOSFET on the Vss side, while the other end extends to and is bonded to the Pout pattern (134). The source terminals of SIC MOSFET11 (220) and SIC MOSFET12 (222) are connected in parallel via multiple bond wires to carry large currents, and one end is bonded to the drain connection pattern (110) of the SIC MOSFET on the Vss side, while the other end extends to and is bonded to the Pout pattern (134). The gate terminals of SIC MOSFET1 (200) and SIC MOSFET2 (202) and the gate terminals of SIC MOSFET3 (204) and SIC MOSFET4 (206) are respectively bonded to the first gate connection auxiliary substrate (112s) of the Vss-side SIC MOSFET. The gate terminals of SIC MOSFET5 (208) and SIC MOSFET6 (210) are respectively bonded to the second gate connection auxiliary substrate (114s) of the Vss-side SIC MOSFET. The first gate connection auxiliary substrate (112s) and the second gate connection auxiliary substrate (114s) of the Vss-side SiC MOSFET are respectively bonded to the gate rail (118) of the Vss-side SiC MOSFET. The gate rail (118) of the Vss-side SiC MOSFET is bonded to the gate connection pattern (137) of the Vss-side SiC MOSFET. The Kelvin terminals of SIC MOSFET1 (200), SIC MOSFET3 (204), and SIC MOSFET5 (208) are bonded to the Kelvin terminal rail (108) of the SIC MOSFET on the Vss side, respectively. One end of the Kelvin terminal rail (108) of the Vss-side SiC MOSFET is bonded to the Kelvin terminal relay pattern (116) of the Vss-side SiC MOSFET. After the Kelvin terminal relay pattern (116) of the Vss-side SiC MOSFET is bonded to the Kelvin terminal lead-out auxiliary substrate (120s) of the Vss-side SiC MOSFET, the Kelvin terminal lead-out auxiliary substrate (120s) of the Vss-side SiC MOSFET is bonded to the Kelvin terminal connection pattern (136) of the Vss-side SiC MOSFET. The gate terminals of SIC MOSFET7 (212) and SIC MOSFET8 (214) are respectively bonded to the first gate connection auxiliary substrate (122s) of the Vdd-side SIC MOSFET. The first gate connection auxiliary substrate (122s) of the Vdd-side SiC MOSFET is bonded to the gate rail (130) of the Vdd-side SiC MOSFET, which is extended to form an external terminal connection pattern. The gate terminals of SIC MOSFET9 (216) and SIC MOSFET10 (218) are respectively bonded to the second gate connection auxiliary substrate (124s) of the Vdd-side SIC MOSFET. The second gate connection auxiliary substrate (124s) of the Vdd-side SiC MOSFET is bonded to the gate rail (130) of the Vdd-side SiC MOSFET, which is extended with an external terminal connection pattern. The gate terminals of SIC MOSFET11 (220) and SIC MOSFET12 (222) are respectively bonded to the third gate connection auxiliary substrate (126s) of the Vdd-side SIC MOSFET, and the third gate connection auxiliary substrate (126s) of the Vdd-side SIC MOSFET is bonded to the gate rail (130) of the Vdd-side SIC MOSFET which is extended with an external terminal connection pattern. The Kelvin terminals of SIC MOSFET8 (214), SIC MOSFET10 (218), and SIC MOSFET12 (222) are bonded to the Kelvin terminal rail (128) of the Vdd-side SIC MOSFET, respectively. The Kelvin terminal rail (128) of the Vdd-side SiC MOSFET is bonded to the Kelvin terminal (129) of the Vdd-side SiC MOSFET.

6. The SiC MOSFET SSC power switch module utilizing a gate rail and an auxiliary substrate according to claim 1, characterized in that, On the SSC substrate (100), A first gate connection auxiliary substrate (112s) of the Vss-side SiC MOSFET is attached to the first gate connection pattern (112) of the Vss-side SiC MOSFET. The four gate resistors corresponding to the SiC MOSFET are attached to the first gate connection auxiliary substrate (112s) of the Vss-side SiC MOSFET by soldering or silver epoxy sintering. A second gate connection auxiliary substrate (114s) of the Vss-side SiC MOSFET is attached to the second gate connection pattern (114) of the Vss-side SiC MOSFET. The two gate resistors corresponding to the SiC MOSFET are attached to the second gate connection auxiliary substrate (114s) of the Vss-side SiC MOSFET by soldering or silver epoxy sintering. An auxiliary substrate (120s) for the Kelvin terminal lead-out pattern (120) of the Vss-side SiC MOSFET is attached. A first gate connection auxiliary substrate (122s) of the Vdd-side SiC MOSFET is attached to the first gate connection pattern (122) of the Vdd-side SiC MOSFET. The gate resistor corresponding to the SiC MOSFET is attached to the first gate connection auxiliary substrate (122s) of the Vdd-side SiC MOSFET by soldering or silver epoxy sintering. A second gate connection auxiliary substrate (124s) of the Vdd-side SiC MOSFET is connected to the second gate connection pattern (124) of the Vdd-side SiC MOSFET. The two gate resistors corresponding to the SiC MOSFET are attached to the second gate connection auxiliary substrate (124s) of the Vdd-side SiC MOSFET by soldering or silver epoxy sintering. A third gate connection auxiliary substrate (126s) for the Vdd-side SiC MOSFET is attached to the third gate connection pattern (126) of the Vdd-side SiC MOSFET. The two gate resistors corresponding to the SiC MOSFET are attached to the third gate connection auxiliary substrate (126s) of the Vdd-side SiC MOSFET by soldering or silver epoxy sintering. On the left side of the first gate connection auxiliary substrate (112s) of the Vss-side SiC MOSFET, the gate terminals and Kelvin terminals of the SiC MOSFET1 (200) and the SiC MOSFET2 (202) are arranged in a direction opposite to the first gate connection auxiliary substrate (112s) of the Vss-side SiC MOSFET. The SiC MOSFET1 (200) and SiC MOSFET2 (202) are attached to the drain connection pattern (110) of the Vss-side SiC MOSFET, so that the drains of the SiC MOSFET1 (200) and SiC MOSFET2 (202) are respectively conductive. On the drain connection pattern (110) of the Vss-side SiC MOSFET between the first gate connection auxiliary substrate (112s) and the second gate connection auxiliary substrate (114s) of the Vss-side SiC MOSFET, the gate terminals and Kelvin terminals of SiC MOSFET3 (204) and SiC MOSFET4 (206) are arranged in a direction opposite to the first gate connection auxiliary substrate (112s) of the Vss-side SiC MOSFET. The SiC MOSFET3 (204) and the SiC MOSFET4 (206) are attached to the drain connection pattern (110) so that the drains of the SiC MOSFET3 (204) and the SiC MOSFET4 (206) are conductive. On the drain connection pattern (110) of the Vss-side SiC MOSFET on the right side of the second gate connection auxiliary substrate (114s) of the Vss-side SiC MOSFET, the gate terminals and Kelvin terminals of SiC MOSFET5 (208) and SiC MOSFET6 (210) are arranged in a direction opposite to the second gate connection auxiliary substrate (114s) of the Vss-side SiC MOSFET. SiC MOSFET5 (208) and SiC MOSFET6 (210) are attached to the drain connection pattern (110) of the Vss-side SiC MOSFET, so that the drains of SiC MOSFET5 (208) and SiC MOSFET6 (210) are respectively conductive. On the right-side Vdd power supply pattern (106) between the auxiliary substrate (120s) for the Kelvin terminal lead-out of the Vss-side SiC MOSFET and the auxiliary substrate (122s) for the first gate connection of the Vdd-side SiC MOSFET, the gate terminals and Kelvin terminals of SiC MOSFET 7 (212) and SiC MOSFET 8 (214) are arranged in a direction opposite to the first gate connection auxiliary substrate (122s) of the Vdd-side SiC MOSFET. SiC MOSFET 7 (212) and SiC MOSFET 8 (214) are attached to the right-side Vdd power supply pattern (106), making the drains of SiC MOSFET 7 (212) and SiC MOSFET 8 (214) conductive. On the right-side Vdd power supply pattern (106) between the first gate connection auxiliary substrate (122s) and the second gate connection auxiliary substrate (124s) of the Vdd-side SiC MOSFET, the gate terminals and Kelvin terminals of SiC MOSFET 9 (216) and SiC MOSFET 10 (218) are arranged in a direction opposite to the second gate connection auxiliary substrate (124s) of the Vdd-side SiC MOSFET. SiC MOSFET 9 (216) and SiC MOSFET 10 (218) are attached to the right-side Vdd power supply pattern (106), making the drains of SiC MOSFET 9 (216) and SiC MOSFET 10 (218) conductive. On the left Vdd power pattern (102) connected to the right Vdd power pattern (106) between the second gate connection auxiliary substrate (124s) and the third gate connection auxiliary substrate (126s) of the Vdd-side SiC MOSFET, the gate terminals and Kelvin terminals of SiC MOSFET 11 (220) and SiC MOSFET 12 (222) are arranged in a direction opposite to the third gate connection auxiliary substrate (126s) of the Vdd-side SiC MOSFET. SiC MOSFET 11 (220) and SiC MOSFET 12 (222) are attached to the left Vdd power pattern (102), making the drains of SiC MOSFET 11 (220) and SiC MOSFET 12 (222) respectively conductive. One end of NTC1 (224) is connected to the external terminal connection pattern (135) of NTC1, and one end of NTC2 (226) is connected to the external terminal connection pattern (138) of NTC2. The other ends of NTC1 and NTC2 are connected to the external terminal connection pattern (139) of NTC_COM.

7. The SiC MOSFET SSC power switch module utilizing a gate rail and an auxiliary substrate according to claim 6, characterized in that, On the SSC substrate (100), The source terminals of SIC MOSFET1 (200) and SIC MOSFET2 (202) are connected in parallel by multiple bond wires to carry large current and are bonded to the Vss power pattern (104) of the half-bridge circuit. The source terminals of SIC MOSFET3 (204) and SIC MOSFET4 (206) are connected in parallel by multiple bond wires to carry large currents and are bonded to the Vss power pattern (104) of the half-bridge circuit. The source terminals of SIC MOSFET5 (208) and SIC MOSFET6 (210) are connected in parallel by multiple bond wires to carry large currents and are bonded to the Vss power pattern (104) of the half-bridge circuit. The source terminals of SIC MOSFET7 (212) and SIC MOSFET8 (214) are connected in parallel via multiple bonding wires to carry large currents, and one end is bonded to the drain connection pattern (110) of the SIC MOSFET on the Vss side, while the other end extends to and is bonded to the Pout pattern (134). The source terminals of SIC MOSFET9 (216) and SIC MOSFET10 (218) are connected in parallel via multiple bond wires to carry large currents, and one end is bonded to the drain connection pattern (110) of the SIC MOSFET on the Vss side, while the other end extends to and is bonded to the Pout pattern (134). The source terminals of SIC MOSFET11 (220) and SIC MOSFET12 (222) are connected in parallel via multiple bond wires to carry large currents, and one end is bonded to the drain connection pattern (110) of the SIC MOSFET on the Vss side, while the other end extends to and is bonded to the Pout pattern (134). The gate terminals of SiC MOSFET1 (200) and SiC MOSFET2 (202) and the gate terminals of SiC MOSFET3 (204) and SiC MOSFET4 (206) are respectively bonded to the gate resistors of the first gate connection auxiliary substrate (112s) of the SiC MOSFETs fixedly attached to the Vss side. The gate terminals of SiC MOSFET5 (208) and SiC MOSFET6 (210) are respectively bonded to the gate resistors of the second gate connection auxiliary substrate (114s) that are respectively fixedly attached to the Vss side of the SiC MOSFET. The first gate connection auxiliary substrate (112s) and the second gate connection auxiliary substrate (114s) of the Vss-side SiC MOSFET are respectively bonded to the gate rail (118) of the Vss-side SiC MOSFET, and the gate rail (118) of the Vss-side SiC MOSFET is bonded to the gate connection pattern (137) of the Vss-side SiC MOSFET. The Kelvin terminals of SIC MOSFET1 (200), SIC MOSFET3 (204), and SIC MOSFET5 (208) are respectively bonded to the gate resistors of the Kelvin terminal rails (108) of the SIC MOSFETs on the Vss side. One end of the Kelvin terminal rail (108) of the Vss-side SiC MOSFET is bonded to the Kelvin terminal relay pattern (116) of the Vss-side SiC MOSFET. After the Kelvin terminal relay pattern (116) of the Vss-side SiC MOSFET is bonded to the Kelvin terminal lead-out auxiliary substrate (120s) of the Vss-side SiC MOSFET, the Kelvin terminal lead-out auxiliary substrate (120s) of the Vss-side SiC MOSFET is bonded to the Kelvin terminal connection pattern (136) of the Vss-side SiC MOSFET. The gate terminals of SIC MOSFET7 (212) and SIC MOSFET8 (214) are respectively bonded to the gate resistors of the first gate connection auxiliary substrate (122s) of the Vdd-side SIC MOSFET, which are respectively fixedly attached to the first gate connection auxiliary substrate (122s) of the Vdd-side SIC MOSFET. The first gate connection auxiliary substrate (122s) of the Vdd-side SIC MOSFET is bonded to the gate rail (130) of the Vdd-side SIC MOSFET, which is extended to form an external terminal connection pattern. The gate terminals of SiC MOSFET9 (216) and SiC MOSFET10 (218) are respectively bonded to the gate resistors of the second gate connection auxiliary substrate (124s) of the SiC MOSFET on the Vdd side. The second gate connection auxiliary substrate (124s) of the Vdd-side SiC MOSFET is bonded to the gate rail (130) of the Vdd-side SiC MOSFET, which is extended with an external terminal connection pattern. The gate terminals of SIC MOSFET11 (220) and SIC MOSFET12 (222) are respectively bonded to the gate resistors of the third gate connection auxiliary substrate (126s) of the Vdd-side SIC MOSFET, which are respectively fixedly attached to the third gate connection auxiliary substrate (126s) of the Vdd-side SIC MOSFET. The third gate connection auxiliary substrate (126s) of the Vdd-side SIC MOSFET is bonded to the gate rail (130) of the Vdd-side SIC MOSFET, which is extended with an external terminal connection pattern. The Kelvin terminals of SIC MOSFET8 (214), SIC MOSFET10 (218), and SIC MOSFET12 (222) are respectively bonded to the Kelvin terminal rail (128) of the Vdd-side SIC MOSFET, and the Kelvin terminal rail (128) of the Vdd-side SIC MOSFET is bonded to the Kelvin terminal (129) of the Vdd-side SIC MOSFET.

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