Method and apparatus for accelerating randomization workloads

Abstract

A computing device or system includes a randomness core, a kernel core, and a randomness distribution element; the randomness core passes one or more random numbers to the randomness distribution element, the randomness distribution element passes one or more random numbers to the kernel core, the kernel core includes the one or more random numbers into one or more computing workloads, and the randomness core and the kernel core are two different logical or physical elements. Also provided are a field programmable gate array, an integrated circuit board assembly, and a method for post-processing random numbers.

Description

Background Technology

[0001] Since its inception, information technology has been a fundamental changer in the society we live in, both industrially and in everyday life. Computers have been seamlessly integrated into the fabric of modern society, becoming indispensable tools and transforming how we interact with each other and how we work. From healthcare and finance to entertainment and transportation, virtually every industry has experienced a paradigm shift, with data-driven decision-making and computational solutions becoming the norm.

[0002] This enhanced capability has also made computationally complex activities, previously considered impossible, possible. Calculations and simulations that seemed infeasible fifty years ago can now be accomplished with the computing power of a mobile phone; proportionally, today's supercomputers run extremely complex simulations, making full use of their computing power and allowing us to push the efficiency and quality of decision-making to unprecedented limits.

[0003] For example, in climate modeling, today's computing power enables scientists to simulate complex climate systems, providing insights into climate change trends and informing mitigation strategies. Similarly, in personalized medicine, computational analysis of individual genomes enables previously unthinkable customized treatment plans and predictive diagnoses. This progress is also evident in the field of communications security, where advanced cryptographic algorithms ensure secure transactions and information exchange—a feat achieved by computing power that was once purely speculative.

[0004] To maintain this speed, our available effective computing power must be increased proportionally. Historically, computing power has been increased by using faster or more processors. However, the limitations of this approach have become apparent with the demands of today's problems. While effective for some tasks, traditional processors need assistance to provide the speed, capacity, efficiency, or latency required by today's problems. Therefore, as data volume and model complexity increase, the need for specialized solutions becomes increasingly evident.

[0005] To address this issue, hardware-based accelerators have entered the market to complement the capabilities of traditional processors. These accelerators offer specialized circuitry optimized for specific workloads, enhancing the efficiency of all tasks from real-time rendering to artificial intelligence.

[0006] Because they focus on specific types of tasks, different types of accelerators have emerged, each offering a specific architecture suitable for a particular workload. The most well-known of these accelerators is the Graphics Processing Unit (GPU), which features a highly parallelizable architecture with many cores optimized for simultaneous computation, providing an excellent platform for workloads requiring massive data parallelization. Examples of such workloads can be found in scientific simulations, machine learning, generative artificial intelligence, or cryptography.

[0007] Other accelerators gaining widespread attention include application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs). They offer specialized circuit systems and high power efficiency levels. Their primary use cases are in networking and cryptography, where they generally outperform any other alternative.

[0008] In addition to these established accelerators, there is a range of promising solutions within the hardware accelerator space, despite their lower industrial penetration or readiness. Examples of these include Tensor Processing Units (TPUs), which are dedicated to matrix-vector multiplication, crucial in machine learning workloads; or Quantum Processing Units (QPUs), which utilize quantum systems to leverage quantum properties to solve computational problems, such as in tasks like optimization and cryptanalysis.

[0009] While hardware accelerators are designed to excel in specific tasks, they often struggle when applications exceed their intended scope, limiting their adaptability and causing inefficiencies. For example, an accelerator optimized for real-time video rendering may encounter problems handling machine learning algorithms or cryptography, resulting in degraded performance and suboptimal results. Another example is an accelerator optimized for large matrix-vector operations, which is extremely inefficient when running word processing applications.

[0010] For example, while GPUs excel at graphics rendering, they fall short in handling real-time physics simulations or other computationally intensive applications, posing a challenge to seamlessly balancing computational complexity and real-time performance. Other accelerators, for instance, may find themselves unable to handle machine learning workloads, as these rely on massive datasets and the ability to process such data rapidly.

[0011] Furthermore, for applications such as autonomous driving, augmented reality, or real-time risk assessment, achieving low-latency performance is crucial for minimizing the delay between input and output. However, existing hardware accelerators may introduce processing latency due to architectural complexity or inefficient data transfer. Additionally, the demanding computational requirements of modern applications can overwhelm existing accelerators, leading to excessive power consumption.

[0012] In addition to the challenges outlined, existing hardware accelerators encounter specific limitations in handling the complex demands of stochastic, intensive workloads. These workloads are critical in diverse domains such as scientific simulations, cryptographic protocols, and specialized machine learning tasks.

[0013] Their fundamental reliance on the precise manipulation of random data is essential for their accurate and reliable results. For example, in scientific simulations, the behavior of complex systems under different conditions requires the injection of randomized variables to simulate real-world scenarios. Similarly, cryptographic protocols depend on generating and managing random keys to ensure unbreakable encryption, security, and privacy.

[0014] GPUs and TPUs excel at parallel processing, but they lack dedicated circuitry optimized for truly random number generation. This deficiency exposes cryptographic applications to potential biases or vulnerabilities, compromising their security and trustworthiness.

[0015] Similarly, FPGAs, which are known for their reconfigurability, may lack the specialized components required to efficiently generate or process randomness, which hinders their performance in analog or cryptographic protocols.

[0016] Moreover, while promising for specific tasks, QPUs still require the maturity and accuracy necessary for reliable randomness generation, which limits their suitability for certain applications.

[0017] Finally, ASICs, known for their application-specific designs, face challenges in accommodating the inherent uncertainty of stochastic, intensive workloads. While their inflexible, specialized architectures can prove advantageous in the target scenario, their lack of versatility prevents them from handling the complex and diverse needs for random data manipulation in fields such as scientific research, cryptography, and machine learning.

[0018] In summary, existing accelerator environments cannot meet the fine-tuning requirements of stochastic-intensive workloads. The complexities arising from the inherent unpredictability and variability of stochasticity receive limited attention within conventional accelerator paradigms.

[0019] With these workloads proliferating in critical sectors, the need for a new hardware accelerator paradigm is stronger than ever, one that is meticulously crafted to overcome the obstacles posed by randomness. Summary of the Invention

[0020] A first aspect of this disclosure relates to a randomness processing device, referred to herein as an RPU or "randomness processing unit," which includes at least a randomness core and a kernel computing core. These at least two cores are physically or logically distinct and communicate between them via a so-called randomness distributed element (RDE).

[0021] According to this disclosure, a randomness core (or multiple cores) is a specialized device or system designed to handle randomness-related computations, such as entropy generation, distribution sampling, or correlated random streams. The primary, non-limiting focus of these randomness cores is to offload the workload of other parts of the computationally intensive burden associated with randomness generation and / or manipulation, and to provide high-quality randomness distributions for consumer applications, thereby improving speed, quality, and efficiency. This allows randomness-intensive workloads to be offloaded to the randomness core, enabling the RPU to be used as a hardware accelerator to perform more complex and computationally demanding tasks, similar to how a GPU frees up the CPU from rendering tasks.

[0022] In some embodiments, the randomness core includes at least one physical entropy source. Examples of these include, but are not limited to, quantum random number generators (QRNGs) or true random number generators (TRNGs). In some embodiments, these randomness cores include at least one hardware-implemented sampler. Examples of these include, but are not limited to, ASICs that generate floating-point random numbers from the randomness source or electronic circuits that generate Gaussian numbers from the randomness source. In some embodiments, these randomness cores include at least one firmware or software-implemented sampler. Examples of these include, but are not limited to, FPGA and / or FPGA intellectual property (IP) cores that generate floating-point random numbers from the randomness source or microcontrollers that execute code to generate Gaussian numbers from the randomness source.

[0023] According to this disclosure, a kernel computing core (also referred to herein as a kernel core) includes at least one device or system capable of executing at least one workload of interest. In a preferred embodiment, these workloads have randomness requirements. Examples of such workloads include, but are not limited to, Monte Carlo simulations, randomized optimizers, or cryptographic cores. In some embodiments, these kernel cores include at least one hardware-implemented workload. Examples of these include, but are not limited to, an ASIC that executes cryptographic primitives or circuitry that performs inference on a neural network. In some embodiments, these kernel cores include at least one firmware or software-implemented workload. Examples of these include, but are not limited to, an FPGA IP core implementing a Monte Carlo sampler or a processor implementing randomized optimization routines.

[0024] In some embodiments, the kernel core supports reprogrammability, allowing the workload it performs to be freely modified by the end user and / or another device that can be communicatively coupled to the core or RPU. Examples of kernel cores include, but are not limited to, a cryptographic primitive core that can change computational security parameters upon end-user request, or a Monte Carlo sampler whose sampling distribution can be configured by the end user.

[0025] In some embodiments, the kernel core supports the execution of a given instruction set, such that the workload it executes can be expressed as a program using that given instruction set. Examples of these include, but are not limited to, using a soft-core or hard-core processor as the kernel core.

[0026] According to this disclosure, a randomness distribution element (RDE) includes at least one element that allows interconnection between at least one randomness core and at least one core core. In some embodiments, the RDE functions as a cache / memory / storage hierarchy. Examples of these include, but are not limited to, static random access memory (SRAM) caches, random access memory (RAM), and solid-state drives (SSDs). In some embodiments, the RDE functions as an internal network interconnection of the implemented device. Examples of this include, but are not limited to, interconnections within memory buffers between FPGAs or NoCs or ASICs, or between entropy sources and processors.

[0027] In some embodiments, all devices and systems including the RPU are integrated within the same device. Examples of these include, but are not limited to, custom-designed silicon devices, such as ASICs or other types of integrated circuits (ICs). In some embodiments, the components including the RPU are made of different types of hardware. Examples of these include, but are not limited to, photonic entropy sources, FPGAs implementing randomness cores, and CPUs implementing kernel cores.

[0028] As a non-limiting example, in some embodiments, the RPU includes a dual-core processor that shares low-level memory between the processors. In this embodiment, one core can be used as a randomization core. In contrast, the other core can be used as a kernel core for computation. The low-level memory acts as a randomization distribution element, sending results from the randomization core to the kernel core. In some other embodiments, the RPU includes at least one processor with more than two cores.

[0029] Another non-limiting example is a combination of a CPU (such as a single-core CPU) and a separate random number generator device, which is, for example, a pseudo-random number generator, a physical entropy source, or a suitable combination of both. In this case, the CPU (e.g., a single-core CPU) contains only the core, and the randomness core is an RNG device.

[0030] More complex, non-restricted implementations might require alternative hardware to the CPU. For example, an RPU architecture could be implemented within a GPU, with one or more blocks / threads dedicated to the randomness generation portion. In contrast, other blocks / threads might be dedicated to executing the kernel core.

[0031] Another non-limiting example implementation is a combination of a field-programmable gate array (FPGA) and a separate random number generator device. In this case, the FPGA can contain the logic required to control the device and all / part of the core computation.

[0032] In some embodiments, randomness and the core reside in different devices: for example, a portion of an FPGA may implement the randomness computation core, while other components implement the core, and the FPGA connectivity device acts as the randomness distribution element.

[0033] In some embodiments, the dedicated regions for randomness and the core may not be monolithic. For example, in implementations, these regions may be interleaved within the FPGA / silicon device, allowing locality to be considered when performing overall computation.

[0034] In some embodiments, the RPU device may be combined with other accelerators to maximize overall performance. As a non-limiting example, the RPU device may be connected to a GPU device on the same card, which computes from the RPU request portion and performs further post-processing on it. The GPU device may also be replaced by a CPU, TPU, FPGA, ASIC, or any suitable combination thereof, which may be used as a pipelined, parallel architecture, or may be displayed in any suitable hierarchy.

[0035] Another aspect of this disclosure relates to a field-programmable gate array configured to emulate at least one RPU, as described in the first aspect.

[0036] Another aspect of this disclosure relates to an integrated circuit board assembly, comprising: at least one RPU as described in the first aspect; a data communication interface for communication between at least the computing device or system and a host device or system; a power connection for receiving power for operating the integrated circuit board; and a software driver executable by the host device or system, configured to manage interaction between the computing device or system and the integrated circuit board assembly, the software driver including instructions for utilizing the device or system to process tasks specified by the computing device.

[0037] Another aspect of this disclosure relates to a method for post-processing random numbers using an RPU device.

[0038] One object of this disclosure is to provide a hardware accelerator that offers superior performance in terms of speed, throughput, capacity, quality, and / or energy efficiency compared to general-purpose computing devices such as CPUs, and is an enabling component for stochastic-intensive workloads. Potential applications and use cases of this disclosure include, but are not limited to, key generation or algorithm acceleration in cryptography, Monte Carlo simulation or heuristic optimization in finance, route optimization and inventory management in logistics, supply chain, grid optimization and risk assessment in energy, genomic analysis in healthcare, synthetic data generation and neural network training in machine learning, atomic system simulation or weather forecasting in scientific computing, etc.

[0039] Overall, this disclosure addresses the limitations of existing solutions in the field of hardware accelerators when computing stochastic-intensive workloads, and provides a more efficient and effective solution for performing such computations.

[0040] The structural and operational details of this disclosure can be best understood by referring to the accompanying drawings, wherein similar reference numerals denote similar parts, and wherein: Attached Figure Description

[0041] Figure 1 An abstract scheme for a randomness processing unit (RPU) device or system is shown.

[0042] Figure 2 An example embodiment of an RPU is shown, which includes two different cores within a CPU device or system.

[0043] Figure 3 An example embodiment of the RPU is shown, which includes multiple different cores within a device or system.

[0044] Figure 4 An example embodiment of an RPU is shown, which includes multiple different cores within a GPU device or system.

[0045] Figure 5 An example embodiment of the RPU is shown, including a heterogeneous combination of different computing devices or systems.

[0046] Figure 6 An example implementation of the RPU is shown, in which multiple randomness cores and kernel cores are intertwined to maximize locality and throughput.

[0047] Figure 7 An example embodiment of the RPU is shown, wherein Figure 5 and 6 The ideas were combined together. Detailed Implementation

[0048] Figure 1An overall scheme of an embodiment of the present disclosure is shown. In this overall scheme, the randomness processing unit (RPU) 100 includes a randomness core 101 and a kernel core 102, which communicate via a randomness distribution element 103.

[0049] Schematic diagram 100 illustrates a single randomness core, a single kernel, and a single randomness distribution element. However, other embodiments include more than one randomness core and / or more than one kernel and / or more than one randomness distribution element. As a non-limiting example, some embodiments include multiple kernels utilizing the results of a single randomness core; other embodiments include multiple randomness cores providing their output data to a single kernel.

[0050] In some embodiments, the randomness core 101 includes a random number generator (RNG) device or system that generates random numbers under a given distribution. In some embodiments, the distribution is a uniform distribution within a given range [a, b) (e.g., [0, 1) or [-1, 1)), i.e., a floating-point uniform distribution. In some embodiments, the distribution is a Gaussian distribution with a given mean and standard deviation.

[0051] Examples of these RNGs include, but are not limited to: pseudo-random number generators (PRNGs), such as linear congruential generators, Mersenne Twister, or Xorshift generators; true random number generators (TRNGs), such as avalanche noise generators, ring oscillator-based RNGs, thermal noise or shot noise-based TRNGs, or analog generators; hardware random number generators (HRNGs), such as physically non-cloning functions, timing jitter-based generators, electronic noise-based generators, or chaos-based generators; quantum random number generators (QRNGs), such as phase-diffusion or VCSEL-based QRNGs; other entropy sources, such as sensor data, radioactive decay detectors, or human input processors; and cryptographic RNGs, specifically designed for cryptographic applications and conforming to cryptographic standards such as NIST SP800-90 and BSI AIS-31.

[0052] In some embodiments, the randomness core 101 combines the output of any of these RNG devices. As a non-limiting example, the cipher PRNG output is combined with the HRNG output to ensure that any failure in the HRNG does not significantly degrade the quality of the randomness core output.

[0053] In some embodiments, the randomness core 101 includes implementations of methods for post-processing random numbers. As a non-limiting example, the randomness core includes a QRNG and a post-processing function that maximizes the entropy per bit of the output. Examples of such post-processing functions include, but are not limited to, hash functions such as SHA-2 and SHA-3; whitening algorithms such as XORing and bit shuffling; error-correcting codes such as matrix transformations and / or Reed-Solomon coding. These post-processing methods are crucial for ensuring the transformation of raw random data into highly unpredictable and statistically robust random bit sequences, making them suitable for a wide range of cryptographic and security-sensitive applications.

[0054] In some embodiments, the input to the randomness core 101 is provided by an RNG device or system. In some embodiments, the input to the randomness core 101 is provided by another randomness core 101. In some embodiments, the input to the post-processing device or system is provided externally, for example, through an RPU input port.

[0055] In some embodiments, the randomness core 101 includes implementations of methods for post-processing random numbers, the purpose of which is not to increase the robustness of the random stream. Examples of such methods include, but are not limited to, generating a floating-point representation of numbers starting from integers or a bitwise representation of random numbers. In some embodiments, the floating-point representation is one of the IEEE-753 floating-point types; for example, 16-bit, 32-bit, and 64-bit floating-point representations. In some embodiments, the floating-point representation is an arbitrary-precision bfloat; for example, an 8-bit or 16-bit bfloat.

[0056] In some embodiments, the randomness core 101 includes a sampler device or system. The purpose of the sampler is to generate samples from a given statistical distribution. In some embodiments, the input to the sampler is provided by an RNG device or system. In some embodiments, the input to the sampler is provided by another randomness core. In some embodiments, the input to a post-processing device or system is provided by a post-processing device or system. In some embodiments, the input to the post-processing device or system is provided by another sampler device or system. In some embodiments, the input to the sampler is provided externally, for example, through an RPU input port.

[0057] In some embodiments, the sampling distribution is a continuous distribution. Examples of such continuous distributions include, but are not limited to: uniform distributions such as [0, 1), [-1, 1], [0, 2^N], [2^(N-1), 2^(N-1)), etc.; normal (Gaussian) distributions with mean and standard deviation such as (0, 1); exponential distributions with rate parameters of 1 or 0.5; gamma distributions with shape and scale parameters such as (2, 1); beta distributions with α and β parameters such as (2, 5); and chi-square distributions with different degrees of freedom, such as 1 or 2. Other continuous distributions include, but are not limited to: Cauchy distribution, log-normal distribution, Weibull distribution, F distribution, Pareto distribution, triangular distribution, Dirichlet distribution, Gombbel distribution, Laplace distribution, and Student's t distribution.

[0058] In some embodiments, the sampling distribution is a discrete distribution. Examples of these include, but are not limited to: a Bernoulli distribution with a success probability of 0.5; a binomial distribution with a number of trials and a success probability of (10, 0.5); and a Poisson distribution with a rate parameter of 1 or 5. Other discrete distributions include, but are not limited to: geometric distributions, negative binomial distributions, hypergeometric distributions, multinomial distributions, discrete uniform distributions, Zipf distributions, and classification distributions.

[0059] In some embodiments, the sampling distribution is a multivariate distribution. Examples of these include, but are not limited to: a multivariate normal distribution with a given mean vector and covariance matrix; a Wieshard distribution with a given degree of freedom and scale matrix parameter; a multivariate Bernoulli distribution; and a Dirichlet multinomial distribution.

[0060] In some embodiments, the sampling distribution is a special type of distribution. Examples of these include, but are not limited to: the generation of copulas with a given correlation structure, the generation of hybrid models combining multiple underlying distributions, Markov chains with specific transition matrices, and hidden Markov models with given state transition and emission probabilities.

[0061] In some embodiments, the sampler implements a specific sampling method. Examples of these include, but are not limited to: inverse transform methods; von Neumann rejection methods; importance sampling methods; hierarchical sampling; Markov chain Monte Carlo methods, such as Metropolis-Hasting or Gibbs samplers; and sequential Monte Carlo methods.

[0062] In some embodiments, the sampling distribution is returned in fixed-point form. As a special case in this regard, in some embodiments, the sampling distribution is returned in integer ranges, such as [0, 2^N) or [-2^(N-1), 2^(N-1)]. In some embodiments, the sampling distribution is returned in floating-point form. Examples of this format include, but are not limited to: IEEE-753 floating-point types, such as 16-bit, 32-bit, and 64-bit floating-point representations; and arbitrary-precision bfloat, such as 8-bit or 16-bit bfloat.

[0063] In some embodiments, some or all of the core randomness components are implemented as hardware-specific devices or systems. The aim of these embodiments is to benefit from the efficiency gained from a custom hardware implementation of the algorithm. Examples of these embodiments include, but are not limited to, QRNGs and ASICs for sampling normal numbers in floating-point form. In this specific example, the ASIC implements the control logic for the QRNG, a method for generating floating-point numbers from the QRNG random stream, and a method for generating floating-point normal random numbers.

[0064] In some embodiments, some or all of the randomness core elements are implemented as firmware or software cores for execution in a hardware device or system. The aim of these embodiments is to benefit from the flexibility offered by firmware or software implementations of the algorithm while still providing reasonable efficiency. Examples of these embodiments include, but are not limited to, QRNGs and FPGAs that implement sampling of normal numbers in floating-point form. Another example of this embodiment is a QRNG with a microprocessor having an instruction set architecture (ISA) containing specific instructions for randomness generation and programs that utilize these instructions within the ISA to improve the performance of the randomness-intensive portions of the execution. Examples of these ISAs include, but are not limited to, RISC-V ISAs with custom extensions.

[0065] According to this disclosure, kernel core 102 includes at least one device or system capable of executing at least one workload of interest. In a preferred embodiment, these workloads have randomness requirements, and a randomness core provides randomness to the kernel via a randomness distribution element. Examples of such workloads include, but are not limited to, Monte Carlo simulations, random optimizers, or cryptographic cores.

[0066] In some embodiments, these kernel cores 102 include at least one hardware-implemented workload. Examples of these include, but are not limited to: ASICs that perform cryptographic primitives to perform encryption / decryption or digital signatures; computing devices that perform inference using neural networks; and digital signal processors (DSPs) that require results from Monte Carlo simulations for operation.

[0067] In some embodiments, these kernel cores 102 include at least one firmware or software-implemented workload. Examples of these include, but are not limited to: GPUs implementing random matrix multiplication, where the coefficients need to have a given structure; FPGA IP cores implementing Monte Carlo samplers (such as the Metropolis-Hasting method); and processors implementing randomized optimization routines, such as genetic algorithms or ant colony optimization algorithms.

[0068] In some embodiments, kernel cores 102 are reprogrammable, allowing the workloads they perform to be changed at will by the end user. Examples of these include, but are not limited to, cryptographic primitive cores whose computational security (e.g., based on requested computational security parameters) can be changed upon request by the end user, or Monte Carlo samplers whose sampling distribution can be configured at will by the end user.

[0069] In some embodiments, kernel core 102 supports the execution of a given instruction set, such that the workloads they execute can be expressed as programs using that given instruction set. Examples of these include, but are not limited to, using a soft-core or hard-core processor as the kernel core.

[0070] According to this disclosure, the Randomness Distribution Element (RDE) 103 includes at least one randomness core and at least one interconnect between at least one core core. In some embodiments, the RDE 103 functions through internal network interconnects of the implemented device. Examples of this include, but are not limited to, interconnects within memory buffers between an FPGA or NoC or ASIC, or between an entropy source and a processor. In some embodiments, the RDE 103 functions through different levels of memory hierarchy. Examples of this include, but are not limited to, storage devices, DDR or HBM memory modules, or different levels of cache memory.

[0071] In some embodiments, a control device or system controls the data flow within the RDE 103. In some of these embodiments, the control device statically or dynamically reconfigures the layout of the RDE, modifying the data flow to better execute the workload currently being performed by the RPU elements.

[0072] The RPU device includes an input port, device, or system 104 that feeds required data and instructions to the randomness core, kernel, and random distribution elements. In some embodiments, input 104 includes a memory-mapped interface, such as direct memory access, remote direct memory access, or shared memory. In some embodiments, input includes a streaming interface. In some embodiments, the interface is a cascading interface.

[0073] The RPU device includes an output port, device, or system 105 that returns processed data from a randomized core, kernel, and randomized distributed elements. In some embodiments, the output includes a memory-mapped interface, such as direct memory access, remote direct memory access, or shared memory. In some embodiments, the output includes a streaming interface. In some embodiments, the interface is a cascading interface.

[0074] In some embodiments, the input 104 and output 105 interfaces are shared. Examples of this include, but are not limited to, direct memory access interfaces or fast peripheral component interconnect (PCIe) interfaces for high-bandwidth memory (HBM) devices or systems.

[0075] RPU devices or systems 100 have a wide range of applications across various industry verticals. Below, we provide a non-limiting list of different applications across different industries.

[0076] In scientific research and development, the device or system 100 is applied to climate modeling and pharmaceutical and genetics. In this context, it assists in supercomputing environments to simulate climate models and changes, drug discovery, and genetic studies involving stochasticity, such as random mutation and protein folding simulations.

[0077] In network security, device 100 finds applications in cryptographic activities, assisting servers in managing SSL / TLS encryption protocols. Furthermore, RPU device 100 is used in workstations for cryptographic research, development, and random-intensive penetration testing.

[0078] In the manufacturing industry, equipment or system 100 is used for quality control processes and supply chain optimization. Here, the server utilizes this equipment for random sampling techniques in quality assurance and random optimization in supply chain logistics.

[0079] In telecommunications, equipment or systems 100 contribute to the network optimization process, particularly the management and optimization of service flows within the network infrastructure.

[0080] In the healthcare industry, devices or systems 100 are used for medical imaging and clinical trials, assisting workstations and servers in applying randomization methods for medical image analysis and for the randomization and analysis of clinical trial participants.

[0081] In the financial industry, the RPU 100 is used in algorithmic trading to assist quantitative analysts in developing and testing trading strategies. It is also used in risk analysis, where servers utilize the device to perform calculations related to the risk of financial portfolios using stochastic methods such as Monte Carlo simulations.

[0082] Within the gaming industry, device or system 100 is used in games and game development workstations to create games with randomized environments and AI behavior. It is also used in servers hosting multiplayer online games with randomized environmental events.

[0083] In the entertainment and media industry, device or system 100 is used in rendering farms for film and animation production, particularly for generating random effects such as simulating weather patterns, crowd behavior, and natural phenomena.

[0084] In the education sector, device or system 100 is used on online learning platforms, where servers use it to randomly generate educational assessments, such as quizzes and test papers.

[0085] In retail, devices or systems 100 assist recommendation systems, helping servers execute stochastic-intensive algorithms for product recommendation generation or data augmentation.

[0086] Devices or systems 100 are also suitable for edge computing, especially in scenarios involving Internet of Things (IoT) devices, to assist devices operating at the network edge (such as business management systems and smart home devices) in making real-time decisions.

[0087] The device or system 100 is used in a hyperscale data center where randomness helps optimize workload distribution and resource allocation.

[0088] To enable these applications, the RPU device or system 100 must be integrated within existing IT infrastructure. In some embodiments, the device or system 100 is used in a variety of infrastructures for stochastic-centric computing. These examples include, but are not limited to, standalone servers, virtual machines, and container-based systems such as Docker and Kubernetes. Other non-limiting examples include: serverless setups that handle stochastic-heavy computing; security tools; IoT edge devices; workstation computers; high-performance computing clusters; and cloud service systems for handling stochastic-centric tasks.

[0089] Figure 2 An embodiment of the RPU concept is illustrated. In this embodiment, a dual-core CPU is configured to follow... Figure 1 The RPU architecture described herein. One core 201 of the cores 201 acts as the randomness core 101, while the other core 202 acts as the kernel core 102. In this case, the randomness distribution element 103 is performed by means of different caches, memories, and storage hierarchies, such as, for example, a shared L3 cache 203 between the two cores.

[0090] In some embodiments, Figure 2The embodiments are directly extended to CPUs with more than two cores, where N cores split the roles of random core 201 and kernel core 202 among them. In some embodiments, this split is equal, with N / 2 random cores 201 and N / 2 kernel cores 202. In some embodiments, there is only one random core 201 and N-1 kernel cores 202.

[0091] Figure 3 Another embodiment of the RPU concept is illustrated. In this embodiment, the RPU 300 is connected to a cache / memory / storage medium 301, which serves as a buffer between the different cores 304 and 305 of the RPU architecture.

[0092] In some embodiments, the RPU device 300 is implemented in a computing device, including but not limited to a CPU, GPU, FPGA, complex programmable logic device (CPLD), or ASIC.

[0093] In some embodiments, cache / memory / storage medium 301 includes, in a non-limiting sense, SRAM cache, RAM memory, or SSD.

[0094] In some embodiments, the RPU device 300 is configured to pass output 302 from randomness core 304 and output 303 from kernel core 305 to or from memory 301.

[0095] Figure 4 Another embodiment of the RPU concept is illustrated. In this embodiment, the GPU 400 is configured such that at least one thread block 401 behaves as a randomness core 101, while other available blocks 402 behave as kernel cores 201. In this case, the role of the randomness distribution element 103 is performed here by different caches, memories, and storage hierarchies, such as, for example, local block memory for intra-block communication and global GPU memory 403.

[0096] In some embodiments, the GPU includes different program counters for kernel and random kernel configuration, thereby enabling these configurations to be independent of the same program counter, thereby improving the overall throughput and / or performance of the configured GPU device.

[0097] Figure 5Another embodiment of the RPU concept is illustrated. In this embodiment, the RPU architecture includes a combination of a CPU 501 and a GPU 502. The CPU 501 is configured to run as a randomness core, generating random batches 503 or tasks in the process, while the GPU 502 is configured to execute a kernel core, generating results 504 in the process. In this embodiment, the randomness distribution element 103 is identified by an internal cache / memory 506.

[0098] In some embodiments, the device or system includes a data connection 505 to a host device. Examples of these data connections include, but are not limited to, PCIe, Ethernet, or Thunderbolt interfaces.

[0099] Figure 6 The illustration shows one of the potential arrangements of different RPU cores within the device. In this embodiment, there are two different types of random cores 101: RNG core 601 and distributed core 602.

[0100] In this embodiment, the RNG core 601 is configured to generate uniform random numbers from a given distribution. In some embodiments, this is a uniform integer distribution of a given size, including but not limited to 16, 32, 64, and 128 bits.

[0101] Random numbers are transmitted via the randomness distribution core to distribution core 602, or directly to kernel core 603 for consumption. In the first case, the results undergo further post-processing before being fed to the kernel. Examples of this include, but are not limited to, generating a given distribution or using it within a Monte Carlo sampler. These post-processed numbers are then transmitted to kernel core 603.

[0102] Figure 7 The diagram illustrates the basis Figure 6 A more complete embodiment of the RPU concept described herein is presented. In this embodiment, the RNG core 701 is isolated from the mesh of the distributed core 702 and the kernel core 703. Random distribution elements 704 connect the mesh entity, the RNG core, and any other auxiliary elements of the device. In some embodiments, this mesh has a checkerboard shape, such that the random core 702 and the kernel core 703 interweave among them, promoting computational locality.

[0103] In some embodiments, these auxiliary components include cache, memory, or storage devices, including but not limited to DDR memory 705. In some embodiments, these auxiliary components include communication interfaces, such as a fast PCI 706, to enable communication between the RPU device 700 and the host CPU 707 and / or memory 708.

[0104] In some embodiments, any combination of these auxiliary components is integrated together on the same integrated circuit board. Examples of these include, but are not limited to, printed circuit board (PCB) boards with PCIe factor.

[0105] In some embodiments, the mesh between distributed core 702 and kernel 703 is configured to enable it to implement pipelined workloads, wherein each of distributed core 702 and / or kernel core 703 performs a portion of the pipelined workload before passing the pipelined workload to the next in the execution pipeline.

[0106] It should be noted that the above examples of this solution are for illustrative purposes. While the solution has been described in conjunction with specific examples, many modifications are possible without substantially departing from the teachings of the subject matter described herein. Other substitutions, modifications, and changes may be made without departing from the spirit of this solution. It should also be noted that, in the context of this disclosure, functions described with reference to a particular device or system refer to devices or systems configured to perform those functions in embodiments.

[0107] All features and applications disclosed in this disclosure (including any appended claims, abstract, and drawings) and / or all parts of any method or process so disclosed may be combined in any combination, except for at least some mutually exclusive combinations of such features and / or parts.

Claims

1. A computing device or system, comprising: a) Random core, b) Kernel core, c) Randomly distributed elements, The randomness core is configured to transmit one or more random numbers to the randomness distribution element. The randomness distribution element is configured to transmit one or more random numbers to the kernel core. The kernel core is configured to include the one or more random numbers into one or more computational workloads.

2. The computing device or system of claim 1, wherein the kernel is configured to be reprogrammed according to the computing workload when executing the one or more computing workloads.

3. The computing device or system according to any one of claims 1 to 2, wherein the randomness distribution element is configured to be reconfigured according to the computing workload when performing the one or more computing workloads.

4. The computing device or system according to any one of claims 1 to 3, wherein the randomness core comprises a physical entropy source.

5. The computing device or system according to any one of claims 1 to 4, wherein the randomness core and the kernel core are arranged in a mesh distribution.

6. The computing device or system of claim 5, wherein the mesh distribution is a checkerboard pattern.

7. The computing device or system according to any one of claims 1 to 6, comprising a plurality of kernel cores and / or random cores, the plurality of kernel cores and / or random cores being pipelined such that the plurality of kernel cores and / or random cores are configured to perform a plurality of transformations in a sequential manner.

8. The computing device or system according to any one of claims 1 to 7, wherein the randomness core and the kernel core are two different logical or physical elements.

9. The computing device or system according to any one of claims 1 to 8, wherein the computing device is a field-programmable gate array (FPGA).

10. An integrated circuit board assembly, comprising: a) A computing device or system according to any one of claims 1 to 9, b) Data communication interface used for communication c) Power connection, configured to receive power for operating the integrated circuit board.

11. The integrated circuit board assembly of claim 10, wherein the data communication interface conforms to the PCIe standard.

12. The integrated circuit board assembly according to any one of claims 10 to 11, further comprising at least one integrated memory and / or storage unit.

13. A method for generating distributions, the method comprising: a. Configure a randomness processing device that includes at least a randomness core associated with a predetermined randomness distribution; b. Request a predetermined amount of randomness from the randomness processing device.

14. The method of claim 13, further comprising: The randomness is consumed at least by the kernel computation core of the randomness processing device.

15. The method according to any one of claims 13 to 14, further comprising: a. One or more random numbers are transmitted from the randomness core to the randomness distribution element of the randomness processing device; b. The randomness distribution element transmits the one or more random numbers to the core computing core of the randomness processing device; c. The kernel computes the one or more random numbers into one or more computational workloads.

16. The method of claim 15, further comprising: The kernel computing core is reprogrammed according to the computing workload when executing the one or more computing workloads.

17. The method according to any one of claims 15 to 16, further comprising: When executing the one or more computing workloads, the randomness distribution element is reconfigured according to the computing workload.

18. The method according to any one of claims 15 to 17, further comprising: The randomness core and the kernel core are arranged using a mesh distribution.

19. The method of claim 18, wherein the mesh distribution is a checkerboard pattern.

20. The method according to any one of claims 15 to 19, further comprising: The randomness processing device is pipelined with multiple core computing cores and / or random cores to perform multiple transformations in a sequential manner.

21. The method according to any one of claims 14 to 20, further comprising: The randomness core and the kernel computing core are arranged as two different logical or physical elements.

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