Display circuit, display panel and preparation method of display panel

Abstract

The application discloses a display circuit (DCX), a display panel (PNL) and a preparation method of the display panel (PNL), and relates to the technical field of display. The display circuit (DCX) comprises a plurality of display units (DU) connected in series, any one display unit (DU) comprises a light emitting element (LD) and a pixel driving circuit (PDC) electrically connected with a first electrode of the light emitting element (LD); in two adjacent display units (DU), a second electrode of the light emitting element (LD) of a former display unit (DU) is electrically connected with a first electrode of the light emitting element (LD) of a latter display unit (DU). The power consumption of the display panel (PNL) can be reduced.

Description

Display circuit, display panel and preparation method of display panel TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a display circuit, a display panel and a preparation method of the display panel. BACKGROUND

[0002] Micro Light Emitting Diode Display (MicroLED) display technology has the advantages of low power consumption, high brightness, super high resolution and color saturation, fast response speed, super power saving, long service life, high efficiency and the like, and is considered to be the most competitive next-generation display technology. Compared with an Organic Light Emitting Display (OLED) device, the driving current of a Light Emitting Display (LED) device can reach microamperes or even milliamperes, which is hundreds to thousands of times the driving current of the OLED device, thereby increasing power consumption.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0004] SUMMARY

[0005] The present disclosure aims to overcome the deficiencies of the prior art, and provides a display circuit, a display panel and a preparation method of the display panel, so as to reduce power consumption.

[0006] According to a first aspect of the present disclosure, a display circuit is provided, which comprises a plurality of display units connected in series, any one of the display units comprising a light emitting element and a pixel driving circuit electrically connected to a first electrode of the light emitting element.

[0007] In adjacent two display units, a second electrode of the light emitting element of the former display unit is electrically connected to a first electrode of the light emitting element of the latter display unit.

[0008] In an embodiment of the present disclosure, the pixel driving circuit of the first display unit comprises one of a first current control unit or a second current control unit.

[0009] The first current control unit is configured to provide a first driving current, the first driving current flowing from the pixel driving circuit to the light emitting element.

[0010] The second current control unit is configured to provide a second driving current flowing from the light emitting element to the pixel driving circuit;

[0011] When the first electrode of the light emitting element is an anode, the pixel driving circuit of the first display unit is capable of loading a driving power voltage VDD(1), and the pixel driving circuit of the first display unit comprises a first current control unit; the second electrode of the light emitting element of the last display unit is capable of loading a reference power voltage VSS(1);

[0012] When the first electrode of the light emitting element is a cathode, the pixel driving circuit of the first display unit is capable of loading a reference power voltage VSS(1), and the pixel driving circuit of the first display unit comprises a second current control unit; the second electrode of the light emitting element of the last display unit is capable of loading a driving power voltage VDD(1).

[0013] In an embodiment of the present disclosure, in the first display unit, the pixel driving circuit comprises a pulse width modulation unit;

[0014] One end of the pulse width modulation unit is electrically connected to an output end of the first current control unit or an output end of the second current control unit, and the other end of the pulse width modulation unit is electrically connected to the first electrode of the light emitting element.

[0015] In an embodiment of the present disclosure, the display circuit comprises y display units connected in series;

[0016] The display unit DU(x) comprises a first current control unit and a second current control unit; the display unit DU(x) is the xth display unit, and x is a positive integer greater than 1 and not greater than y, and y is a positive integer greater than 1;

[0017] The first current control unit is capable of loading a driving power voltage VDD(x), and the second current control unit is capable of loading a reference power voltage VSS(x), the driving power voltage VDD(x) is the xth driving power voltage, and the reference power voltage VSS(x) is the xth reference power voltage;

[0018] The driving power voltage VDD(x1) is greater than the driving power voltage VDD(x2), x1 is less than x2, x1 is a positive integer not greater than y, and x2 is a positive integer not greater than y;

[0019] The reference power voltage VSS(x3) is less than the reference power voltage VSS(x4), x3 is less than x4, x3 is a positive integer greater than 1 and not greater than y, and x4 is a positive integer greater than 1 and not greater than y.

[0020] In an embodiment of the present disclosure, in the display unit DU(x), the pixel driving circuit further comprises a pulse width modulation unit.

[0021] In the display unit DU(x), one end of the pulse width modulation unit is electrically connected to the output end of the first current control unit and the output end of the second current control unit, and the other end of the pulse width modulation unit is electrically connected to the first electrode of the light emitting element.

[0022] In an embodiment of the present disclosure, the number of display units is 3-6.

[0023] In an embodiment of the present disclosure, the light emitting colors of the light emitting elements in each display unit are the same.

[0024] According to a second aspect of the present disclosure, a display panel is also provided, which comprises the above-mentioned display circuit arranged in an array.

[0025] In an embodiment of the present disclosure, the display panel comprises a substrate, a driving layer and a light emitting layer arranged in sequence; the light emitting element is arranged in the light emitting layer, and the pixel driving circuit is arranged in the driving layer.

[0026] The driving layer is provided with a driving power supply voltage trace for loading the required driving power supply voltage to the display circuit and a reference power supply voltage trace for loading the required reference power supply voltage to the display circuit.

[0027] In an embodiment of the present disclosure, the display panel comprises pixels arranged in an array, and the pixels form pixel columns and pixel rows.

[0028] The display panel further comprises a display circuit column.

[0029] The display circuit column comprises one pixel column or a plurality of adjacent pixel columns.

[0030] The display panel further comprises a voltage trace column group corresponding to the display circuit column in one-to-one correspondence, and the voltage trace column group comprises each driving power supply voltage trace and each reference power supply voltage trace required for driving the display circuit.

[0031] In an embodiment of the present disclosure, the display panel further comprises a display circuit row.

[0032] The display circuit row comprises one pixel row or a plurality of adjacent pixel rows.

[0033] In an embodiment of the present disclosure, the display circuit column comprises one pixel column, and the display circuit row comprises a plurality of pixel rows.

[0034] Alternatively, the display circuit column includes two pixel columns, and the display circuit row includes a plurality of pixel rows.

[0035] Alternatively, the display circuit column includes at least three pixel columns, and the display circuit row includes two pixel rows.

[0036] In an embodiment of the present disclosure, the light-emitting layer includes a plurality of light-emitting elements and a plurality of transfer lines.

[0037] In adjacent two display units of the same display circuit, the second electrode of the light-emitting element of the former display unit is electrically connected to the first electrode of the light-emitting element of the latter display unit through the transfer line.

[0038] In an embodiment of the present disclosure, the light-emitting layer includes a pad layer, a light-emitting element layer, and a transfer line which are sequentially stacked.

[0039] The pad layer has a pad corresponding to the second electrode of each light-emitting element; the second electrode of the light-emitting element is electrically connected to the corresponding pad.

[0040] In adjacent two display units of the same display circuit, the pad to which the second electrode of the light-emitting element of the former display unit is electrically connected is connected to the first electrode of the light-emitting element of the latter display unit through the transfer line.

[0041] In an embodiment of the present disclosure, the light-emitting layer further includes a third planarization layer covering each light-emitting element, and the third planarization layer has a first via hole exposing the first electrode of the light-emitting element.

[0042] The transfer line is disposed on the side of the third planarization layer away from the pad layer, and is electrically connected to the first electrode of the light-emitting element through the first via hole.

[0043] In an embodiment of the present disclosure, the light-emitting layer further includes a third planarization layer, a first transfer layer, a fourth passivation layer, and a second transfer layer which are sequentially stacked on the side of the light-emitting element layer away from the pad layer.

[0044] The transfer line includes a first transfer line in the first transfer layer and a second transfer line in the second transfer layer.

[0045] The third planarization layer has a first via hole exposing the first electrode of the light-emitting element; the fourth passivation layer has a second via hole exposing the first electrode of the light-emitting element, and the second transfer line is electrically connected to the first electrode of the light-emitting element through the second via hole; the fourth passivation layer has a third via hole exposing a partial region of the first transfer line, and the second transfer line is electrically connected to the first transfer line through the third via hole.

[0046] The third planarization layer has a fourth via hole exposing a part of the pad area, and the first jumper is electrically connected to the pad through the fourth via hole.

[0047] In an embodiment of the present disclosure, the light emitting elements in the light emitting layer all emit light of the same color.

[0048] The display panel further comprises a color defining layer on a side of the light emitting layer away from the substrate.

[0049] The color defining layer has color defining units corresponding to the light emitting elements one by one, and at least part of the color defining units can convert light emitted by the corresponding light emitting elements into light of a longer wavelength.

[0050] In an embodiment of the present disclosure, the color defining units comprise first color defining units.

[0051] The first color defining units comprise a quantum dot sublayer and a first color film sublayer on a side of the quantum dot sublayer away from the light emitting elements.

[0052] The quantum dot sublayer can convert light provided by the light emitting elements into light of a longer wavelength, and the light emitting color of the quantum dot sublayer is the same as the color of the first color film sublayer.

[0053] In an embodiment of the present disclosure, the color defining units further comprise second color defining units.

[0054] The second color defining units comprise a scattering film sublayer and a second color film sublayer on a side of the scattering film sublayer away from the light emitting elements; the color of the second color film sublayer is the same as the light emitting color of the light emitting elements.

[0055] In an embodiment of the present disclosure, the display panel comprises pixels arranged in an array.

[0056] The pixels comprise a plurality of subpixels and at least one redundant subpixel.

[0057] The subpixels comprise the light emitting elements and the color defining units corresponding to the light emitting elements; the redundant subpixels comprise redundant light emitting elements and the color defining units corresponding to the redundant light emitting elements.

[0058] In at least two pixels, the subpixels emitting light of the same color have different relative positions in the pixels.

[0059] According to a third aspect of the present disclosure, a method for manufacturing a display panel is provided, the display panel comprising a plurality of sub-pixels of different colors; the display panel comprising a light-emitting substrate and a color definition layer stacked together; the color definition layer having color definition units corresponding to the light-emitting elements one by one, at least part of the color definition units being capable of converting light emitted by the corresponding light-emitting elements into light of a longer wavelength;

[0060] The method for manufacturing the display panel comprises:

[0061] forming a light-emitting substrate;

[0062] detecting each of the light-emitting elements to determine the positions of the light-emitting elements of each sub-pixel;

[0063] generating a layout of a plurality of color definition sub-layers corresponding to the sub-pixels of different colors one by one according to the positions of the light-emitting elements of each sub-pixel, the color definition sub-layers comprising color definition units of each sub-pixel of the same color;

[0064] generating each color definition sub-layer according to the layout of each color definition sub-layer using a digital exposure machine.

[0065] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and are not intended to limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0066] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is apparent that the accompanying drawings described below are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0067] FIG. 1 is a schematic diagram of a pixel driving circuit in the related art.

[0068] FIG. 2 is a schematic diagram of a display circuit in an embodiment of the present disclosure.

[0069] FIG. 3 is a schematic diagram of a display circuit in an embodiment of the present disclosure.

[0070] FIG. 4 is a schematic diagram of a display circuit in an embodiment of the present disclosure.

[0071] FIG. 5 is a driving timing diagram of a display circuit in an embodiment of the present disclosure.

[0072] FIG. 6 is a schematic diagram of a display circuit in an embodiment of the present disclosure.

[0073] FIG. 7 is a working mode diagram of a display circuit in one embodiment of the present disclosure.

[0074] FIG. 8 is a diagram of signal duty cycles in various modes in one embodiment of the present disclosure.

[0075] FIG. 9 is a diagram of a display panel in one embodiment of the present disclosure.

[0076] FIG. 10 is a diagram of a display panel in one embodiment of the present disclosure.

[0077] FIG. 11 is a diagram of a display panel in one embodiment of the present disclosure.

[0078] FIG. 12 is a diagram of a display panel in one embodiment of the present disclosure.

[0079] FIG. 13 is a diagram of a second source-drain metal layer in one embodiment of the present disclosure.

[0080] FIG. 14 is a diagram of a second source-drain metal layer in one embodiment of the present disclosure.

[0081] FIG. 15 is a diagram of a third source-drain metal layer in one embodiment of the present disclosure.

[0082] FIG. 16 is a diagram of a display panel in one embodiment of the present disclosure.

[0083] FIG. 17 is a diagram of a combination of a second source-drain metal layer and a third source-drain metal layer in one embodiment of the present disclosure.

[0084] FIG. 18 is a diagram of a second source-drain metal layer in one embodiment of the present disclosure.

[0085] FIG. 19 is a diagram of a third source-drain metal layer in one embodiment of the present disclosure.

[0086] FIG. 20 is a diagram of a fourth source-drain metal layer in one embodiment of the present disclosure.

[0087] FIG. 21 is a diagram of a fourth source-drain metal layer in one embodiment of the present disclosure.

[0088] FIG. 22 is a wiring diagram of a width-modulated data line and an amplitude-modulated data line in one embodiment of the present disclosure.

[0089] FIG. 23 is a wiring diagram of a width-modulated data line and an amplitude-modulated data line in one embodiment of the present disclosure.

[0090] FIG. 24 is a wiring diagram of a width-modulated data line and an amplitude-modulated data line in one embodiment of the present disclosure.

[0091] FIG. 25 is a schematic diagram of the layout of the pulse-width modulation data line and the pulse-amplitude modulation data line in one embodiment of the present disclosure.

[0092] FIG. 26 is a schematic diagram of the layout of the pulse-width modulation data line and the pulse-amplitude modulation data line in one embodiment of the present disclosure.

[0093] FIG. 27 is a schematic diagram of the connection of the light emitting elements in the same display circuit in one embodiment of the present disclosure.

[0094] FIG. 28 is a schematic diagram of the connection of the light emitting elements in the same display circuit in one embodiment of the present disclosure.

[0095] FIG. 29 is a schematic diagram of the connection of the light emitting elements in the same display circuit in one embodiment of the present disclosure.

[0096] FIG. 30 is a schematic diagram of the connection of the light emitting elements in the same display circuit in one embodiment of the present disclosure.

[0097] FIG. 31 is a schematic diagram of the display panel in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0098] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, may, however, be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and thus a detailed description of the same will not be repeated. In addition, the drawings are only schematic and the dimensions are not necessarily to scale.

[0099] Although relative terms such as "upper", "lower", etc. are used herein to describe one component's relationship to another component as illustrated in the figures, these terms are used herein for ease of description only and are not intended to limit the scope of the disclosure. It is to be understood that if a device were turned over so that its upper portion is below its lower portion, as a result, the described "upper" part would then be a "lower" part. When a structure is on another structure, it can mean that the structure is formed integrally with the other structure, or that the structure is "directly" on the other structure, or that the structure is "indirectly" on the other structure via another structure.

[0100] The terms "one", "a", "an", and "the" are used to indicate the existence of one or more elements / components / etc.; the term "includes" and the term "including" are used to indicate an open-ended inclusion of one or more elements / components / etc. and that other elements / components / etc. are possible; the terms "first", "second", and "third" are used to indicate a relative order / position of the elements / components / etc. and are not necessarily used to indicate a number of the elements / components / etc.

[0101] In the embodiments of the present disclosure, a transistor refers to an element including at least three terminals of a gate, a source, and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and a current can flow through the source, the channel region, and the drain. The channel region refers to a region through which the current mainly flows. In the embodiments of the present disclosure, in the case of using a transistor with opposite polarity or in the case of changing the current direction in the operation of a circuit, the functions of the "source" and the "drain" are sometimes exchanged with each other, that is, the "source" and the "drain" can be exchanged with each other. In the embodiments of the present disclosure, for any one transistor, one of the "source" and the "drain" is referred to as a first electrode of the transistor, and the other is referred to as a second electrode of the transistor, and the gate is referred to as a control terminal of the transistor. In the embodiments of the present disclosure, at least part of a signal has a high level and a low level; one of the high level and the low level can be a gate-on level of the signal, which can turn on a controlled transistor; the other of the high level and the low level can be a gate-off level of the signal, which can turn off the controlled transistor. For example, for a signal for controlling a P-type transistor (which can be loaded to the control terminal of the P-type transistor), the gate-on level thereof is the low level, and the gate-off level thereof is the high level. For another example, for a signal for controlling an N-type transistor (which can be loaded to the control terminal of the N-type transistor), the gate-on level thereof is the high level, and the gate-off level thereof is the low level.

[0102] The structure layer A is located on the side of the structure layer B away from the substrate, which can be understood as that the structure layer A is formed on the side of the structure layer B away from the substrate. When the structure layer B is a patterned structure, part of the structure of the structure layer A can also be located at the same physical height as the structure layer B or below the physical height of the structure layer B, wherein the substrate is the height reference.

[0103] With the continuous increase in demand for various display products such as notebook computers, smart phones, televisions, tablet computers, smart watches, and fitness wristbands, more new display products will emerge in the industry in the future. Micro LED display technology has the advantages of low power consumption, high brightness, ultra-high resolution and color saturation, fast response speed, ultra-power saving, long service life, high efficiency, and the like, and is considered to be the most competitive next-generation display technology.

[0104] In the related art, the driving current of the LED device can reach microamperes or even milliamperes, which is 100 to 1000 times of the OLED driving current. The power consumption P=U*I of the light emitting element. In a conventional OLED, one driving transistor drives one light emitting element to emit light. The voltage difference U between the driving power supply voltage and the reference power supply voltage in the pixel driving circuit is the sum of the voltage drop of the driving power supply voltage VDD, the source-drain voltage of the switch transistor, the source-drain voltage of the driving transistor, the voltage of the light emitting element, and the voltage drop of the reference power supply voltage VSS. Referring to FIG. 1, in general, the source-drain voltage of the driving transistor accounts for more than 50% of the voltage difference U between the driving power supply voltage and the reference power supply voltage. For the order of magnitude change of the LED current, the power consumption of the driving transistor is greater than half of the power consumption of the display panel, and the power consumption of the driving transistor is greater when the gray scale is 255, thereby increasing the power consumption of the display panel.

[0105] To solve the above problems, the display circuit DCX is provided. Referring to FIG. 2, the display circuit DCX includes a plurality of display units DU connected in series. Any one of the display units DU includes a light emitting element LD and a pixel driving circuit PDC electrically connected to a first electrode of the light emitting element LD, and the pixel driving circuit PDC is configured to drive the light emitting element LD to emit light. In two adjacent display units DU, a second electrode of the light emitting element LD of the former display unit DU is electrically connected to a first electrode of the light emitting element LD of the latter display unit DU. On the one hand, the plurality of light emitting elements LD are connected in series, and the pixel driving circuit PDC of the first display unit DU generates a driving current flowing through the plurality of light emitting elements LD connected in series, so that one pixel driving circuit PDC drives a plurality of light emitting elements LD to emit light, which is advantageous to reduce the power consumption of the display panel PNL (for example, when the gray scale of each light emitting element LD is 255) compared with the way that one pixel driving circuit PDC drives one light emitting element LD to emit light. On the other hand, the pixel driving circuit PDC of the first display unit DU can provide a driving current for each light emitting element LD, and the pixel driving circuit PDC of the remaining display unit DU can control the current size of the corresponding light emitting element LD, so as to compensate the brightness of the corresponding light emitting element LD. Since most of the driving current of each light emitting element LD is generated by the pixel driving circuit PDC of the first display unit DU, and the pixel driving circuit PDC of the remaining display unit DU only provides a compensation current difference for the corresponding light emitting element LD or stops working, compared with the way that one pixel driving circuit PDC drives one light emitting element LD to emit light, the power consumption of the display panel PNL can be reduced. In an example, when the driving current required by the light emitting element LD of the second display unit DU is greater than the driving current required by the light emitting element LD of the first display unit DU, the pixel driving circuit PDC of the second display unit DU can charge the light emitting element LD of the second display unit DU with a current difference, so that the driving current required by the light emitting element LD of the second display unit DU is greater than the driving current required by the light emitting element LD of the first display unit DU. In another example, when the driving current required by the light emitting element LD of the second display unit DU is less than the driving current required by the light emitting element LD of the first display unit DU, the pixel driving circuit PDC of the second display unit DU can discharge the light emitting element LD of the second display unit DU with a current difference, so that the driving current required by the light emitting element LD of the second display unit DU is less than the driving current required by the light emitting element LD of the first display unit DU. When the driving current required by each light emitting element LD and the light emitting time are the same, only the pixel driving circuit PDC of the first display unit DU generates the driving current, and the pixel driving circuit PDC of the remaining display unit DU does not provide the current difference or stops working.

[0106] It is to be noted that in the embodiments of the present disclosure, when the first electrode of the light emitting element LD is an anode and the second electrode of the light emitting element LD is a cathode, the "preceding display unit DU", the "subsequent display unit DU", the "first display unit DU", and the "second display unit DU" are all ordered in the direction of the flow of the driving current in the display circuit DCX. For example, in the direction of the flow of the driving current, the display units DU can be sequentially the "first display unit DU", the "second display unit DU", the "third display unit DU", and so on. When the first electrode of the light emitting element LD is a cathode and the second electrode of the light emitting element LD is an anode, the "preceding display unit DU", the "subsequent display unit DU", the "first display unit DU", and the "second display unit DU" are all ordered in the direction opposite to the direction of the flow of the driving current in the display circuit DCX. For example, in the direction opposite to the direction of the flow of the driving current, the display units DU can be sequentially the "first display unit DU", the "second display unit DU", the "third display unit DU", and so on.

[0107] It is to be understood that in the embodiments of the present disclosure, the first electrode and the second electrode are two electrodes of the light emitting element LD, either of the first electrode and the second electrode can be a cathode of the light emitting element LD and the other can be an anode of the light emitting element LD. In one example, the first electrode can be a cathode of the light emitting element LD and the second electrode can be an anode of the light emitting element LD. In another example, the first electrode can be an anode of the light emitting element LD and the second electrode can be a cathode of the light emitting element LD.

[0108] In one embodiment of the present disclosure, referring to FIG. 2 and FIG. 3, the pixel driving circuit PDC of the first display unit DU includes one of the first current control unit IU1 or the second current control unit IU2. The first current control unit IU1 is configured to provide a first driving current flowing from the pixel driving circuit PDC to the light emitting element LD. The second current control unit IU2 is configured to provide a second driving current flowing from the light emitting element LD to the pixel driving circuit PDC. In one example, referring to FIG. 2, when the first electrode of the light emitting element LD is an anode and the second electrode of the light emitting element LD is a cathode, the pixel driving circuit PDC of the first display unit DU is capable of loading a driving power supply voltage VDD(1) and includes the first current control unit IU1. The second electrode of the light emitting element LD of the last display unit DU is capable of loading a reference power supply voltage VSS(1). In another example, referring to FIG. 3, when the first electrode of the light emitting element LD is a cathode and the second electrode of the light emitting element LD is an anode, the pixel driving circuit PDC of the first display unit DU is capable of loading a reference power supply voltage VSS(1) and includes the second current control unit IU2. The second electrode of the light emitting element LD of the last display unit DU is capable of loading a driving power supply voltage VDD(1). Wherein the driving power supply voltage VDD(1) is a first driving power supply voltage VDD and the reference power supply voltage VSS(1) is a first reference power supply voltage VSS. In this way, the first current control unit IU1 or the second current control unit IU2 is capable of generating a driving current required by a plurality of series-connected light emitting elements LD so as to drive the plurality of light emitting elements LD to emit light by the pixel driving circuit PDC of the first display unit DU.

[0109] In one embodiment of the present disclosure, referring to FIG. 4, the first current control unit IU1 includes first to fifth transistors T1-T5, a seventh transistor T7, and a second capacitor C1. The first transistor T1 is configured to load a main initialization voltage Vinit to a control electrode of the third transistor T3 and one end of the second capacitor C1 in response to a gating level of a main reset control signal RST, and the other end of the second capacitor C1 is configured to load a driving power voltage VDD. The second transistor T2 is configured to connect the control electrode of the third transistor T3 and a second electrode of the third transistor T3 in response to a gating level of a threshold compensation control signal GB. The third transistor T3 is configured to generate a driving current. The fourth transistor T4 is configured to load an amplitude-modulated data signal Data to a first electrode of the third transistor T3 in response to a gating level of a main data write control signal GA. The fifth transistor T5 is configured to load the driving power voltage VDD to the first electrode of the third transistor T3 in response to a gating level of a first light-emitting control signal EM1. The seventh transistor T7 is configured to load the main initialization voltage Vinit to a first electrode of a light-emitting element LD in response to the gating level of the main reset control signal RST. The first transistor T1, the second transistor T2, and the seventh transistor T7 are N-type transistors to reduce a leakage current. The other transistors are P-type transistors. The first electrode is an anode of the light-emitting element LD.

[0110] In one embodiment of the present disclosure, referring to FIG. 4, the second current control unit IU2 includes first to fifth transistors T1-T5, a seventh transistor T7, and a second capacitor C1. The first transistor T1 is configured to load a main initialization voltage Vinit to a control electrode of the third transistor T3 and one end of the second capacitor C1 in response to a gating level of a main reset control signal RST, and the other end of the second capacitor C1 is configured to load a reference power voltage VSS. The second transistor T2 is configured to connect the control electrode of the third transistor T3 and a second electrode of the third transistor T3 in response to a gating level of a sub data write control signal GC. The third transistor T3 is configured to generate a driving current. The fourth transistor T4 is configured to load an amplitude-modulated data signal Data to a first electrode of the third transistor T3 in response to a gating level of the sub data write control signal GC. The fifth transistor T5 is configured to load the reference power voltage VSS to the first electrode of the third transistor T3 in response to a gating level of a first light-emitting control signal EM1. The seventh transistor T7 is configured to load the main initialization voltage Vinit to a first electrode of a light-emitting element LD in response to the gating level of the main reset control signal RST. The first transistor T1, the second transistor T2, the third transistor T3, and the seventh transistor T7 are N-type transistors to reduce a leakage current. The other transistors are P-type transistors. The first electrode is a cathode of the light-emitting element LD.

[0111] In one embodiment of the present disclosure, in the first display unit DU, the pixel driving circuit PDC includes a pulse width modulation unit PWM. One end of the pulse width modulation unit PWM is electrically connected to the output end of the first current control unit IU1 or the output end of the second current control unit IU2, and the other end of the pulse width modulation unit PWM is electrically connected to the first electrode of the light emitting element LD. In one example, referring to FIG. 2, one end of the pulse width modulation unit PWM is electrically connected to the output end of the first current control unit IU1, and the other end is electrically connected to the first electrode of the light emitting element LD. In another example, referring to FIG. 3, one end of the pulse width modulation unit PWM is electrically connected to the output end of the second current control unit IU2, and the other end is electrically connected to the first electrode of the light emitting element LD. In this way, the light emitting time of the light emitting element LD of the first display unit DU can be controlled by the pulse width modulation unit PWM.

[0112] It should be noted that in the present disclosure, in the first display unit DU, the output end of the first current control unit IU1 refers to the end of the pixel driving circuit PDC from which the driving current flows out of the pixel driving circuit PDC. The output end of the second current control unit IU2 refers to the end of the pixel driving circuit PDC into which the driving current flows into the pixel driving circuit PDC.

[0113] In an embodiment of the present disclosure, referring to FIG. 4, the pulse width modulation unit PWM includes a sixth transistor T6, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a first capacitor C2. The sixth transistor T6 is configured to connect the first electrode of the light emitting element LD to the second electrode of the third transistor T3 in response to the gating level of the first light emitting control signal EM1 or the second light emitting control signal EM2. The eighth transistor T8 is configured to load the first light emitting control signal EM1 to the control electrode of the sixth transistor T6 in response to the voltage of the second electrode of the tenth transistor T10. The ninth transistor T9 is configured to load the second light emitting control signal EM2 to the control electrode of the sixth transistor T6 in response to the voltage of the second electrode of the tenth transistor T10. The tenth transistor T10 is configured to load the width data signal DataT to the control electrode of the eighth transistor T8, the control electrode of the ninth transistor T9, and one end of the first capacitor C2 in response to the gating level of the auxiliary reset control signal RST'. Optionally, the ninth transistor T9 and the tenth transistor T10 are N-type transistors to reduce the leakage current. The rest of the transistors are P-type transistors. In this way, the duty cycles of the first light emitting control signal EM1 and the second light emitting control signal EM2 can be different. The eighth transistor T8 and the ninth transistor T9 are alternatively turned on to alternatively load the first light emitting control signal EM1 and the second light emitting control signal EM2 to the control electrode of the sixth transistor T6, thereby controlling the turn-on time of the sixth transistor T6 to control the light emitting time of the light emitting element LD of the first display unit DU, so that the light emitting elements LD of the first display unit DU have different light emitting time.

[0114] In an embodiment of the present disclosure, the thin film transistor can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor. The material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material.

[0115] In an embodiment of the present disclosure, referring to FIG. 2, the display circuit DCX includes y display units DU connected in series. The display unit DU(x) includes a first current control unit IU1 and a second current control unit IU2. The display unit DU(x) is the xth display unit DU, and x is a positive integer greater than 1 and not greater than y, and y is a positive integer greater than 1. In other words, in an embodiment of the present disclosure, the display unit DU is not the first display unit DU, but the second display unit DU, the third display unit DU, etc. Herein, y can be 2, 3, 4, 5, etc. x can be 2, 3, 4, 5, etc.

[0116] The first current control unit IU1 can load the driving power supply voltage VDD(x), and the second current control unit IU2 can load VSS(x), where VDD(x) is the xth driving power supply voltage VDD, and VSS(x) is the xth reference power supply voltage VSS. In other words, the first current control unit IU1 charges the corresponding light emitting element LD with a difference current, so as to increase the driving current of the corresponding light emitting element LD; and the second current control unit IU2 discharges the corresponding light emitting element LD with a difference current, so as to decrease the driving current of the corresponding light emitting element LD.

[0117] The driving power supply voltage VDD(x1) is greater than the driving power supply voltage VDD(x2), x1 is less than x2, and x1 is a positive integer not greater than y, and x2 is a positive integer not greater than y. For example, the driving power supply voltage VDD(2) is greater than the driving power supply voltage VDD(3), the driving power supply voltage VDD(3) is greater than the driving power supply voltage VDD(4), the driving power supply voltage VDD(4) is greater than VDD(5), and so on.

[0118] The reference power supply voltage VSS(x3) is less than the reference power supply voltage VSS(x4), x3 is less than x4, and x3 is a positive integer greater than 1 and not greater than y, and x4 is a positive integer greater than 1 and not greater than y. For example, the reference power supply voltage VSS(2) is less than the reference power supply voltage VSS(3), the reference power supply voltage VSS(3) is less than the reference power supply voltage VSS(4), the reference power supply voltage VSS(4) is less than VSS(5), and so on.

[0119] It can be understood that, in two adjacent light emitting elements LD in series, the difference current of the latter light emitting element LD refers to the difference between the driving current required by the latter light emitting element LD and the driving current of the former light emitting element LD, and the size of the difference current can be positive or negative. When the size of the difference current is positive, the corresponding light emitting element LD needs to be charged with the difference current by the first current control unit IU1, so as to increase the driving current flowing through the light emitting element LD. When the size of the difference current is negative, the corresponding light emitting element LD needs to be discharged with the difference current by the second current control unit IU2, so as to decrease the driving current flowing through the light emitting element LD, thereby realizing the effect that the driving currents required by the light emitting elements LD in the same display circuit DCX are different, and further realizing the effect that the light emitting elements LD have different brightness.

[0120] In an embodiment of the present disclosure, the driving power supply voltage VDD(1) is greater than the driving power supply voltage VDD(2), and the reference power supply voltage VSS(1) is less than the reference power supply voltage VSS(2).

[0121] In one embodiment of the present disclosure, the circuit structure of the first current control unit IU1 of the first display unit DU is the same as the circuit structure of the first current control unit IU1 of the xth display unit DU. The circuit structure of the second current control unit IU2 of the first display unit DU is the same as the circuit structure of the second current control unit IU2 of the xth display unit DU, where x is a positive integer greater than 1. For example, x is 2, 3, 4, 5, etc. In another embodiment of the present disclosure, referring to FIG. 4, the circuit structure of the first current control unit IU1 of the first display unit DU is different from the circuit structure of the first current control unit IU1 of the xth display unit DU in that the first current control unit IU1 of the first display unit DU has the seventh transistor T7, while the first current control unit IU1 of the xth display unit DU does not include the seventh transistor T7. The circuit structure of the second current control unit IU2 of the first display unit DU is different from the circuit structure of the second current control unit IU2 of the xth display unit DU in that the second current control unit IU2 of the first display unit DU has the seventh transistor T7, while the second current control unit IU2 of the xth display unit DU does not include the seventh transistor T7.

[0122] It should be noted that in the same display circuit DCX, when the first electrode of the light emitting element LD of the first display unit DU is an anode, the pixel driving circuit PDC of the first display unit DU includes the first current control unit IU1 and the pulse width modulation unit PWM. The pixel driving circuits PDC of the remaining display units DU all include the first current control unit IU1, the second current control unit IU2 and the pulse width modulation unit PWM. When the first electrode of the light emitting element LD of the first display unit DU is a cathode, the pixel driving circuit PDC of the first display unit DU includes the second current control unit IU2 and the pulse width modulation unit PWM. The pixel driving circuits PDC of the remaining display units DU all include the first current control unit IU1, the second current control unit IU2 and the pulse width modulation unit PWM. In the xth display unit DU, the first electrode of the fourth transistor T4 in the first current control unit IU1 and the first electrode of the fourth transistor T4 in the second current control unit IU2 are electrically connected, and the first electrode of the fourth transistor T4 in the first current control unit IU1 and the first electrode of the fourth transistor T4 in the second current control unit IU2 are both used to load the amplitude modulation data signal Data. The second electrode of the third transistor T3 in the first current control unit IU1 and the second electrode of the third transistor T3 in the second current control unit IU2 are both electrically connected to the first electrode of the sixth transistor T6, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light emitting element LD of the xth display unit DU. Wherein, x is a positive integer greater than 1, for example, x is 2, 3, 4, 5, etc. Optionally, in the xth display unit DU, the fourth transistor T4 in the second current control unit IU2 can be an N-type transistor, so that the fourth transistor T4 in the first current control unit IU1 and the fourth transistor T4 in the second current control unit IU2 can be controlled by one signal.

[0123] In an embodiment of the present disclosure, referring to FIG. 2, in the display unit DU(x), the pixel driving circuit PDC further includes the pulse width modulation unit PWM. One end of the pulse width modulation unit PWM is electrically connected to the output end of the first current control unit IU1 and the output end of the second current control unit IU2, and the other end of the pulse width modulation unit PWM is electrically connected to the first electrode of the light emitting element LD. In this way, the light emitting time length of the corresponding light emitting element LD can be controlled by the pulse width modulation unit PWM. The circuit structure of the pulse width modulation unit PWM in the xth display unit DU is the same as that of the pulse width modulation unit PWM in the first display unit DU. Wherein, x is a positive integer greater than 1, for example, x is 2, 3, 4, 5, etc.

[0124] It can be understood that the driving power supply voltage VDD(m), the reference power supply voltage VSS(m), the main reset control signal RST(m), the auxiliary reset control signal RST'(m), the main data write control signal GA(m), the threshold compensation control signal GB(m), the auxiliary data write control signal GC(m), the amplitude modulation data signal Data(m), the width modulation data signal DataT(m), and the main initialization voltage Vinit(m) are used in the display unit DU(m). Wherein, the display unit DU(m) is the mth display unit DU; the driving power supply voltage VDD(m) is the mth driving power supply voltage VDD; the reference power supply voltage VSS(m) is the mth reference power supply voltage VSS; the main reset control signal RST(m) is the mth main reset control signal RST; the auxiliary reset control signal RST'(m) is the mth auxiliary reset control signal RST'; the main data write control signal GA(m) is the mth main data write control signal GA; the threshold compensation control signal GB(m) is the mth threshold compensation control signal GB; the amplitude modulation data signal Data(m) is the mth amplitude modulation data signal Data; the width modulation data signal DataT(m) is the mth width modulation data signal DataT; and the main initialization voltage Vinit(m) is the mth main initialization voltage Vinit. m is a positive integer. For example, the driving power supply voltage VDD(1), the reference power supply voltage VSS(1), the main reset control signal RST(1), the auxiliary reset control signal RST'(1), the main data write control signal GA(1), the threshold compensation control signal GB(1), the auxiliary data write control signal GC(1), the amplitude modulation data signal Data(1), the width modulation data signal DataT(1), and the main initialization voltage Vinit(1) are used in the display unit DU(1). However, the reference power supply voltage VSS(1) is used to load the second electrode of the light emitting element LD in the last display unit DU. For another example, the driving power supply voltage VDD(4), the reference power supply voltage VSS(4), the main reset control signal RST(4), the auxiliary reset control signal RST'(4), the main data write control signal GA(4), the threshold compensation control signal GB(4), the auxiliary data write control signal GC(4), the amplitude modulation data signal Data(4), the width modulation data signal DataT(4), and the main initialization voltage Vinit(4) are used in the display unit DU(4).

[0125] In an embodiment of the present disclosure, the number of display units DU is 3-6. For example, the number of display units DU can be 3, 4, 5, or 6. In this way, a plurality of light emitting elements LD can be driven by one pixel driving circuit PDC, so as to reduce the power consumption of the display panel PNL.

[0126] In one embodiment of the present disclosure, the light emitting colors of the light emitting elements LD in each display unit DU are the same. In this way, it is convenient to control the light emitting elements LD to emit light. In other embodiments of the present disclosure, the light emitting colors of the light emitting elements LD in the same display circuit DCX can be different.

[0127] In one embodiment of the present disclosure, the light emitting elements LD are LEDs, which can be normal chips or flip chips, to adapt to a high gray scale (e.g., a gray scale of 255) display scenario. In other embodiments of the present disclosure, the light emitting elements LD can be Micro LEDs, MiNi LEDs, or other light emitting elements.

[0128] In one embodiment of the present disclosure, referring to FIG. 4, the display circuit DCX includes four display units DU connected in series. Any one of the display units DU includes a light emitting element LD and a pixel drive circuit PDC electrically connected to a first electrode of the light emitting element LD, the pixel drive circuit PDC being configured to drive the light emitting element LD to emit light, the first electrode of the light emitting element LD being an anode and the second electrode being a cathode. In two adjacent display units DU, the second electrode of the light emitting element LD of the former display unit DU is electrically connected to the first electrode of the light emitting element LD of the latter display unit DU. In other words, the second electrode of the first light emitting element LD1 is electrically connected to the first electrode of the second light emitting element LD2, the second electrode of the second light emitting element LD2 is electrically connected to the first electrode of the third light emitting element LD3, and the second electrode of the third light emitting element LD3 is electrically connected to the first electrode of the fourth light emitting element LD4. In the first display unit DU, the pixel drive circuit PDC includes a first current control unit IU1 and a pulse width modulation unit PWM. In the second display unit DU to the fourth display unit DU, the pixel drive circuit PDC includes the first current control unit IU1, a second current control unit IU2, and the pulse width modulation unit PWM. The pixel drive circuit PDC in the display unit DU(1) uses a driving power supply voltage VDD(1), a reference power supply voltage VSS(1), a main reset control signal RST(1), a sub-reset control signal RST'(1), a main data write control signal GA(1), a threshold compensation control signal GB(1), an amplitude modulation data signal Data(1), a pulse width modulation data signal DataT(1), and a main initialization voltage Vinit(1). However, the reference power supply voltage VSS(1) is used to be loaded to the second electrode of the fourth light emitting element LD4 in the fourth display unit DU. The pixel drive circuit PDC in the display unit DU(2) uses a driving power supply voltage VDD(2), a reference power supply voltage VSS(2), a main reset control signal RST(2), a sub-reset control signal RST'(2), a main data write control signal GA(2), a threshold compensation control signal GB(2), a sub-data write control signal GC(2), an amplitude modulation data signal Data(2), a pulse width modulation data signal DataT(2), a main initialization voltage Vinit(2), and a sub-initialization voltage Vinit'(2). The pixel drive circuit PDC in the display unit DU(3) uses a driving power supply voltage VDD(3), a reference power supply voltage VSS(3), a main reset control signal RST(3), a sub-reset control signal RST'(3), a main data write control signal GA(3), a threshold compensation control signal GB(3), a sub-data write control signal GC(3), an amplitude modulation data signal Data(3), a pulse width modulation data signal DataT(3), a main initialization voltage Vinit(3), and a sub-initialization voltage Vinit'(3).The pixel driving circuit PDC in the display unit DU (4) uses a driving power voltage VDD (4), a reference power voltage VSS (4), a main reset control signal RST (4), a sub-reset control signal RST' (4), a main data write control signal GA (4), a threshold compensation control signal GB (4), a sub-data write control signal GC (4), an amplitude modulation data signal Data (4), a width modulation data signal DataT (4), a main initialization voltage Vinit (4), and a sub initialization voltage Vinit' (4). Wherein, the driving power voltage VDD (1) = the reference power voltage VSS (1) + Vds + Vds1 + 3*Vf; the driving power voltage VDD (2) = the driving power voltage VDD (1) - Vf; the driving power voltage VDD (3) = the driving power voltage VDD (2) - Vf; the driving power voltage VDD (4) = the driving power voltage VDD (3) - Vf; the reference power voltage VSS (2) = the reference power voltage VSS (1) + 3*Vf - Vds - Vds1; the reference power voltage VSS (3) = the reference power voltage VSS (2) + 2*Vf - Vds - Vds1; the reference power voltage VSS (4) = the reference power voltage VSS (1) + Vf - Vds - Vds1. Wherein, Vds is the source-drain voltage of the driving transistor, Vds1 is the source-drain voltage of the switch transistor, and Vf is the voltage of the light emitting element LD.

[0129] It should be noted that the third transistor T3 in the first current control unit IU1 is a P-type transistor, and therefore the main initialization voltage Vinit (m) is needed to reset the control electrode of the third transistor T3. The third transistor T3 in the second current control unit IU2 is an N-type transistor, and therefore the sub initialization voltage Vinit' (m) is needed to reset the control electrode of the third transistor T3. Wherein, the main initialization voltage Vinit (m) is the mth main initialization voltage Vinit, the sub initialization voltage Vinit' (m) is the mth sub initialization voltage Vinit', and m is a positive integer.

[0130] When the driving currents required by the first light emitting element LD1 to the fourth light emitting element LD4 are the same, the pixel driving circuits PDC of the second display unit DU to the fourth display unit DU do not work, and only the pixel driving circuit PDC of the first display unit DU generates the driving current to drive the first light emitting element LD1 to the fourth light emitting element LD4 to emit light. Since one pixel driving circuit PDC drives four light emitting elements LD to emit light, compared with the driving mode in the related art, the power consumption of the display panel PNL is reduced.

[0131] When the driving current required by the second light emitting element LD2 is greater than the driving current of the first light emitting element LDl, the first current control unit IUl and the pulse width modulation unit PWM of the second display unit DU work, the third transistor T3 of the first current control unit IUl of the second display unit DU generates a difference current and compensates to the first electrode of the second light emitting element LD2, so as to increase the driving current of the second light emitting element LD2, and realize that the brightness of the second light emitting element LD2 is greater than the brightness of the first light emitting element LDl.

[0132] When the driving current required by the third light emitting element LD3 is less than the driving current of the second light emitting element LD2, the second current control unit IU2 and the pulse width modulation unit PWM of the third display unit DU work, the third transistor T3 of the second current control unit IU2 of the third display unit DU generates a difference current and compensates to the first electrode of the third light emitting element LD3, so as to decrease the driving current of the third light emitting element LD3, and realize that the brightness of the second light emitting element LD2 is greater than the brightness of the third light emitting element LD3.

[0133] The working principle of the display circuit DCX of the example of Fig. 4 is exemplarily described below in combination with Fig. 5. The duty cycle of the first light emitting control signal EMl is twice the duty cycle of the second light emitting control signal EM2 in Fig. 5. The working period of the pixel driving circuit PDC of the first display unit DU is the Hl period and the H2 period; the working period of the pixel driving circuit PDC of the second display unit DU is the H3 period to the H5 period; the working period of the pixel driving circuit PDC of the third display unit DU is the H5 period to the H7 period; the working period of the pixel driving circuit PDC of the fourth display unit DU is the H7 period to the H9 period. The H10 period and the Hl 1 period are the periods in which the light emitting elements LD of the four display units DU emit light.

[0134] Firstly, the working principle of the pixel driving circuit PDC of the display unit DU(1) is described.

[0135] Referring to FIG. 4 and FIG. 5, in the H1 period, the first light emitting control signal EM1, the second light emitting control signal EM2, the main reset control signal RST(1), the auxiliary reset control signal RST'(1), and the main data write control signal GA(1) are high, and the threshold compensation control signal GB(1) is low. In the display unit DU(1), the first transistor T1, the third transistor T3, the seventh transistor T7, and the tenth transistor T10 are turned on, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off, so as to realize the reset of the control electrode of the third transistor T3 and the first electrode of the first light emitting element LD1. Since the width-modulated data signal DataT(1) is loaded to the control electrodes of the eighth transistor T8 and the ninth transistor T9, the eighth transistor T8 and the ninth transistor T9 are selectively turned on, so as to load the first light emitting control signal EM1 or the second light emitting control signal EM2 to the control electrode of the sixth transistor T6, and the sixth transistor T6 is turned off.

[0136] Referring to FIG. 4 and FIG. 5, in the H2 period, the first light emitting control signal EM1, the second light emitting control signal EM2, and the threshold compensation control signal GB(1) are high, and the main reset control signal RST(1), the auxiliary reset control signal RST'(1), and the main data write control signal GA(1) are low. In the display unit DU(1), the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on, and the first transistor T1, the fifth transistor T5, the seventh transistor T7, and the tenth transistor T10 are turned off, so as to write the amplitude-modulated data signal Data(1) to the second capacitor C1 and the control electrode of the third transistor T3. The sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 remain in the state in the H1 period.

[0137] In the H1 period and the H2 period, since the duty cycles of the first light emitting control signal EM1 and the second light emitting control signal EM2 are different, in the subsequent light emitting phase of the first light emitting element LD1, either one of the first light emitting control signal EM1 and the second light emitting control signal EM2 can be loaded to the control electrode of the sixth transistor T6, so as to control the light emitting duration of the first light emitting element LD1.

[0138] Secondly, the working principle of the pixel driving circuit PDC of the display unit DU(2) is described.

[0139] Referring to FIG. 4 and FIG. 5, in the H3 period, the first light emitting control signal EM1, the second light emitting control signal EM2, the main reset control signal RST(2), the auxiliary reset control signal RST'(2), and the main data write control signal GA(2) are high, and the threshold compensation control signal GB(2) is low. In the first current control unit IU1 and the pulse width modulation unit PWM of the display unit DU(2), the first transistor T1, the third transistor T3, and the tenth transistor T10 are turned on, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off, so as to realize the reset of the control electrode of the third transistor T3. Since the width-modulated data signal DataT(2) is loaded to the control electrodes of the eighth transistor T8 and the ninth transistor T9, the eighth transistor T8 and the ninth transistor T9 are selectively turned on, so as to load the first light emitting control signal EM1 or the second light emitting control signal EM2 to the control electrode of the sixth transistor T6, and the sixth transistor T6 is turned off. In the second current control unit IU2 of the display unit DU(2), the first transistor T1 and the third transistor T3 are turned on, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off, so as to realize the reset of the control electrode of the third transistor T3.

[0140] Referring to FIG. 4 and FIG. 5, in the H4 period, the first light emitting control signal EM1, the second light emitting control signal EM2, and the threshold compensation control signal GB(2) are high, and the main reset control signal RST(2), the auxiliary reset control signal RST'(2), the main data write control signal GA(2), and the auxiliary data write control signal GC(2) are low. In the first current control unit IU1 and the pulse width modulation unit PWM of the display unit DU(2), the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on, and the first transistor T1, the fifth transistor T5, and the tenth transistor T10 are turned off, so as to realize the writing of the amplitude-modulated data signal Data(2) to the second capacitor C1 and the control electrode of the third transistor T3. The sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 remain in the state of the H4 period.

[0141] Referring to FIG. 4 and FIG. 5, during the H5 period, the first light emitting control signal EM1, the second light emitting control signal EM2, the main data write control signal GA(2), and the auxiliary data write control signal GC(2) are high, and the main reset control signal RST(2), the auxiliary reset control signal RST'(2), and the threshold compensation control signal GB(2) are low. In the second current control unit IU2 of the display unit DU(2), the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on, and the first transistor T1 and the fifth transistor T5 are turned off, so as to write the amplitude modulation data signal Data(2) into the control electrode of the third transistor T3 and the second capacitor C1. It should be noted that, during the H4 period and the H5 period, the amplitude modulation data signal Data(2) can turn on one of the third transistor T3 of the first current control unit IU1 and the third transistor T3 of the second current control unit IU2 in the subsequent light emitting stage, so as to charge or discharge the difference current to the second light emitting element LD2.

[0142] During the H3 period to the H5 period, due to the different duty cycles of the first light emitting control signal EM1 and the second light emitting control signal EM2, in the subsequent light emitting stage of the second light emitting element LD2, any one of the first light emitting control signal EM1 and the second light emitting control signal EM2 can be loaded to the control electrode of the sixth transistor T6, so as to control the light emitting duration of the second light emitting element LD2.

[0143] Next, the working principle of the pixel driving circuit PDC of the display unit DU(3) is described.

[0144] Referring to FIG. 4 and FIG. 5, during the H5 period, the first light emitting control signal EM1, the second light emitting control signal EM2, the main reset control signal RST(3), the auxiliary reset control signal RST'(3), and the main data write control signal GA(3) are high, and the threshold compensation control signal GB(3) is low. In the first current control unit IU1 and the pulse width modulation unit PWM of the display unit DU(3), the first transistor T1, the third transistor T3, and the tenth transistor T10 are turned on, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off, so as to reset the control electrode of the third transistor T3. Due to the fact that the width modulation data signal DataT(3) is loaded to the control electrodes of the eighth transistor T8 and the ninth transistor T9, the eighth transistor T8 and the ninth transistor T9 are alternatively turned on, so as to load the first light emitting control signal EM1 or the second light emitting control signal EM2 to the control electrode of the sixth transistor T6, and the sixth transistor T6 is turned off. In the second current control unit IU2 of the display unit DU(3), the first transistor T1 and the third transistor T3 are turned on, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off, so as to reset the control electrode of the third transistor T3.

[0145] Referring to FIG. 4 and FIG. 5, in the H6 period, the first light emitting control signal EM1, the second light emitting control signal EM2, and the threshold compensation control signal GB(3) are high, and the main reset control signal RST(3), the auxiliary reset control signal RST'(3), the main data write control signal GA(3), and the auxiliary data write control signal GC(3) are low. In the first current control unit IU1 and the pulse width modulation unit PWM of the display unit DU(3), the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on, and the first transistor T1, the fifth transistor T5, and the tenth transistor T10 are turned off, so as to write the amplitude modulation data signal Data(3) to the control electrode of the second capacitor C1 and the third transistor T3. The sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 remain in the state in the H5 period.

[0146] Referring to FIG. 4 and FIG. 5, in the H7 period, the first light emitting control signal EM1, the second light emitting control signal EM2, the main data write control signal GA(3), and the auxiliary data write control signal GC(3) are high, and the main reset control signal RST(3), the auxiliary reset control signal RST'(3), and the threshold compensation control signal GB(3) are low. In the second current control unit IU2 of the display unit DU(3), the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on, and the first transistor T1 and the fifth transistor T5 are turned off, so as to write the amplitude modulation data signal Data(3) to the control electrode of the second capacitor C1 and the third transistor T3. It should be noted that, in the H6 period and the H7 period, the amplitude modulation data signal Data(3) can turn on one of the third transistor T3 of the first current control unit IU1 and the third transistor T3 of the second current control unit IU2 in the subsequent light emitting stage, so as to charge or discharge the difference current to or from the third light emitting element LD3.

[0147] In the H5 period to the H7 period, due to the different duty cycles of the first light emitting control signal EM1 and the second light emitting control signal EM2, in the subsequent light emitting stage of the third light emitting element LD3, either of the first light emitting control signal EM1 and the second light emitting control signal EM2 can be loaded to the control electrode of the sixth transistor T6, so as to control the light emitting duration of the third light emitting element LD3.

[0148] Subsequently, the working principle of the pixel driving circuit PDC of the display unit DU(4) is described.

[0149] Referring to FIG. 4 and FIG. 5, in the H7 period, the first light emitting control signal EM1, the second light emitting control signal EM2, the main reset control signal RST(4), the auxiliary reset control signal RST'(4), the main data write control signal GA(4) are high, and the threshold compensation control signal GB(4) is low. In the first current control unit IU1 and the pulse width modulation unit PWM of the display unit DU(4), the first transistor T1, the third transistor T3, the tenth transistor T10 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5 are turned off, so as to realize the reset of the control electrode of the third transistor T3. Since the width-modulated data signal DataT(4) is loaded to the control electrodes of the eighth transistor T8 and the ninth transistor T9, the eighth transistor T8 and the ninth transistor T9 are selectively turned on, so as to load the first light emitting control signal EM1 or the second light emitting control signal EM2 to the control electrode of the sixth transistor T6, and the sixth transistor T6 is turned off. In the second current control unit IU2 of the display unit DU(4), the first transistor T1, the third transistor T3 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5 are turned off, so as to realize the reset of the control electrode of the third transistor T3.

[0150] Referring to FIG. 4 and FIG. 5, in the H8 period, the first light emitting control signal EM1, the second light emitting control signal EM2, the threshold compensation control signal GB(4) are high, and the main reset control signal RST(4), the auxiliary reset control signal RST'(4), the main data write control signal GA(4), the auxiliary data write control signal GC(4) are low. In the first current control unit IU1 and the pulse width modulation unit PWM of the display unit DU(4), the second transistor T2, the third transistor T3, the fourth transistor T4 are turned on, and the first transistor T1, the fifth transistor T5, the tenth transistor T10 are turned off, so as to realize the writing of the amplitude-modulated data signal Data(4) to the second capacitor C1 and the control electrode of the third transistor T3. The sixth transistor T6, the eighth transistor T8, the ninth transistor T9 are still in the state of the H7 period.

[0151] Referring to FIG. 4 and FIG. 5, in the H9 period, the first light emitting control signal EM1, the second light emitting control signal EM2, the main data write control signal GA(4), the auxiliary data write control signal GC(4) are high, the main reset control signal RST(4), the auxiliary reset control signal RST'(4), the threshold compensation control signal GB(4) are low, in the second current control unit IU2 of the display unit DU(4), the second transistor T2, the third transistor T3, the fourth transistor T4 are turned on, the first transistor T1, the fifth transistor T5 are turned off, so as to write the amplitude modulation data signal Data(4) into the control electrode of the third transistor T3 and the second capacitor C1. It should be noted that in the H8 period and the H9 period, the amplitude modulation data signal Data(4) can turn on one of the third transistor T3 of the first current control unit IU1 and the third transistor T3 of the second current control unit IU2 in the subsequent light emitting stage, so as to charge or discharge the difference current to the fourth light emitting element LD4.

[0152] In the H7 period to the H9 period, due to the different duty cycles of the first light emitting control signal EM1 and the second light emitting control signal EM2, in the subsequent light emitting stage of the fourth light emitting element LD4, any one of the first light emitting control signal EM1 and the second light emitting control signal EM2 can be loaded to the control electrode of the sixth transistor T6, so as to control the light emitting duration of the fourth light emitting element LD4.

[0153] Finally, the light emitting principle of the light emitting elements LD of the four display units DU is described.

[0154] Referring to FIG. 4 and FIG. 5, in the H10 period, the first light emitting control signal EM1 and the second light emitting control signal EM2 are low, so that each fifth transistor T5 and each sixth transistor T6 in the four display units DU are turned on, so that the third transistor T3 of the display unit DU(1) generates a driving current to drive each light emitting element LD to emit light. Whether the pixel driving circuit PDC of the remaining display units DU works needs to be determined according to specific needs.

[0155] Referring to FIG. 4 and FIG. 5, in the H11 period, the first light emitting control signal EM1 is low and the second light emitting control signal EM2 is high. At this time, if the control electrode of the sixth transistor T6 of the display unit DU(1) loads the first light emitting control signal EM1, the four light emitting elements LD still emit light. If the control electrode of the sixth transistor T6 of the display unit DU(1) loads the second light emitting control signal EM2, the four light emitting elements LD do not emit light. So as to control the light emitting duration of each light emitting element LD.

[0156] In the related art, when the four light emitting elements LD reach the same gray scale (e.g., gray scale 255), the generated power consumption P1 = U * I = (Vds + Vf) * Id * 4 = Vds * Id * 4 + Vf * Id * 4. When the four light emitting elements LD reach the same gray scale (e.g., gray scale 255) driven by the embodiment of the present disclosure, referring to FIG. 6, the power consumption P2 = U * I = (Vds + Vf * 4) * Id = Vds * Id + Vf * Id * 4 generated by one display circuit. Compared with the power consumption P1 in the related art, the reduced power consumption ΔP = P2 - P1 = Vds * Id * 3, ΔP is 25% to 50% of P1, which can effectively reduce the power consumption of the display panel PNL. Wherein, Vds is the source-drain voltage of the driving transistor, Id is the driving current, and Vf is the voltage of the light emitting element LD.

[0157] In an embodiment of the present disclosure, in order to further reduce the power consumption of the light emitting element LD at 255 gray scale, referring to FIG. 7, the display circuit has three working modes in the interval of 1 gray scale to 255 gray scale, namely mode one, mode two and mode three. Wherein, in mode three, the gray scale of the light emitting element LD is 1 to Lm. In mode two, the gray scale of the light emitting element LD is Lm to Ln. In mode one, the gray scale of the light emitting element LD is Ln to 255. Wherein, 1 < Lm < Ln < 255.

[0158] In mode one, referring to FIG. 7 and FIG. 8, the duty cycle duty1 of the first light emitting control signal EM1 and the second light emitting control signal EM2 in the pulse width modulation unit PWM is equal to the required brightness of the gray scale / the brightness corresponding to the peak EQE of the chip. Wherein, the peak EQE is the highest light emitting frequency of the chip. For example, the peak EQE is 3000 Hz.

[0159] In mode two, referring to FIG. 7 and FIG. 8, the duty cycle duty2 of the first light emitting control signal EM1 and the second light emitting control signal EM2 in the pulse width modulation unit PWM is equal to the duty cycle corresponding to 3000 * the minimum pulse width. Wherein, the light emitting frequency of the pulse width modulation unit PWM is 3000 Hz. For example, the minimum pulse width is 2.4 μs, and duty2 = 3000 * 2.4 / 1000000 = 0.72%.

[0160] In mode three, referring to FIG. 7 and FIG. 8, the duty cycle duty3 of the first light emitting control signal EM1 and the second light emitting control signal EM2 in the pulse width modulation unit PWM is equal to the required brightness of the gray scale / the lowest uniform brightness. Wherein, the light emitting frequency of the pulse width modulation unit PWM is less than 3000 Hz. The lowest uniform brightness is the lowest brightness corresponding to the brightness uniformity that the chip can maintain, and at this time there is also a corresponding lowest current density, and the gray scale 1 to Lm are all working under the lowest current density. The gray scale of mode three is distinguished by adjusting the width or the number of pulses in each pulse of a frame.

[0161] The number N of the light emitting pulses of the first light emitting control signal EM1 and the second light emitting control signal EM2 in a frame time is f1 / f2. Wherein, f1 refers to the display frame refresh frequency, f2 refers to the light emitting frequency of the pulse width modulation unit PWM, and f2 is determined according to the eye protection frequency. For example, f1=90Hz, f2=3000Hz, and the number N of the light emitting pulses of the first light emitting control signal EM1 and the second light emitting control signal EM2 in a frame time is 3000 / 90≈33, that is, the first light emitting control signal EM1 and the second light emitting control signal EM2 are divided into 33 light emitting pulses in a display frame.

[0162] The display panel PNL further includes a display area AA and a peripheral area BB located at least one side of the display area AA. In the display area AA, the display panel PNL is provided with display circuits DCX arranged in an array. The display circuit DCX includes a plurality of display units DU connected in series. Any one display unit DU includes a light emitting element LD and a pixel driving circuit PDC electrically connected to a first electrode of the light emitting element LD, and the pixel driving circuit PDC is configured to drive the light emitting element LD to emit light. In adjacent two display units DU, a second electrode of the light emitting element LD of the former display unit DU is electrically connected to a first electrode of the light emitting element LD of the latter display unit DU. The display panel PNL is not provided with display circuits DCX in the peripheral area BB, or the display circuits DCX provided are not used for displaying pictures. Referring to FIG. 9, the display panel PNL is provided with a plurality of scan lines GL extending along a row direction DH in the display area AA, and each scan line GL is arranged in one-to-one correspondence with each display circuit row. The pixel driving circuit PDC of each display unit DU in the display circuit row is electrically connected to the corresponding scan line GL. The display panel PNL is further provided with a plurality of amplitude modulation data lines DL extending along a column direction DV in the display area AA, and each amplitude modulation data line DL is arranged in one-to-one correspondence with each display circuit column. The pixel driving circuit PDC of each display unit DU in the display circuit column is electrically connected to the corresponding amplitude modulation data line DL. The display panel PNL is further provided with a plurality of width modulation data lines DTL extending along the column direction DV in the display area AA, and each width modulation data line DTL is arranged in one-to-one correspondence with each display circuit column. The pixel driving circuit PDC of each display unit DU in the display circuit column is electrically connected to the corresponding width modulation data line DTL. In this way, the pixel driving circuit PDC of each display unit DU is connected to the scan line GL, the amplitude modulation data line DL, and the width modulation data line DTL. A scan signal is loaded on the scan line GL to control the state of the pixel driving circuit PDC. It can be understood that in the example of FIG. 9, only one kind of scan line GL corresponding to the display circuit row is illustrated; according to needs, the display panel PNL can be provided with a plurality of different scan lines GL corresponding to the display circuit row. An amplitude modulation data signal Data for driving the pixel driving circuit PDC can be loaded on the amplitude modulation data line DL, and the pixel driving circuit PDC can drive the light emitting element LD according to the written amplitude modulation data signal Data, thereby controlling the brightness of the light emitting element LD. A width modulation data signal DataT for driving the pixel driving circuit PDC can be loaded on the width modulation data line DTL, and the pixel driving circuit PDC can drive the light emitting element LD according to the written width modulation data signal DataT, thereby controlling the brightness of the light emitting element LD. It can be understood that the pixel driving circuit PDC can also control the brightness of the light emitting element LD according to other signals.

[0163] In one embodiment of the present disclosure, a gate driving circuit is provided in the peripheral region BB to provide a scanning signal to the pixel driving circuit PDC. According to the requirement of the pixel driving circuit PDC, a plurality of gate driving circuits can be provided in the peripheral region BB to provide different scanning signals respectively. Of course, some scanning signals can also share one gate driving circuit.

[0164] Optionally, according to the requirement of the pixel driving circuit PDC, the scanning signal can include, but is not limited to, one or more of the following signals: a write control signal for controlling the writing of a data voltage to the pixel driving circuit PDC, a light emitting control signal for the pixel driving circuit PDC to output a driving current, a reset control signal for controlling the reset of the pixel driving circuit PDC, and the like.

[0165] In one embodiment of the present disclosure, referring to FIG. 10, the display panel PNL includes a substrate SBT, a driving layer DRL, and a light-emitting layer LEL, which are sequentially stacked. The light-emitting element LD is disposed on the light-emitting layer LEL, and the pixel driving circuit PDC is disposed on the driving layer DRL. The driving layer DRL is provided with a driving power voltage wire VDDL for loading a required driving power voltage VDD to the display circuit DCX and a reference power voltage wire VSSL for loading a required reference power voltage VSS to the display circuit DCX. For example, the display circuit DCX includes three display units DU which are sequentially connected in series. Any one of the display units DU includes the light-emitting element LD and the pixel driving circuit PDC electrically connected to the first electrode of the light-emitting element LD, and the pixel driving circuit PDC is used to drive the light-emitting element LD to emit light. The first electrode of the light-emitting element LD is an anode. The driving layer DRL is provided with a driving power voltage wire VDDL(1) for loading a required driving power voltage VDD(1) to the pixel driving circuit PDC of the first display unit DU, a driving power voltage wire VDDL(2) for loading a required driving power voltage VDD(2) to the pixel driving circuit PDC of the second display unit DU, and a driving power voltage wire VDDL(3) for loading a required driving power voltage VDD(3) to the pixel driving circuit PDC of the third display unit DU. The driving layer DRL is also provided with a reference power voltage wire VSSL(2) for loading a required reference power voltage VSS(2) to the pixel driving circuit PDC of the second display unit DU, a reference power voltage wire VSSL(3) for loading a required reference power voltage VSS(3) to the pixel driving circuit PDC of the third display unit DU, and a reference power voltage wire VSSL(1) for loading a required reference power voltage VSS(1) to the second electrode of the third display unit DU. Among them, the driving power voltage wire VDDL(1) is the first driving power voltage wire VDDL; the driving power voltage wire VDDL(2) is the second driving power voltage wire VDDL; the driving power voltage wire VDDL(3) is the third driving power voltage wire VDDL; the reference power voltage wire VSSL(1) is the first reference power voltage wire VSSL; the reference power voltage wire VSSL(2) is the second reference power voltage wire VSSL; and the reference power voltage wire VSSL(3) is the third reference power voltage wire VSSL.

[0166] Optionally, the substrate SBT can be a substrate of inorganic material, or a substrate of organic material, or a composite substrate of inorganic material and organic material. For example, in some embodiments of the present disclosure, the substrate SBT can be made of glass material such as soda lime glass, quartz glass, sapphire glass, etc. In some other embodiments of the present disclosure, the substrate SBT can be made of poly(methyl methacrylate), polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT can be a flexible substrate, for example, the substrate SBT can include polyimide.

[0167] In one embodiment of the present disclosure, referring to FIG. 11, the display panel PNL includes pixels PX arranged in an array. The pixels PX form pixel columns VPX and pixel rows HPX. The display panel PNL further includes display circuit columns VDCX. Each display circuit column VDCX includes one pixel column VPX or a plurality of adjacent pixel columns VPX. For example, each display circuit column VDCX includes one pixel column VPX. For another example, each display circuit column VDCX includes two pixel columns VPX. For yet another example, each display circuit column VDCX includes three or four pixel columns VPX. The display panel PNL further includes a voltage trace column group corresponding to each display circuit column VDCX. The voltage trace column group includes each driving power voltage trace VDDL and each reference power voltage trace VSSL required for driving the display circuit DCX. In this way, each driving power voltage VDD and each reference power voltage VSS required for the display circuit column VDCX can be loaded by the voltage trace column group.

[0168] In one embodiment of the present disclosure, referring to FIG. 11, the display panel PNL further includes display circuit rows HDCX. Each display circuit row HDCX includes one pixel row HPX or a plurality of adjacent pixel rows HPX. In one example, each display circuit row HDCX includes one pixel row HPX. In another example, each display circuit row HDCX includes two pixel rows HPX. In other examples, each display circuit row HDCX can include three, four, or more pixel rows HPX.

[0169] In one embodiment of the present disclosure, referring to FIG. 11, each display circuit column VDCX includes one pixel column VPX, and each display circuit row HDCX includes a plurality of pixel rows HPX. In one example, each display circuit column VDCX includes one pixel column VPX, and each display circuit row HDCX includes three pixel rows HPX. In another example, each display circuit column VDCX includes one pixel column VPX, and each display circuit row HDCX includes four pixel rows HPX.

[0170] In an embodiment of the present disclosure, the display circuit column VDCX includes two pixel columns VPX, and the display circuit row HDCX includes a plurality of pixel rows HPX. In an example, the display circuit column VDCX includes two pixel columns VPX, and the display circuit row HDCX includes two pixel rows HPX. In another example, the display circuit column VDCX includes one pixel column VPX, and the display circuit row HDCX includes three pixel rows HPX.

[0171] In an embodiment of the present disclosure, the display circuit column VDCX includes at least three pixel columns VPX, and the display circuit row HDCX includes two pixel rows HPX. In an example, the display circuit column VDCX includes three pixel columns VPX, and the display circuit row HDCX includes two pixel rows HPX. In another example, the display circuit column VDCX includes four pixel columns VPX, and the display circuit row HDCX includes two pixel rows HPX.

[0172] In an embodiment of the present disclosure, referring to FIG. 10, the light-emitting layer LEL includes a plurality of light-emitting elements LD and a plurality of transfer lines TRL. In two adjacent display units DU, the second electrode of the light-emitting element LD of the former display unit DU is electrically connected to the first electrode of the light-emitting element LD of the latter display unit DU through the transfer line TRL. In this way, the light-emitting elements LD of the two adjacent display units DU can be electrically connected through the TEL to realize the series connection of the two adjacent light-emitting elements LD. The material of the transfer line TRL can be indium tin oxide (ITO) to facilitate the improvement of the light transmittance.

[0173] In an embodiment of the present disclosure, referring to FIG. 11, the light-emitting layer LEL includes a pad layer PADL, a light-emitting element layer LDL and a transfer line TRL which are sequentially stacked. The pad layer PADL has a pad PAD corresponding to each second electrode of the light-emitting element LD. The second electrode of the light-emitting element LD is electrically connected to the corresponding pad PAD. In two adjacent display units DU, the pad PAD to which the second electrode of the light-emitting element LD of the former display unit DU is electrically connected is connected to the first electrode of the light-emitting element LD of the latter display unit DU through the transfer line TRL. In this way, the series connection of the two adjacent light-emitting elements LD can be realized.

[0174] In an embodiment of the present disclosure, referring to FIG. 11, the light-emitting layer LEL further comprises a third planarization layer PLN3 covering each light-emitting element LD. The third planarization layer PLN3 has a first via hole exposing the first electrode of the light-emitting element LD. The jumper wire TRL is disposed on the side of the third planarization layer PLN3 away from the pad layer PADL and is electrically connected to the first electrode of the light-emitting element LD through the first via hole. In this way, in two adjacent light-emitting elements LD, the second electrode of one light-emitting element LD can be electrically connected to the first electrode of the other light-emitting element LD through the jumper wire TRL and the first via hole.

[0175] In an embodiment of the present disclosure, referring to FIG. 11, the light-emitting layer LEL further comprises a third planarization layer PLN3, a first jumper layer TR1, a fourth passivation layer PVX4, and a second jumper layer TR2, which are disposed in sequence on the side of the light-emitting element layer LDL away from the pad layer PADL. The jumper wire TRL comprises a first jumper wire TRL1 on the first jumper layer TR1 and a second jumper wire TRL2 on the second jumper layer TR2. The third planarization layer PLN3 has a first via hole exposing the first electrode of the light-emitting element LD, and the fourth passivation layer PVX4 has a second via hole exposing the first electrode of the light-emitting element LD. The second jumper wire TRL2 is electrically connected to the first electrode of the light-emitting element LD through the second via hole. The fourth passivation layer PVX4 has a third via hole exposing a partial region of the first jumper wire TRL1, and the second jumper wire TRL2 is electrically connected to the first jumper wire TRL1 through the third via hole. The third planarization layer PLN3 has a fourth via hole exposing a partial region of the pad PAD, and the first jumper wire TRL1 is electrically connected to the pad PAD through the fourth via hole. The material of the first jumper wire TRL1 can be a metal material (e.g., copper, silver, or other metal materials) to reduce the resistance. The material of the second jumper wire TRL2 can be indium tin oxide (ITO) to improve the light transmittance.

[0176] In an embodiment of the present disclosure, the light-emitting color of each light-emitting element LD in the light-emitting layer LEL is the same. For example, the light-emitting color of each light-emitting element LD in the light-emitting layer LEL can be blue, purple, red, or the like. The display panel PNL further comprises a color definition layer CDL on the side of the light-emitting layer LEL away from the substrate SBT. The color definition layer CDL has color definition units CU corresponding to each light-emitting element LD. At least part of the color definition units CU can convert the light emitted by the corresponding light-emitting element LD into light with a longer wavelength. For example, the color definition unit CU converts the blue light emitted by the blue light-emitting element LD into red light or green light. When blue light is needed to be output, the color definition unit CU only scatters the blue light emitted by the blue light-emitting element LD without converting the light. In this way, the display of red, green, and blue can be realized through the color definition unit CU.

[0177] In an embodiment of the present disclosure, referring to FIG. 11, the color defining unit CU comprises a first color defining unit CU1. The first color defining unit CU1 comprises a quantum dot sub-layer QD and a first color filter sub-layer CF1 located on a side of the quantum dot sub-layer QD away from the light emitting element LD. The quantum dot sub-layer QD is capable of converting light provided by the light emitting element LD into light with a longer wavelength, and the light emitting color of the quantum dot sub-layer QD is the same as the color of the first color filter sub-layer CF1. In this way, the same color of light emitted by the light emitting element LD can be converted into light of different colors by the quantum dot sub-layer QD and the first color filter sub-layer CF1 to improve the display effect. For example, blue light emitted by a blue light emitting element LD can be converted into red light or green light by the quantum dot sub-layer QD and the first color filter sub-layer CF1. Further, the orthogonal projection of the quantum dot sub-layer QD and the first color filter sub-layer CF1 on the substrate SBT covers the orthogonal projection of the light emitting element LD on the substrate SBT to improve the light transmittance.

[0178] In an embodiment of the present disclosure, referring to FIG. 11, the color defining unit CU further comprises a second color defining unit CU2. The second color defining unit CU2 comprises a scattering film sub-layer SC and a second color filter sub-layer CF2 located on a side of the scattering film sub-layer SC away from the light emitting element LD. The scattering film sub-layer SC is used to scatter light emitted by the light emitting element LD, and the color of the second color filter sub-layer CF2 is the same as the light emitting color of the light emitting element LD. For example, when the light emitting element LD emits blue light, the scattering film sub-layer SC scatters the blue light to improve the light emission uniformity, and the color of the second color filter sub-layer CF2 is blue to improve the purity of the blue light. In this way, the purity of light emitted by the light emitting element LD can be improved by the second color defining unit CU2 without converting the light emitted by the light emitting element LD.

[0179] In an embodiment of the present disclosure, referring to FIG. 11 and FIG. 12, the display panel PNL includes pixels PX arranged in an array. The pixel PX includes a plurality of sub-pixels and at least one redundant sub-pixel. The sub-pixel includes a light emitting element LD and a color defining unit CU corresponding to the light emitting element LD. The redundant sub-pixel includes a redundant light emitting element SLD and a color defining unit CU corresponding to the redundant light emitting element SLD, and is used to emit light of a corresponding color in place of a failed sub-pixel when the sub-pixel fails. For example, when a green sub-pixel in the pixel PX fails, the redundant sub-pixel is used to emit green light in place of the green sub-pixel. For another example, when a blue sub-pixel in the pixel PX fails, the redundant sub-pixel is used to emit blue light in place of the blue sub-pixel, so as to improve the yield of the display panel PNL. In at least two pixels PX, the relative positions of the sub-pixels emitting light of the same color in the pixel PX are different. For example, in any two display circuits DCX, the sub-pixel emitting red light in one of the display circuits DCX can be a red sub-pixel, and the sub-pixel emitting red light in the other of the display circuits DCX can be a redundant sub-pixel. Since the redundant sub-pixel and the original red sub-pixel are arranged at different positions in the pixel PX, the relative positions of the sub-pixels emitting red light in the pixel PX are different. When the redundant sub-pixel is used to emit red light, the redundant sub-pixel can be regarded as a new red sub-pixel, and the original red sub-pixel fails and cannot be used to emit red light.

[0180] In an embodiment of the present disclosure, referring to FIG. 10, from the perspective of the film layer structure, the display panel PNL includes a substrate substrate SBT, a driving layer DRL, a light emitting layer LEL, and a color defining layer CDL which are sequentially stacked. The driving layer DRL includes a first buffer layer BUF1, a first semiconductor layer SCL1, a first gate insulating layer GI1, a first gate layer GT1, a second gate insulating layer GI2, a second gate layer GT2, a first interlayer dielectric layer ILD1, a second buffer layer BUF2, a second semiconductor layer SCL2, a third gate insulating layer GI3, a third gate layer GT3, a second interlayer dielectric layer ILD2, a first source-drain metal layer SD1, a first planarization layer PLN1, a first passivation layer PVX1, a second source-drain metal layer SD2, a second planarization layer PLN2, and a second passivation layer PVX2 which are sequentially stacked in the direction away from the substrate substrate SBT. The light emitting layer LEL includes a third source-drain metal layer SD3, a second electrode layer EL2, a third passivation layer PVX3, a light emitting element layer LDL, a first electrode layer EL1, a third planarization layer PLN3, a first transfer layer TR1, a fourth passivation layer PVX4, a second transfer layer TR2, and a fourth planarization layer PLN4 which are sequentially stacked on the second passivation layer PVX2 away from the substrate substrate SBT. The color defining layer CDL includes a color defining sub-layer CUL and a blocking layer BML which are sequentially stacked away from the substrate substrate SBT on the fourth planarization layer PLN4.

[0181] The material of the first semiconductor layer SCL1 is low temperature polysilicon, and the material of the second semiconductor layer SCL2 is metal oxide (for example, indium gallium zinc oxide, IGZO). The P-type thin film transistor and the capacitor can be composed of the first semiconductor layer SCL1, the first gate insulating layer GI1, the first gate layer GT1, the second gate insulating layer GI2, the second gate layer GT2, the first interlayer dielectric layer ILD1, the first source-drain metal layer SD1, and the like. The N-type transistor can be composed of the second gate layer GT2, the first interlayer dielectric layer ILD1, the second buffer layer BUF2, the second semiconductor layer SCL2, the third gate insulating layer GI3, the third gate layer GT3, the second interlayer dielectric layer ILD2, the first source-drain metal layer SD1, and the like. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. Further, the first semiconductor layer SCL1 and the second semiconductor layer SCL2 can be used to form the channel region of the transistor, and can also be partially routed or conductive structure by conductorization when necessary. The gate layer can be used to form one or more scan lines, such as one or more of the write control line, the reset control line, the light-emitting control line, and the like. The gate layer can also be used to form the gate of the transistor, and can also be used to form part or all of the electrode plate of the capacitor. The source-drain metal layer can be used to form the data line, the driving power voltage line, and the like, and can also be used to form part of the electrode plate of the capacitor.

[0182] The first source-drain metal layer SD1 is electrically connected with the first semiconductor layer SCL1, the second gate layer GT2, the IGZO and the third gate layer GT3 through the via holes respectively. Each driving power supply voltage trace VDDL is arranged on the second source-drain metal layer SD2, and each reference power supply voltage trace VSSL and the pad layer PADL are arranged on the third source-drain metal layer SD3. The pad layer PADL includes a pad PAD corresponding to each light emitting element LD, and one reference power supply voltage trace VSSL is arranged between two adjacent pads PAD. The orthographic projection of the light emitting element LD on the substrate substrate SBT is located within the orthographic projection of the corresponding pad PAD on the substrate substrate SBT. The pad PAD is electrically connected with the first source-drain metal layer SD1 through the via hole, and each driving power supply voltage trace VDDL has a via hole for electrically connecting with the pad PAD and the first source-drain metal layer SD1. The second electrode layer EL2 includes each second electrode, the light emitting element layer LDL includes each light emitting element LD, and the first electrode layer EL1 includes each first electrode. The light emitting element LD corresponds to the second electrode one by one, and the light emitting element LD corresponds to the first electrode one by one. The orthographic projection of the light emitting element LD on the substrate substrate SBT covers the orthographic projection of the corresponding second electrode on the substrate substrate SBT, and the orthographic projection of the first electrode on the substrate substrate SBT covers the orthographic projection of the corresponding light emitting element LD on the substrate substrate SBT. The second electrode of the light emitting element LD is electrically connected with the corresponding pad PAD through the via hole. The first transfer layer TR1 includes each first transfer line TRL1, and the second transfer line TRL2 includes each second transfer line TRL2. The third planarization layer PLN3 has a first via hole exposing the first electrode of the light emitting element LD, and the fourth passivation layer PVX4 has a second via hole exposing the first electrode of the light emitting element LD. The second transfer line TRL2 is electrically connected with the first electrode of the light emitting element LD through the second via hole. The fourth passivation layer PVX4 has a third via hole exposing a partial region of the first transfer line TRL1, and the second transfer line TRL2 is electrically connected with the first transfer line TRL1 through the third via hole. The third planarization layer PLN3 has a fourth via hole exposing a partial region of the pad PAD, and the first transfer line TRL1 is electrically connected with the pad PAD through the fourth via hole. The material of the first transfer line TRL1 can be a metal material (for example, copper, silver or other metal materials), so as to reduce the resistance. The material of the second transfer line TRL2 can be indium tin oxide (ITO), so as to improve the light transmittance and have good conductivity. The orthographic projection of the first transfer line TRL1 on the substrate substrate SBT covers the orthographic projection of the corresponding light emitting element LD on the substrate substrate SBT, so as to improve the transmittance of the light emitted by the light emitting element LD. It can be understood that the first electrode is an anode, and the second electrode is a cathode.

[0183] The color definition sub-layer CUL includes color definition units CU corresponding to the light emitting elements LD one by one. The color definition unit CU includes a first color definition unit CU1 and a second color definition unit CU2; the first color definition unit CU1 includes a quantum dot sub-layer QD and a first color film sub-layer CF1 located on the side of the quantum dot sub-layer QD away from the light emitting element LD; the quantum dot sub-layer QD can convert the light provided by the light emitting element LD into light with a longer wavelength, and the light emitting color of the quantum dot sub-layer QD is the same as the color of the first color film sub-layer CF1. The second color definition unit CU2 includes a scattering film sub-layer SC and a second color film sub-layer CF2 located on the side of the scattering film sub-layer SC away from the light emitting element LD; the color of the second color film sub-layer CF2 is the same as the light emitting color of the light emitting element LD. Two adjacent color definition units CU are separated by a blocking layer BML for blocking the light emitted by the light emitting element LD. The orthographic projection of the color definition unit CU on the substrate SBT covers the orthographic projection of the corresponding light emitting element LD on the substrate SBT.

[0184] From the perspective of a plan view, in an example, referring to FIG. 11 and FIG. 13, the arrangement of the display circuit column VDCX including two pixel columns VPX and the display circuit row HDCX including two pixel rows HPX is taken as an example. The second source-drain metal layer SD2 includes four driving power voltage wires VDDL extending along the column direction DV and a lapping pad LJ electrically connected to the pad PAD corresponding to each light emitting element LD in each pixel PX, the four driving power voltage wires VDDL are distributed along the row direction DH, the lapping pad LJ is used to electrically connect the pad PAD and the corresponding pixel driving circuit PDC, and a gap for accommodating the lapping pad LJ can be provided between two adjacent driving power voltage wires VDDL. In the same pixel PX, the number of lapping pads LJ on the second source-drain metal layer SD2 is three, and the three lapping pads LJ can be a lapping pad LJ of a red sub-pixel, a lapping pad LJ of a green sub-pixel and a lapping pad LJ of a blue sub-pixel, respectively, and the three lapping pads LJ are arranged in a delta arrangement.

[0185] In another example, referring to FIG. 11 and FIG. 14, the arrangement of the display circuit column VDCX including two pixel columns VPX and the display circuit row HDCX including three pixel rows HPX is taken as an example. The second source-drain metal layer SD2 includes six driving power voltage wires VDDL extending along the column direction DV and a plurality of landing pads LJ corresponding to each light emitting element LD in each pixel PX and electrically connected to each landing pad PAD. The six driving power voltage wires VDDL are distributed along the row direction DH. The landing pads LJ are used to electrically connect the landing pads PAD and the corresponding pixel driving circuit PDC. A gap for accommodating the landing pads LJ can be provided between two adjacent driving power voltage wires VDDL. In the same pixel PX, the number of landing pads LJ on the second source-drain metal layer SD2 is three. The three landing pads LJ can be a landing pad LJ of a red sub-pixel, a landing pad LJ of a green sub-pixel and a landing pad LJ of a blue sub-pixel respectively. The three landing pads LJ are distributed along the row direction DH.

[0186] Referring to FIG. 11 and FIG. 15, the arrangement mode of the display circuit column VDCX including two pixel columns VPX and the display circuit row HDCX including two pixel rows HPX is taken as an example. The third source-drain metal layer SD3 includes four reference source voltage wires VSSL extending along the column direction DV, and a pad PAD corresponding to each sub-pixel and a connection pad PDD corresponding to the output terminal of the pixel driving circuit PDC. The four reference source voltage wires VSSL are distributed along the row direction DH. In the same pixel PX, the number of pads PAD in the third source-drain metal layer SD3 is three, which can be the pad PAD of the red sub-pixel, the pad PAD of the green sub-pixel and the pad PAD of the blue sub-pixel, and the three pads PAD are distributed in a right-angled triangle shape, two pads PAD are located on one side of the reference source voltage wire VSSL, and one pad PAD is located on the other side of the reference source voltage wire VSSL. The connection pad PDD corresponds to the pad PAD, and the pad PAD is electrically connected to the corresponding connection pad PDD. In the same display circuit DCX, the pad PAD corresponding to the light emitting element LD of the first display unit DU is electrically connected to the connection pad PDD corresponding to the pixel driving circuit PDC of the second display unit DU, the pad PAD corresponding to the light emitting element LD of the second display unit DU is electrically connected to the connection pad PDD corresponding to the pixel driving circuit PDC of the third display unit DU, the pad PAD corresponding to the light emitting element LD of the third display unit DU is electrically connected to the connection pad PDD corresponding to the pixel driving circuit PDC of the fourth display unit DU, the pad PAD corresponding to the light emitting element LD of the fourth display unit DU is not connected to the connection pad PDD of the pixel driving circuit PDC of the first display unit DU, and the pad PAD corresponding to the light emitting element LD of the fourth display unit DU is electrically connected to the first reference source voltage wire VSSL. In some other embodiments of the present disclosure, the pad PAD corresponding to the light emitting element LD of the fourth display unit DU can be reused as the first reference source voltage wire VSSL.

[0187] In this way, by arranging each driving source voltage wire VDDL in the second source-drain metal layer SD2 and each reference source voltage wire VSSL in the third source-drain metal layer SD3, the resistance of the driving source voltage wire VDDL and the reference source voltage wire VSSL is reduced, and the wiring space of the driving source voltage wire VDDL and the reference source voltage wire VSSL is improved.

[0188] In some other embodiments of the present disclosure, each driving source voltage wire VDDL and each reference source voltage wire VSSL can be arranged in the same film layer, so as to reduce the thickness of the display panel PNL and reduce the production cost.

[0189] In an embodiment of the present disclosure, referring to FIG. 16, from the perspective of the film layer structure, the display panel PNL includes a substrate substrate SBT, a driving layer DRL, a light-emitting layer LEL, and a color definition layer CDL which are sequentially stacked. The driving layer DRL includes a first buffer layer BUF1, a first semiconductor layer SCL1, a first gate insulating layer GI1, a first gate layer GT1, a second gate insulating layer GI2, a second gate layer GT2, a first interlayer dielectric layer ILD1, a second buffer layer BUF2, a second semiconductor layer SCL2, a third gate insulating layer GI3, a third gate layer GT3, a second interlayer dielectric layer ILD2, a first source-drain metal layer SD1, a first planarization layer PLN1, a first passivation layer PVX1, a second source-drain metal layer SD2, a second planarization main layer PLN2A, a third source-drain metal layer SD3, a second planarization sub-layer PLN2B, and a second passivation layer PVX2, which are sequentially stacked in the direction away from the substrate substrate SBT. The light-emitting layer LEL includes a fourth source-drain metal layer SD4, a second electrode layer EL2, a third passivation layer PVX3, a light-emitting element layer LDL, a first electrode layer EL1, a third planarization layer PLN3, a first transfer layer TR1, a fourth passivation layer PVX4, a second transfer layer TR2, and a fourth planarization layer PLN4, which are sequentially stacked on the second passivation layer PVX2 away from the substrate substrate SBT. The color definition layer CDL includes a color definition sub-layer CUL and a shielding layer BML, which are sequentially stacked away from the substrate substrate SBT on the fourth planarization layer PLN4.

[0190] The material of the first semiconductor layer SCL1 is low-temperature polysilicon, and the material of the second semiconductor layer SCL2 is metal oxide (for example, indium gallium zinc oxide, IGZO). The P-type thin-film transistor and the capacitor can be composed of the first semiconductor layer SCL1, the first gate insulating layer GI1, the first gate layer GT1, the second gate insulating layer GI2, the second gate layer GT2, the first interlayer dielectric layer ILD1, the first source-drain metal layer SD1, and the like. The N-type transistor can be composed of the second gate layer GT2, the first interlayer dielectric layer ILD1, the second buffer layer BUF2, the second semiconductor layer SCL2, the third gate insulating layer GI3, the third gate layer GT3, the second interlayer dielectric layer ILD2, the first source-drain metal layer SD1, and the like. The positional relationship of each film layer can be determined according to the film layer structure of the thin-film transistor. Further, the first semiconductor layer SCL1 and the second semiconductor layer SCL2 can be used to form the channel region of the transistor, and can also be partially routed or conductive structures by conductive if necessary. The gate layer can be used to form one or more scan lines, such as one or more of the write control line, the reset control line, the light-emitting control line, and the like. It can also be used to form the gate of the transistor, and can also be used to form part or all of the electrode plate of the capacitor. The source-drain metal layer can be used to form the data line, the driving power voltage line, and the like, and can also be used to form part of the electrode plate of the capacitor.

[0191] The first source-drain metal layer SD1 is electrically connected with the first semiconductor layer SCL1, the second gate layer GT2, the IGZO and the third gate layer GT3 through the via holes respectively. Each driving power supply voltage trace VDDL is arranged on the second source-drain metal layer SD2, each reference power supply voltage trace VSSL is arranged on the third source-drain metal layer SD3, and the pad layer PADL is arranged on the fourth source-drain metal layer SD4. The pad layer PADL includes a pad PAD corresponding to the second electrode of each light emitting element LD. The orthographic projection of the light emitting element LD on the substrate substrate SBT is located within the orthographic projection of the corresponding pad PAD on the substrate substrate SBT. The pad PAD is electrically connected with the first source-drain metal layer SD1 through the via hole, and there is a via hole between the two adjacent driving power supply voltage traces VDDL for electrically connecting the pad PAD and the first source-drain metal layer SD1. The second electrode layer EL2 includes each second electrode, the light emitting element layer LDL includes each light emitting element LD, the first electrode layer EL1 includes each first electrode, the light emitting element LD corresponds to the second electrode one by one, and the light emitting element LD corresponds to the first electrode one by one. The orthographic projection of the light emitting element LD on the substrate substrate SBT covers the orthographic projection of the corresponding second electrode on the substrate substrate SBT, and the orthographic projection of the first electrode on the substrate substrate SBT covers the orthographic projection of the corresponding light emitting element LD on the substrate substrate SBT. The second electrode of the light emitting element LD is electrically connected with the corresponding pad PAD through the via hole. The first transfer layer TR1 includes each first transfer line TRL1, and the second transfer line TRL2 includes each second transfer line TRL2. The third planarization layer PLN3 has a first via hole exposing the first electrode of the light emitting element LD, and the fourth passivation layer PVX4 has a second via hole exposing the first electrode of the light emitting element LD. The second transfer line TRL2 is electrically connected with the first electrode of the light emitting element LD through the second via hole. The fourth passivation layer PVX4 has a third via hole exposing a partial region of the first transfer line TRL1, and the second transfer line TRL2 is electrically connected with the first transfer line TRL1 through the third via hole. The third planarization layer PLN3 has a fourth via hole exposing a partial region of the pad PAD, and the first transfer line TRL1 is electrically connected with the pad PAD through the fourth via hole. The material of the first transfer line TRL1 can be a metal material (for example, can be a metal material such as copper, silver, etc.), so as to reduce the resistance. The material of the second transfer line TRL2 can be indium tin oxide (ITO), so as to improve the light transmittance and have good conductivity. The orthographic projection of the first transfer line TRL1 on the substrate substrate SBT covers the orthographic projection of the corresponding light emitting element LD on the substrate substrate SBT, so as to improve the transmittance of the light emitted by the light emitting element LD. It can be understood that the first electrode is an anode, and the second electrode is a cathode.

[0192] The color definition sub-layer CUL includes color definition units CU corresponding to the light emitting elements LD one by one. The color definition unit CU includes a first color definition unit CU1 and a second color definition unit CU2; the first color definition unit CU1 includes a quantum dot sub-layer QD and a first color film sub-layer CF1 located on the side of the quantum dot sub-layer QD away from the light emitting element LD; the quantum dot sub-layer QD can convert the light provided by the light emitting element LD into light with a longer wavelength, and the light emitting color of the quantum dot sub-layer QD is the same as the color of the first color film sub-layer CF1. The second color definition unit CU2 includes a scattering film sub-layer SC and a second color film sub-layer CF2 located on the side of the scattering film sub-layer SC away from the light emitting element LD; the color of the second color film sub-layer CF2 is the same as the light emitting color of the light emitting element LD. Two adjacent color definition units CU are separated by a blocking layer BML for blocking the light emitted by the light emitting element LD. The orthographic projection of the color definition unit CU on the substrate SBT covers the orthographic projection of the corresponding light emitting element LD on the substrate SBT.

[0193] From the perspective of a plan view, in one example, referring to FIGS. 11, 17 and 18, the arrangement of the display circuit column VDCX including two pixel columns VPX and the display circuit row HDCX including two pixel rows HPX is taken as an example. The second source-drain metal layer SD2 includes four driving power supply voltage traces VDDL extending along the column direction DV, and the four driving power supply voltage traces VDDL are distributed along the row direction DH.

[0194] Referring to FIGS. 11 and 19, the arrangement of the display circuit column VDCX including two pixel columns VPX and the display circuit row HDCX including two pixel rows HPX is taken as an example. The layout in which the reference power supply voltage trace VSSL is located includes four reference power supply voltage traces VSSL located on the third source-drain metal layer SD3, the four reference power supply voltage traces VSSL extend along the column direction DV, and the four reference power supply voltage traces VSSL are distributed along the row direction DH, and the side of the adjacent two reference power supply voltage traces VSSL close to each other is provided with a notch for a transfer pad PAD.

[0195] Referring to FIG. 11, FIG. 16, FIG. 20 and FIG. 21, for example, the arrangement of the display circuit column VDCX including two pixel columns VPX and the display circuit row HDCX including two pixel rows HPX. In an example, referring to FIG. 20, the fourth source-drain metal layer SD4 includes a pad PAD corresponding to each sub-pixel and a connecting pad PDD corresponding to the output of the pixel driving circuit PDC. In the same pixel PX, the number of the pads PAD in the fourth source-drain metal layer SD4 is three, which can be the pad PAD of the red sub-pixel, the pad PAD of the green sub-pixel and the pad PAD of the blue sub-pixel, respectively, and the three pads PAD are distributed in a right triangle shape. The connecting pad PDD corresponds to the pad PAD one by one, and the pad PAD is electrically connected to the corresponding connecting pad PDD. In the same pixel PX, the three connecting pads PDD are distributed in a right triangle shape. In the same display circuit DCX, the pad PAD corresponding to the light emitting element LD of the first display unit DU is electrically connected to the connecting pad PDD corresponding to the pixel driving circuit PDC of the second display unit DU, the pad PAD corresponding to the light emitting element LD of the second display unit DU is electrically connected to the connecting pad PDD corresponding to the pixel driving circuit PDC of the third display unit DU, the pad PAD corresponding to the light emitting element LD of the third display unit DU is electrically connected to the connecting pad PDD corresponding to the pixel driving circuit PDC of the fourth display unit DU, the pad PAD corresponding to the light emitting element LD of the fourth display unit DU is not connected to the connecting pad PDD of the pixel driving circuit PDC of the first display unit DU, and the pad PAD corresponding to the light emitting element LD of the fourth display unit DU is electrically connected to the first reference power supply voltage trace VSSL through a via (not shown in FIG. 16).

[0196] In another example, referring to FIG. 16 and FIG. 21, the fourth source-drain metal layer SD4 includes a pad PAD corresponding to each sub-pixel and a connection pad PDD corresponding to the output of the pixel driving circuit PDC. In the same pixel PX, the number of pads PAD in the fourth source-drain metal layer SD4 is three, which can be the pad PAD of the red sub-pixel, the pad PAD of the green sub-pixel, and the pad PAD of the blue sub-pixel, respectively, and the three pads PAD are arranged in a right-angled triangle shape. The connection pad PDD corresponds to the pad PAD one-to-one, and the pad PAD is electrically connected to the corresponding connection pad PDD. In the same pixel PX, the three connection pads PDD are arranged in a delta arrangement. In the same display circuit DCX, the pad PAD corresponding to the light emitting element LD of the first display unit DU is electrically connected to the connection pad PDD corresponding to the pixel driving circuit PDC of the second display unit DU, the pad PAD corresponding to the light emitting element LD of the second display unit DU is electrically connected to the connection pad PDD corresponding to the pixel driving circuit PDC of the third display unit DU, the pad PAD corresponding to the light emitting element LD of the third display unit DU is electrically connected to the connection pad PDD corresponding to the pixel driving circuit PDC of the fourth display unit DU, the pad PAD corresponding to the light emitting element LD of the fourth display unit DU is not connected to the connection pad PDD of the pixel driving circuit PDC of the first display unit DU, and the pad PAD corresponding to the light emitting element LD of the fourth display unit DU is electrically connected to the first VSSL (not shown in FIG. 16).

[0197] In other examples, the three connection pads PDD of the same pixel PX can be arranged in a straight line shape.

[0198] In this way, by arranging each driving power supply voltage wire VDDL in the second source-drain metal layer SD2, arranging the reference power supply voltage wire VSSL in the third source-drain metal layer SD3, and arranging each pad PAD in the fourth source-drain metal layer SD4, the resistance of the driving power supply voltage wire VDDL and the reference power supply voltage wire VSSL is reduced, and the wiring space of the driving power supply voltage wire VDDL and the reference power supply voltage wire VSSL is further improved.

[0199] In an embodiment of the present disclosure, the first reference power supply voltage wire VSSL can be arranged in the fourth source-drain metal layer SD4, and the pad PAD corresponding to the last light emitting element LD can be reused as the first reference power supply voltage wire VSSL.

[0200] In one embodiment of the present disclosure, referring to FIG. 11 and FIG. 22, the arrangement of the display circuit column VDCX including two pixel columns VPX and the display circuit row HDCX including two pixel rows HPX is taken as an example. If each pixel PX has three sub-pixels of red, green and blue, three corresponding display circuits DCX are needed, each of which has four display units DU in series, and the light-emitting elements LD in the same display circuit DCX have the same light-emitting color. In one pixel column VPX, three amplitude data lines DL extending along the column direction DV are needed to provide the pixel driving circuit PDC of each display unit DU with an amplitude data signal Data, and correspondingly, three width data lines DTL extending along the column direction DV are needed to provide the pixel driving circuit PDC of each display unit DU with a width data signal DataT, and the three amplitude data lines DL and the three width data lines DTL are arranged along the row direction DH. For example, the amplitude data line DL provides the pixel driving circuit PDC of the red sub-pixel with an amplitude data signal Data, the amplitude data line DL provides the pixel driving circuit PDC of the green sub-pixel with an amplitude data signal Data, and the amplitude data line DL provides the pixel driving circuit PDC of the blue sub-pixel with an amplitude data signal Data. For another example, the width data line DTL provides the pixel driving circuit PDC of the red sub-pixel with a width data signal DataT, the width data line DTL provides the pixel driving circuit PDC of the green sub-pixel with a width data signal DataT, and the width data line DTL provides the pixel driving circuit PDC of the blue sub-pixel with a width data signal DataT. In the same pixel column VPX, one width data line DTL is arranged between two adjacent amplitude data lines DL.

[0201] In one embodiment of the present disclosure, referring to FIG. 11 and FIG. 23, the arrangement of display circuit columns VDCX including two pixel columns VPX and display circuit rows HDCX including two pixel rows HPX is taken as an example. If each pixel PX has three sub-pixels of red, green and blue colors and one redundant sub-pixel, four display circuits DCX corresponding to each display circuit DCX having four display units DU in series are needed, and the light emitting elements LD in the same display circuit DCX have the same light emitting color. In one pixel column VPX, four amplitude data lines DL extending along the column direction DV are needed to provide the pixel driving circuit PDC of each display unit DU with amplitude data signals Data, and four width data lines DTL extending along the column direction DV are needed to provide the pixel driving circuit PDC of each display unit DU with width data signals DataT, and the four amplitude data lines DL and the four width data lines DTL are arranged along the row direction DH. For example, the amplitude data line DL providing the pixel driving circuit PDC of the red sub-pixel with the amplitude data signal Data, the amplitude data line DL providing the pixel driving circuit PDC of the green sub-pixel with the amplitude data signal Data, the amplitude data line DL providing the pixel driving circuit PDC of the blue sub-pixel with the amplitude data signal Data, and the amplitude data line DL providing the pixel driving circuit PDC of the redundant sub-pixel with the amplitude data signal Data. For another example, the width data line DTL providing the pixel driving circuit PDC of the red sub-pixel with the width data signal DataT, the width data line DTL providing the pixel driving circuit PDC of the green sub-pixel with the width data signal DataT, the width data line DTL providing the pixel driving circuit PDC of the blue sub-pixel with the width data signal DataT, and the width data line DTL providing the pixel driving circuit PDC of the redundant sub-pixel with the width data signal DataT. In the same pixel column VPX, one width data line DTL is arranged between two adjacent amplitude data lines DL. In this way, when the sub-pixel of one color fails, the redundant sub-pixel can be used to replace the failed sub-pixel to emit light of the corresponding color, so as to improve the product yield.

[0202] In one embodiment of the present disclosure, referring to FIG. 11 and FIG. 24, the display circuit column VDCX includes one pixel column VPX, and the display circuit row HDCX includes four pixel rows HPX. If each pixel PX has three sub-pixels of red, green and blue, three display circuits DCX are needed, each of which has four display units DU in series, and the light-emitting elements LD in the same display circuit DCX have the same light-emitting color. In one pixel column VPX, three amplitude data lines DL extending along the column direction DV are needed to provide the pixel driving circuit PDC of each display unit DU with an amplitude data signal Data, and correspondingly, three width data lines DTL extending along the column direction DV are needed to provide the pixel driving circuit PDC of each display unit DU with a width data signal DataT, and the three amplitude data lines DL and the three width data lines DTL are arranged along the row direction DH. For example, the amplitude data line DL provides the amplitude data signal Data to the pixel driving circuit PDC of the red sub-pixel, the amplitude data line DL provides the amplitude data signal Data to the pixel driving circuit PDC of the green sub-pixel, and the amplitude data line DL provides the amplitude data signal Data to the pixel driving circuit PDC of the blue sub-pixel. For another example, the width data line DTL provides the width data signal DataT to the pixel driving circuit PDC of the red sub-pixel, the width data line DTL provides the width data signal DataT to the pixel driving circuit PDC of the green sub-pixel, and the width data line DTL provides the width data signal DataT to the pixel driving circuit PDC of the blue sub-pixel. In the same pixel column VPX, one width data line DTL is arranged between two adjacent amplitude data lines DL.

[0203] In one embodiment of the present disclosure, referring to FIG. 11 and FIG. 25, the arrangement of the display circuit columns VDCX includes three pixel columns VPX, and the arrangement of the display circuit rows HDCX includes two pixel rows HPX. If each pixel PX has three sub-pixels of red, green and blue, three display circuits DCX are needed, each of which has six display units DU in series, and the light-emitting elements LD in the same display circuit DCX have the same light-emitting color. In one pixel column VPX, three amplitude data lines DL extending along the column direction DV are needed to provide the pixel driving circuits PDC of the display units DU with amplitude data signals Data, and correspondingly, three width data lines DTL extending along the column direction DV are needed to provide the pixel driving circuits PDC of the display units DU with width data signals DataT, and the three amplitude data lines DL and the three width data lines DTL are arranged along the row direction DH. For example, the amplitude data line DL provides the pixel driving circuit PDC of the red sub-pixel with the amplitude data signal Data, the amplitude data line DL provides the pixel driving circuit PDC of the green sub-pixel with the amplitude data signal Data, and the amplitude data line DL provides the pixel driving circuit PDC of the blue sub-pixel with the amplitude data signal Data. For another example, the width data line DTL provides the pixel driving circuit PDC of the red sub-pixel with the width data signal DataT, the width data line DTL provides the pixel driving circuit PDC of the green sub-pixel with the width data signal DataT, and the width data line DTL provides the pixel driving circuit PDC of the blue sub-pixel with the width data signal DataT. In the same pixel column VPX, one width data line DTL is arranged between two adjacent amplitude data lines DL.

[0204] In an embodiment of the present disclosure, referring to FIG. 11 and FIG. 26, the arrangement of the display circuit column VDCX includes two pixel columns VPX, and the arrangement of the display circuit row HDCX includes three pixel rows HPX. If each pixel PX has three sub-pixels of red, green and blue, three corresponding display circuits DCX are needed, and each display circuit DCX has six display units DU connected in series, and the light-emitting elements LD in the same display circuit DCX have the same light-emitting color. In one pixel column VPX, three amplitude data lines DL extending along the column direction DV are needed to provide the amplitude data signals Data to the pixel driving circuits PDC of the display units DU, and correspondingly, three width data lines DTL extending along the column direction DV are needed to provide the width data signals DataT to the pixel driving circuits PDC of the display units DU, and the three amplitude data lines DL and the three width data lines DTL are arranged along the row direction DH. For example, the amplitude data line DL provides the amplitude data signals Data to the pixel driving circuits PDC of the red sub-pixels, the amplitude data line DL provides the amplitude data signals Data to the pixel driving circuits PDC of the green sub-pixels, and the amplitude data line DL provides the amplitude data signals Data to the pixel driving circuits PDC of the blue sub-pixels. For another example, the width data line DTL provides the width data signals DataT to the pixel driving circuits PDC of the red sub-pixels, the width data line DTL provides the width data signals DataT to the pixel driving circuits PDC of the green sub-pixels, and the width data line DTL provides the width data signals DataT to the pixel driving circuits PDC of the blue sub-pixels. In the same pixel column VPX, one width data line DTL is arranged between two adjacent amplitude data lines DL.

[0205] In an embodiment of the present disclosure, referring to FIG. 11 and FIG. 27, the arrangement of the display circuit column VDCX includes two pixel columns VPX, and the arrangement of the display circuit row HDCX includes two pixel rows HPX. One pixel PX includes three light-emitting elements LD, and the colors of the three light-emitting elements LD are red, green and blue respectively, and the arrangement of the three light-emitting elements LD is delta arrangement. In four pixels PX, four red light-emitting elements LD are connected in series, four green light-emitting elements LD are connected in series, and four blue light-emitting elements LD are connected in series.

[0206] The series connection mode of the two adjacent red light emitting elements LD is described by taking the red light emitting element LD as an example. The series connection modes of the four blue light emitting elements LD and the four green light emitting elements LD are identical to that of the red light emitting element LD. In the two adjacent red light emitting elements LD, the second electrode of the first red light emitting element LD is electrically connected to the corresponding pad PAD through the via, the corresponding pad PAD of the first red light emitting element LD is electrically connected to the second transfer line TRL2 through the fourth via, the second transfer line TRL2 is electrically connected to the first transfer line TRL1 through the third via, and the first transfer line TRL1 is electrically connected to the first electrode of the second red light emitting element LD through the second via, so as to realize the series connection of the two adjacent red light emitting elements LD.

[0207] In an embodiment of the present disclosure, referring to FIG. 11 and FIG. 28, the arrangement mode of the display circuit column VDCX including two pixel columns VPX and the display circuit row HDCX including two pixel rows HPX is taken as an example. One pixel PX includes three light emitting elements LD, the colors of the three light emitting elements LD are red, green and blue respectively, and the three light emitting elements LD are arranged in a straight line along the row direction DH. In the four pixels PX, the four red light emitting elements LD are connected in series, the four green light emitting elements LD are connected in series, and the four blue light emitting elements LD are connected in series.

[0208] The series connection mode of the two adjacent red light emitting elements LD is described by taking the red light emitting element LD as an example. The series connection modes of the four blue light emitting elements LD and the four green light emitting elements LD are identical to that of the red light emitting element LD. In the two adjacent red light emitting elements LD, the second electrode of the first red light emitting element LD is electrically connected to the corresponding pad PAD through the via, the corresponding pad PAD of the first red light emitting element LD is electrically connected to the second transfer line TRL2 through the fourth via, the second transfer line TRL2 is electrically connected to the first transfer line TRL1 through the third via, and the first transfer line TRL1 is electrically connected to the first electrode of the second red light emitting element LD through the second via, so as to realize the series connection of the two adjacent red light emitting elements LD.

[0209] In an embodiment of the present disclosure, referring to FIG. 11 and FIG. 29, the arrangement mode of the display circuit column VDCX including two pixel columns VPX and the display circuit row HDCX including two pixel rows HPX is taken as an example. One pixel PX includes four light emitting elements LD, three of which are red, green and blue respectively, and the other one is a redundant light emitting element SLD, and the four light emitting elements LD are arranged in a rectangle along the row direction DH. In the four pixels PX, the four red light emitting elements LD are connected in series, the four green light emitting elements LD are connected in series, the four blue light emitting elements LD are connected in series, and the four redundant light emitting elements SLD are connected in series.

[0210] The series connection of two adjacent light emitting elements LD is described by taking the red light emitting element LD as an example. The series connection of the four blue light emitting elements LD, the four green light emitting elements LD, and the four redundant light emitting elements SLD is similar to that of the red light emitting element LD. In the two adjacent red light emitting elements LD, the second electrode of the first red light emitting element LD is electrically connected to the corresponding pad PAD through a via, the corresponding pad PAD of the first red light emitting element LD is electrically connected to the second transfer line TRL2 through a fourth via, the second transfer line TRL2 is electrically connected to the first transfer line TRL1 through a third via, and the first transfer line TRL1 is electrically connected to the first electrode of the second red light emitting element LD through a second via, so as to realize the series connection of the two adjacent red light emitting elements LD.

[0211] In an embodiment of the present disclosure, referring to FIG. 11 and FIG. 30, the arrangement of the display circuit column VDCX includes two pixel columns VPX, and the arrangement of the display circuit row HDCX includes three pixel rows HPX. One pixel PX includes three light emitting elements LD, and the colors of the three light emitting elements LD are red, green, and blue respectively. The arrangement of the three light emitting elements LD is a delta arrangement. In the four pixels PX, the four red light emitting elements LD are connected in series, the four green light emitting elements LD are connected in series, and the four blue light emitting elements LD are connected in series.

[0212] The series connection of two adjacent light emitting elements LD is described by taking the red light emitting element LD as an example. The series connection of the four blue light emitting elements LD and the four green light emitting elements LD is similar to that of the red light emitting element LD. In the two adjacent red light emitting elements LD, the second electrode of the first red light emitting element LD is electrically connected to the corresponding pad PAD through a via, the corresponding pad PAD of the first red light emitting element LD is electrically connected to the second transfer line TRL2 through a fourth via, the second transfer line TRL2 is electrically connected to the first transfer line TRL1 through a third via, and the first transfer line TRL1 is electrically connected to the first electrode of the second red light emitting element LD through a second via, so as to realize the series connection of the two adjacent red light emitting elements LD.

[0213] In an embodiment of the present disclosure, referring to FIG. 31, the material of the first transfer line TRL1 (not shown in FIG. 31) and the second transfer line TRL2 (not shown in FIG. 31) can be indium tin oxide (ITO), and the first transfer line TRL1 and the second transfer line TRL2 are the same transfer line TRL. Since indium tin oxide is a transparent material, the light emitting efficiency of the light emitting element LD can be improved.

[0214] The present disclosure also provides a method for manufacturing a display panel PNL. The display panel PNL includes a plurality of sub-pixels of different colors. For example, the display panel PNL has red sub-pixels, blue sub-pixels, green sub-pixels, and redundant sub-pixels.

[0215] The display panel PNL includes a light-emitting substrate and a color definition layer CDL. The color definition layer CDL has color definition units CU corresponding to the light-emitting elements LD one-to-one. At least part of the color definition units CU can convert light emitted by the corresponding light-emitting elements LD into light of a longer wavelength. For example, the color definition units CU can convert blue light emitted by the corresponding light-emitting elements LD into red light or green light.

[0216] The method for manufacturing the display panel PNL includes:

[0217] Step S100, forming a light-emitting substrate;

[0218] Step S200, detecting each light-emitting element LD to determine the position of the light-emitting element LD of each sub-pixel;

[0219] Step S300, generating a layout of a plurality of color definition sub-layers CUL corresponding to sub-pixels of different colors one-to-one according to the position of the light-emitting element LD of each sub-pixel. The color definition sub-layers CUL include color definition units CU of each sub-pixel of the same color;

[0220] Step S400, using a digital exposure machine to generate each color definition sub-layer CUL according to the layout of each color definition sub-layer CUL.

[0221] After the light-emitting substrate is formed, the light-emitting elements LD are tested. If the light-emitting elements LD are normal, the layout of the color definition sublayer CUL of the red subpixel, the green subpixel, and the blue subpixel is generated, respectively, and then a digital exposure machine generates the color definition sublayer CUL of each red subpixel, green subpixel, and blue subpixel according to the layout of the color definition sublayer CUL of the red subpixel, the green subpixel, and the blue subpixel. In an example, if a light-emitting element LD of a red subpixel fails, and the light-emitting elements LD of other red subpixels in the same display circuit DCX fail, the display circuit DCX in which the red subpixel is located cannot be used again, and a display circuit DCX in which a redundant subpixel is located is used to replace the display circuit DCX in which the red subpixel fails, so that a redundant light-emitting element SLD replaces the light-emitting element LD of the red subpixel that fails to emit light, and thus the layout of the color definition sublayer CUL of the redundant subpixel is the layout of the color definition sublayer CUL corresponding to the red subpixel that fails. In another example, if a light-emitting element LD of a red subpixel fails, and the light-emitting elements LD of other red subpixels in the same display circuit DCX emit light normally, a redundant light-emitting element SLD of a display circuit DCX in which a redundant subpixel is located is used to replace the light-emitting element LD of the red subpixel that fails to emit light, and since only one redundant light-emitting element SLD replaces one light-emitting element LD that fails to emit light, the relative positions of the light-emitting elements LD that emit red light in two adjacent pixels PX are different. In this way, the redundant subpixel replaces the subpixel that fails to emit light, and the yield of the product can be improved.

[0222] In an embodiment of the present disclosure, in step S300, the light emitted by each light-emitting element LD is of the same color. For example, the light emitted by each light-emitting element LD is blue or purple. In a red subpixel, the light-emitting element LD corresponds to a red quantum dot sublayer QD and a red first color film sublayer CF1. In a green subpixel, the light-emitting element LD corresponds to a green quantum dot sublayer QD and a green first color film sublayer CF1. In a blue subpixel, if the light-emitting element LD emits blue light, the light-emitting element LD corresponds to a scattering film sublayer SC and a blue second color film sublayer CF2. In a blue subpixel, if the light-emitting element LD emits purple light, the light-emitting element LD corresponds to a blue quantum dot sublayer QD and a blue first color film sublayer CF1.

[0223] In one embodiment of the present disclosure, when it is necessary to replace the failed light emitting element LD with the redundant light emitting element SLD, if other light emitting elements LD in the same display circuit DCX as the failed light emitting element LD also fail, then all the light emitting elements LD in the display circuit DCX in which the failed light emitting element LD is located need to be replaced with the redundant light emitting elements SLD. If other light emitting elements LD in the same display circuit DCX as the failed light emitting element LD are normal, then only one redundant light emitting element SLD is used to replace the failed light emitting element LD.

[0224] In one embodiment of the present disclosure, in step S300, referring to FIG. 12, each light emitting element LD can emit light of different colors. For example, there are red light emitting elements LD, green light emitting elements LD and blue light emitting elements LD. If a red light emitting element LD fails, then the red light emitting element LD is replaced by a redundant light emitting element SLD to emit red light. If a green light emitting element LD fails, then the green light emitting element LD is replaced by a redundant light emitting element SLD to emit green light. If a blue light emitting element LD fails, then the blue light emitting element LD is replaced by a redundant light emitting element SLD to emit blue light. It should be noted that in the embodiment of the present disclosure, the red light emitting element LD corresponds to the scattering film sub-layer SC and the red second color film sub-layer CF2, the green light emitting element LD corresponds to the scattering film sub-layer SC and the green second color film sub-layer CF2, and the blue light emitting element LD corresponds to the scattering film sub-layer SC and the blue second color film sub-layer CF2.

[0225] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

Claims

1. A display circuit, wherein, The display circuit comprises a plurality of display units connected in series, and each display unit comprises a light emitting element and a pixel driving circuit electrically connected to a first electrode of the light emitting element. In two adjacent display units, a second electrode of the light emitting element of the former display unit is electrically connected to a first electrode of the light emitting element of the latter display unit.

2. The display circuit of claim 1, wherein, The pixel driving circuit of the first display unit comprises one of a first current control unit or a second current control unit. The first current control unit is configured to provide a first driving current flowing from the pixel driving circuit to the light emitting element. The second current control unit is configured to provide a second driving current flowing from the light emitting element to the pixel driving circuit. When the first electrode of the light emitting element is an anode, the pixel driving circuit of the first display unit is capable of being loaded with a driving power supply voltage VDD(1), and the pixel driving circuit of the first display unit comprises the first current control unit; and a second electrode of the light emitting element of the last display unit is capable of being loaded with a reference power supply voltage VSS(1). When the first electrode of the light emitting element is a cathode, the pixel driving circuit of the first display unit is capable of being loaded with the reference power supply voltage VSS(1), and the pixel driving circuit of the first display unit comprises the second current control unit; and the second electrode of the light emitting element of the last display unit is capable of being loaded with the driving power supply voltage VDD(1).

3. The display circuit of claim 2, wherein, In the first display unit, the pixel driving circuit comprises a pulse width modulation unit. One end of the pulse width modulation unit is electrically connected to an output end of the first current control unit or an output end of the second current control unit, and the other end of the pulse width modulation unit is electrically connected to the first electrode of the light emitting element.

4. The display circuit of claim 1, wherein, The display circuit comprises y display units connected in series. A display unit DU(x) comprises a first current control unit and a second current control unit; the display unit DU(x) is an xth display unit, and x is a positive integer greater than 1 and not greater than y, and y is a positive integer greater than 1. The first current control unit is capable of being loaded with a driving power supply voltage VDD(x), and the second current control unit is capable of being loaded with a reference power supply voltage VSS(x); the driving power supply voltage VDD(x) is an xth driving power supply voltage; and the reference power supply voltage VSS(x) is an xth reference power supply voltage. A driving power supply voltage VDD(x1) is greater than a driving power supply voltage VDD(x2), x1 is less than x2, x1 is a positive integer not greater than y, and x2 is a positive integer not greater than y. A reference power supply voltage VSS(x3) is less than a reference power supply voltage VSS(x4), x3 is less than x4, x3 is a positive integer greater than 1 and not greater than y, and x4 is a positive integer greater than 1 and not greater than y.

5. The display circuit of claim 4, wherein, In the display unit DU(x), the pixel driving circuit further comprises a pulse width modulation unit. In the display unit DU(x), one end of the pulse width modulation unit is electrically connected to the output end of the first current control unit and the output end of the second current control unit, and the other end of the pulse width modulation unit is electrically connected to the first electrode of the light emitting element.

6. The display circuit of claim 1, wherein, The number of the display units is 3-6.

7. The display circuit of any one of claims 1 to 6, wherein, The light emitting elements in each of the display units have the same light emitting color.

8. A display panel, wherein, The display panel comprises a plurality of display circuits as claimed in any one of claims 1-7 arranged in an array.

9. The display panel of claim 8, wherein, The display panel comprises a substrate, a driving layer, and a light emitting layer arranged in sequence; the light emitting elements are arranged in the light emitting layer, and the pixel driving circuit is arranged in the driving layer. The driving layer is provided with a driving power supply voltage trace for loading the required driving power supply voltage to the display circuit and a reference power supply voltage trace for loading the required reference power supply voltage to the display circuit.

10. The display panel of claim 9, wherein, The display panel comprises a plurality of pixels arranged in an array, and the pixels form pixel columns and pixel rows. The display panel further comprises a display circuit column. The display circuit column comprises one pixel column or a plurality of adjacent pixel columns. The display panel further comprises a voltage trace column group corresponding to the display circuit column one by one. The voltage trace column group comprises each driving power supply voltage trace and each reference power supply voltage trace required for driving the display circuit.

11. The display panel of claim 10, wherein, The display panel further comprises a display circuit row. The display circuit row comprises one pixel row or a plurality of adjacent pixel rows.

12. The display panel of claim 10, wherein, The display circuit column comprises one pixel column, and the display circuit row comprises a plurality of pixel rows. Alternatively, the display circuit column comprises two pixel columns, and the display circuit row comprises a plurality of pixel rows. Alternatively, the display circuit column comprises at least three pixel columns, and the display circuit row comprises two pixel rows.

13. The display panel of claim 9, wherein, The light emitting layer comprises a plurality of light emitting elements and a plurality of transfer lines. In adjacent two display units of the same display circuit, the second electrode of the light emitting element of the former display unit is electrically connected to the first electrode of the light emitting element of the latter display unit through the transfer line.

14. The display panel of claim 13, wherein, The light emitting layer comprises a pad layer, a light emitting element layer, and a transfer line arranged in sequence. The pad layer has a pad corresponding to the second electrode of each light emitting element; the second electrode of the light emitting element is electrically connected to the corresponding pad. In adjacent two display units of the same display circuit, the pad to which the second electrode of the light emitting element of the former display unit is electrically connected is connected to the first electrode of the light emitting element of the latter display unit through the transfer line.

15. The display panel of claim 14, wherein, The light emitting layer further comprises a third planarization layer covering each light emitting element, and the third planarization layer has a first via hole exposing the first electrode of the light emitting element. The transfer line is arranged on the side of the third planarization layer away from the pad layer and is electrically connected to the first electrode of the light emitting element through the first via hole.

16. The display panel of claim 14, wherein, The light emitting layer further comprises a third planarization layer, a first transfer layer, a fourth passivation layer, and a second transfer layer arranged in sequence on the side of the light emitting element layer away from the pad layer. The transfer line comprises a first transfer line in the first transfer layer and a second transfer line in the second transfer layer. The third planarization layer has a first via hole exposing a first electrode of the light emitting element; The fourth passivation layer has a second via hole exposing the first electrode of the light emitting element, and the second transfer line is electrically connected to the first electrode of the light emitting element through the second via hole; The fourth passivation layer has a third via hole exposing a partial region of the first transfer line, and the second transfer line is electrically connected to the first transfer line through the third via hole; The third planarization layer has a fourth via hole exposing a partial region of the pad, and the first transfer line is electrically connected to the pad through the fourth via hole.

17. The display panel of claim 9, wherein, The light emitting color of each of the light emitting elements in the light emitting layer is the same; The display panel further comprises a color definition layer located on a side of the light emitting layer away from the substrate; The color definition layer has color definition units corresponding to each of the light emitting elements, and at least part of the color definition units can convert light emitted by the corresponding light emitting elements into light with a longer wavelength.

18. The display panel of claim 17, wherein, The color definition unit comprises a first color definition unit; The first color definition unit comprises a quantum dot sub-layer and a first color film sub-layer located on a side of the quantum dot sub-layer away from the light emitting element; The quantum dot sub-layer can convert light provided by the light emitting element into light with a longer wavelength, and the light emitting color of the quantum dot sub-layer is the same as the color of the first color film sub-layer.

19. The display panel of claim 17, wherein, The color definition unit further comprises a second color definition unit; The second color definition unit comprises a scattering film sub-layer and a second color film sub-layer located on a side of the scattering film sub-layer away from the light emitting element; the color of the second color film sub-layer is the same as the light emitting color of the light emitting element.

20. The display panel of claim 17, wherein, The display panel comprises pixels arranged in an array; The pixel comprises a plurality of sub-pixels and at least one redundant sub-pixel; The sub-pixel comprises the light emitting element and the color definition unit corresponding to the light emitting element; the redundant sub-pixel comprises a redundant light emitting element and a color definition unit corresponding to the redundant light emitting element; In at least two pixels, the relative positions of the sub-pixels emitting the same color light in the pixels are different.

21. A method of manufacturing a display panel, wherein, The display panel comprises sub-pixels of multiple different colors; the display panel comprises a light emitting substrate and a color definition layer stacked together; the color definition layer has color definition units corresponding to each of the light emitting elements, and at least part of the color definition units can convert light emitted by the corresponding light emitting elements into light with a longer wavelength; The preparation method of the display panel comprises: forming a light emitting substrate; detecting each of the light emitting elements to determine the position of the light emitting element of each sub-pixel; generating a layout of a plurality of color definition sub-layers corresponding to sub-pixels of different colors according to the position of the light emitting element of each sub-pixel, wherein the color definition sub-layer comprises color definition units of each sub-pixel of the same color; using a digital exposure machine to generate each color definition sub-layer according to the layout of each color definition sub-layer.

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