Pixel circuit and driving method thereof, display substrate

Abstract

A pixel circuit, a driving method thereof and a display substrate, the pixel circuit comprising a driving sub-circuit (21), a data writing sub-circuit (22), a compensation sub-circuit (23), a coupling sub-circuit (24) and a first control sub-circuit (25), the driving sub-circuit (21) being connected with a first node (N1), a third node (N3) and a fourth node (N4), the compensation sub-circuit (23) being connected with a first scan line (GL1), the first node (N1) and the fourth node (N4), and the coupling sub-circuit (24) being connected with the first node (N1) and a second node (N2); the pixel circuit comprises a first refresh stage, a threshold compensation stage and a data writing stage which are sequentially performed, or comprises a first refresh stage, a data writing stage and a threshold compensation stage which are sequentially performed, and in the first refresh stage, the data writing stage and the threshold compensation stage, the compensation sub-circuit (23) is always in a conducting state under the control of the first scan line (GL1).

Description

Pixel circuit, driving method thereof and display substrate TECHNICAL FIELD

[0001] The present application relates to, but is not limited to, the technical field of display, and in particular to a pixel circuit, a driving method thereof and a display substrate. BACKGROUND

[0002] Organic light emitting diode (OLED) has the advantages of ultra-thin, large viewing angle, active light-emitting, high brightness, continuously adjustable light-emitting color, low cost, fast response speed, low power consumption, wide operating temperature range and flexible display, and has gradually become the next generation display technology with great development prospects and is attracting more and more attention. According to different driving modes, OLED can be divided into passive matrix (PM) and active matrix (AM). AMOLED is a current-driven device, which uses independent thin film transistors (TFT) to control each sub-pixel, and each sub-pixel can be continuously and independently driven to emit light.

[0003] SUMMARY

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present application provides a pixel circuit, a driving method thereof and a display substrate.

[0006] In one aspect, the present application provides a pixel circuit, which comprises at least a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a coupling sub-circuit and a first control sub-circuit. The driving sub-circuit is connected with a first node, a third node and a fourth node. The compensation sub-circuit is connected with a first scan line, the first node and the fourth node. The data writing sub-circuit is connected with a second scan line, a data line and a second node. The coupling sub-circuit is connected with the first node and the second node. The first control sub-circuit is connected with the second node and a first reference voltage line. The pixel circuit comprises at least a first refresh stage, a threshold compensation stage and a data writing stage in sequence during driving, or at least a first refresh stage, a data writing stage and a threshold compensation stage in sequence, and the compensation sub-circuit is in a conductive state under the control of the first scan line during the first refresh stage, the data writing stage and the threshold compensation stage.

[0007] In another aspect, the embodiment provides a driving method of a pixel circuit, the pixel circuit comprising at least a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a coupling sub-circuit and a first control sub-circuit, the driving sub-circuit being connected with a first node, a third node and a fourth node, the compensation sub-circuit being connected with a first scan line, the first node and the fourth node, the data writing sub-circuit being connected with a second scan line, a data line and a second node, the coupling sub-circuit being connected with the first node and the second node, and the first control sub-circuit being connected with the second node and a first reference voltage line; the driving method of the pixel circuit comprises at least a first refresh stage, a threshold compensation stage and a data writing stage, or comprises at least a first refresh stage, a data writing stage and a threshold compensation stage, and in the first refresh stage, the data writing stage and the threshold compensation stage, the compensation sub-circuit is always in a conductive state under the control of the first scan line.

[0008] In another aspect, the embodiment provides a display substrate comprising the pixel circuit according to any one of the embodiments of the present disclosure.

[0009] Other aspects can become apparent from the following detailed description when read in conjunction with the drawings.

[0010] SUMMARY

[0011] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0012] Fig. 1 is an equivalent circuit diagram of a pixel circuit;

[0013] Fig. 2 is a structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0014] Fig. 3 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0015] Fig. 4 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0016] Fig. 5 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0017] Fig. 6 is a working timing diagram of the pixel circuit shown in Fig. 5;

[0018] Fig. 7 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0019] Fig. 8 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0020] FIG. 9 is a timing chart of operation of the pixel circuit shown in FIG. 8;

[0021] FIG. 10 is another structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0022] FIG. 11 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0023] FIG. 12 is a timing chart of operation of the pixel circuit shown in FIG. 11;

[0024] FIG. 13A is a flowchart of a driving method of a pixel circuit according to at least one embodiment of the present disclosure;

[0025] FIG. 13B is another flowchart of a driving method of a pixel circuit according to at least one embodiment of the present disclosure.

[0026] Detailed Description

[0027] Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. Embodiments can be implemented in various forms. It is readily apparent to those skilled in the art that the embodiments and features thereof can be changed or replaced without departing from the gist of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the following embodiments. Embodiments in the present disclosure and features in the embodiments can be combined with each other as long as they do not conflict with each other.

[0028] In the drawings, the size, the thickness or the region of one or a plurality of components may, at times, be exaggerated for the sake of clarity. Thus, one embodiment of the present disclosure is not necessarily limited by the size, the shape or the region of one or a plurality of components illustrated in the drawings. The drawings are schematically shown an ideal example, and one embodiment of the present disclosure is not limited to the shape or the numerical value illustrated in the drawings.

[0029] The ordinal numbers "first", "second", "third" and the like in the present specification are used to avoid confusion among components, and are not intended to indicate the number in the order of limitation. "A plurality of" in the present disclosure means two or more.

[0030] In this specification, terms of "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or locational relationship are used to describe the positional relationship of the components with reference to the drawings for the convenience of the description of this specification and the simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is changed as appropriate according to the direction of the components described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0031] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected", "coupled" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or connected; it can be directly connected, or indirectly connected through an intermediate, or connected between two elements. The above-mentioned terms in the present disclosure can be understood according to the situation by those skilled in the art. Among them, "coupled" can include "electrically connected", "electrically connected" can include the case where the components are connected together through elements having certain electrical effects. The "element having certain electrical effects" is not particularly limited as long as it can transmit electrical signals between the connected components. Examples of "elements having certain electrical effects" include not only electrodes and wires, but also switching elements such as transistors, resistors, inductors, capacitors, other elements with multiple functions, and the like.

[0032] In this specification, a transistor refers to an element including at least a gate (gate electrode), a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to a region where current mainly flows.

[0033] In this specification, the first electrode can be a drain, and the second electrode can be a source, or the first electrode can be a source, and the second electrode can be a drain. In addition, the gate can also be referred to as a control electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source" and "drain" are sometimes exchanged with each other. Therefore, in this specification, "source" and "drain" can be exchanged with each other.

[0034] In this specification, "about", "approximately", and the like mean that the limit is not strictly defined, and the range of process and measurement error is allowed. In the present disclosure, "the same" includes the case where the numerical value differs by 10% or less, such as the case where the numerical value differs by 5% or less.

[0035] In the present disclosure, the effective level signal includes a level signal for turning on a transistor, for example, the effective level signal for turning on a P-type transistor is a low level signal, and the effective level signal for turning on an N-type transistor is a high level signal.

[0036] FIG. 1 is an equivalent circuit diagram of a pixel circuit. As shown in FIG. 1, the pixel circuit includes seven transistors (i.e., transistors T01 to T07) and a storage capacitor Cst. The seven transistors are of the same type, for example, the seven transistors are all P-type transistors. Among them, the gates of transistors T02 and T04 are both connected with a first gate line GATE1, the gate of transistor T01 is connected with a second gate line GATE2, the gate of transistor T07 is connected with a third gate line GATE3, and the gates of transistors T05 and T06 are both connected with an emission control line EML. In the pixel circuit, the data voltage provided by the data signal line DATA can drive transistor T03 to write the data voltage and compensate the threshold voltage Vth. In the data writing stage, transistors T02 and T04 use the same scan signal provided by the first gate line GATE1 to realize data writing and threshold voltage compensation.

[0037] However, with the increase of the resolution and the increase of the frequency of the display device, the above-mentioned scheme of using the data voltage to compensate the threshold voltage will appear a driving bottleneck. For example, with the increase of the display refresh rate, the data writing time length (1H) of a single row of pixel circuits in a frame will gradually decrease, and with the decrease of the data writing time length, the phenomenon of difficult data writing and insufficient threshold voltage compensation will appear.

[0038] The present embodiment provides a pixel circuit, a driving method thereof and a display substrate, which can improve the compensation effect of the threshold voltage and thus improve the display performance.

[0039] FIG. 2 is a structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 2, the pixel circuit according to the present embodiment can at least include a driving sub-circuit 21, a data writing sub-circuit 22, a compensation sub-circuit 23, a coupling sub-circuit 24 and a first control sub-circuit 25.

[0040] The driving sub-circuit 21 is connected with the first node N1, the third node N3 and the fourth node N4 respectively, and is configured to provide a driving signal to the fourth node N4 under the control of the first node N1. The data writing sub-circuit 22 is connected with the second scan line GL2, the data line DL and the second node N2 respectively, and is configured to write a data signal provided by the data line DL to the second node N2 under the control of the second scan line GL2. The compensation sub-circuit 23 is connected with the first scan line GL1, the first node N1 and the fourth node N4 respectively, and is configured to turn on the first node N1 and the fourth node N4 under the control of the first scan line GL1, so that the threshold voltage of the driving sub-circuit 21 is written to the first node N1. The coupling sub-circuit 24 is connected with the first node N1 and the second node N2 respectively. The first control sub-circuit 25 is connected with the second node N2 and the first reference voltage line REF1 respectively, and is connected with the first light-emitting control line EM1 or the third reset control line RST3, and is configured to write a first reference voltage signal provided by the first reference voltage line REF1 to the second node N2 under the control of the first light-emitting control line EM1 or the third reset control line RST3 after the data writing sub-circuit 22 writes the data signal to the second node N2, so that the data signal is coupled to the first node N1 through the coupling sub-circuit 24.

[0041] The pixel circuit provided by the embodiment of the present disclosure includes at least a first refresh stage, a threshold compensation stage and a data writing stage which are sequentially performed, or includes at least a first refresh stage, a data writing stage and a threshold compensation stage which are sequentially performed, and in the first refresh stage, the data writing stage and the threshold compensation stage, the compensation sub-circuit 23 is always in the on state under the control of the first scan line GL1.

[0042] The pixel circuit provided by the embodiment of the present disclosure includes at least a first refresh stage, a threshold compensation stage and a data writing stage which are sequentially performed, or includes at least a first refresh stage, a data writing stage and a threshold compensation stage which are sequentially performed, and in the first refresh stage, the data writing stage and the threshold compensation stage, the compensation sub-circuit 23 is always in the on state under the control of the first scan line GL1.

[0043] In some examples, the time length for the data writing sub-circuit 22 to write the data signal to the second node N2 can be less than the time length for the compensation sub-circuit 23 to write the threshold voltage of the driving sub-circuit 21 to the first node N1. The present example can control the data writing process and the threshold voltage compensation process separately, and by increasing the compensation time length of the threshold voltage, the compensation effect of the threshold voltage can be improved, thereby improving the picture display uniformity.

[0044] In some examples, the first scan line GL1 can be configured to provide a first scan signal, and the second scan line GL2 can be configured to provide a second scan signal. The first scan signal can be configured to control the compensation sub-circuit 23 to write the threshold voltage of the driving sub-circuit 21 to the first node N1, and the second scan signal can be configured to control the data writing sub-circuit 22 to write the data signal to the second node N2. The first scan signal can be different from the second scan signal. For example, the duration of the active level signal of the first scan signal can be greater than the duration of the active level signal of the second scan signal.

[0045] FIG. 3 is another schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 3, the pixel circuit can further include a first light emitting control sub-circuit 26 connected with the first light emitting control line EM2, the first power supply line VDD, and the third node N3, respectively.

[0046] In the threshold compensation phase, the first light emitting control sub-circuit 26 is turned on under the control of the first light emitting control line EM2, and the threshold voltage of the driving sub-circuit 21 is written to the first node through the first light emitting control sub-circuit 26, the driving sub-circuit 21, and the compensation sub-circuit 23.

[0047] In some examples, the pixel circuit can further include a second light emitting control sub-circuit 27 connected with the second light emitting control line EM1, the fourth node N4, and the fifth node N5, respectively, and the fifth node N5 is connected with the first electrode of the light emitting element, and the second electrode of the light emitting element is connected with the second power supply line VSS.

[0048] The pixel circuit can further include a light emitting phase after the threshold compensation phase and the data writing phase during driving. In the light emitting phase, the first light emitting control sub-circuit 26 is turned on under the control of the first light emitting control line EM2, the second light emitting control sub-circuit 27 is turned on under the control of the second light emitting control line EM1, the first power supply line VDD provides a driving current to the first electrode of the light emitting element, and the light emitting element is driven to emit light.

[0049] In some examples, the first light emitting control line EM2 can be configured to provide a first light emitting control signal, and the second light emitting control line EM1 can be configured to provide a second light emitting control signal. The first light emitting control signal can be configured to control the first light emitting control sub-circuit 26 to write the first power supply signal to the third node N3, and the second light emitting control signal can be configured to control the second light emitting control sub-circuit 27 to turn on the fourth node N4 and the fifth node N5 to provide a driving signal to the light emitting element, so that the light emitting element emits light. The first light emitting control signal can be different from the second light emitting control signal.

[0050] In some examples, the light emitting element can be an organic light emitting diode (OLED). The first electrode of the light emitting element can be an anode, and the second electrode can be a cathode. However, the present embodiments are not limited thereto.

[0051] In some examples, the first power line VDD can continuously provide a constant high level signal, for example, the first power line VDD can provide a first power signal. The second power line VSS can continuously provide a constant low level signal, for example, the second power line VSS can provide a second power signal. The first power signal can be greater than the second power signal.

[0052] FIG. 4 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 4, the coupling sub-circuit 24 can include a first coupling sub-circuit 241 and a second coupling sub-circuit 242, the first coupling sub-circuit 241 being connected with the first node N1 and the sixth node N6 respectively, and the second coupling sub-circuit 242 being connected with the sixth node N6 and the second node N2 respectively.

[0053] In some examples, as shown in FIG. 4, the first control sub-circuit 25 is connected with the second light emitting control line EM1, the first reference voltage line REF1 and the second node N2 respectively, and in the second reset phase and the light emitting phase, the first control sub-circuit 25 writes the first reference voltage of the first reference voltage line REF1 into the second node N2 under the control of the second light emitting control line EM1.

[0054] In some examples, as shown in FIG. 4, the pixel circuit can further include a second control sub-circuit 30, the second control sub-circuit 30 being connected with the first scan line GL1, the sixth node N6 and the first reference voltage line REF1 respectively, and in the first refresh phase, the data writing phase and the threshold compensation phase, the second control sub-circuit 30 is always in an on state under the control of the first scan line GL1, and the voltage of the sixth node N6 is maintained as the first reference voltage provided by the first reference voltage line REF1.

[0055] In some examples, as shown in FIG. 4, the pixel circuit can further include a first reset sub-circuit 28 and a second reset sub-circuit 29, the first reset sub-circuit 28 being connected with the first reset control line RST1, the first initial voltage line INIT1 and the fifth node N5 respectively, and the second reset sub-circuit 29 being connected with the second reset control line RST2, the second reference voltage line REF2 and the third node N3 respectively.

[0056] In some examples, the first reset control line RST1 can be configured to provide a first reset control signal, and the second reset control line RST2 can be configured to provide a second reset control signal. The first reset control signal can be configured to control the first reset sub-circuit 28 to reset the fifth node N5, and the second reset control signal can be configured to control the second reset sub-circuit 29 to reset the third node N3. The first reset control signal can be different from the second reset control signal.

[0057] In some examples, the first initial voltage line INIT1 can be configured to provide a first initial voltage signal. The first reference voltage line REF1 can be configured to provide a first reference voltage signal, and the second reference voltage line REF2 can be configured to provide a second reference voltage signal. The first initial voltage signal, the first reference voltage signal, and the second reference voltage signal can be different. For example, the first reset voltage signal can be less than the first reference voltage signal, the first reference voltage signal can be less than the first power voltage signal, and the second reference voltage signal can be greater than the first power voltage signal. For example, the threshold voltage of the driving transistor can be -3V, the first reset voltage can be -2V, the first reference voltage can be 3V, the first power voltage can be 4.6V, and the second reference voltage can be 7V. However, the present disclosure is not limited thereto.

[0058] By resetting the fifth node N5 through the first reset sub-circuit 28, the present embodiment of the present disclosure can eliminate the leakage current of the second light-emitting control sub-circuit 27, avoid the light-emitting element from emitting light in the dark state due to the influence of the leakage current, and improve the display quality. Moreover, the present embodiment of the present disclosure can eliminate the residual positive charge on the surface of the first electrode of the light-emitting element, and improve the service life of the light-emitting element. By writing the second reference voltage to the third node N3 through the second reset sub-circuit 29, the present embodiment of the present disclosure can reset the third node N3.

[0059] In some examples, the first refresh stage can include a first reset stage and a second reset stage performed in sequence.

[0060] In the first reset stage, the second reset sub-circuit 29 is turned on under the control of the second reset control line RST2, and the second reference voltage signal output by the second reference voltage line REF2 is provided to the first node N1 through the second reset sub-circuit 29, the driving sub-circuit 21, and the compensation sub-circuit 23, so as to reset the first node N1.

[0061] In the second reset stage, the first reset sub-circuit 28 is turned on under the control of the first reset control line RST1, the second light-emitting control sub-circuit 27 is turned on under the control of the second light-emitting control line EM1, and the first initial voltage signal output by the first initial voltage line INIT1 is provided to the first node N1 through the first reset sub-circuit 28, the second light-emitting control sub-circuit 27 and the compensation sub-circuit 23, so that the first node N1 is reset.

[0062] Fig. 5 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Fig. 5, the driving sub-circuit 21 can include a driving transistor T3; the data writing sub-circuit 22 can include a data writing transistor T7; the compensation sub-circuit 23 can include a compensation transistor T2; the first coupling sub-circuit 241 can include a first capacitor C1; the second coupling sub-circuit 242 can include a second capacitor C2; the first control sub-circuit 25 can include a first control transistor T8; the first light-emitting control sub-circuit 26 can include a first light-emitting control transistor T5; the second light-emitting control sub-circuit 27 can include a second light-emitting control transistor T6; the first reset sub-circuit 28 can include a first reset transistor T1; the second reset sub-circuit 29 can include a second reset transistor T4; and the second control sub-circuit 30 can include a second control transistor T9.

[0063] In some examples, as shown in FIG. 5, a gate of the driving transistor T3 is coupled with the first node N1, a first electrode of the driving transistor T3 is coupled with the third node N3, and a second electrode of the driving transistor T3 is coupled with the fourth node N4. A gate of the compensation transistor T2 is coupled with the first scan line GL1, a first electrode of the compensation transistor T2 is coupled with the fourth node N4, and a second electrode of the compensation transistor T2 is coupled with the first node N1. A gate of the data write transistor T7 is coupled with the second scan line GL2, a first electrode of the data write transistor T7 is coupled with the data line DL, and a second electrode of the data write transistor T7 is coupled with the second node N2. A first plate of the first capacitor C1 is coupled with the first node N1, and a second plate of the first capacitor C1 is coupled with the sixth node N6. A first plate of the second capacitor C2 is coupled with the sixth node N6, and a second plate of the second capacitor C2 is coupled with the second node N2. A gate of the first control transistor T8 is coupled with the first emission control line EM1, a first electrode of the first control transistor T8 is coupled with the first reference voltage line REF1, and a second electrode of the first control transistor T8 is coupled with the second node N2. A gate of the second control transistor T9 is coupled with the first scan line GL1, a first electrode of the second control transistor T9 is coupled with the first reference voltage line REF1, and a second electrode of the second control transistor T9 is coupled with the sixth node N6. A gate of the first emission control transistor T5 is coupled with the first emission control line EM2, a first electrode of the first emission control transistor T5 is coupled with the first power supply line VDD, and a second electrode of the first emission control transistor T5 is coupled with the third node N3. A gate of the second emission control transistor T6 is coupled with the second emission control line EM1, a first electrode of the second emission control transistor T6 is coupled with the fourth node N4, and a second electrode of the second emission control transistor T6 is coupled with the fifth node N5. A gate of the first reset transistor T1 is coupled with the first reset control line RST1, a first electrode of the first reset transistor T1 is coupled with the first initial voltage line INIT1, and a second electrode of the first reset transistor T1 is coupled with the fifth node N5. A gate of the second reset transistor T4 is coupled with the second reset control line RST2, a first electrode of the second reset transistor T4 is coupled with the second reference voltage line REF2, and a second electrode of the second reset transistor T4 is coupled with the third node N3. A first electrode of the light emitting element EL is coupled with the fifth node N5, and a second electrode of the light emitting element EL is coupled with the second power supply line VSS.

[0064] In some examples, the first node N1 is a connection point of the first capacitor C1, the compensation transistor T2 and the driving transistor T3. The second node N2 is a connection point of the second capacitor C2, the data write transistor T7 and the first control transistor T8. The third node N3 is a connection point of the first light emitting control transistor T5, the second reset transistor T4 and the driving transistor T3. The fourth node N4 is a connection point of the compensation transistor T2, the driving transistor T3 and the second light emitting control transistor T6. The fifth node N5 is a connection point of the second light emitting control transistor T6, the first reset transistor T1 and the light emitting element EL. The sixth node N6 is a connection point of the first capacitor C1, the second capacitor C2 and the second control transistor T9.

[0065] FIG. 5 shows an exemplary structure of the driving sub-circuit 21, the data write sub-circuit 22, the compensation sub-circuit 23, the first coupling sub-circuit 241, the second coupling sub-circuit 242, the first control sub-circuit 25, the first light emitting control sub-circuit 26, the second light emitting control sub-circuit 27, the first reset sub-circuit 28, the second reset sub-circuit 29 and the second control sub-circuit 30. It is easy for those skilled in the art to understand that the implementation of the above sub-circuits is not limited thereto as long as the functions thereof can be realized.

[0066] In some examples, as shown in FIG. 5, the first reset transistor T1, the compensation transistor T2, the driving transistor T3, the second reset transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the data write transistor T7, the first control transistor T8 and the second control transistor T9 can be P-type thin film transistors, for example, low temperature poly-silicon thin film transistors can be adopted. The active layer of the low temperature poly-silicon thin film transistor can adopt low temperature poly-silicon (LTPS, Low Temperature Poly-Silicon). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging.

[0067] FIG. 6 is a working timing diagram of the pixel circuit shown in FIG. 5. As shown in FIG. 5, the pixel circuit of the present example can include 9 transistors (i.e., transistors T1 to T9), 2 capacitor units (i.e., the first capacitor C1 and the second capacitor C2), 10 input terminals (i.e., the data line DL, the first scan line GL1, the second scan line GL2, the first light emitting control line EM2, the second light emitting control line EM1, the first reset control line RST1, the second reset control line RST2, the first reference voltage line REF1, the second reference voltage line REF2 and the first initial voltage line INIT1), and 2 power terminals (i.e., the first power line VDD and the second power line VSS).

[0068] In some examples, as shown in FIG. 6, the working process of the pixel circuit in a frame time period can include a first stage t11 to a sixth stage t16.

[0069] Before the current frame is displayed, i.e. before the first stage t11 of the current frame is displayed, the output of the second light-emitting control line EM1 is set to a low-level signal, i.e. the second light-emitting control signal provided by the second light-emitting control line EM1 is a low-level signal, the second light-emitting control transistor T6 is in an open state under the action of the second light-emitting control signal, the output of the first light-emitting control line EM2 is set to a low-level signal, i.e. the first light-emitting control signal provided by the first light-emitting control line EM2 is a low-level signal, the first light-emitting control transistor T5 is in an open state under the action of the first light-emitting control signal. At the same time, the outputs of the first scan line GL1, the second scan line GL2, the first reset control line RST1 and the second reset control line RST2 are all set to high-level signals, and the corresponding controlled transistors are all in a closed state, and the light-emitting device EL is in the previous frame light-emitting display stage of the current frame.

[0070] Then, the outputs of the second light-emitting control line EM1 and the first light-emitting control line EM2 are both set to high-level signals, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both in a closed state, and each node is in a floating state, and the previous frame display ends.

[0071] The first stage t11 can also be referred to as the first reset stage. In the first stage t11 of the current frame, the first scan signal provided by the first scan line GL1 jumps to a low level, the second reset signal provided by the second reset control line RST2 first maintains a high level for a pixel row scanning time, and then jumps to a low level, and the second scan line GL2, the first reset control line RST1, the first light-emitting control line EM2 and the second light-emitting control line EM1 all maintain high-level signals.

[0072] Under the action of the low-level signal provided by the first scan line GL1, the compensation transistor T2 and the second control transistor T9 are turned on, and under the action of the low-level signal provided by the second reset control line RST2, the second reset transistor T4 is turned on. The first reference voltage signal provided by the first reference voltage line REF1 can be provided to the sixth node N6 through the turned-on second control transistor T9, so that the sixth node N6 is reset to the first reference voltage Vref1. The second reference voltage signal provided by the second reference voltage line REF2 can be provided to the third node N3 through the turned-on second reset transistor T4, so that the third node N3 is reset to the second reference voltage Vref2, to perform bias voltage refreshing before compensating the threshold voltage Vth of the driving transistor T3, and the voltage refreshing of the first node N1 is restored to Vref2+Vth, wherein Vth is the threshold voltage of the driving transistor T3, so that the hysteresis level of the driving transistor T3 can be effectively improved. In addition, due to the influence of the driving circuit and the device structure, the brightness of the first frame is usually only 60% of the required brightness when the display screen switches the display picture. For the more sensitive human eye, the phenomenon seen is that the first frame after switching the picture will appear trailing. In the embodiment of the present disclosure, by refreshing the voltage of the first node N1 with high voltage (Vref2+Vth) in the first stage t11 and then resetting the voltage of the first node N1 with low voltage (Vinit1) in the second stage t12, the first frame brightness ratio (First Frame Ratio, FFR) can be improved, the trailing problem can be improved, and the image quality can be improved.

[0073] In the transition stage between the first stage t11 and the second stage t12, the second reset signal provided by the second reset control line RST2 jumps to high level, the first reset signal provided by the first reset control line RST1 first maintains high level for one pixel row scanning time, and then jumps to low level, and the remaining signals maintain the state of the first stage t11.

[0074] The second stage t12 can also be referred to as a second reset stage. In the second stage t12 of the current frame, the first scan signal provided by the first scan line GL1 remains low level, the second emission control signal provided by the second emission control line EM1 jumps to low level, the first reset signal provided by the first reset control line RST1 remains low level, and the first emission control line EM2, the second scan line GL2 and the second reset control line RST2 all output high level signals.

[0075] Under the action of the continuous low-level signal provided by the first scan line GL1, the compensation transistor T2 and the second control transistor T9 remain in the open state, under the action of the low-level signal provided by the second light-emitting control line EM1, the second light-emitting control transistor T6 and the first control transistor T8 are open, and under the action of the low-level signal provided by the first reset control line RST1, the first reset transistor T1 is open. The first reference voltage signal provided by the first reference voltage line REF1 is written into the second node N2 through the conductive first control transistor T8, and the voltage of the second node N2 is the first reference voltage Vref1. The first initial voltage signal provided by the first initial voltage line INIT1 is written into the fifth node N5 through the conductive first reset transistor T1, and the voltage of the fifth node N5 is the first initial voltage Vinit1, so as to reset the first electrode of the light-emitting element EL; at the same time, the first initial voltage of the fifth node N5 can be provided to the first node N1 through the conductive second light-emitting control transistor T6 and the compensation transistor T2, so that the first node N1 is reset to the first initial voltage Vinit1, that is, the reset refresh process of the control electrode of the driving transistor T3 is realized, which can improve the residual image problem, and at the same time, the driving transistor T3 is in the open state in response to the control of the first initial voltage Vinit1 provided by the first node N1, and the fourth node N4 and the third node N3 are connected, and the voltage of the third node N3 is refreshed to Vinit1-Vth.

[0076] Between the second stage t12 and the third stage t13 of the current frame, the second light-emitting control signal provided by the second light-emitting control line EM1 first remains a low-level signal and then jumps to a high-level signal, the first reset signal provided by the first reset control line RST1 jumps to a high-level signal, and the remaining signals remain in the state of the second stage t12.

[0077] The third stage t13 can also be referred to as a data writing stage. In the third stage t13 of the current frame, the first scan signal provided by the first scan line GL1 remains low, the second scan signal provided by the second scan line GL2 jumps to low, and the first light-emitting control line EM2, the second light-emitting control line EM1, the first reset control line RST1 and the second reset control line RST2 all output high-level signals.

[0078] Under the action of the continuous low-level signal provided by the first scan line GL1, the compensation transistor T2 and the second control transistor T9 remain in the open state, under the action of the low-level signal provided by the second scan line GL2, the data writing transistor T7 is open. The data signal provided by the data line DL is written into the second node N2 through the conductive data writing transistor T7, and the voltage of the second node N2 is Vdata.

[0079] Between the third stage t13 and the fourth stage t14 of the current frame, the second scan signal provided by the second scan line GL2 jumps to high level, and the rest of the signals remain the state of the third stage t13.

[0080] The fourth stage t14 can also be referred to as a threshold compensation stage. In the fourth stage t14 of the current frame, the first scan signal provided by the first scan line GL1 remains at low level, the first light-emitting control signal provided by the first light-emitting control line EM2 jumps to low level, and the second light-emitting control line EM1, the second scan line GL2, the first reset control line RST1, and the second reset control line RST2 all maintain output of high level signals.

[0081] Under the action of the low level signal provided by the first scan line GL1, the compensation transistor T2 and the second control transistor T9 remain in an open state, and under the action of the low level signal provided by the first light-emitting control line EM2, the first light-emitting control transistor T5 is turned on. The first node N1 is in communication with the fourth node N4 through the turned-on compensation transistor T2. Since the second control transistor T9 remains in an open state, the first reference voltage signal provided by the first reference voltage line REF1 can be provided to the sixth node N6 through the turned-on second control transistor T9, and the voltage of the sixth node N6 is maintained at the first reference voltage Vref1 (the second control transistor T9 remains in an open state from the first stage t11 to the fourth stage t14, and the voltage of the sixth node N6 is maintained at the first reference voltage Vref1). The first power signal provided by the first power supply line VDD is provided to the third node N3 through the turned-on first light-emitting control transistor T5. In this stage, the driving transistor T3 is turned on, and the driving transistor T3 is threshold compensated by using the first power signal provided by the first power supply line VDD, so as to write the threshold voltage Vth of the driving transistor T3 into the first node N1, and the voltage of the first node N1 is Vdd+Vth, where Vdd is the first power voltage of the first power signal provided by the first power supply line VDD.

[0082] In the embodiments of the present disclosure, by placing the data writing stage before the threshold compensation stage, the residual image problem can be improved, and the reason is as follows: after the first node N1 is reset to the first initial voltage Vinit1, if threshold compensation is performed first, the voltage of the first node N1 will change from the first initial voltage Vinit1 to Vdd+Vth, which is equivalent to that the reset time of the first node N1 is shortened; if data writing is performed first, the voltage of the first node N1 remains unchanged at the first initial voltage Vinit1, which is equivalent to that the reset time of the first node N1 is lengthened, and the longer the reset time, the more conducive to improving the residual image problem.

[0083] Between the fourth stage t14 and the fifth stage t15 of the current frame, the first emission control signal provided by the first emission control line EM2 jumps to a high level signal, the first scan signal provided by the first scan line GL1 first keeps a low level signal, and then jumps to a high level signal, and the rest of the signals keep the state of the fourth stage t14.

[0084] The fifth stage t15 can also be referred to as a third reset stage (i.e., a second refresh stage). In the fifth stage t15 of the current frame, the first reset signal provided by the first reset control line RST1 jumps to a low level, the second reset signal provided by the second reset control line RST2 jumps to a low level, and the first emission control line EM2, the second emission control line EM1, the first scan line GL1 and the second scan line GL2 all keep outputting a high level signal.

[0085] Under the action of the low level signal provided by the first reset control line RST1, the first reset transistor T1 is turned on. Under the action of the low level signal provided by the second reset control line RST2, the second reset transistor T4 is turned on. The first initial voltage signal provided by the first initial voltage line INIT1 is written into the fifth node N5 through the turned-on first reset transistor T1, and the voltage of the fifth node N5 is the first initial voltage Vinit1. The second reference voltage signal provided by the second reference voltage line REF2 is provided to the third node N3 through the turned-on second reset transistor T4, so that the third node N3 is reset to the second reference voltage Vref2.

[0086] Between the fifth stage t15 and the sixth stage t16 of the current frame, the first emission control signal provided by the first emission control line EM2 jumps to a low level signal, the first reset signal provided by the first reset control line RST1 jumps to a high level, the second reset signal provided by the second reset control line RST2 jumps to a high level, and the rest of the signals keep the state of the fifth stage t15.

[0087] The sixth stage t16 can also be referred to as an emission stage. In the sixth stage t16 of the current frame, the first emission control signal provided by the first emission control line EM2 keeps outputting a low level signal, the second emission control signal provided by the second emission control line EM1 jumps to a low level signal, the first reset control line RST1, the second reset control line RST2, the first scan line GL1 and the second scan line GL2 all keep outputting a high level signal.

[0088] Under the action of the low-level signal provided by the second light-emitting control line EM1, the second light-emitting control transistor T6 and the first control transistor T8 are turned on, and the voltage of the second node N2 remains the first reference voltage Vref1. Under the action of the low-level signal provided by the first light-emitting control line EM2, the first light-emitting control transistor T5 is turned on. The compensation transistor T2, the second control transistor T9, the data writing transistor T7, the first reset transistor T1 and the second reset transistor T4 are all turned off. In this phase, the driving transistor T3 is turned on. The first node N1 can record the compensation information of the data voltage and the threshold voltage at the same time. The second control transistor T9 is turned off, and the sixth node N6 is floating. The data signal written into the second node N2 in the data writing phase can be coupled to the first node N1 through the second capacitor C2 and the first capacitor C1, and the voltage of the first node N1 is Vdd+Vth+Vref1-Vdata, wherein Vdata is the data voltage. The gate-source voltage difference Vgs of the driving transistor T3 is Vdd+Vth+Vref1-Vdata-Vdd=Vth+Vref1-Vdata. In the driving process of the pixel circuit, the driving current flowing through the driving transistor T3 is determined by the gate-source voltage difference thereof. Therefore, the driving current of the driving transistor T3 is: Id=0.5×K×(Vgs-Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2 =0.5×K×(Vref1-Vdata) 2 .

[0089] wherein K is a constant.

[0090] In this example, the driving signal output by the driving transistor T3 is irrelevant to the threshold voltage Vth of the driving transistor T3, which can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring the uniformity of display brightness and improving the display effect.

[0091] FIG. 7 is another structural schematic diagram of the pixel circuit of at least one embodiment of the present disclosure. In some examples, as shown in FIG. 7, the pixel circuit of this example can include a driving sub-circuit 21, a data writing sub-circuit 22, a compensation sub-circuit 23, a first coupling sub-circuit 241, a second coupling sub-circuit 242, a first control sub-circuit 25, a first light-emitting control sub-circuit 26, a second light-emitting control sub-circuit 27, a first reset sub-circuit 28 and a second reset sub-circuit 29. In this embodiment, the first coupling sub-circuit 241 is connected with the first node N1 and the second node N2 respectively, and the second coupling sub-circuit 242 is connected with the second node N2 and the first power supply line VDD respectively. The remaining structures of the pixel circuit of this example can be referred to the description of the foregoing embodiments, and thus will not be described here again.

[0092] FIG. 8 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 8, the driving sub-circuit 21 can include a driving transistor T3; the data writing sub-circuit 22 can include a data writing transistor T7; the compensation sub-circuit 23 can include a compensation transistor T2; the first coupling sub-circuit 241 can include a first capacitor C1; the second coupling sub-circuit 242 can include a second capacitor C2; the first control sub-circuit 25 can include a first control transistor T8; the first light emitting control sub-circuit 26 can include a first light emitting control transistor T5; the second light emitting control sub-circuit 27 can include a second light emitting control transistor T6; the first reset sub-circuit 28 can include a first reset transistor T1; and the second reset sub-circuit 29 can include a second reset transistor T4.

[0093] In some examples, as shown in FIG. 8, a gate of the driving transistor T3 is coupled with the first node N1, a first electrode of the driving transistor T3 is coupled with the third node N3, and a second electrode of the driving transistor T3 is coupled with the fourth node T4. A gate of the compensation transistor T2 is coupled with the first scan line GL1, a first electrode of the compensation transistor T2 is coupled with the fourth node N4, and a second electrode of the compensation transistor T2 is coupled with the first node N1. A gate of the data write transistor T7 is coupled with the second scan line GL2, a first electrode of the data write transistor T7 is coupled with the data line DL, and a second electrode of the data write transistor T7 is coupled with the second node N2. A first plate of the first capacitor C1 is coupled with the first node N1, and a second plate of the first capacitor C1 is coupled with the second node N2. A first plate of the second capacitor C2 is coupled with the second node N2, and a second plate of the second capacitor C2 is coupled with the first power supply line VDD. A gate of the first control transistor T8 is coupled with the first emission control line EM1, a first electrode of the first control transistor T8 is coupled with the first reference voltage line REF1, and a second electrode of the first control transistor T8 is coupled with the second node N2. A gate of the first emission control transistor T5 is coupled with the first emission control line EM2, a first electrode of the first emission control transistor T5 is coupled with the first power supply line VDD, and a second electrode of the first emission control transistor T5 is coupled with the third node N3. A gate of the second emission control transistor T6 is coupled with the second emission control line EM1, a first electrode of the second emission control transistor T6 is coupled with the fourth node N4, and a second electrode of the second emission control transistor T6 is coupled with the fifth node N5. A gate of the first reset transistor T1 is coupled with the first reset control line RST1, a first electrode of the first reset transistor T1 is coupled with the first initial voltage line INIT1, and a second electrode of the first reset transistor T1 is coupled with the fifth node N5. A gate of the second reset transistor T4 is coupled with the second reset control line RST2, a first electrode of the second reset transistor T4 is coupled with the second reference voltage line REF2, and a second electrode of the second reset transistor T4 is coupled with the third node N3. A first electrode of the light emitting element EL is coupled with the fifth node N5, and a second electrode of the light emitting element EL is coupled with the second power supply line VSS.

[0094] In some examples, the first node N1 is a connection point of the first capacitor C1, the compensation transistor T2, and the driving transistor T3. The second node N2 is a connection point of the first capacitor C1, the second capacitor C2, the data write transistor T7, and the first control transistor T8. The third node N3 is a connection point of the first emission control transistor T5, the second reset transistor T4, and the driving transistor T3. The fourth node N4 is a connection point of the compensation transistor T2, the driving transistor T3, and the second emission control transistor T6. The fifth node N5 is a connection point of the second emission control transistor T6, the first reset transistor T1, and the light emitting element EL.

[0095] FIG. 8 shows an exemplary structure of the driving sub-circuit 21, the data writing sub-circuit 22, the compensation sub-circuit 23, the first coupling sub-circuit 241, the second coupling sub-circuit 242, the first control sub-circuit 25, the first light emitting control sub-circuit 26, the second light emitting control sub-circuit 27, the first reset sub-circuit 28 and the second reset sub-circuit 29. It is easy for those skilled in the art to understand that the implementation of the above sub-circuits is not limited thereto as long as the functions thereof can be realized.

[0096] In some examples, as shown in FIG. 8, the first reset transistor T1, the compensation transistor T2, the driving transistor T3, the second reset transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the data writing transistor T7 and the first control transistor T8 can be P-type thin film transistors, for example, low temperature poly-silicon thin film transistors can be adopted. The active layer of the low temperature poly-silicon thin film transistor can adopt low temperature poly-silicon (LTPS, Low Temperature Poly-Silicon). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging.

[0097] FIG. 9 is a working timing diagram of the pixel circuit shown in FIG. 8. As shown in FIG. 8, the pixel circuit of the present example can include 8 transistors (i.e., transistors T1-T8), 2 capacitor units (i.e., the first capacitor C1 and the second capacitor C2), 10 input terminals (i.e., the data line DL, the first scan line GL1, the second scan line GL2, the first light emitting control line EM2, the second light emitting control line EM1, the first reset control line RST1, the second reset control line RST2, the first reference voltage line REF1, the second reference voltage line REF2 and the first initial voltage line INIT1), 2 power terminals (i.e., the first power line VDD and the second power line VSS).

[0098] In some examples, as shown in FIG. 9, in a frame period, the working process of the pixel circuit can include a first stage t21 to a sixth stage t26.

[0099] Before the current frame is displayed, i.e. before the first stage t21 of the current frame is displayed, the output of the first light-emitting control line EM2 is set to a low-level signal, i.e. the first light-emitting control signal provided by the first light-emitting control line EM2 is a low-level signal, the first light-emitting control transistor T5 is in an open state under the action of the first light-emitting control signal, the output of the second light-emitting control line EM1 is set to a low-level signal, i.e. the second light-emitting control signal provided by the second light-emitting control line EM1 is a low-level signal, the second light-emitting control transistor T6 is in an open state under the action of the second light-emitting control signal. At the same time, the outputs of the first scan line GL1, the second scan line GL2, the first reset control line RST1 and the second reset control line RST2 are all set to high-level signals, and the corresponding controlled transistors are all in a closed state, and the light-emitting device EL is in a previous frame light-emitting display stage of the current frame.

[0100] Then, the outputs of the first light-emitting control line EM2 and the second light-emitting control line EM1 are both set to high-level signals, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both in a closed state, and each node is in a floating state. The display of the previous frame ends.

[0101] The first stage t21 can also be referred to as a first reset stage. In the first stage t21 of the current frame, the first scan signal provided by the first scan line GL1 jumps to a low level, the second reset signal provided by the second reset control line RST2 is first maintained at a high level for a pixel row scanning time and then jumps to a low level, and the second scan line GL2, the first reset control line RST1, the first light-emitting control line EM2 and the second light-emitting control line EM1 all maintain an output high-level signal.

[0102] Under the action of the low-level signal provided by the first scan line GL1, the compensation transistor T2 is opened, and under the action of the low-level signal provided by the second reset control line RST2, the second reset transistor T4 is opened. The second reference voltage signal provided by the second reference voltage line REF2 can be provided to the third node N3 through the conductive second reset transistor T4, so that the third node N3 is reset to the second reference voltage Vref2, to refresh the bias voltage before compensating the threshold voltage Vth of the driving transistor T3, and the voltage of the first node N1 is refreshed to Vref2+Vth, wherein Vth is the threshold voltage of the driving transistor T3, so that the hysteresis level of the driving transistor T3 can be effectively improved.

[0103] In the transition stage between the first stage t21 and the second stage t22, the second reset signal provided by the second reset control line RST2 jumps to a high level, the first reset signal provided by the first reset control line RST1 is first maintained at a high level for a pixel row scanning time and then jumps to a low level, and the remaining signals maintain the state of the first stage t21.

[0104] The second stage t22 can also be referred to as a second reset stage. In the second stage t22 of the current frame, the first scan signal provided by the first scan line GL1 remains at a low level, the second emission control signal provided by the second emission control line EM1 jumps to a low level, the first reset signal provided by the first reset control line RST1 remains at a low level, and the first emission control line EM2, the second scan line GL2, and the second reset control line RST2 all output high level signals.

[0105] Under the action of the low level signal provided by the first scan line GL1, the compensation transistor T2 remains in an open state. Under the action of the low level signal provided by the second emission control line EM1, the second emission control transistor T6 and the first control transistor T8 are open. Under the action of the low level signal provided by the first reset control line RST1, the first reset transistor T1 is open. The first reference voltage signal provided by the first reference voltage line REF1 is written to the second node N2 through the open first control transistor T8, and the voltage of the second node N2 is the first reference voltage Vref1. The first initial voltage signal provided by the first initial voltage line INIT1 is written to the fifth node N5 through the open first reset transistor T1, and the voltage of the fifth node N5 is the first initial voltage Vinit1, so as to reset the first electrode of the light emitting element EL. At the same time, the first initial voltage of the fifth node N5 can be provided to the first node N1 through the open second emission control transistor T6 and the compensation transistor T2, so that the first node N1 is reset to the first initial voltage Vinit1, that is, the reset refresh process of the control electrode of the driving transistor T3 is realized. At the same time, the driving transistor T3 is in an open state in response to the control of the first initial voltage Vinit1 provided by the first node N1, and the third node N3 and the fourth node N4 are connected, and the voltage of the third node N3 is refreshed to Vinit1-Vth.

[0106] Between the second stage t22 and the third stage t23 of the current frame, the second emission control signal provided by the second emission control line EM1 first remains a low level signal and then jumps to a high level signal. The first reset signal provided by the first reset control line RST1 jumps to a high level signal, and the remaining signals remain in the state of the second stage t22.

[0107] The third stage t23 can also be referred to as a data writing stage. In the third stage t23 of the current frame, the first scan signal provided by the first scan line GL1 remains at a low level, the second scan signal provided by the second scan line GL2 jumps to a low level, and the first emission control line EM2, the second emission control line EM1, the first reset control line RST1, and the second reset control line RST2 all output high level signals.

[0108] Under the action of the low-level signal provided by the first scan line GL1, the compensation transistor T2 keeps open state, and under the action of the low-level signal provided by the second scan line GL2, the data write transistor T7 is open. The data signal provided by the data line DL is written into the second node N2 through the open data write transistor T7, and the voltage of the second node N2 is Vdata.

[0109] Between the third stage t23 and the fourth stage t24 of the current frame, the second scan signal provided by the second scan line GL2 jumps to high level, and the rest of the signals remain the state of the third stage t23.

[0110] The fourth stage t24 can also be referred to as a threshold compensation stage. In the fourth stage t24 of the current frame, the first scan signal provided by the first scan line GL1 remains low level, the first emission control signal provided by the first emission control line EM2 jumps to low level, and the second emission control line EM1, the second scan line GL2, the first reset control line RST1 and the second reset control line RST2 all maintain output of high level signal.

[0111] Under the action of the low-level signal provided by the first scan line GL1, the compensation transistor T2 keeps open state, and under the action of the low-level signal provided by the first emission control line EM2, the first emission control transistor T5 is open. The first node N1 is in communication with the fourth node N4 through the open compensation transistor T2. The first power signal provided by the first power line VDD is provided to the third node N3 through the open first emission control transistor T5. In this stage, the driving transistor T3 is open, and the threshold voltage Vth of the driving transistor T3 is written into the first node N1 by using the first power signal provided by the first power line VDD to perform threshold compensation on the driving transistor T3, and the voltage of the first node N1 is Vdd+Vth, Vdd being the first power voltage of the first power signal provided by the first power line VDD.

[0112] Between the fourth stage t24 and the fifth stage t25 of the current frame, the first emission control signal provided by the first emission control line EM2 jumps to high level signal, the first scan signal provided by the first scan line GL1 remains low level signal first and then jumps to high level signal, and the rest of the signals remain the state of the fourth stage t24.

[0113] The fifth stage t25 can also be referred to as a third reset stage (i.e. a second refresh stage). In the fifth stage t25 of the current frame, the first reset signal provided by the first reset control line RST1 jumps to low level, the second reset signal provided by the second reset control line RST2 jumps to low level, and the first emission control line EM2, the second emission control line EM1, the first scan line GL1 and the second scan line GL2 all maintain output of high level signal.

[0114] Under the action of the low-level signal provided by the first reset control line RST1, the first reset transistor T1 is turned on. Under the action of the low-level signal provided by the second reset control line RST2, the second reset transistor T4 is turned on. The first initial voltage signal provided by the first initial voltage line INIT1 is written into the fifth node N5 through the turned-on first reset transistor T1, and the voltage of the fifth node N5 is the first initial voltage Vinit1. The second reference voltage signal provided by the second reference voltage line REF2 is provided to the third node N3 through the turned-on second reset transistor T4, so that the third node N3 is reset to the second reference voltage Vref2.

[0115] Between the fifth stage t25 and the sixth stage t26 of the current frame, the first emission control signal provided by the first emission control line EM2 jumps to a low-level signal, the first reset signal provided by the first reset control line RST1 jumps to a high level, the second reset signal provided by the second reset control line RST2 jumps to a high level, and the rest of the signals remain in the state of the fifth stage t25.

[0116] The sixth stage t26 can also be referred to as an emission stage. In the sixth stage t26 of the current frame, the first emission control signal provided by the first emission control line EM2 remains output as a low-level signal, the second emission control signal provided by the second emission control line EM1 jumps to a low-level signal, and the first reset control line RST1, the second reset control line RST2, the first scan line GL1 and the second scan line GL2 all remain output as high-level signals.

[0117] Under the action of the low-level signal provided by the second emission control line EM1, the second emission control transistor T6 and the first control transistor T8 are turned on, and the voltage of the second node N2 is reset to the first reference voltage Vref1. Under the action of the low-level signal provided by the first emission control line EM2, the first emission control transistor T5 is turned on. The compensation transistor T2, the second control transistor T9, the data write transistor T7, the first reset transistor T1 and the second reset transistor T4 are all turned off. In this stage, the driving transistor T3 is turned on. The first node N1 can record the compensation information of the data voltage and the threshold voltage at the same time. The voltage of the first node N1 is Vdd+Vth+Vref1-Vdata, wherein Vdata is the data voltage. The gate-source voltage difference Vgs of the driving transistor T3 is Vdd+Vth+Vref1-Vdata-Vdd=Vth+Vref1-Vdata. In the driving process of the pixel circuit, the driving current flowing through the driving transistor T3 is determined by the gate-source voltage difference thereof. Therefore, the driving current of the driving transistor T3 is: Id=0.5×K×(Vgs-Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2= 0.5 x K x (Vref1 - Vdata) 2 .

[0118] wherein K is a constant.

[0119] In the example, the driving signal output by the driving transistor T3 is irrelevant to the threshold voltage Vth of the driving transistor T3, and the influence of the threshold voltage of the driving transistor on the driving signal can be eliminated, so that the display brightness is uniform and the display effect is improved.

[0120] FIG. 10 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 10, the pixel circuit of the example can include a driving sub-circuit 21, a data writing sub-circuit 22, a compensation sub-circuit 23, a first coupling sub-circuit 241, a second coupling sub-circuit 242, a first control sub-circuit 25, a first light emitting control sub-circuit 26, a second light emitting control sub-circuit 27, a first reset sub-circuit 28, a second reset sub-circuit 29, and a second control sub-circuit 30.

[0121] In some examples, as shown in FIG. 10, the first control sub-circuit 25 is connected with the third reset control line RST3, the first reference voltage line REF1, and the second node N2, respectively. The pixel circuit further includes a second refresh stage after the threshold compensation stage and the data writing stage and before the light emitting stage; in the second refresh stage, the first control sub-circuit 25 writes the first reference voltage of the first reference voltage line REF1 into the second node N2 under the control of the third reset control line RST3. In the example, the potential of the second node N2 is controlled by the third reset control signal provided by the third reset control line RST3, and the leakage of the second node can be improved.

[0122] In some examples, as shown in FIG. 10, the second control sub-circuit 30 is connected with the first scan line GL1, the sixth node N6, and the first power supply line VDD, respectively. In the first refresh stage, the data writing stage, and the threshold compensation stage, the second control sub-circuit 30 is always in the on state under the control of the first scan line GL1, and the voltage of the sixth node N6 is maintained as the first power voltage provided by the first power supply line VDD.

[0123] In some examples, as shown in FIG. 10, the first reset sub-circuit 28 is connected with the first reset control line RST1, the first initial voltage line INIT1, and the fifth node N5, and the second reset sub-circuit 29 is connected with the second reset control line RST2, the first reference voltage line REF1, and the third node N3.

[0124] In the embodiment, the first reset voltage signal can be less than the first power voltage signal, and the first reference voltage signal can be greater than the first power voltage signal. For example, the threshold voltage of the drive transistor can be -3V, the first reset voltage can be -2V, the first reference voltage can be 7V, and the first power voltage can be 4.6V. However, the present disclosure is not limited thereto.

[0125] In some examples, the first refresh stage can include a first reset stage and a second reset stage performed in sequence.

[0126] In the first reset stage, the first reset sub-circuit 28 is turned on under the control of the first reset control line RST1, the second light-emitting control sub-circuit 27 is turned on under the control of the first light-emitting control line EM1, and the first initial voltage signal output by the first initial voltage line INIT1 is provided to the first node N1 through the first reset sub-circuit 28, the second light-emitting control sub-circuit 27, and the compensation sub-circuit 23, so as to reset the first node N1.

[0127] In the second reset stage, the second reset sub-circuit 29 is turned on under the control of the second reset control line RST2, and the first reference voltage signal output by the first reference voltage line REF1 is provided to the first node N1 through the second reset sub-circuit 29, the drive sub-circuit 21, and the compensation sub-circuit 23, so as to reset the first node N1.

[0128] The embodiment of the present disclosure sets two reset stages (the first reset stage and the second reset stage) to strongly bias the drive transistor, which is beneficial to improve the residual image problem.

[0129] The remaining structure of the pixel circuit of the present example can refer to the description of the foregoing embodiments, and thus will not be described here again.

[0130] FIG. 11 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 11, the drive sub-circuit 21 can include a drive transistor T3, the data writing sub-circuit 22 can include a data writing transistor T7, the compensation sub-circuit 23 can include a compensation transistor T2, the first coupling sub-circuit 241 can include a first capacitor C1, the second coupling sub-circuit 242 can include a second capacitor C2, the first control sub-circuit 25 can include a first control transistor T8, the first light-emitting control sub-circuit 26 can include a first light-emitting control transistor T5, the second light-emitting control sub-circuit 27 can include a second light-emitting control transistor T6, the first reset sub-circuit 28 can include a first reset transistor T1, the second reset sub-circuit 29 can include a second reset transistor T4, and the second control sub-circuit 30 can include a second control transistor T9.

[0131] In some examples, as shown in FIG. 11, a gate of the drive transistor T3 is coupled with the first node N1, a first electrode of the drive transistor T3 is coupled with the third node N3, and a second electrode of the drive transistor T3 is coupled with the fourth node T4. A gate of the compensation transistor T2 is coupled with the first scan line GL1, a first electrode of the compensation transistor T2 is coupled with the fourth node N4, and a second electrode of the compensation transistor T2 is coupled with the first node N1. A gate of the data write transistor T7 is coupled with the second scan line GL2, a first electrode of the data write transistor T7 is coupled with the data line DL, and a second electrode of the data write transistor T7 is coupled with the second node N2. A first plate of the first capacitor C1 is coupled with the first node N1, and a second plate of the first capacitor C1 is coupled with the sixth node N6. A first plate of the second capacitor C2 is coupled with the sixth node N6, and a second plate of the second capacitor C2 is coupled with the second node N2. A gate of the first control transistor T8 is coupled with the third reset control line RST3, a first electrode of the first control transistor T8 is coupled with the first reference voltage line REF1, and a second electrode of the first control transistor T8 is coupled with the second node N2. A gate of the first emission control transistor T5 is coupled with the first emission control line EM2, a first electrode of the first emission control transistor T5 is coupled with the first power supply line VDD, and a second electrode of the first emission control transistor T5 is coupled with the third node N3. A gate of the second emission control transistor T6 is coupled with the second emission control line EM1, a first electrode of the second emission control transistor T6 is coupled with the fourth node N4, and a second electrode of the second emission control transistor T6 is coupled with the fifth node N5. A gate of the first reset transistor T1 is coupled with the first reset control line RST1, a first electrode of the first reset transistor T1 is coupled with the first initial voltage line INIT1, and a second electrode of the first reset transistor T1 is coupled with the fifth node N5. A gate of the second reset transistor T4 is coupled with the second reset control line RST2, a first electrode of the second reset transistor T4 is coupled with the first reference voltage line REF1, and a second electrode of the second reset transistor T4 is coupled with the third node N3. A gate of the second control transistor T9 is coupled with the first scan line GL1, a first electrode of the second control transistor T9 is coupled with the first power supply line VDD, and a second electrode of the second control transistor T9 is coupled with the sixth node N6. A first electrode of the light emitting element EL is coupled with the fifth node N5, and a second electrode of the light emitting element EL is coupled with the second power supply line VSS.

[0132] In some examples, the first node N1 is a connection point of the first capacitor C1, the compensation transistor T2 and the driving transistor T3. The second node N2 is a connection point of the second capacitor C2, the data write transistor T7 and the first control transistor T8. The third node N3 is a connection point of the first light emitting control transistor T5, the second reset transistor T4 and the driving transistor T3. The fourth node N4 is a connection point of the compensation transistor T2, the driving transistor T3 and the second light emitting control transistor T6. The fifth node N5 is a connection point of the second light emitting control transistor T6, the first reset transistor T1 and the light emitting element EL. The sixth node N6 is a connection point of the first capacitor C1, the second capacitor C2 and the second control transistor T9.

[0133] FIG. 11 shows an exemplary structure of the driving sub-circuit 21, the data write sub-circuit 22, the compensation sub-circuit 23, the first coupling sub-circuit 241, the second coupling sub-circuit 242, the first control sub-circuit 25, the first light emitting control sub-circuit 26, the second light emitting control sub-circuit 27, the first reset sub-circuit 28, the second reset sub-circuit 29 and the second control sub-circuit 30. It is easy for those skilled in the art to understand that the implementation of the above-mentioned sub-circuits is not limited thereto as long as the functions thereof can be realized.

[0134] In some examples, as shown in FIG. 11, the first reset transistor T1, the compensation transistor T2, the driving transistor T3, the second reset transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the data write transistor T7, the first control transistor T8 and the second control transistor T9 can be P-type thin film transistors, for example, low temperature poly-silicon thin film transistors can be adopted. The active layer of the low temperature poly-silicon thin film transistor can adopt low temperature poly-silicon (LTPS, Low Temperature Poly-Silicon). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging.

[0135] FIG. 12 is a working timing diagram of the pixel circuit shown in FIG. 11. As shown in FIG. 11, the pixel circuit of the present example can include 9 transistors (i.e., transistors T1 to T9), 2 capacitor units (i.e., the first capacitor C1 and the second capacitor C2), 10 input terminals (i.e., the data line DL, the first scan line GL1, the second scan line GL2, the first light emitting control line EM2, the second light emitting control line EM1, the first reset control line RST1, the second reset control line RST2, the third reset control line RST3, the first reference voltage line REF1 and the first initial voltage line INIT1), and 2 power terminals (i.e., the first power line VDD and the second power line VSS).

[0136] In some examples, as shown in FIG. 12, in a frame time period, the working process of the pixel circuit can include a first stage t31 to a sixth stage t36.

[0137] Before the current frame is displayed, specifically before the first stage t31 of the current frame display, the output of the first light-emitting control line EM2 is set to a low-level signal. This means the first light-emitting control signal provided by EM2 is a low-level signal, and the first light-emitting control transistor T5 is turned on under the influence of this signal. The output of the second light-emitting control line EM1 is also set to a low-level signal, meaning the second light-emitting control signal provided by EM1 is a low-level signal, and the second light-emitting control transistor T6 is turned on under the influence of this signal. Simultaneously, the output of the third reset control line RST3 is set to a low-level signal, and the first control transistor T8 is turned on under the influence of this reset signal. This resets the second node N2 to the first reference voltage Vref1. The outputs of the first scan line GL1, the second scan line GL2, the first reset control line RST1, and the second reset control line RST2 are all set to high-level signals, and the corresponding controlled transistors are all turned off. The light-emitting device EL is in the previous frame's light-emitting display stage.

[0138] The first stage t31 can also be called the first reset stage. In the first stage t31 of the current frame, the outputs of the third reset control line RST3 and the second light emission control line EM1 are continuously low-level signals. The output of the first reset control line RST1 jumps to a low level. The first scan signal provided by the first scan line GL1 first maintains a high level for one pixel line scan time, and then jumps to a low level. The second scan line GL2, the second reset control line RST2, and the first light emission control line EM2 all output high-level signals.

[0139] Under the action of the low-level signal provided by the first scan line GL1, the compensation transistor T2 and the second control transistor T9 are turned on, under the action of the low-level signal provided by the first reset control line RST1, the first reset transistor T1 is turned on, under the action of the low-level signal provided by the second light-emitting control line EM1, the second light-emitting control transistor T6 remains in the turned-on state, and under the action of the low-level signal provided by the third reset control line RST3, the first control transistor T8 remains in the turned-on state. The first reference voltage signal provided by the first reference voltage line REF1 is written into the second node N2 through the turned-on first control transistor T8, and the voltage of the second node N2 is the first reference voltage Vref1. The first initial voltage signal provided by the first initial voltage line INIT1 is written into the fifth node N5 through the turned-on first reset transistor T1, and the voltage of the fifth node N5 is the first initial voltage Vinit1, so as to reset the first electrode of the light-emitting element EL; at the same time, the first initial voltage of the fifth node N5 can be provided to the first node N1 through the turned-on second light-emitting control transistor T6 and the compensation transistor T2, so that the first node N1 is reset to the first initial voltage Vinit1, that is, the reset refresh process of the control electrode of the driving transistor T3 is realized, and at the same time, the driving transistor T3 is in the turned-on state in response to the control of the first initial voltage Vinit1 provided by the first node N1, and the fourth node N4 and the third node N3 are connected, and the voltage of the third node N3 is refreshed to Vinit1-Vth.

[0140] The second stage t32 can also be referred to as a second reset stage. In the second stage t32 of the current frame, the third reset control line RST3 and the output of the first scan line GL1 continue to be low-level signals, the second reset signal provided by the second reset control line RST2 jumps to a low level, and the first reset control line RST1, the second scan line GL2, the first light-emitting control line EM2, and the second light-emitting control line EM1 all output high-level signals.

[0141] Under the action of the low-level signal provided by the first scan line GL1, the compensation transistor T2 and the second control transistor T9 remain in the open state, under the action of the low-level signal provided by the second reset control line RST2, the second reset transistor T4 is open, and under the action of the low-level signal provided by the third reset control line RST3, the first control transistor T8 remains in the open state. The first power supply signal provided by the first power supply line VDD can be provided to the sixth node N6 through the second control transistor T9, so that the sixth node N6 is reset to the first power supply voltage Vdd. The first reference voltage signal provided by the first reference voltage line REF1 can be provided to the third node N3 through the second reset transistor T4, so that the third node N3 is reset to the first reference voltage Vref1, and the voltage of the first node N1 is refreshed to Vref1+Vth, wherein Vth is the threshold voltage of the driving transistor T3, so that the hysteresis level of the driving transistor T3 can be effectively improved.

[0142] Between the second stage t32 and the third stage t33 of the current frame, the second reset signal provided by the second reset control line RST2 jumps to a high-level signal, and the remaining signals remain in the state of the second stage t32.

[0143] The third stage t33 can also be referred to as a threshold compensation stage. In the third stage t33 of the current frame, the output of the third reset control line RST3 and the first scan line GL1 continues to be a low-level signal, the first emission control signal provided by the first emission control line EM2 jumps to a low-level signal, and the second emission control line EM1, the second scan line GL2, the first reset control line RST1, and the second reset control line RST2 all remain to output a high-level signal.

[0144] Under the action of the low-level signal provided by the first scan line GL1, the compensation transistor T2 and the second control transistor T9 remain in the open state, under the action of the low-level signal provided by the second reset control line RST2, the second reset transistor T4 is open, and under the action of the low-level signal provided by the third reset control line RST3, the first control transistor T8 remains in the open state. The first power supply signal provided by the first power supply line VDD can be provided to the sixth node N6 through the second control transistor T9, so that the sixth node N6 is reset to the first power supply voltage Vdd. The first reference voltage signal provided by the first reference voltage line REF1 can be provided to the third node N3 through the second reset transistor T4, so that the third node N3 is reset to the first reference voltage Vref1, and the voltage of the first node N1 is refreshed to Vref1+Vth, wherein Vth is the threshold voltage of the driving transistor T3, so that the hysteresis level of the driving transistor T3 can be effectively improved.

[0145] Between the third stage t33 and the fourth stage t34 of the current frame, the first emission control signal provided by the first emission control line EM2 jumps to a high level signal, the third reset signal provided by the third reset control line RST3 jumps to a high level signal, and the rest of the signals remain in the state of the third stage t33.

[0146] The fourth stage t34 can also be referred to as a data writing stage. In the fourth stage t34 of the current frame, the first scan signal provided by the first scan line GL1 remains at a low level, the second scan signal provided by the second scan line GL2 jumps to a low level, and the first emission control line EM2, the second emission control line EM1, the first reset control line RST1, the second reset control line RST2, and the third reset control line RST3 all output high level signals.

[0147] Under the action of the low level signal provided by the first scan line GL1, the compensation transistor T2 and the second control transistor T9 remain in an open state (the second control transistor T9 remains in an open state from the first stage t31 to the fourth stage t34, and the voltage of the sixth node N6 is maintained at the first power supply voltage Vdd). Under the action of the low level signal provided by the second scan line GL2, the data writing transistor T7 is turned on. The data signal provided by the data line DL is written to the second node N2 through the conductive data writing transistor T7, and the voltage of the second node N2 changes from Vref1 to Vdata.

[0148] Between the fourth stage t34 and the fifth stage t35 of the current frame, the first scan signal provided by the first scan line GL1 remains at a low level signal and then jumps to a high level signal, the second scan signal provided by the second scan line GL2 jumps to a high level, the third reset signal provided by the third reset control line RST3 remains at a high level signal and then jumps to a low level signal, and the rest of the signals remain in the state of the fourth stage t34.

[0149] The fifth stage t35 can also be referred to as a third reset stage (i.e., a second refresh stage). In the fifth stage t35 of the current frame, the first emission control signal provided by the first emission control line EM2 jumps to a low level, the third reset signal provided by the third reset control line RST3 remains at a low level, and the second emission control line EM1, the first reset control line RST1, the second reset control line RST2, the first scan line GL1, and the second scan line GL2 all output high level signals.

[0150] Under the action of the low-level signal provided by the third reset control line RST3, the first control transistor T8 is turned on. Under the action of the low-level signal provided by the first emission control line EM2, the first emission control transistor T5 is turned on. The first power supply signal provided by the first power supply line VDD is written into the third node N3 through the turned-on first emission control transistor T5, and the voltage of the third node N3 is the first power supply voltage Vdd. The first reference voltage signal provided by the first reference voltage line REF1 is written into the second node N2 through the turned-on first control transistor T8, and the voltage of the second node N2 changes from Vdata to the first reference voltage Vref1. The second control transistor T9 is turned off, and the sixth node N6 is floating. The data signal written into the second node N2 in the data writing stage can be coupled to the first node N1 through the second capacitor C2 and the first capacitor C1, and the voltage of the first node N1 is refreshed to Vref1-Vdata+Vdd+Vth.

[0151] The sixth stage t36 can also be referred to as an emission stage. In the sixth stage t36 of the current frame, the first emission control signal provided by the first emission control line EM2 remains output as a low-level signal, the second emission control signal provided by the second emission control line EM1 jumps to a low-level signal, the third reset signal provided by the third reset control line RST3 remains output as a low-level signal, and the first reset control line RST1, the second reset control line RST2, the first scan line GL1 and the second scan line GL2 all remain output as high-level signals.

[0152] Under the action of the low-level signal provided by the third reset control line RST3, the first control transistor T8 remains in an open state. Under the action of the low-level signal provided by the second emission control line EM1, the second emission control transistor T6 is turned on. Under the action of the low-level signal provided by the first emission control line EM2, the first emission control transistor T5 is turned on. The compensation transistor T2, the second control transistor T9, the data writing transistor T7, the first reset transistor T1 and the second reset transistor T4 are all turned off. In this stage, the driving transistor T3 is turned on. The first node N1 can record the compensation information of the data voltage and the threshold voltage at the same time. The voltage of the first node N1 is Vdd+Vth+Vref1-Vdata, wherein Vdata is the data voltage. The gate-source voltage difference Vgs of the driving transistor T3 is Vdd+Vth+Vref1-Vdata-Vdd=Vth+Vref1-Vdata. In the driving process of the pixel circuit, the driving current flowing through the driving transistor T3 is determined by the gate-source voltage difference thereof. Therefore, the driving current of the driving transistor T3 is:

[0153] Id=0.5×K×(Vgs-Vth) 2 =0.5×K×(Vth+Vref1-Vdata-Vth) 2= 0.5 x K x (Vref1 - Vdata) 2 .

[0154] wherein K is a constant.

[0155] In this example, the driving signal output by the driving transistor T3 is irrelevant to the threshold voltage Vth of the driving transistor T3, and the influence of the threshold voltage of the driving transistor on the driving signal can be eliminated, thereby ensuring uniform display brightness and improving display effect.

[0156] FIGS. 13A and 13B are flowcharts of a driving method of a pixel circuit according to at least two embodiments of the present disclosure. The pixel circuit includes at least a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a coupling sub-circuit, and a first control sub-circuit. The driving sub-circuit is connected to a first node, a third node, and a fourth node. The compensation sub-circuit is connected to a first scan line, the first node, and the fourth node. The data writing sub-circuit is connected to a second scan line, a data line, and a second node. The coupling sub-circuit is connected to the first node and the second node. The first control sub-circuit is connected to the second node and a first reference voltage line.

[0157] In some examples, as shown in FIGS. 13A and 13B, the pixel circuit in this example includes at least a first refresh stage, a threshold compensation stage, and a data writing stage performed in sequence when driving, or at least a first refresh stage, a data writing stage, and a threshold compensation stage performed in sequence, and in the first refresh stage, the data writing stage, and the threshold compensation stage, the compensation sub-circuit is always in a conductive state under the control of the first scan line.

[0158] In some examples, the pixel circuit further includes a first light emitting control sub-circuit connected to a first light emitting control line, a first power supply line, and the third node. In the threshold compensation stage, the first light emitting control sub-circuit is turned on under the control of the first light emitting control line, and the threshold voltage of the driving sub-circuit is written to the first node through the first light emitting control sub-circuit, the driving sub-circuit, and the compensation sub-circuit.

[0159] In some examples, the pixel circuit further includes a second light emitting control sub-circuit connected to a second light emitting control line, the fourth node, and a fifth node connected to a first electrode of a light emitting element. The pixel circuit further includes a light emitting stage after the threshold compensation stage and the data writing stage when driving. In the light emitting stage, the first light emitting control sub-circuit is turned on under the control of the first light emitting control line, the second light emitting control sub-circuit is turned on under the control of the second light emitting control line, and the first power supply line provides a driving current to the first electrode of the light emitting element to drive the light emitting element to emit light.

[0160] In some examples, the coupling sub-circuit includes a first coupling sub-circuit and a second coupling sub-circuit, the first coupling sub-circuit is connected with the second node and a sixth node, the second coupling sub-circuit is connected with the sixth node and the first node, and the pixel circuit further includes a second control sub-circuit connected with the first scan line, the sixth node and a first reference voltage line; in the first refresh stage, the data writing stage and the threshold compensation stage, the second control sub-circuit is always in a conductive state under the control of the first scan line, and a voltage of the sixth node is maintained as a first reference voltage provided by the first reference voltage line.

[0161] In some examples, the coupling sub-circuit includes a first coupling sub-circuit and a second coupling sub-circuit, the first coupling sub-circuit is connected with the first node and the second node, and the second coupling sub-circuit is connected with the second node and a first power supply line.

[0162] In some examples, the pixel circuit further includes a first reset sub-circuit and a second reset sub-circuit, the first reset sub-circuit is connected with a first reset control line, a first initial voltage line and a fifth node, and the second reset sub-circuit is connected with a second reset control line, a first reference voltage line and a third node, the first refresh stage includes a first reset stage and a second reset stage performed in sequence; in the first reset stage, the second reset sub-circuit is turned on under the control of the second reset control line, a first reference voltage signal output by the first reference voltage line is provided to the first node through the second reset sub-circuit and the driving sub-circuit, and the first node is reset; in the second reset stage, the first reset sub-circuit is turned on under the control of the first reset control line, the second light-emitting control sub-circuit is turned on under the control of the second light-emitting control line, and a first initial voltage signal output by the first initial voltage line is provided to the first node through the first reset sub-circuit, the second light-emitting control sub-circuit and the compensation sub-circuit, and the first node is reset.

[0163] In some examples, the coupling sub-circuit includes a first coupling sub-circuit and a second coupling sub-circuit, the first coupling sub-circuit is connected with the first node and a sixth node, the second coupling sub-circuit is connected with the sixth node and the second node, and the pixel circuit further includes a second control sub-circuit connected with the first scan line, the sixth node and a first power supply line; in the first refresh stage, the data writing stage and the threshold compensation stage, the second control sub-circuit is always in a conductive state under the control of the first scan line, and a voltage of the sixth node is maintained as a first power supply voltage provided by the first power supply line.

[0164] In some examples, the pixel circuit further includes a first reset sub-circuit and a second reset sub-circuit, the first reset sub-circuit is connected with the first reset control line, the first initial voltage line and the fifth node, the second reset sub-circuit is connected with the second reset control line, the first reference voltage line and the third node, the first refresh stage includes a first reset stage and a second reset stage performed in sequence; in the first reset stage, the first reset sub-circuit is turned on under the control of the first reset control line, the second light-emitting control sub-circuit is turned on under the control of the first light-emitting control line, and the first initial voltage signal output by the first initial voltage line is provided to the first node through the first reset sub-circuit, the second light-emitting control sub-circuit and the compensation sub-circuit, so as to reset the first node; in the second reset stage, the second reset sub-circuit is turned on under the control of the second reset control line, the first reference voltage signal output by the first reference voltage line is provided to the first node through the second reset sub-circuit and the driving sub-circuit, so as to reset the first node.

[0165] The driving method of the pixel circuit of the present embodiment can refer to the description of the foregoing embodiments, and thus will not be described here in detail.

[0166] The present embodiment further provides a display substrate, including: a plurality of sub-pixels, at least one of the plurality of sub-pixels including a light-emitting element and a pixel circuit for driving the light-emitting element to emit light; the pixel circuit being the pixel circuit as described in the foregoing embodiments.

[0167] In some examples, the display substrate can be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device containing the display substrate can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. However, the present embodiment is not limited thereto.

[0168] In the description of the present specification, the description of the terms “one embodiment”, “some embodiments”, “an example” or “some examples” and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

[0169] Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary and are not to be construed as limiting the present application, and that changes, modifications, substitutions and variations can be made by those skilled in the art without departing from the scope of the present application.

Claims

1. A pixel circuit, comprising at least a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a coupling sub-circuit and a first control sub-circuit, the driving sub-circuit being connected with a first node, a third node and a fourth node, the compensation sub-circuit being connected with a first scan line, the first node and the fourth node, the data writing sub-circuit being connected with a second scan line, a data line and a second node, the coupling sub-circuit being connected with the first node and the second node, and the first control sub-circuit being connected with the second node and a first reference voltage line. The pixel circuit comprises at least a first refresh stage, a threshold compensation stage and a data writing stage in sequence, or at least a first refresh stage, a data writing stage and a threshold compensation stage in sequence, and in the first refresh stage, the data writing stage and the threshold compensation stage, the compensation sub-circuit is always in a conductive state under the control of the first scan line.

2. The pixel circuit of claim 1, wherein, The pixel circuit further comprises a first light emitting control sub-circuit, which is connected with a first light emitting control line, a first power supply line and the third node. In the threshold compensation stage, the first light emitting control sub-circuit is turned on under the control of the first light emitting control line, and the threshold voltage of the driving sub-circuit is written into the first node through the first light emitting control sub-circuit, the driving sub-circuit and the compensation sub-circuit.

3. The pixel circuit of claim 2, wherein, The pixel circuit further comprises a second light emitting control sub-circuit, which is connected with a second light emitting control line, the fourth node and a fifth node, and the fifth node is connected with a first electrode of a light emitting element. The pixel circuit further comprises a light emitting stage after the threshold compensation stage and the data writing stage, in which the first light emitting control sub-circuit is turned on under the control of the first light emitting control line, the second light emitting control sub-circuit is turned on under the control of the second light emitting control line, and the first power supply line provides a driving current to the first electrode of the light emitting element to drive the light emitting element to emit light.

4. The pixel circuit of claim 3, wherein, The coupling sub-circuit comprises a first coupling sub-circuit and a second coupling sub-circuit, the first coupling sub-circuit being connected with the first node and a sixth node, and the second coupling sub-circuit being connected with the sixth node and the second node, and the pixel circuit further comprises a second control sub-circuit, which is connected with the first scan line, the sixth node and the first reference voltage line, and in the first refresh stage, the data writing stage and the threshold compensation stage, the second control sub-circuit is always in a conductive state under the control of the first scan line, and the voltage of the sixth node is maintained as a first reference voltage provided by the first reference voltage line.

5. The pixel circuit of claim 3, wherein, The coupling sub-circuit comprises a first coupling sub-circuit and a second coupling sub-circuit, the first coupling sub-circuit being connected with the first node and the second node, and the second coupling sub-circuit being connected with the second node and a first power supply line.

6. The pixel circuit of claim 4 or 5, wherein, The pixel circuit further comprises a first reset sub-circuit and a second reset sub-circuit, the first reset sub-circuit is connected with a first reset control line, a first initial voltage line and a fifth node, the second reset sub-circuit is connected with a second reset control line, a second reference voltage line and a third node, and the first refresh stage comprises a first reset stage and a second reset stage in sequence. In the first reset stage, the second reset sub-circuit is turned on under the control of the second reset control line, and a second reference voltage signal output by the second reference voltage line is provided to the first node through the second reset sub-circuit and the driving sub-circuit to reset the first node; In the second reset stage, the first reset sub-circuit is turned on under the control of the first reset control line, the second light-emitting control sub-circuit is turned on under the control of the second light-emitting control line, and a first initial voltage signal output by the first initial voltage line is provided to the first node through the first reset sub-circuit, the second light-emitting control sub-circuit and the compensation sub-circuit to reset the first node.

7. The pixel circuit of claim 6, wherein, The first control sub-circuit is connected with the second light-emitting control line, and the first control sub-circuit writes a first reference voltage of the first reference voltage line into the second node under the control of the second light-emitting control line.

8. The pixel circuit of claim 3, wherein, The coupling sub-circuit comprises a first coupling sub-circuit and a second coupling sub-circuit, the first coupling sub-circuit is connected with the first node and a sixth node, the second coupling sub-circuit is connected with the sixth node and the second node, and the pixel circuit further comprises a second control sub-circuit, the second control sub-circuit is connected with the first scanning line, the sixth node and a first power supply line, and in the first refresh stage, the data writing stage and the threshold compensation stage, the second control sub-circuit is always in a turned-on state under the control of the first scanning line, and the voltage of the sixth node is maintained as a first power supply voltage provided by the first power supply line.

9. The pixel circuit of claim 8, wherein, The pixel circuit further comprises a first reset sub-circuit and a second reset sub-circuit, the first reset sub-circuit is connected with a first reset control line, a first initial voltage line and a fifth node, the second reset sub-circuit is connected with a second reset control line, a second reference voltage line and a third node, and the first refresh stage comprises a first reset stage and a second reset stage in sequence. In the first reset stage, the second reset sub-circuit is turned on under the control of the second reset control line, and a second reference voltage signal output by the second reference voltage line is provided to the first node through the second reset sub-circuit and the driving sub-circuit to reset the first node; In the second reset stage, the first reset sub-circuit is turned on under the control of the first reset control line, the second light-emitting control sub-circuit is turned on under the control of the second light-emitting control line, and a first initial voltage signal output by the first initial voltage line is provided to the first node through the first reset sub-circuit, the second light-emitting control sub-circuit and the compensation sub-circuit to reset the first node. In the second reset stage, the first reset sub-circuit is turned on under the control of the first reset control line, the second light-emitting control sub-circuit is turned on under the control of the second light-emitting control line, and a first initial voltage signal output by the first initial voltage line is provided to the first node through the first reset sub-circuit, the second light-emitting control sub-circuit and the compensation sub-circuit to reset the first node.

10. The pixel circuit of claim 2, wherein, The first control sub-circuit is connected with a third reset control line, and the pixel circuit further comprises a second refresh stage after the threshold compensation stage and the data writing stage and before the light emitting stage when the pixel circuit is driven. In the second refresh stage, the first control sub-circuit writes the first reference voltage of the first reference voltage line into the second node under the control of the third reset control line.

11. A display substrate comprising the pixel circuit according to any one of claims 1 to 10.

12. A driving method of a pixel circuit, the pixel circuit comprising at least a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a coupling sub-circuit and a first control sub-circuit, the driving sub-circuit being connected with a first node, a third node and a fourth node, the compensation sub-circuit being connected with a first scan line, the first node and the fourth node, the data writing sub-circuit being connected with a second scan line, a data line and a second node, the coupling sub-circuit being connected with the first node and the second node, and the first control sub-circuit being connected with the second node and a first reference voltage line; The pixel circuit comprises at least a first refresh stage, a threshold compensation stage and a data writing stage in sequence, or at least a first refresh stage, a data writing stage and a threshold compensation stage in sequence when the pixel circuit is driven, and in the first refresh stage, the data writing stage and the threshold compensation stage, the compensation sub-circuit is always in a conductive state under the control of the first scan line.

13. The driving method according to claim 12, wherein The pixel circuit further comprises a first light emitting control sub-circuit and a second light emitting control sub-circuit, the first light emitting control sub-circuit being connected with a first light emitting control line, a first power supply line and the third node, the second light emitting control sub-circuit being connected with a second light emitting control line, the fourth node and a fifth node, and the fifth node being in conduction with a first electrode of a light emitting element; In the threshold compensation stage, the first light emitting control sub-circuit is turned on under the control of the first light emitting control line, and the threshold voltage of the driving sub-circuit is written into the first node through the first light emitting control sub-circuit, the driving sub-circuit and the compensation sub-circuit. The pixel circuit further comprises a light emitting stage after the threshold compensation stage and the data writing stage when the pixel circuit is driven, in the light emitting stage, the first light emitting control sub-circuit is turned on under the control of the first light emitting control line, the second light emitting control sub-circuit is turned on under the control of the second light emitting control line, the first power supply line provides a driving current to the first electrode of the light emitting element, and the light emitting element is driven to emit light.

14. The driving method according to claim 13, wherein The pixel circuit further comprises a first reset sub-circuit and a second reset sub-circuit, the first reset sub-circuit being connected with a first reset control line, a first initial voltage line and a fifth node, and the second reset sub-circuit being connected with a second reset control line, a first reference voltage line and a third node, the first refresh stage comprising a first reset stage and a second reset stage in sequence. In the first reset stage, the second reset sub-circuit is turned on under the control of the second reset control line, and a first reference voltage signal output by the first reference voltage line is provided to the first node through the second reset sub-circuit and the driving sub-circuit, so as to reset the first node; In the second reset stage, the first reset sub-circuit is turned on under the control of the first reset control line, the second light-emitting control sub-circuit is turned on under the control of the second light-emitting control line, and a first initial voltage signal output by the first initial voltage line is provided to the first node through the first reset sub-circuit, the second light-emitting control sub-circuit and the compensation sub-circuit, so as to reset the first node.

15. The driving method according to claim 13, wherein The pixel circuit further comprises a first reset sub-circuit and a second reset sub-circuit, the first reset sub-circuit is connected with a first reset control line, a first initial voltage line and a fifth node, and the second reset sub-circuit is connected with a second reset control line, a first reference voltage line and a third node, the first refresh stage comprises a first reset stage and a second reset stage which are sequentially performed; In the first reset stage, the first reset sub-circuit is turned on under the control of the first reset control line, the second light-emitting control sub-circuit is turned on under the control of the first light-emitting control line, and a first initial voltage signal output by the first initial voltage line is provided to the first node through the first reset sub-circuit, the second light-emitting control sub-circuit and the compensation sub-circuit, so as to reset the first node; In the second reset stage, the second reset sub-circuit is turned on under the control of the second reset control line, and a first reference voltage signal output by the first reference voltage line is provided to the first node through the second reset sub-circuit and the driving sub-circuit, so as to reset the first node.

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